AMC1035DR [TI]
具有 ±1V 双极输入和 2.5V 基准输出的精密 Δ-Σ 调制器 | D | 8 | -40 to 125;型号: | AMC1035DR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 ±1V 双极输入和 2.5V 基准输出的精密 Δ-Σ 调制器 | D | 8 | -40 to 125 光电二极管 转换器 |
文件: | 总35页 (文件大小:1910K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
具有 ±1V 双极输入和 2.5V 基准电压输出的 AMC1035 Δ-Σ 调制器
1 特性
3 说明
1
•
针对电压和温度感应进行了优化的 Δ-Σ 调制器:
AMC1035 是一款精密 Δ-Σ 调制器,可在 3.0V 至 5.5V
的单电源下运行,且具有 9MHz 至 21MHz 的时钟信
号。在曼彻斯特模式下,额定时钟范围为 9MHz 至
11MHz。该器件的差分 ±1V 输入结构经过优化,可适
应工业应用中的典型高噪声 环境。
–
–
–
±1V 输入电压范围
高差分输入电阻:1.6GΩ(典型值)
集成 2.5V、±5mA 基准,可实现比例测量
•
出色的直流性能:
AMC1035 可选择曼彻斯特编码式输出位流,这样便无
需考虑接收器件的设置和保留时间要求并减少总体电路
布局工作。当用于与数字滤波器(例如集成到
TMS320F28004x、TMS320F2807x 或
–
–
–
–
–
失调电压误差:±0.5mV(最大值)
温漂:±6µV/°C(最大值)
增益误差:±0.25%(最大值)
增益漂移:±45ppm/°C(最大值)
比例增益漂移:±15ppm/°C(最大值)
TMS320F2837x 微控制器系列中)一起抽取输出位流
时,该器件可在 82kSPS 的数据速率下实现具有 87dB
动态范围的 16 位分辨率。
•
•
可选曼彻斯特编码式或未编码式位流输出
完整的额定工作温度范围:–40°C 至 +125°C
AMC1035 的内部基准源支持比例电路架构,可最大限
度降低电源电压变化和温漂对测量精度的负面影响。
2 应用
•
工业应用中的交流电压和温度 感应:
AMC1035 还可用于与数字隔离器和隔离电源一起实现
交流电力线电压检测。
–
–
–
–
电机驱动器
光电逆变器
不间断电源
工业运输系统
器件信息(1)
器件型号
AMC1035
封装
SOIC (8)
封装尺寸(标称值)
4.9mm x 3.9mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
应用示例
3.3 V or 5 V
AMC1035
REFOUT
VDD
2.5 V, 3.3 V or 5 V
Voltage
Reference
ISO7721
VDD1 VDD2
AINP
OUTA
INA
OUTB
GND2
CLKIN
DOUT
ûꢀ-Modulator
Manchester
Coding
T
INB
AINN
GND
MCE
GND1
GND2
GND1
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBAS837
AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 文档支持 ............................................................... 26
11.2 接收文档更新通知 ................................................. 26
11.3 社区资源................................................................ 26
11.4 商标....................................................................... 26
11.5 静电放电警告......................................................... 26
11.6 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2018) to Revision B
Page
•
•
Deleted PSRR specification for TA > 85°C from Reference Output section of Electrical Characteristics table ..................... 6
已更改 SINAD equation ........................................................................................................................................................ 22
Changes from Original (August 2018) to Revision A
Page
•
已更改 将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2018–2020, Texas Instruments Incorporated
AMC1035
www.ti.com.cn
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
MCE
AINP
1
2
3
4
8
7
6
5
VDD
CLKIN
DOUT
GND
AINN
REFOUT
Not to scale
Pin Functions
PIN
I/O
NO.
NAME
DESCRIPTION
Manchester coding enabled, active high, with internal pulldown resistor (typical value: 200 kΩ).
The polarity of this signal must not be changed when the clock signal is applied.
1
MCE
I
2
3
4
5
AINP
AINN
I
I
Noninverting analog input.
Inverting analog input.
REFOUT
GND
O
—
Reference output: 2.5 V nominal, maximum ±5-mA sink and source capability.
Ground reference.
Modulator bitstream data output, updated with the rising edge of the clock signal present on CLKIN.
6
DOUT
O
This pin is a Manchester coded output if MCE is pulled high. Use the rising edge of the clock to latch the
modulator bitstream at the input of the digital filter device.
Modulator clock input: 9 MHz to 21 MHz with an internal pulldown resistor (typical value: 200 kΩ).
7
8
CLKIN
VDD
I
The clock signal must be applied continuously for proper device operation; see the Clock Input section for
additional details.
Power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
—
Copyright © 2018–2020, Texas Instruments Incorporated
3
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ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
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6 Specifications
6.1 Absolute Maximum Ratings
(1)
see
MIN
–0.3
MAX
7
UNIT
V
Supply voltage, VDD to GND
Analog input voltage at AINP, AINN
Analog output voltage at REFOUT
Digital input voltage at CLKIN or MCE
Digital output voltage at DOUT
Input current to any pin except supply pins
Junction temperature, TJ
GND – 5
GND – 0.5
GND – 0.5
GND – 0.5
–10
VDD + 0.5
VDD + 0.5
VDD + 0.5
VDD + 0.5
10
V
V
V
V
mA
°C
°C
150
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD) Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
3.3
MAX UNIT
POWER SUPPLY
VDD
Supply voltage
VDD to GND
3.0
5.5
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
VIN = VAINP – VAINN
±1.25
V
V
V
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage(1)
VIN = VAINP – VAINN
–1
–2
1
(VAINP + VAINN) / 2 to GND
VDD
(VAINP + VAINN) / 2 to GND,
3.0 V ≤ VDD < 4 V,
VAINP = VAINN
–1.4
–0.8
–1.4
–0.8
VDD – 1.4
VDD – 2.4
2.7
(VAINP + VAINN) / 2 to GND,
3.0 V ≤ VDD < 4.5 V,
|VAINP – VAINN| = 1.25 V
VCM
Operating common-mode input voltage(2)
V
(VAINP + VAINN) / 2 to GND,
4 V ≤ VDD ≤ 5.5 V,
VAINP = VAINN
(VAINP + VAINN) / 2 to GND,
4.5 V ≤ VDD ≤ 5.5 V,
2.1
|VAINP – VAINN| = 1.25 V
DIGITAL INPUT
Input voltage
TEMPERATURE RANGE
TA Operating ambient temperature
VMCE or VCLKIN to GND
GND
–40
VDD
V
25
125 °C
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) See the Analog Input section for more details.
4
Copyright © 2018–2020, Texas Instruments Incorporated
AMC1035
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ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
6.4 Thermal Information
AMC1035
THERMAL METRIC(1)
D (SOIC)
8 PINS
120
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
52
61
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10
ψJB
60
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN =
GND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, and
VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
(VAINP + VAINN) / 2, VAINP = VAINN
(VAINP + VAINN) / 2, |VAINP – VAINN| = 1.25 V
3.0 V ≤ VDD < 4 V, VAINP = VAINN
3.0 V ≤ VDD < 4.5 V, |VAINP – VAINN| = 1.25 V
4 V ≤ VDD ≤ 5.5 V, VAINP = VAINN
4.5 V ≤ VDD ≤ 5.5 V, |VAINP – VAINN| = 1.25 V
AINN = GND
–1.45
–0.85
Negative common-mode undervoltage
detection level(2)
(1)
VCMuv
V
VDD – 1.35
VDD – 2.35
Positive common-mode overvoltage
detection level(2)
(1)
VCMov
V
2.75
2.15
0.1
RIN
RIND
CIN
CIND
IIB
Single-ended input resistance
Differential input resistance
Single-ended input capacitance
Differential input capacitance
Input bias current
0.4
1.6
2
GΩ
GΩ
pF
0.16
AINN = GND
2
pF
AINP = AINN = GND, (IAINP + IAINN) / 2
AINP = AINN = GND, (IAINP + IAINN) / 2
IIO = IAINP – IAINN
–10
–5
±3
10
5
nA
TCIIB
IIO
Input bias current thermal drift
Input offset current
±5
pA/°C
nA
±1
AINP = AINN, fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max
–104
CMRR
Common-mode rejection ratio
dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
–0.5 V ≤ VIN ≤ 0.5 V
–88
DC ACCURACY
Resolution(3)
16
–12
Bits
LSB
mV
INL
Integral nonlinearity(4)
Resolution: 16 bits
±2
±0.03
±0.1
12
0.5
EO
Offset error
Initial, at TA = 25°C, AINP = AINN = GND
–0.5
TCEO
Offset error thermal drift(5)
–6
6
µV/°C
Initial, at TA = 25°C
–0.25%
–0.3%
–45
±0.02%
±0.02%
±20
0.25%
0.3%
45
EG
Gain error
Initial, at TA = 25°C, ratiometric mode
TCEG
PSRR
Gain error thermal drift(6)
Power-supply rejection ratio
ppm/°C
dB
Ratiometric mode
–15
±4
15
AINP = AINN = GND, at dc
AINP = AINN = GND, 10 kHz, 100-mV ripple
–90
–84
(1) See the Analog Input section for more details.
(2) The common-mode overvoltage detection level has a typical hysteresis of 35 mV.
(3) The filter output is truncated to 16 bits. 16 bits of no missing codes is specified by design.
(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
valueMAX - valueMIN
TempRange
TCEO
=
(5) Offset error drift is calculated using the box method, as described by the following equation:
.
≈ value MAX - value MIN
’
6
∆
∆
÷
÷
TCEG ( ppm) =
ì10
value ìTempRange
«
◊
(6) Gain error drift is calculated using the box method, as described by the following equation:
Copyright © 2018–2020, Texas Instruments Incorporated
.
5
AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
www.ti.com.cn
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, AINP = –1 V to 1 V, AINN =
GND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, and
VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
81
77
87
83
dB
dB
dB
dB
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion
Spurious-free dynamic range
–87
87
–78
SFDR
78
REFERENCE OUTPUT
VREFOUT
TCVREFOUT
IREFOUT
Reference output voltage
Initial, at TA = 25°C, no load
2.495
–50
–5
2.5
2.505
V
Reference output voltage drift
Reference output current
Load regulation
±20
50 ppm/°C
mA
CLOAD < 1 nF(7)
5
Load to GND or VDD
REFOUT to GND
REFOUT to VDD
0.15
23
0.35 mV/mA
ISC
Short-circuit current
mA
–21
±30
PSRR
Power-supply rejection ratio
–200
200
35
µV/V
DIGITAL INPUTS (CMOS Logic With Schmitt-Trigger)
IIN
Input current
GND ≤ VIN ≤ VDD
μA
pF
V
CIN
VIH
VIL
Input capacitance
High-level input voltage
Low-level input voltage
3
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
V
DIGITAL OUTPUT: CMOS
CLOAD Output load capacitance
fCLKIN = 21 MHz
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
15
30
pF
V
VDD – 0.1
VDD – 0.4
VOH
High-level output voltage
Low-level output voltage
0.1
0.4
VOL
V
IOL = 4 mA
POWER SUPPLY
3.0 V ≤ VDD ≤ 3.6 V, IREFOUT = 0 mA, MCE = 0,
CLOAD = 15 pF
5.2
4.6
6.4
5.4
6.8
6.1
8.3
7.2
3.0 V ≤ VDD ≤ 3.6 V, IREFOUT = 0 mA, MCE = 1,
CLOAD = 15 pF(8)
IVDD
High-side supply current
mA
4.5 V ≤ VDD ≤ 5.5 V, IREFOUT = 0 mA, MCE = 0,
CLOAD = 15 pF
4.5 V ≤ VDD ≤ 5.5 V, IREFOUT = 0 mA, MCE = 1,
CLOAD = 15 pF(8)
(7) Capacitive load with a value ≥ 1nF requires series resistor to be connected to the REFOUT pin. See the Reference Output section for
more details.
(8) Typical value is specified at fCLKIN = 10 MHz, maximum value is specified at fCLKIN = 11 MHz.
6
Copyright © 2018–2020, Texas Instruments Incorporated
AMC1035
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ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
9
TYP
20
MAX UNIT
MCE = 0
MCE = 1
21
fCLKIN
CLKIN clock frequency
MHz
11
9
10
DutyCycle CLKIN clock duty cycle(1)
40%
6
50%
60%
ns
tH1
tH2
tH3
tD1
tD2
tD3
DOUT hold time after rising edge of CLKIN
MCE = 0, CLOAD = 15 pF
MCE = 1, CLOAD = 15 pF
MCE = 1, CLOAD = 15 pF
MCE = 0, CLOAD = 15 pF
MCE = 1, CLOAD = 15 pF
MCE = 1, CLOAD = 15 pF
DOUT hold time after rising edge of CLKIN
DOUT hold time after falling edge of CLKIN
Rising edge of CLKIN to DOUT valid delay
Rising edge of CLKIN to DOUT valid delay
Falling edge of CLKIN to DOUT valid delay
6
23
26
25
27
30
ns
ns
ns
ns
ns
10
11
15
10% to 90%, 3.0 V ≤ VDD ≤ 3.6 V,
CLOAD = 15 pF
2.5
1.5
5
3.5
5.8
4.4
tr
DOUT rise time
ns
10% to 90%, 4.5 V ≤ VDD ≤ 5.5 V,
CLOAD = 15 pF
90% to 10%, 3.0 V ≤ VDD ≤ 3.6 V,
CLOAD = 15 pF
2.5
tf
DOUT fall time
ns
90% to 10%, 4.5 V ≤ VDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
VDD step to 3.0 V, 0.1% settling,
CLKIN applied
tASTART
Analog startup time
0.25
ms
(1) The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.
tCLKIN
CLKIN
tHIGH
tLOW
tH1
tD1
tr / tf
DOUT
(MCE = 0)
tD2
tD3
tH2
tH3
tr / tf
DOUT
(MCE = 1)
图 1. Digital Interface Timing
VDD
tASTART
CLKIN
DOUT
...
Bitstream not valid (analog settling)
Valid bitstream
图 2. Device Startup Timing
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AMC1035
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6.7 Typical Characteristics
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
0
-20
10
7.5
5
-40
2.5
0
-60
-2.5
-5
-80
-100
-7.5
-10
-120
-0.65 -0.3
0.05
0.4
0.75
VCM (V)
1.1
1.45
1.8
2.15
0.01
0.1
1
10
100
1000
fIN (kHz)
D001
D002
VDD = 5.5 V
图 3. Input Bias Current vs
图 4. Common-Mode Rejection Ratio vs
Common-Mode Input Voltage
Input Signal Frequency
12
9
12
10
8
MCE = 0, fCLKIN = 20 MHz
MCE = 1, fCLKIN = 10 MHz
6
3
0
6
-3
-6
-9
-12
4
2
0
-1
-0.75 -0.5 -0.25
0
VIN (mV)
0.25
0.5
0.75
1
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D031
D003
图 5. Integral Nonlinearity vs Input Voltage
图 6. Integral Nonlinearity vs Temperature
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
Device 1
Device 2
Device 3
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
D004
D005
图 7. Offset Error vs Supply Voltage
图 8. Offset Error vs Temperature
8
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Typical Characteristics (接下页)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
MCE = 0
MCE = 1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
3
3.5
4
4.5
5
5.5
VDD (V)
D006
D007
图 9. Offset Error vs Clock Frequency
图 10. Gain Error vs Supply Voltage
0.25
0.2
0.3
0.2
0.1
0
Device 1
Device 2
Device 3
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D008
D009
图 11. Gain Error vs Temperature
图 12. Ratiometric Gain Error vs Temperature
0.3
0.2
0.1
0
0
-20
MCE = 0
MCE = 1
-40
-60
-0.1
-0.2
-0.3
-80
-100
-120
9
11
13
15
fCLKIN (MHz)
17
19
21
0.1
1
10
Ripple Frequency (kHz)
100
1000
D010
D011
图 13. Gain Error vs Clock Frequency
图 14. Power-Supply Rejection Ratio vs
Ripple Frequency
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Typical Characteristics (接下页)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
91
89
87
85
83
81
79
77
91
89
87
85
83
81
79
77
SNR
SINAD
SNR
SINAD
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
VDD (V)
D012
D013
图 15. Signal-to-Noise Ratio and
图 16. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Supply Voltage
Signal-to-Noise + Distortion vs Temperature
91
89
87
85
83
81
79
77
91
89
87
85
83
81
79
77
75
73
SNR, MCE = 0
SNR, MCE = 1
SINAD, MCE = 0
SINAD, MCE = 1
SNR
SINAD
9
11
13
15
fCLKIN (MHz)
17
19
21
0.1
1
10
100
fIN (kHz)
D014
D015
图 17. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Clock Frequency
图 18. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Frequency
100
95
90
85
80
75
70
65
60
55
-76
SNR
SINAD
-80
-84
-88
-92
-96
-100
-104
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
3
3.5
4
4.5
5
5.5
VDD (V)
D016
D017
图 19. Signal-to-Noise Ratio and
Signal-to-Noise + Distortion vs Input Signal Amplitude
图 20. Total Harmonic Distortion vs Supply Voltage
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Typical Characteristics (接下页)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
-76
-76
MCE = 0
MCE = 1
-80
-80
-84
-84
-88
-88
-92
-92
-96
-96
-100
-104
-100
-104
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
9
11
13
15
fCLKIN (MHz)
17
19
21
D018
D019
图 21. Total Harmonic Distortion vs Temperature
图 22. Total Harmonic Distortion vs Clock Frequency
-76
-80
-76
-80
-84
-84
-88
-88
-92
-92
-96
-96
-100
-104
-100
-104
0.1
1
fIN (kHz)
10
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
D020
D021
图 23. Total Harmonic Distortion vs
图 24. Total Harmonic Distortion vs
Input Signal Frequency
Input Signal Amplitude
109
105
101
97
109
105
101
97
93
93
89
89
85
85
81
81
77
77
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
VDD (V)
D022
D023
图 25. Spurious-Free Dynamic Range vs Supply Voltage
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图 26. Spurious-Free Dynamic Range vs Temperature
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Typical Characteristics (接下页)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
109
105
101
97
109
105
101
97
MCE = 0
MCE = 1
93
93
89
89
85
85
81
81
77
77
9
0
0
11
13
15
fCLKIN (MHz)
17
19
21
0.1
1
fIN (kHz)
10
D024
D025
图 27. Spurious-Free Dynamic Range vs
图 28. Spurious-Free Dynamic Range vs
Clock Frequency
Input Signal Frequency
109
105
101
97
0
-20
-40
-60
93
-80
89
-100
-120
-140
-160
85
81
77
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8
VIN (Vpp)
2
0
5
10
15
20
Frequency (kHz)
25
30
35
40
D026
D027
4096-point FFT, VIN = 2 VPP
图 30. Frequency Spectrum With 1-kHz Input Signal
图 29. Spurious-Free Dynamic Range vs
Input Signal Amplitude
0
-20
2.505
2.503
2.501
2.499
2.497
2.495
-40
-60
-80
-100
-120
-140
-160
5
10
15
Frequency (kHz)
20
25
30
35
40
3
3.5
4
4.5
5
5.5
VDD (V)
D028
D029
4096-point FFT, VIN = 2 VPP
图 31. Frequency Spectrum With 5-kHz Input Signal
图 32. Reference Output Voltage vs Supply Voltage
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Typical Characteristics (接下页)
at VDD = 3.3 V, AINP = –1 V to 1 V, AINN = GND, fCLKIN = 20 MHz, MCE = 0, and sinc3 filter with OSR = 256 (unless
otherwise noted)
2.52
2.515
2.51
11
10
9
Device 1
Device 2
Device 3
MCE = 0
MCE = 1
2.505
2.5
8
7
2.495
2.49
6
5
2.485
2.48
4
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
5
5.5
VDD (V)
D030
D032
图 33. Reference Output Voltage vs Temperature
图 34. Supply Current vs Supply Voltage
11
10
9
11
10
9
MCE = 0
MCE = 1
MCE = 1
MCE = 0
8
8
7
7
6
6
5
5
4
4
3
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
9
11
13
15
fCLKIN (MHz)
17
19
21
D033
D034
图 35. Supply Current vs Temperature
图 36. Supply Current vs Clock Frequency
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7 Detailed Description
7.1 Overview
The differential analog input (comprised of input signals AINP and AINN) of the AMC1035 is a chopper-stabilized
buffer, followed by the switched-capacitor input of a second-order, delta-sigma (ΔΣ) modulator stage that digitizes
the input signal into a 1-bit output stream. The data output DOUT of the converter provides a stream of digital
ones and zeros that is synchronous to the externally-provided clock source at the CLKIN pin with a frequency in
the range of 9 MHz to 21 MHz. The time average of this serial bitstream output is proportional to the analog input
voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1035. The 1.6-GΩ differential
input resistance of the analog input stage supports low gain-error signal sensing in high-voltage applications
using resistive dividers. The external clock input simplifies the synchronization of multiple measurement channels
on the system level. The extended frequency range of up to 21 MHz supports higher performance levels
compared to the other solutions available on the market.
7.2 Functional Block Diagram
VDD
MCE
Manchester
Coding
DOUT
CLKIN
AINP
AINN
ûꢀ-Modulator
Voltage
Reference
REFOUT
GND
7.3 Feature Description
7.3.1 Analog Input
The AMC1035 incorporates front-end circuitry that contains a buffered sampling stage, followed by a ΔΣ
modulator. To support a bipolar input range, the device uses a charge pump that allows single-supply operation
to simplify the overall system design and minimize the circuit cost. For reduced offset and offset drift, the input
buffer is chopper-stabilized with the switching frequency set at fCLKIN / 32. 图 37 shows the spur created by the
switching frequency.
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10 100
Frequency (kHz)
1000
10000
D036
sinc3 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz
图 37. Quantization Noise Shaping
14
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Feature Description (接下页)
The linearity and noise performance of the device are ensured only when the differential analog input voltage
remains within the specified linear full-scale range (FSR), that is ±1 V, and within the specified input common-
mode range.
图 38 shows the specified common-mode input voltage that applies for the full-scale input voltage range as
specified in this document along with the corresponding common-mode undervoltage and overvoltage threshold
levels.
If smaller input signals are used, the operational common-mode input voltage range widens. 图 39 shows the
common-mode input voltage that applies with no differential input signal; that is, when the voltage applied on
AINP is equal to the voltage applied on AINN. The common-mode input voltage range scales with the actual
differential input voltage between this range and the range in 图 38.
4
4
VCMov
VCMuv
VCMov
VCMuv
3
3
2
2
1
1
Specified VCM
Range
Specified VCM
Range
0
0
-1
-1
-2
-2
3
3.25
3.5
3.75
4
4.25
4.5
5
5.5
3
3.25
3.5
3.75
4
4.25
4.5
5
5.5
VDD (V)
VDD (V)
图 38. Common-Mode Input Voltage Range With a
Full-Scale Differential Input Signal of ±1.25 V
图 39. Common-Mode Input Voltage Range With a
Zero Differential Input Signal
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Feature Description (接下页)
7.3.2 Modulator
The modulator implemented in the AMC1035 (such as the one conceptualized in 图 40) is a second-order,
switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit
digital-to-analog converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is summed with the input signal VIN and the output of the first integrator V2. Depending on the polarity of
the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing the associated analog output voltage V5, causing the integrators to progress in the
opposite direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
V3
V4
VIN
Integrator 1
Integrator 2
ꢀ
ꢀ
CMP
0 V
V5
DAC
图 40. Block Diagram of a Second-Order Modulator
As depicted in 图 37, the modulator shifts the quantization noise to high frequencies. Therefore, use a low-pass
digital filter at the output of the device to increase the overall performance. This filter is also used to convert from
the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller families TMS320F28004x, TMS320F2807x, and TMS320F2837x offer a suitable programmable,
hardwired filter structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1035.
Also, SD24_B converters on the MSP430F677x microcontrollers offer a path to directly access the integrated
sinc-filters for a simple system-level solution for multichannel, isolated current sensing. An additional option is to
use a suitable application-specific device, such as the AMC1210 (a four-channel digital sinc filter). Alternatively, a
field-programmable gate array (FPGA) can be used to implement the filter.
7.3.3 Reference Output
The AMC1035 offers a voltage reference output that can source or sink current to significantly reduce the gain
error thermal drift in ratiometric applications as specified in the Electrical Characteristics table. The IGBT
Temperature Sensing section provides an example of a ratiometric use case for the AMC1035.
The reference output can drive capacitive loads less than 1 nF. Use a series resistor to avoid oscillations and
degradation of performance for capacitive loads ≥ 1 nF. 表 1 lists the recommended series resistor values for
given capacitor value examples. Interpolate for capacitive loads with a value between the given examples.
表 1. Series Resistor Value for Capacitive Loads ≥ 1 nF on REFOUT Pin
CAPACITIVE LOAD ON
1 nF
3.3 nF
10 nF
33 nF
100 nF
330 nF
1 µF
3.3 µF
10 µF
REFOUT PIN
Recommended series
resistor
33 Ω
56 Ω
47 Ω
33 Ω
15 Ω
10 Ω
5.6 Ω
3.3 Ω
1.8 Ω
16
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7.3.4 Clock Input
The AMC1035 system clock is provided externally at the CLKIN pin. The clock signal must be applied
continuously for proper device operation.
To support the bipolar input voltage range with a single supply, the AMC1035 includes a charge pump. This
charge pump stops operating if the clock signal is below the specified frequency range or if the signal is paused
or missing. Additionally, the input bias current increases beyond the specified range and significantly reduces the
input resistance of the device. When the clock signal is paused or missing, the modulator stops the analog signal
conversion and the digital output signal remains frozen in the last logic state. When the clock signal is applied
again after a pause, the internal analog circuitry biasing must settle for proper device performance. In this case,
consider the tASTART specification in the Switching Characteristics table.
7.3.5 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of
resolution, that percentage ideally corresponds to code 58982 (an unsigned code). A differential input of –1 V
produces a stream of ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit
resolution. These input voltages are also the specified linear range of the AMC1035 with performance as
specified in this document. If the input voltage value exceeds this range, the output of the modulator shows
nonlinear behavior when the quantization noise increases. The output of the modulator clips with a stream of only
zeros with an input less than or equal to –1.25 V or with a stream of only ones with an input greater than or equal
to 1.25 V. In this case, however, the AMC1035 generates a single 1 (if the input is at negative full-scale) or 0
every 128 clock cycles to indicate proper device function (see the Fail-Safe Output section for more details). 图
41 shows the input voltage versus the output modulator signal.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
图 41. Analog Input versus the AMC1035 Modulator Output
公式 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception of a
full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN + VClipping
2ì VClipping
(1)
The modulator bitstream on the DOUT pin changes with the rising edge of the clock signal applied on the CLKIN
pin. Use the rising edge of the clock to latch the modulator bitstream at the input of the digital filter device.
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7.3.6 Manchester Coding Feature
The AMC1035 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one transition
per bit to support clock signal recovery from the bitstream. The Manchester coding combines the clock and data
information using exclusive-OR (XOR) logical operation that results in a bitstream free of DC components. 图 42
shows the resulting bitstream from this coding. The duty cycle of the Manchester encoded bitstream depends on
the duty cycle of the input clock CLKIN. To enable Manchester coding on the AMC1035, pull the input pin MCE
high. The DOUT signal is inverted if the MCE status changes when CLKIN is high.
Clock
Uncoded
Bitstream
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
Machester
Coded
Bitstream
图 42. Manchester Coded Output of the AMC1035
7.4 Device Functional Modes
The AMC1035 is operational when the power supply VDD and clock signal CLKIN are applied, as specified in 图
39 and the Switching Characteristics table.
7.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1035 (that is, |VIN| ≥ |VClipping|), the device generates a single one
or zero every 128 bits at DOUT, as shown in 图 43, depending on the actual polarity of the signal being sensed.
This feature is also supported with Manchester-coded output and allows full-scale and invalid input signals to be
identified as described in the Fail-Safe Output section and can be used for advanced system-level diagnostics.
127 CLKIN cycles
127 CLKIN cycles
CLKIN
...
...
DOUT
(MCE = 0)
(VAINP t VAINN) ≤ t1.25 V
...
...
DOUT
(MCE = 1)
...
...
...
...
DOUT
(MCE = 0)
(VAINP t VAINN) ≥ 1.25 V
...
...
DOUT
(MCE = 1)
图 43. Overrange Output of the AMC1035
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Device Functional Modes (接下页)
7.4.2 Fail-Safe Output
图 44 shows that if the common-mode voltage of the input reaches or exceeds the specified common-mode
undervoltage, VCMuv, or overvoltage detection level, VCMov as defined in the Electrical Characteristics table, the
DOUT of the AMC1035 is held at steady-state high.
VCMuv < VCM < VCMov
VCMov G ëCM or VCM G ëCMuv
VCM
CLKIN
DOUT
(MCE = 0)
DOUT
(MCE = 1)
图 44. Fail-Safe Output of the AMC1035
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Digital Filter Usage
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). 公式 2 shows a sinc3-type filter, which is a
very simple filter, built with minimal effort and hardware:
3
-OSR
≈
’
1- z
H z =
( )
∆
∆
÷
÷
1- z-1
«
◊
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling
ratio (OSR) of 256 and an output word width of 16 bits.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
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8.2 Typical Applications
8.2.1 Voltage Sensing
ΔΣ modulators are widely used in frequency inverter designs because of their high AC and DC performance.
Frequency inverters are critical parts of industrial motor drives, photovoltaic inverters (string and central
inverters), uninterruptible power supplies (UPS), and other industrial applications.
图 45 shows a simplified schematic of a motor drive application with the AMC1035 used for the DC-link and
output phase voltage sensing. In this example, all resistive dividers reference to the negative DC-link voltage that
is also used as a ground reference point for the microcontroller. An additional fifth AMC1035 can be used for
temperature sensing of the insulated-gate bipolar transistor (IGBT) module; see the IGBT Temperature Sensing
section for more details.
Current feedback is performed with shunt resistors (RSHUNT) and TI's AMC1306M25 isolated modulators.
Depending on the system design, either all three or only two motor phase currents are sensed.
Depending on the overall digital processing power requirements and with a total of eight ΔΣ modulator bitstreams
to be processed by the MCU, a derivate from either the low-cost single-core TMS320F2807x or the dual-core
TMS320F2837x families can be used in this application.
+VBUS
Motor
IDC
RSHUNT
U
VBUS
RDC1
RDC2
RSHUNT
V
IAC
RSHUNT
W
RAC1
RAC1
RAC1
3.3VISO
3.3 V
AMC1306M25
AVDD
INP
DVDD
DOUT
RFLT
CFLT
RFLT
RAC2
RAC2
RAC2
INN
CLKIN
RDC3
AGND DGND
RAC3
RAC3
RAC3
3.3 V
AMC1035
-VBUS
MCE
VDD
RFLT
CFLT
RFLT
3.3 VISO
TMS320F28x7x
AINP
DOUT
3.3 VISO
3.3 V
SDFM1
SD1_D1
AMC1306M25
AINN
CLKIN
REFOUT GND
AVDD
INP
DVDD
DOUT
RFLT
CFLT
RFLT
SD1_D2
SD1_D3
SD1_D4
SD1_C1
SD1_C2
SD1_C3
SD1_C4
3.3 V
AMC1306M25
INN
CLKIN
AVDD
DVDD
DOUT
RFLT
CFLT
RFLT
AGND DGND
INP
3.3 V
AMC1035
INN
CLKIN
AGND DGND
MCE
VDD
RFLT
CFLT
RFLT
AINP
DOUT
SDFM2
SD2_D1
3.3 V
AMC1035
AINN
CLKIN
SD2_D2
SD2_D3
SD2_D4
SD2_C1
SD2_C2
SD2_C3
SD2_C4
MCE
VDD
RFLT
CFLT
RFLT
REFOUT GND
AINP
DOUT
AINN
CLKIN
REFOUT GND
3.3 V
AMC1035
MCE
VDD
RFLT
CFLT
RFLT
AINP
DOUT
CDCLVC1106
AINN
CLKIN
PWMx
Y0
Y2
Y4
REFOUT GND
Y1
Y2
1G
Y5
3.3 V
CLKIN
图 45. The AMC1035 in a Frequency Inverter Application
20
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Typical Applications (接下页)
8.2.1.1 Design Requirements
表 2 lists the parameters for this typical application.
表 2. Design Requirements
PARAMETER
VALUE
3.3 V
Supply voltage
Voltage drop across the sensing resistor RDC1 for a linear response
Voltage drop across the sensing resistors RACx for a linear response
Current through the sensing resistors RACx
1 V (maximum)
±1 V (maximum)
±100 µV (maximum)
8.2.1.2 Detailed Design Procedure
Use Ohm's Law to calculate the minimum total resistance of the resistive dividers to limit the cross current to the
desired values:
•
•
For the voltage sensing on the DC bus: RDC1 + RDC2 + RDC3 = VBUS / IDC
For the voltage sensing on the output phases U, V, and W: RAC1 + RAC2 + RAC3 = VPHASE (max) / IAC
Consider the following two restrictions to choose the proper value of the resistors RDC3 and RAC3
:
•
The voltage drop caused by the nominal voltage range of the system must not exceed the recommended
input voltage range of the AMC1035: VxC3 ≤ VFSR
•
The voltage drop caused by the maximum allowed system overvoltage must not exceed the input voltage that
causes a clipping output: VxC3 ≤ VClipping
Use similar approach for calculation of the shunt resistor values RSHUNT and see the AMC1306M25 data sheet
for further details.
表 3 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 600 V and 800 V on
the DC bus.
表 3. Resistor Value Examples for DC Bus Sensing
PARAMETER
600-V DC BUS
3.01 MΩ
3.01 MΩ
10 kΩ
800-V DC Bus
4.22 MΩ
4.22 MΩ
10.5 kΩ
Resistive divider resistor RDC1
Resistive divider resistor RDC2
Sense resistor RDC3
Resulting current through resistive divider IDC
Resulting voltage drop on sense resistor VRDC3
99.5 µA
94.7 µA
0.995 V
0.994 V
表 4 lists examples of nominal E96-series (1% accuracy) resistor values for systems using 230 V and 690 V on
the output phases.
表 4. Resistor Value Examples for Output Phase Voltage Sensing
PARAMETER
±400-VAC PHASE
2.0 MΩ
±690-VAC PHASE
3.48 MΩ
Resistive divider resistor RAC1
Resistive divider resistor RAC2
2.0 MΩ
3.48 MΩ
Sense resistor RAC3
10.0 kΩ
10.0 kΩ
Resulting current through resistive divider IAC
Resulting voltage drop on sense resistor VRAC3
99.8 µA
99.0 µA
±0.998 V
±0.990 V
版权 © 2018–2020, Texas Instruments Incorporated
21
AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
www.ti.com.cn
Use a power supply with a nominal voltage of 3.3 V to directly connect all modulators to the microcontroller.
For modulator output bitstream filtering, a device from TI's TMS320F2807x family of low-cost microcontrollers
(MCUs) or TMS320F2837x family of dual-core MCUs is recommended. These MCU families support up to eight
channels of dedicated hardwired filter structures called sigma-delta filter modules (SDFMs) that significantly
simplify system level design by offering two filtering paths per channel: one providing high accuracy results for
the control loop and one that offers a fast response path for overcurrent detection. Use one of the pulse-width
modulation (PWM) sources inside the MCU to generate the clock for the modulators and for easy
synchronization of all feedback signals and the switching control of the gate drivers.
图 45 uses a clock buffer to distribute the clock reference signal generated on one of the PWM outputs of the
MCU (called PWMx in 图 45) to all modulators used in the circuit and as a reference for the digital filters in the
MCU. In this example, TI's CDCLVC1106 is used for this purpose. Each CDCLVC1106 output can drive a load of
8 pF that is sufficient to drive up to two modulator and up to four SDFM clock inputs.
8.2.1.3 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. 图
46 shows the ENOB of the AMC1035 with different oversampling ratios on a sinc3 filter. This number is
calculated from the SINAD by using 公式 3 in this document.
SINAD = 1.76 dB + 6.02 dB x ENOB
(3)
16
15
14
13
12
11
10
9
8
7
10
100
OSR
1000
D035
Sinc3 filter
图 46. Measured Effective Number of Bits vs Oversampling Ratio
22
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AMC1035
www.ti.com.cn
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
8.2.2 IGBT Temperature Sensing
The high input impedance of the AMC1035 is optimized for usage in voltage-sensing applications. Additionally,
the internal voltage reference supports temperature sensing using a positive temperature coefficient (PTC) or a
negative temperature coefficient (NTC) sensor often integrated in the IGBT module.
The same reference is internally used by the modulator, resulting in a ratiometric system solution that minimizes
the overall temperature drift of the sensing path. 图 47 shows a simplified schematic of the AMC1035 used for
temperature sensing of the IGBT module.
3.3 V
VDD
REFOUT
AMC1035
MCE
TMS320F28x7x
IGBT Module
Digital
Filter
AINP
AINN
DOUT
CLKIN
SD-Dx
SD-Cx
GND
T
PWMx
图 47. Using the AMC1035 for Temperature Sensing
8.2.3 What to Do and What Not to Do
Do not leave the analog inputs of the AMC1035 unconnected (floating) when the device is powered up. If either
modulator input is left floating, the input bias current may drive this input beyond the specified common-mode
input voltage range. If both inputs are beyond that range, the gain of the front-end diminishes. In both cases, the
modulator outputs a fail-safe bitstream as described in the Fail-Safe Output section.
版权 © 2018–2020, Texas Instruments Incorporated
23
AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
www.ti.com.cn
9 Power Supply Recommendations
For decoupling of the power supply, a 0.1-µF capacitor is recommended to be placed as close to the VDD pin of
the AMC1035 as possible, as shown in 图 48, followed by an additional capacitor in the range of 1 µF to 10 µF.
Phase X
R1
AMC1035
VDD
GND
3.0 V to 3.6 V
C1
0.1 ꢀF
C2
2.2 ꢀF
MCE
optional
anti-aliasing filter
R2
R3
TMS320F2837x
DOUT
CLKIN
AINP
AINN
SD-Dx
ûꢁ Modulator
SD-Cx
PWMx
图 48. Decoupling the AMC1035
Safety considerations or high common-mode voltage levels may require the AMC1035 to be galvanically isolated
from other parts of the system. 图 49 shows an example of a circuit that uses the ISO7721 to isolate the signal
path and the SN6501 and a transformer to generate the required isolated power.
AMC1035
ISO7721
AINP
AINN
DOUT
CLKIN
DATA
CLK
ûꢀ Modulator
VDD2
VDD1
VDD
GND
VDD1
GND1
VDD2
GND2
2.2 …F 0.1 …F
0.1 …F
0.1 …F
MCE
GND2
GND1
GND1
TLV70450
OUT
GND
IN
SN6501
D1 VCC
10 …F
0.1 …F 10 …F
20 V
0.1 …F
D2 GND
GND1
10 …F
20 V
GND1
GND2
图 49. Galvanic Isolation of the AMC1035
图 50 shows an alternative solution that uses the ISOW7821 to isolate the signal path and provide the isolated
power supply for the AMC1035.
AMC1035
ISOW7821
3.3 V
3.3 V or 5 V
DATA
CLK
0.1 …F 10 …F
AINP
AINN
DOUT
CLKIN
ûꢀ Modulator
VDD
MCE
GND
VISO
SEL
VCC
EN1
0.1 …F 2.2 …F
10 …F 0.1 …F
GND2
GND1
GND1
GND2
图 50. Galvanic Isolation of the AMC1035 for PCB Space-Constrained Applications
24
版权 © 2018–2020, Texas Instruments Incorporated
AMC1035
www.ti.com.cn
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
10 Layout
10.1 Layout Guidelines
图 51 shows two layout recommendations for designs based on 1206-SMD or 0603-SMD size decoupling
capacitors placed as close as possible to the AMC1035. For best performance, place the AMC1035 as close as
possible to the source of the analog signal to be converted and keep the layout of the AINP and AINN traces
symmetrical.
10.2 Layout Example
AMC1035
AMC1035
MCE
VDD
MCE
VDD
AINP
AINN
CLKIN
DOUT
GND
AINP
AINN
CLKIN
DOUT
GND
To
digital
filter
To
digital
filter
0.1 µF
1206
2.2 µF
1206
To
Sensor
To
Sensor
REFOUT
REFOUT
LEGEND
Copper Pour and Traces
Via to Ground Plane
Via to Supply Plane
图 51. Recommended Layout of the AMC1035
版权 © 2018–2020, Texas Instruments Incorporated
25
AMC1035
ZHCSIP8B –AUGUST 2018–REVISED APRIL 2020
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
•
•
德州仪器 (TI),《TMS320F28004x Piccolo™ 微控制器》数据表
德州仪器 (TI),《TMS320F2807x Piccolo™ 微控制器》数据表
德州仪器 (TI),《TMS320F2837xD 双核 Delfino™ 微控制器》数据表
德州仪器 (TI),《具有优异 EMC 性能的 ISO772x 高速双通道数字隔离器》数据表
德州仪器 (TI),《MSP430F677x 多相位仪表计量片上系统》数据表
德州仪器 (TI),《适用于二阶 Δ-Σ 调制器的 AMC1210 四路数字滤波器》数据表
德州仪器 (TI),《将 ADS1202 与 FPGA 数字滤波器结合,以便在电机控制应用中进行 电流测量》中的电流》
应用报告
•
•
•
•
•
德州仪器 (TI),《具有高 CMTI 的 AMC1306x 小型、高精度、增强型隔离式 Δ-Σ 调制器》数据表
德州仪器 (TI),《CDCLVC11xx 3.3V 和 2.5V LVCMOS 高性能时钟缓冲器系列》数据表
德州仪器 (TI),《LM117、LM317-N 宽温度范围三引脚可调稳压器》数据表
德州仪器 (TI),《用于隔离式电源的 SN6502 低噪声 350mA 410kHz 变压器驱动器》数据表
德州仪器 (TI),《具有集成式高效低辐射直流/直流转换器的 ISOW7821 高性能 5000VRMS 增强型双通道数字隔
离器》数据表
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
26
版权 © 2018–2020, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1035D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
MC1035
MC1035
AMC1035DR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1035DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 336.1 25.0
AMC1035DR
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
AMC1035D
D
8
75
507
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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