AMC1106M05DWV [TI]

±50mV 输入、精密电流检测基本隔离式调制器

| DWV | 8 | -40 to 125;


型号：	AMC1106M05DWV
厂家：	TEXAS INSTRUMENTS
描述：	±50mV 输入、精密电流检测基本隔离式调制器 \| DWV \| 8 \| -40 to 125 光电二极管转换器
文件：	总39页 (文件大小：1292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

AMC1106x 小型高精度基本型隔离式 Δ-Σ 调制器

1 特性

3 说明

•

±50mV 输入电压范围，针对使用分流电阻器测量电

流进行了优化

AMC1106 是一款精密 Δ-Σ 调制器，此调制器的输出与

输入电路由抗电磁干扰性能极强的电容式隔离层隔开。

•

曼彻斯特编码或未编码的位流选项

出色的直流性能，支持系统级高精度检测：

AMC1106 的输入级针对直接连接到分流电阻器或其他

低电压等级信号源的情况进行了优化，通常用于多相电

量计，可实现出色的交流和直流性能。该器件具有

±50mV 的低输入电压范围，支持使用具有较小电阻值

的分流电阻器来最大限度地降低功率耗散。利用适当的

数字滤波器消除 AMC1106 的输出位流。

–

失调误差和温漂：±50 µV，±1 µV/°C（最大

值）

–

增益误差和温漂：±0.2%，±40 ppm/°C（最大

值）

•

3.3V 运行电压，可降低隔离栅两侧的功率耗散

MSP430F67x、TMS320F2807x 和 TMS320F2837x

微控制器以及 AMC1210 均集成了这些数字滤波器，

可实现与 AMC1106 的无缝运行。

系统级诊断特性

高电磁场抗扰度

（参见《ISO72x 数字隔离器磁场抗扰度》应用报

告）

在高侧，调制器由

•

安全相关认证：

3.3V 或 5V 电源 (AVDD) 供电。隔离式数字接口由

3.0V、3.3V 或 5V 电源 (DVDD) 供电。

–

符合 DIN V VDE V 0884-11 (VDE V 0884-11):

2017-01 标准的 5657 V_PK基本型隔离

AMC1106 额定扩展工业运行温度范围为 -40°C 至

+125°C。

符合 UL 1577 标准且长达 1 分钟的 4000V_RMS

隔离

CAN/CSA No. 5A 组件接受服务通知、

IEC 60950-1 和 IEC 60065 终端设备标准

器件信息⁽¹⁾

器件编号

封装

SOIC (8)

封装尺寸（标称值）

AMC1106x

5.85mm × 7.50mm

2 应用

三相电量计中基于分流电阻器的电流检测

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

Phase Phase Phase

3.3 V

MSP430F67641A

SD24_B

Module

Decimation

Filter

Neutral

AVDD1

AVDD2

AMC1106M05

ûꢀ

Modulator

AMC1106M05

Decimation

Filter

ûꢀ

Modulator

Metrology

Calculation

Engine

Clock

Generator

System

Interface

AVDD3

AMC1106M05

Decimation

Filter

ûꢀ

Modulator

Level-Shifted

Voltage Divider

10-Bit

SAR

ADC

Level-Shifted

Voltage Divider

Level-Shifted

Voltage Divider

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS789

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram ....................................... 17

8.3 Feature Description................................................. 18

8.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 23

9.1 Application Information............................................ 23

9.2 Typical Application .................................................. 24

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Power Ratings........................................................... 4

7.6 Insulation Specifications............................................ 5

7.7 Safety-Related Certifications..................................... 6

7.8 Safety Limiting Values .............................................. 6

7.9 Electrical Characteristics: AMC1106x....................... 7

7.10 Timing Requirements.............................................. 9

7.11 Switching Characteristics........................................ 9

7.12 Insulation Characteristics Curves ......................... 10

7.13 Typical Characteristics.......................................... 11

Detailed Description ............................................ 17

10 Power Supply Recommendations ..................... 27

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 28

12 器件和文档支持 ..................................................... 29

12.1 器件支持................................................................ 29

12.2 文档支持................................................................ 29

12.3 相关链接................................................................ 29

12.4 接收文档更新通知 ................................................. 29

12.5 社区资源................................................................ 29

12.6 商标....................................................................... 30

12.7 静电放电警告......................................................... 30

12.8 术语表 ................................................................... 30

13 机械、封装和可订购信息....................................... 30

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (October 2017) to Revision A

Page

•

Changed test conditions of DTI parameter............................................................................................................................. 5

Changed test conditions of V_IOSMparameter.......................................................................................................................... 5

Changed test conditions of second q_pdparameter row ......................................................................................................... 5

Changed test conditions of third q_pdparameter row .............................................................................................................. 5

Changed VDE certification details in Safety Related Certifications table............................................................................... 6

Changed Block Diagram of an Isolation Channel figure....................................................................................................... 20

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

5 Device Comparison Table

PART NUMBER

AMC1106E05

AMC1106M05

DIGITAL OUTPUT INTERFACE

Manchester coded CMOS

Uncoded CMOS

6 Pin Configuration and Functions

DWV Package

8-Pin SOIC

Top View

AVDD

AINP

DVDD

CLKIN

DOUT

DGND

AINN

AGND

Not to scale

Pin Functions

I/O

NO.

NAME

DESCRIPTION

Analog (high-side) power supply, 3.0 V to 5.5 V.

AVDD

—

See the Power Supply Recommendations section for decoupling recommendations.

AINP

AINN

Noninverting analog input

Inverting analog input

AGND

DGND

DOUT

CLKIN

—

Analog (high-side) ground reference

Digital (controller-side) ground reference

Modulator data output. This pin is a Manchester coded output for the AMC1106E05.

Modulator clock input

Digital (controller-side) power supply, 2.7 V to 5.5 V.

See the Power Supply Recommendations section for decoupling recommendations.

DVDD

—

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

UNIT

Supply voltage, AVDD to AGND or DVDD to DGND

Analog input voltage at AINP, AINN

6.5

AGND – 6

DGND – 0.5

–10

AVDD + 0.5

DVDD + 0.5

Digital output voltage at DOUT, or digital input voltage on CLKIN

Input current to any pin except supply pins

Junction temperature, T_J

°C

150

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

3.0

NOM

5.0

MAX UNIT

AVDD

DVDD

T_A

Analog (high-side) supply voltage (AVDD to AGND)

Digital (controller-side) supply voltage (DVDD to DGND)

Operating ambient temperature

5.5

2.7

3.3

–40

125

°C

7.4 Thermal Information

AMC1106x

DWV (SOIC)

8 PINS

112.2

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

47.6

R_θJB

ψ_JT

Junction-to-board thermal resistance

60.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

23.1

ψ_JB

60.0

R_θJC(bot)Junction-to-case (bottom) thermal resistance

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Power Ratings

PARAMETER

TEST CONDITIONS

AMC1106E05, AVDD = DVDD = 5.5 V

AMC1106M05, AVDD = DVDD = 5.5 V

MIN

TYP

MAX UNIT

91.85

Maximum power dissipation

(both sides)

P_D

86.90

Maximum power dissipation

(high-side supply)

P_D1

P_D2

AVDD = 5.5 V

53.90

AMC1106E05, AVDD = DVDD = 5.5 V

AMC1106M05, AVDD = DVDD = 5.5 V

37.95

33.00

Maximum power dissipation

(low-side supply)

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance through air

≥ 9

Shortest pin-to-pin distance across the package surface

Minimum internal gap (internal clearance) of the

insulation

DTI

CTI

Distance through insulation

≥ 0.021

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

≥ 600

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

I-IV

Overvoltage category per IEC 60664-1

DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01⁽²⁾

V_IORM

Maximum repetitive peak isolation voltage

At ac voltage (bipolar)

849

600

V_PK

V_RMS

V_DC

At ac voltage (sine wave)

V_IOWM

Maximum-rated isolation working voltage

At dc voltage

849

V_TEST= V_IOTM, t = 60 s (qualification test)

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production test)

5657

6789

V_IOTM

V_IOSM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 60065, 1.2/50-µs waveform,

V_TEST= 1.3 × V_IOSM= 7800 V_PK(qualification)

6000

Method a, after input/output safety test subgroup 2 / 3,

V_ini= V_IOTM, t_ini= 60 s,

≤ 5

V_pd(m)= 1.2 × V_IORM= 1019 V_PK, t_m= 10 s

Method a, after environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s,

V_pd(m)= 1.3 × V_IORM= 1104 V_PK, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

≤ 5

Method b1, at routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s,

V_pd(m)= 1.5 × V_IORM= 1274 V_PK, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

Pollution degree

V_IO= 0.5 V_PPat 1 MHz

1.2

> 10⁹

V_IO= 500 V at T_S= 150°C

Climatic category

40/125/21

UL1577

V_TEST= V_ISO= 4000 V_RMSor 5657 V_DC, t = 60 s

(qualification), V_TEST= 1.2 × V_ISO= 4800 V_RMS, t = 1 s

(100% production test)

V_ISO

Withstand isolation voltage

4000

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed

circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as

inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

7.7 Safety-Related Certifications

VDE

Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):

2017-01, DIN EN60950-1 (VDE 0805 Teil 1): 2014-08, and

DIN EN 60065 (VDE 0860): 2005-11

Recognized under 1577 component recognition and

CSA component acceptance NO 5 programs

Basic insulation

Single protection

Certificate number: 40047657

File number: E181974

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output (I/O) circuitry.

A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to

overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

θ_JA= 112.2°C/W, VDD1 = VDD2 = 5.5 V,

T_J= 150°C, T_A= 25°C

202.5

Safety input, output, or supply current,

see Figure 3

I_S

θ_JA= 112.2°C/W, VDD1 = VDD2 = 3.6 V,

T_J= 150°C, T_A= 25°C

309.4

Safety input, output, or total power,

see Figure 4

P_S

T_S

θ_JA= 112.2°C/W, T_J= 150°C, T_A= 25°C

1114⁽¹⁾

150

°C

Maximum safety temperature

(1) Input, output, or the sum of input and output power must not exceed this value.

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that

of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended

maximum input voltage times the current. The junction temperature is then the ambient temperature plus the

power times the junction-to-air thermal resistance.

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

7.9 Electrical Characteristics: AMC1106x

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications are

at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

V_ClippingDifferential input voltage before clipping output

V_IN= AINP – AINN

±64

FSR

Specified linear differential full-scale

Absolute common-mode input voltage⁽¹⁾

Operating common-mode input voltage

Common-mode overvoltage detection level⁽²⁾

Single-ended input capacitance

Differential input capacitance

Input bias current

V_IN= AINP – AINN

–50

–2

AVDD

(AINP + AINN) / 2 to AGND

AINN = AGND

V_CM

V_CMov

C_IN

–0.032

AVDD – 2

AVDD – 2.1

µA

kΩ

kV/µs

C_IND

I_IB

AINP = AINN = AGND, I_IB= I_IBP+ I_IBN

AINN = AGND

–97

–72

4.75

4.9

±10

–57

R_IN

Single-ended input resistance

Differential input resistance

R_IND

I_IO

Input offset current

CMTI

Common-mode transient immunity

AINP = AINN, f_IN= 0 Hz,

–99

V_{CM min}≤ V_IN≤ V_{CM max}

CMRR Common-mode rejection ratio

AINP = AINN, f_INfrom 0.1 Hz to 50 kHz,

–98

800

V_{CM min}≤ V_IN≤ V_{CM max}

DC ACCURACY

Input bandwidth⁽³⁾

kHz

DNL

Differential nonlinearity

Resolution: 16 bits

–0.99

–4

0.99

LSB

Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V

Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V

Initial, at 25°C, AINP = AINN = AGND

±1

±1.5

INL

Integral nonlinearity⁽⁴⁾

–5

E_O

Offset error

Offset error thermal drift⁽⁵⁾

–50

–1

±2.5

µV

TCE_O

E_G

±0.25

±0.005%

±20

μV/°C

Gain error

Gain error thermal drift⁽⁶⁾

Initial, at 25°C

–0.2%

–40

0.2%

TCE_G

ppm/°C

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V, at dc

–108

PSRR

Power-supply rejection ratio

AINP = AINN = AGND,

3.0 V ≤ AVDD ≤ 5.5 V,

10 kHz, 100-mV ripple

–107

AC ACCURACY

SNR

Signal-to-noise ratio

f_IN= 1 kHz

82.5

82.3

SINAD Signal-to-noise + distortion

77.5

4.5 V ≤ AVDD ≤ 5.5 V,

5 MHz ≤ f_CLKIN≤ 21 MHz, f_IN= 1 kHz

–98

–84

–83

THD

Total harmonic distortion

3.0 V ≤ AVDD ≤ 3.6 V,

5 MHz ≤ f_CLKIN≤ 20 MHz, f_IN= 1 kHz

–93

100

SFDR

Spurious-free dynamic range

f_IN= 1 kHz

(1) Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage V_CMfor normal

operation. Observe the analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.

(3) This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter

designs.

(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).

(5) Offset error drift is calculated using the box method, as described by the following equation:

value_MAX- value_MIN

TCE_O

TempRange

(6) Gain error drift is calculated using the box method, as described by the following equation:

≈ value _MAX- value _MIN

’

∆

TCE_G( ppm) =

ì10

value ìTempRange

◊

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

Electrical Characteristics: AMC1106x (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –50 mV to 50 mV, AINN = AGND, and sinc³filter with OSR = 256 (unless otherwise noted); typical specifications are

at T_A= 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS/OUTPUTS (CMOS Logic With Schmitt-Trigger)

I_IN

Input current

DGND ≤ V_CLKIN≤ DVDD

µA

C_IN

V_IH

V_IL

Input capacitance

High-level input voltage

Low-level input voltage

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

I_OH= –20 µA

I_OH= –4 mA

I_OL= 20 µA

I_OL= 4 mA

DVDD – 0.1

DVDD – 0.4

V_OH

High-level output voltage

0.1

0.4

V_OL

Low-level output voltage

Output load capacitance

C_LOAD

POWER SUPPLY

3.0 V ≤ AVDD ≤ 3.6 V

4.5 V ≤ AVDD ≤ 5.5 V

6.3

7.2

8.5

9.8

I_AVDDHigh-side supply current

AMC1106E05, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

4.1

3.3

5.0

3.9

5.5

4.8

6.9

6.0

AMC1106M05, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

I_DVDD

Controller-side supply current

AMC1106E05, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

AMC1106M05, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

7.10 Timing Requirements

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

4.5 V ≤ AVDD ≤ 5.5 V

f_CLKIN

CLKIN clock frequency

MHz

3.0 V ≤ AVDD ≤ 5.5 V

4.5 V ≤ AVDD ≤ 5.5 V

3.0 V ≤ AVDD ≤ 5.5 V

47.6

200

120

CLKIN clock period,

see Figure 1

t_CLKIN

t_HIGH

t_LOW

CLKIN clock high time, see Figure 1

CLKIN clock low time, see Figure 1

7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DOUT hold time after rising edge

of CLKIN, see Figure 1

t_H

t_D

AMC1106M05⁽¹⁾, C_LOAD= 15 pF

3.5

Rising edge of CLKIN to DOUT

valid delay, see Figure 1

AMC1106M05⁽¹⁾, C_LOAD= 15 pF

3.5

3.9

3.5

3.9

10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

0.8

1.8

0.8

1.8

t_r

DOUT rise time, see Figure 1

DOUT fall time, see Figure 1

10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,

C_LOAD= 15 pF

t_f

90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,

C_LOAD= 15 pF

Interface startup time,

see Figure 2

DVDD at 2.7 V (min) to DOUT valid with

AVDD ≥ 3.0 V

t_ISTART

t_ASTART

t_CLKIN

Analog startup time,

see Figure 2

AVDD step to 3.0 V with DVDD ≥ 2.7 V,

0.1% settling

0.5

(1) The output of the Manchester encoded versions of the AMC1106E05 can change with every edge of CLKIN with a typical delay of 6 ns;

see the Manchester Coding Feature section for additional details.

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t_CLKIN

t_HIGH

CLKIN

t_LOW

t_H

t_D

t_r/ t_f

DOUT

Figure 1. Digital Interface Timing

AVDD

DVDD

t_ASTART

CLKIN

DOUT

...

Bitream not valid

(analog settling)

Test Pattern

Valid bitstream

t_ISTART

Figure 2. Device Startup Timing

7.12 Insulation Characteristics Curves

500

1200

1100

1000

900

800

700

600

500

400

300

200

100

AVDD = DVDD = 3.6 V

AVDD = DVDD = 5.5 V

400

300

200

100

T_A(°C)

150

200

100

T_A(°C)

150

200

D001

D002

Figure 3. Thermal Derating Curve for Safety-Limiting

Current per VDE

Figure 4. Thermal Derating Curve for Safety-Limiting

Power per VDE

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7.13 Typical Characteristics

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

3.5

3.3

3.25

3.2

3.15

3.1

2.5

3.05

1.5

2.95

2.9

0.5

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D003

D004

Figure 5. Maximum Operating Common-Mode Input Voltage

vs High-Side Supply Voltage

Figure 6. Common-Mode Overvoltage Detection Level vs

Temperature

-20

-40

-60

-80

-20

-40

-60

-80

-100

-120

-0.5

0.5

1.5

2.5

3.5

0.1 0.2 0.5

3 45 7 10 2030 50 100 200 5001000

V_CM(V)

f_IN(kHz)

D005

D006

Figure 7. Input Bias Current vs

Common-Mode Input Voltage

Figure 8. Common-Mode Rejection Ratio vs

Input Signal Frequency

100

AVDD = 5 V

AVDD = 3.3 V

3.5

2.5

-25

-50

-75

-100

1.5

0.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

3.5

4.5

AVDD (V)

5.5

D008

D009

Figure 9. Integral Nonlinearity vs Temperature

Figure 10. Offset Error vs High-Side Supply Voltage

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Typical Characteristics (continued)

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

100

-20

-40

-60

-80

-100

-20

-40

-60

-80

-100

Device 1

Device 2

Device 3

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

f_CLKIN(MHz)

D010

D011

Figure 11. Offset Error vs Temperature

Figure 12. Offset Error vs Clock Frequency

0.3

0.2

0.1

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D012

D013

Figure 13. Gain Error vs High-Side Supply Voltage

Figure 14. Gain Error vs Temperature

-20

0.3

0.2

0.1

-40

-60

-80

-0.1

-0.2

-0.3

-100

-120

0.1

100

1000

f_CLKIN(MHz)

Ripple Frequency (kHz)

D014

D015

Figure 15. Gain Error vs Clock Frequency

Figure 16. Power-Supply Rejection Ratio vs

Ripple Frequency

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Typical Characteristics (continued)

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

SNR

SINAD

SNR

SINAD

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D016

D017

Figure 17. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs High-Side Supply Voltage

Figure 18. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Temperature

SNR

SINAD

SNR

SINAD

0.1

100

f_CLKIN(MHz)

f_IN(kHz)

D018

D019

Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Clock Frequency

Figure 20. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Frequency

-86

-88

-90

-92

-94

-96

-98

-100

-102

-104

-106

-108

-110

SNR

SINAD

90 100

4.5

4.75

5.25

5.5

V_IN(mVpp)

AVDD (V)

D020

D021

f_CLKIN= 21 MHz

Figure 21. Signal-to-Noise Ratio and Signal-to-Noise +

Distortion vs Input Signal Amplitude

Figure 22. Total Harmonic Distortion vs

High-Side Supply Voltage

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Typical Characteristics (continued)

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

-86

-88

-90

-92

-94

-96

-98

-100

-102

-104

-106

-108

-110

-100

-102

-104

-106

-108

-110

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D039

D022

f_CLKIN= 20 MHz

Figure 23. Total Harmonic Distortion vs

High-Side Supply Voltage

Figure 24. Total Harmonic Distortion vs Temperature

-86

-88

-85

-90

-95

-90

-92

-94

-96

-100

-105

-110

-115

-120

-98

-100

-102

-104

-106

-108

-110

0.1

f_CLKIN(MHz)

f_IN(kHz)

D023

D024

Figure 25. Total Harmonic Distortion vs Clock Frequency

Figure 26. Total Harmonic Distortion vs

Input Signal Frequency

-65

-70

118

114

110

106

102

-75

-80

-85

-90

-95

-100

-105

-110

-115

90 100

3.5

4.5

AVDD (V)

5.5

V_IN(mVpp)

D025

D026

Figure 27. Total Harmonic Distortion vs

Input Signal Amplitude

Figure 28. Spurious-Free Dynamic Range vs

High-Side Supply Voltage

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Typical Characteristics (continued)

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

118

114

110

106

102

118

114

110

106

102

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

f_CLKIN(MHz)

D027

D028

Figure 29. Spurious-Free Dynamic Range vs Temperature

Figure 30. Spurious-Free Dynamic Range vs

Clock Frequency

118

114

110

106

102

120

115

110

105

100

0.1

90 100

f_IN(kHz)

V_IN(mVpp)

D029

D030

Figure 31. Spurious-Free Dynamic Range vs

Input Signal Frequency

Figure 32. Spurious-Free Dynamic Range vs

Input Signal Amplitude

-20

-40

-60

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

Frequency (kHz)

D031

D032

4096-point FFT, V_IN= 100 mV_PP

Figure 33. Frequency Spectrum With 1-kHz Input Signal

Figure 34. Frequency Spectrum With 10-kHz Input Signal

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Typical Characteristics (continued)

at T_A= 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, f_CLKIN= 20 MHz, and sinc³filter with

OSR = 256 (unless otherwise noted)

9.5

8.5

7.5

6.5

5.5

4.5

3.5

4.5

AVDD (V)

5.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (°C)

D033

D034

Figure 35. High-Side Supply Current vs

High-Side Supply Voltage

Figure 36. High-Side Supply Current vs Temperature

9.5

AMC1106M05

AMC1106E05

7.5

8.5

6.5

7.5

5.5

6.5

4.5

5.5

3.5

4.5

2.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

f_CLKIN(MHz)

DVDD (V)

D035

D036

Figure 37. High-Side Supply Current vs Clock Frequency

Figure 38. Controller-Side Supply Current vs

Controller-Side Supply Voltage

7.5

AMC1106M05, DVDD = 3.3 V

AMC1106M05, DVDD = 5 V

AMC1106E05, DVDD = 3.3 V

AMC1106E05, DVDD = 5 V

AMC1106M05, DVDD = 3.3 V

AMC1106M05, DVDD = 5 V

AMC1106E05, DVDD = 3.3 V

AMC1106E05, DVDD = 5 V

7.5

6.5

5.5

4.5

3.5

2.5

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

f_CLKIN(MHz)

D037

D038

Figure 39. Controller-Side Supply Current vs Temperature

Figure 40. Controller-Side Supply Current vs

Clock Frequency

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8 Detailed Description

8.1 Overview

The analog input stage of the AMC1106 is a fully differential amplifier that feeds the second-order, delta-sigma

(ΔΣ) modulator that digitizes the input signal into a 1-bit output stream. The isolated data output DOUT of the

converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source

at the CLKIN pin with a frequency as specified in the Switching Characteristics table. The time average of this

serial bitstream output is proportional to the analog input voltage.

The Functional Block Diagram section shows a detailed block diagram of the AMC1106. The analog input range

is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The silicon-

dioxide (SiO₂) based capacitive isolation barrier supports a high level of magnetic field immunity as described in

the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at www.ti.com. The

external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The

extended frequency range of up to 21 MHz supports higher performance levels compared to the other solutions

available on the market.

8.2 Functional Block Diagram

AVDD

DVDD

Isolation

Barrier

AMC1106x05

AINP

AINN

ûꢀ Modulator

DOUT

CLKIN

Bandgap

Reference

V_CM, AVDD

Diagnostic

AGND

DGND

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8.3 Feature Description

8.3.1 Analog Input

The AMC1106 incorporates front-end circuitry that contains a differential amplifier and sampling stage, followed

by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 20 with

a differential input resistance of 4.9 kΩ. For reduced offset and offset drift, the differential amplifier is chopper-

stabilized with the switching frequency set at f_CLKIN/ 32. Figure 41 shows that the switching frequency generates

a spur. The impact of this spur on the overall system-level performance depends on the digital filter settings.

-20

-40

-60

-80

-100

-120

-140

-160

0.1

100

1000

10000

Frequency (kHz)

D007

sinc³filter, OSR = 2, f_CLKIN= 20 MHz, f_IN= 1 kHz

Figure 41. Quantization Noise Shaping

There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the

range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input

electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are

ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR)

and within the specified input common-mode voltage range (V_CM).

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Feature Description (continued)

8.3.2 Modulator

The modulator implemented in the AMC1106 (such as the one conceptualized in Figure 42) is a second-order,

switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage V_INand the output V₅of the 1-bit

digital-to-analog converter (DAC) are subtracted, providing an analog voltage V₁at the input of the first integrator

stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage

V₃that is subtracted from the input signal V_INand the output of the first integrator V₂. Depending on the polarity

of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC responds on the

next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in the opposite

direction and forcing the value of the integrator output to track the average value of the input.

f_CLKIN

V₁

V₂

V₃

V₄

V_IN

Integrator 1

Integrator 2

ꢀ

CMP

0 V

V₅

DAC

Figure 42. Block Diagram of a Second-Order Modulator

The modulator shifts the quantization noise to high frequencies; see Figure 41. Therefore, use a low-pass digital

filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1-

bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's

microcontroller family MSP430F67x offers a path to directly access the integrated sinc-filters of the SD24_B

ADCs for a simple system-level solution for multichannel, isolated current sensing. Also, the microcontroller

families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a

sigma-delta filter module (SDFM) optimized for usage with the AMC1106. An additional option is to use a suitable

application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a field-

programmable gate array (FPGA) can be used to implement the filter.

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Feature Description (continued)

8.3.3 Isolation Channel Signal Transmission

The AMC1106 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream

across the capacitive SiO₂-based isolation barrier. The transmitter modulates the bitstream at TX IN in Figure 43

with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and sends a

no signal to represent the digital zero. The receiver demodulates the signal after advanced signal conditioning

and produces the output. The symmetrical design of each isolation channel improves the CMTI performance and

reduces the radiated emissions caused by the high-frequency carrier. Figure 43 shows a block diagram of an

isolation channel integrated in the AMC1106.

Transmitter

Receiver

OOK

Modulation

SiO₂-Based

Capacitive

Basic

Isolation

Barrier

TX IN

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

RX OUT

Oscillator

Figure 43. Block Diagram of an Isolation Channel

Figure 44 shows the concept of the on-off keying scheme.

TX IN

Carrier Signal Across

the Isolation Barrier

RX OUT

Figure 44. OOK-Based Modulation Scheme

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Feature Description (continued)

8.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 50 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of

resolution on the decimation filter, that percentage ideally corresponds to code 58368. A differential input of –50

mV produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a

16-bit resolution decimation filter. This –50-mV to 50-mV input voltage range is also the specified linear range

FSR of the AMC1106 with performance as specified in this document. If the input voltage value exceeds this

range, the output of the modulator shows nonlinear behavior where the quantization noise increases. The output

of the modulator clips with a stream of only zeros with an input less than or equal to –64 mV or with a stream of

only ones with an input greater than or equal to 64 mV. In this case, however, the AMC1106 generates a single 1

(if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-

Safe Output section for more details). Figure 45 shows the input voltage versus the modulator output signal.

Modulator Output

+FS (Analog Input)

-FS (Analog Input)

Analog Input

Figure 45. Analog Input versus AMC1106 Modulator Output

Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception

of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):

V_IN+ V_Clipping

2ì V_Clipping

(1)

The AMC1106 system clock is provided externally at the CLKIN pin. For more details, see the Switching

Characteristics table and the Manchester Coding Feature section.

8.3.5 Manchester Coding Feature

The AMC1106E05 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one

transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc

components and supports single-wire data and clock transfer without having to consider the setup and hold time

requirements of the receiving device. The Manchester coding combines the clock and data information using

exclusive or (XOR) logical operation. Figure 46 shows the resulting bitstream. The duty cycle of the Manchester

encoded bitstream depends on the duty cycle of the input clock CLKIN.

Clock

Uncoded

Bitstream

Machester

Coded

Bitstream

Figure 46. Manchester Coded Output of the AMC1106E05

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8.4 Device Functional Modes

8.4.1 Fail-Safe Output

In the case of a missing AVDD high-side supply voltage, the output of the ΔΣ modulator is not defined and can

cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.

Therefore, as shown in Figure 47, the AMC1106 implements a fail-safe output function that ensures that the

DOUT output of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD.

Similarly, as also shown in Figure 47, if the common-mode voltage of the input reaches or exceeds the specified

common-mode overvoltage detection level V_CMovas defined in the Electrical Characteristics table, the AMC1106

generates a steady-state bitstream of logic 1's at the DOUT output.

t_ASTART

t_ISTART

CLKIN

...

AVDD

AVDD good

Missing AVDD

AVDD good

V_CM

V_CM< V_CMov

V_CM≥ V_CMov

V_CM< V_CMov

DOUT

Valid bitstream

”1‘

”0‘

Test pattern

”1‘

Bitstream not valid

Valid bitstream

Figure 47. Fail-Safe Output of the AMC1106

8.4.2 Output Behavior in Case of a Full-Scale Input

If a full-scale input signal is applied to the AMC1106 (that is, |V_IN| ≥ |V_Clipping|), Figure 48 shows that the device

generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being

sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the

system level.

CLKIN

...

DOUT

AINP - AINN ≤ -64 mV

...

AINP œ AINN ≥ 64 mV

127 t_CLKIN

Figure 48. Overrange Output of the AMC1106

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Digital Filter Usage

The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a

conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, shown in Equation 2,

built with minimal effort and hardware, is a sinc³-type filter:

-OSR

≈

’

1- z

H z =

( )

∆

1- z^-1

◊

(2)

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-

order modulator. All the characterization in this document is also done with a sinc³filter with an oversampling

ratio (OSR) of 256 and an output word width of 16 bits.

An example code for implementing a sinc³filter in an FPGA is discussed in application note Combining ADS1202

with FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at

www.ti.com.

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9.2 Typical Application

ΔΣ ADCs are widely used for current measurement in electricity meters because of the high ac accuracy

obtained over a wide dynamic range that is achieved by averaging in the digital filter. As a result of their inherent

isolation, current transformers (CT) were commonly used as current sensors in 3-phase electricity meters in the

past. A strong magnetic field can saturate a CT and stop proper energy measurement. Shunt resistors are

immune to magnetic fields and can be used to design temper-free electricity meters. The input structure of the

AMC1106 is optimized for use with low-impedance shunt resistors to minimize the power dissipation of the

circuit. The transformerless galvanic isolation of the bitstream as implemented in the AMC1106 is tailored for

shunt-based current sensing in modern 3-phase electricity meter designs.

Figure 49 shows a simplified schematic of the AMC1106 in a shunt-based, 3-phase electricity meter application.

Source

Phase C

Phase A

Isolation

Barrier

Phase B

DVDD

MSP430F67641A

AVDD1

AVDD2

AVDD3

SD24_B

Filter 1

AMC1106

SD24_B

Filter 2

AMC1106

Metrology

Calculation

Engine

SD24_B

Filter 3

System

Interface

AMC1106

Clock &

Trigger

Generator

Level-Shifted

Voltage Divider

Level-Shifted

Voltage Divider

ADC10

Module

Level-Shifted

Voltage Divider

DGND

Phase B

Phase C

Isolated

Power Supply

Generation

Phase A

Load

Figure 49. The AMC1106 in a 3-Phase Electricity Meter Application

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Typical Application (continued)

9.2.1 Design Requirements

Table 1 lists the parameters for the this typical application.

Table 1. Design Requirements

PARAMETER

AVDD1, AVDD2, and AVDD3 high-side supply voltages

DVDD low-side supply voltage

VALUE

3.3 V or 5 V

Voltage drop across the shunt for a linear response

Accuracy

±50 mV (maximum)

Class 0.5 or better

9.2.2 Detailed Design Procedure

The high-side power supply (AVDD) for the AMC1106 is externally derived from either a capacitive-drop or a

coreless transformer power-supply circuit. Further details are provided in the Power Supply Recommendations

section.

The floating ground reference (AGND) is derived from one of the ends of the shunt resistor that is connected to

the analog inputs of the AMC1106. If a four-pin shunt is used, the inputs of the device are connected to the inner

leads and AGND is connected to one of the outer shunt leads.

Use Ohm's Law to calculate the voltage drop across the shunt resistor (V_SHUNT) for the desired measured

current: V_SHUNT= I × R_SHUNT

Consider the following two restrictions to choose the proper value of the shunt resistor R_SHUNT

•

The voltage drop caused by the nominal current range must not exceed the recommended differential input

voltage range: V_SHUNT≤ ±50 mV

The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes

a clipping output: |V_SHUNT| ≤ |V_Clipping

Use an RC filter in front of the AMC1106 to improve the overall signal-to-noise performance of the system and

improve the immunity of the circuit to high-frequency electromagnetic fields.

For the AMC1106 output bitstream averaging, a poly-phase device version from TI's MSP430F67x family of low-

power microcontrollers (MCUs) is recommended. This family offers the sigma-delta module (SD24_B) that allows

for bypassing the internal modulator and directly accessing the digital filter. The integrated trigger and clock

generator support synchronization of all three AMC1106 devices and the internal 10-bit SAR ADC that is used to

deliver the voltage information of all phases.

Figure 50 shows a voltage divider circuit with a common-mode set to 1/3 of the supply voltage that is used to

adjust the mains voltage signal to the input voltage range of the SAR ADC used in the MSP430F67641A.

Phase

Neutral

DVDD

MSP430F67641A

1 Mꢀ

10-Bit

SAR

ADC

DGND

Figure 50. Level-Shifted Voltage Divider

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

For further design recommendations and system level considerations, see the Multi-Phase Power Quality

Measurement With Isolated Shunt Sensors or the Magnetically Immune Transformerless Power Supply for

Isolated Shunt Current Measurement reference designs offered by TI.

9.2.3 Application Curve

In electricity metering applications, the initial calibration of the offset, gain, and phase errors is absolutely

necessary to correctly sense the current and voltage signals, and calculate the power with the required system

level accuracy as per regional regulations. After system calibration, an electricity meter circuit based on the shunt

resistors, the AMC1106, and the MSP430F67x support error levels below ±0.2%, as shown in Figure 51 and the

documentation of the reference designs listed previously.

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.4

Current (A)

D039

Figure 51. Active Energy Error

9.2.4 Do's and Don'ts

Do not leave the inputs of the AMC1106 unconnected (floating) when the device is powered up. If both modulator

inputs are left floating, the input bias current drives these inputs to the output common-mode voltage level of the

differential amplifier of approximately 1.9 V. If that voltage is above the specified input common-mode range, the

gain of the differential amplifier diminishes and the modulator outputs a bitstream resembling a zero differential

input voltage.

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

10 Power Supply Recommendations

For lowest system-level cost, the high-side power supply (AVDD) for the AMC1106 is derived from an external

capacitive-drop power supply. The Magnetically Immune Transformerless Power Supply for Isolated Shunt

Current Measurement reference design and Figure 52 shows a proven solution based on a 6.2-V diode and the

TLV70450 5-V low dropout (LDO) regulator. A low equivalent series resistance (ESR) decoupling capacitor of 0.1

µF is recommended for filtering this power-supply path. Place this capacitor (C5 in Figure 52) as close as

possible to the AVDD pin of the AMC1106 for best performance.

The floating ground reference (AGND) is derived from the end of the shunt resistor that is also connected to the

negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads

and AGND is connected to one of the outer leads of the shunt.

For decoupling of the digital power supply on the controller side, TI recommends using a 0.1-µF capacitor (C6 in

Figure 52) assembled as close to the DVDD pin of the AMC1106 as possible, followed by an additional capacitor

in the range of 1 µF to 10 µF.

Phase

Neutral

Isolation

Barrier

470 Ω

TLV70450

AVDD

DVDD

OUT

470 nF / 400 V

GND

2200 …F

0.1 …F

2.2 …F

0.1 …F

2.2 …F

6.2 V

AMC1106

AGND

DGND

Figure 52. Capacitive-Drop Solution for the AMC1106 AVDD Supply

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

Figure 53 shows a layout recommendation example based on an on-board, 4-wire shunt resistor that details the

critical placement of the decoupling capacitors (as close as possible to the AMC1106 supply pins) and the

placement of the other components required by the device. For best performance, place the shunt resistor close

to the AINP and AINN inputs of the AMC1106 and keep the layout of both connections symmetrical.

11.2 Layout Example

Clearance area,

to be kept free of any

conductive materials.

0.1 µF

2.2 µF

0.1 µF

SMD

0603

SMD

0603

SMD

0603

SMD

0603

To Floating

Power

Supply

AVDD

AINP

DVDD

CLKIN

DOUT

DGND

SMD

R_FLT

From Clock

Source

0603

C_FLT

AMC1106x

SMD

0603

To Digital

Filter

(MCU)

SMD

R_FLT

AINN

AGND

0603

LEGEND

Copper Pour and Traces

High-Side Area

Controller-Side Area

Via to Ground Plane

Via to Supply Plane

Figure 53. Recommended Layout of the AMC1106

AMC1106E05, AMC1106M05

www.ti.com.cn

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

12.1.1.1 隔离相关术语

请参阅隔离相关术语

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

《AMC1210 适用于二阶 Δ-Σ 调制器的四路数字滤波器》

《MSP430F67x 多相位仪表计量片上系统 (SoC)》

《TMS320F2807x Piccolo™ 微控制器》

《TMS320F2837xD 双核 Delfino™ 微控制器》

《TLV704 24V 输入电压、150mA 超低 I_Q低压降稳压器》

《ISO72x 数字隔离器磁场抗扰度》

《将 ADS1202 与 FPGA 数字滤波器结合，以便在电机控制应用中进行电流测量》

《使用隔离式分流传感器进行多相电源质量测量》

《适用于隔离式分流电流测量的抗磁干扰无变压器电源》

12.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。

表 2. 相关链接

部件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

AMC1106E05

AMC1106M05

12.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

AMC1106E05, AMC1106M05

ZHCSH11A –OCTOBER 2017–REVISED JUNE 2018

www.ti.com.cn

12.6 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.8 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

AMC1106E05DWV

AMC1106E05DWVR

AMC1106M05DWV

AMC1106M05DWVR

ACTIVE

SOIC

DWV

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-40 to 125

1106E05

1000 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

NIPDAU

1106E05

1106M05

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

6-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AMC1106E05DWVR

AMC1106M05DWVR

SOIC

DWV

1000

330.0

16.4

12.05 6.15

3.3

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AMC1106E05DWVR

AMC1106M05DWVR

SOIC

DWV

1000

350.0

43.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

6-May-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

AMC1106E05DWV

AMC1106M05DWV

DWV

SOIC

505.46

13.94

4826

6.6

Pack Materials-Page 3

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AMC1106M05DWV [TI]

相关型号：

AMC1106M05DWVR

AMC1112

AMC1112KF

AMC1112SJ

AMC1112SJF

AMC1112SK

AMC1117

AMC1117-1.5

AMC1117-1.8

AMC1117-2.5

AMC1117-3.3

AMC1117-5.0