AMC1211AQDWVRQ1 [TI]
2V 输入、精密电压检测基本隔离式放大器
| DWV | 8 | -40 to 125;
| 型号： | AMC1211AQDWVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2V 输入、精密电压检测基本隔离式放大器 | DWV | 8 | -40 to 125 放大器 分离技术 隔离技术 光电二极管 |
| 文件： | 总35页 (文件大小：1803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC1211-Q1
ZHCSHJ0C –JUNE 2018 –REVISED NOVEMBER 2022
AMC1211-Q1 汽车类高阻抗2V 输入基础型隔离放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 功能安全型
AMC1211-Q1 是一款隔离式精密放大器，此放大器的
输出与输入电路由抗电磁干扰性能极强的电容隔离层隔
开。该隔离栅经认证可提供高达 3kVRMS 的基本电隔
离，符合 DIN EN IEC 60747-17 (VDE 0884-17) 和
UL1577 标准，并且可支持高达 1000VRMS 的工作电
压。
– 可提供用于功能安全系统设计的文档
• 针对隔离式电压测量优化了2V 高阻抗输入电压范
围
• 固定增益：1
• 低直流误差：
该隔离层可将系统中以不同共模电压电平运行的各器件
隔开，防止高电压冲击导致低压侧器件电气损坏或对操
作员造成伤害。
– 失调电压误差：±1.5mV（最大值）
– 温漂±10μV/°C（最大值）
– 增益误差：±0.2%（最大值）
– 增益漂移：±40ppm/°C（最大值）
– 非线性度：0.04%（最大值）
• 高侧3.3V 工作电压
AMC1211-Q1 的高阻抗输入针对与高阻抗电阻分压器
或任何其他高阻抗电压信号源的连接进行了优化。出色
的直流精度和低温漂支持在闭环系统中进行精确的隔离
式电压检测和控制。集成的高侧电源电压缺失检测功能
可简化系统级设计和诊断。
• 高CMTI：30 kV/µs（最小值）
• 高侧电源缺失指示
• 安全相关认证：
AMC1211-Q1 采用宽体 8 引脚 SOIC 封装，符合面向
汽车应用的 AEC-Q100 标准，并支持 –40°C 至
+125°C 的温度范围。
– 符合DIN EN IEC 60747-17 (VDE 0884-17) 的
4250VPK 基础型隔离
封装信息(1)
– 符合UL1577 标准且长达1 分钟的3000VRMS
隔离
封装尺寸（标称值）
器件型号
封装
AMC1211-Q1
DWV (SOIC, 8)
5.85mm × 7.50mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 可用于以下应用的隔离式电压感应：
– 牵引逆变器
– 车载充电器
– 直流/直流转换器
VDC
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
R1
AMC1211-Q1
VDD1
IN
VDD2
OUTP
R2
0..2V
RSNS
VCMout
2 V
ADC
SHTDN
GND1
OUTN
GND2
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS896
AMC1211-Q1
ZHCSHJ0C –JUNE 2018 –REVISED NOVEMBER 2022
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Table of Contents
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
8.3 Best Design Practices...............................................24
8.4 Power Supply Recommendations.............................24
8.5 Layout....................................................................... 25
9 Device and Documentation Support............................26
9.1 Documentation Support............................................ 26
9.2 接收文档更新通知..................................................... 26
9.3 支持资源....................................................................26
9.4 Trademarks...............................................................26
9.5 Electrostatic Discharge Caution................................26
9.6 术语表....................................................................... 26
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics........................................10
6.11 Timing Diagram.......................................................10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................12
7 Detailed Description......................................................18
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (June 2022) to Revision C (November 2022)
Page
• 将特性部分中的CMTI 额定值从100kV/μs（最小值）更正为30kV/μs（最小值） ....................................... 1
• Added specified ambient temperature range to Recommended Operating Conditions table.............................4
• Corrected Rise, Fall, and Delay Time Definition timing diagram...................................................................... 10
Changes from Revision A (June 2020) to Revision B (June 2022)
Page
• 将隔离标准从DIN VDE V 0884-11 (VDE V 0884-11) 更改为DIN EN IEC 60747-17 (VDE 0884-17)，并相应更
新了绝缘规格和安全相关认证表....................................................................................................................... 1
• 将器件名称从AMC1211A-Q1 更改为AMC1211-Q1（不影响可订购器件型号）............................................... 1
• 更改了特性部分..................................................................................................................................................1
• Changed pin names: VIN to IN, VOUTP to OUTP, and VOUTN to OUTN......................................................... 3
• Merged VOS specs for 4.5V ≤VDD1 ≤5.5 V and 3.0 V ≤VDD1 ≤5.5 V ranges..........................................8
• Changed VDD1 DC PSRR from –65 dB (typical) to –80 dB (typical)..............................................................8
• Changed VDD1UV (VDD1 falling) from 1.75 V / 2.53 V / 2.7 V to 2.4 V / 2.6 V / 2.8 V (minimum / typical /
maximum)...........................................................................................................................................................8
• Changed Rise, Fall, and Delay Time Definition timing diagram....................................................................... 10
• Changed Isolation Capacitor Lifetime Projection figure ...................................................................................11
• Changed functional block diagram................................................................................................................... 18
• Deleted Failsafe Output section, added Analog Output section....................................................................... 20
• Changed Typical Application section and subsections.....................................................................................21
• Changed What To Do and What Not To Do section......................................................................................... 24
• Changed Layout section...................................................................................................................................25
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5 Pin Configuration and Functions
VDD1
IN
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
SHTDN
GND1
Not to scale
图5-1. DWV Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
2
3
4
5
6
7
8
VDD1
IN
High-side power
Analog input
High-side power supply(1)
Analog input
SHTDN
GND1
GND2
OUTN
OUTP
VDD2
Digital input
Shutdown input, active high, with internal pullup resistor (typical value: 100 kΩ)
High-side analog ground
High-side ground
Low-side ground
Analog output
Analog output
Low-side power
Low-side analog ground
Inverting analog output
Noninverting analog output
Low-side power supply(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
High-side VDD1 to GND1
6.5
6.5
Power-supply voltage
Input voltage
V
Low-side VDD2 to GND2
–0.3
IN
VDD1 + 0.5
VDD1 + 0.5
VDD2 + 0.5
10
GND1 –6
GND1 –0.5
GND2 –0.5
–10
V
SHTDN
Output voltage
Input current
OUTP, OUTN
V
Continuous, any pin except power-supply pins
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1), HBM ESD classification Level 2
Charged-device model (CDM), per AEC Q100-011, CDM ESD classification Level C6
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
Low-side power supply
ANALOG INPUT
VDD1 to GND1
VDD2 to GND2
3
3
5
5.5
5.5
V
V
3.3
VClipping
VFSR
Input voltage before clipping output
Specified linear full-scale voltage
IN to GND1
IN to GND1
2.516
V
V
2
–0.1
ANALOG OUTPUT
CLOAD Capacitive load
Resistive load
On OUTP or OUTN to GND2
OUTP to OUTN
500
250
1
pF
RLOAD
DIGITAL INPUT
Input voltage
TEMPERATURE RANGE
TA Specified ambient temperature
On OUTP or OUTN to GND2
10
kΩ
SHTDN to GND1
0
VDD1
125
V
°C
–40
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6.4 Thermal Information
DWV (SOIC)
UNIT
THERMAL METRIC(1)
8 PINS
RθJA
Junction-to-ambient thermal resistance
84.6
28.3
41.1
4.9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ΨJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
39.1
n/a
ΨJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD1 = VDD2 = 5.5 V
VALUE
98
UNIT
PD
Maximum power dissipation (both sides)
mW
VDD1 = VDD2 = 3.6V
VDD1 = 5.5 V
56
53
PD1
Maximum power dissipation (high-side)
Maximum power dissipation (low-side)
mW
mW
VDD1 = 3.6 V
30
VDD2 = 5.5 V
45
PD2
VDD2 = 3.6 V
26
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UNIT
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Distance through insulation
Comparative tracking index
Material group
Shortest pin-to-pin distance through air
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the insulation
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
mm
mm
µm
V
≥8.5
≥8.5
≥21
≥600
I
CPG
DTI
CTI
I-IV
Rated mains voltage ≤150 VRMS
Overvoltage category
per IEC 60664-1
I-III
Rated mains voltage ≤300 VRMS
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM
At AC voltage
1400
VPK
isolation voltage
At AC voltage (sine wave)
At DC voltage
1000
1400
VRMS
VDC
Maximum-rated isolation
VIOWM
working voltage
Maximum transient
VIOTM
VTEST = VIOTM, t = 60 s (qualification test),
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
4250
6000
7800
VPK
VPK
VPK
isolation voltage
VIMP
Maximum impulse voltage(3)
Tested in air, 1.2/50-µs waveform per IEC 62368-1
Maximum surge
Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1
VIOSM
isolation voltage(4)
Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
≤5
≤5
~1.5
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.3 × VIORM, tm = 10 s
qpd
Apparent charge(5)
pC
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1 s, Vpd(m) = 1.5 × VIORM, tm = 1 s
Method b2, at routine test (100% production)(7)
Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1 s
,
Barrier capacitance,
input to output(6)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(6)
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO, t = 60 s (qualification test),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
VISO
Withstand isolation voltage
3000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.
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6.7 Safety-Related Certifications
VDE
UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
Recognized under 1577 component recognition and
DIN EN 61010-1 (VDE 0411-1) Clause : 6.4.3 ; 6.7.1.3 ; 6.7.2.1 ;
6.7.2.2 ; 6.7.3.4.2 ; 6.8.3.1
CSA component acceptance NO 5 programs
Basic insulation
Single protection
Certificate number: 40047657
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-
heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 84.6°C/W, VDDx = 5.5 V,
268
TJ = 150°C, TA = 25°C
θJA = 84.6°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 84.6°C/W, TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
mA
R
410
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1477
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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MAX UNIT
6.9 Electrical Characteristics
typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
ANALOG INPUT
VOS
TCVOS
RIN
Input offset voltage(1) (2)
Input offset thermal drift(1) (2) (5)
Input resistance
TA = 25°C(3)
±0.4
±3
1
1.5
mV
–1.5
–10
10 µV/°C
TA = 25℃
GΩ
IIB
Input bias current
3.5
7
15
nA
pF
IN = GND1, TA = 25℃
fIN = 275 kHz
–15
CIN
Input capacitance
ANALOG OUTPUT
Nominal gain
1
±0.05%
±5
V/V
EG
Gain error(1)
0.2%
TA = 25℃
–0.2%
–40
TCEG
Gain error drift(1) (6)
Nonlineartity(1)
40 ppm/°C
0.04%
±0.01%
–0.04%
VIN = 2 VPP, VIN > 0 V,
fIN = 10 kHz, BW = 10 kHz
THD
SNR
Total harmonic distortion(4)
dB
–87
VIN = 2 VPP, fIN = 1 kHz, BW = 10 kHz
VIN = 2 VPP, fIN = 10 kHz, BW = 100 kHz
VIN = GND1, BW = 100 kHz
vs VDD1, at DC
79
82.6
70.9
220
Signal-to-noise ratio
Output noise
dB
µVrms
–80
–85
–65
–70
1.44
vs VDD2, at DC
PSRR
Power-supply rejection ratio(2)
dB
vs VDD1, 10 kHz / 100-mV ripple
vs VDD2, 10 kHz / 100-mV ripple
VCMout
Output common-mode voltage
1.39
220
30
1.49
V
V
VOUT = (VOUTP –VOUTN);
VIN > VClipping
VCLIPout
Clipping differential output voltage
2.49
SHTDN = high, or VDD1 undervoltage,
or VDD1 missing
VFAILSAFE Failsafe differential output voltage
V
–2.6
–2.5
BW
Output bandwidth
Output resistance
275
kHz
ROUT
On OUTP or OUTN
<0.2
Ω
On OUTP or OUTN, sourcing or sinking,
IN = GND1, outputs shorted to
either GND or VDD2
Output short-circuit current
14
45
mA
CMTI
Common-mode transient immunity
kV/µs
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6.9 Electrical Characteristics (continued)
typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIGITAL INPUT
IIN
Input current
1
µA
pF
SHTDN pin, GND1 ≤SHTDN ≤VDD1
–70
CIN
Input capacitance
SHTDN pin
5
0.7 ×
VDD1
VIH
VIL
High-level input voltage
V
V
0.3 ×
VDD1
Low-level input voltage
POWER SUPPLY
VDD1 rising
2.5
2.4
2.7
2.6
2.45
2.0
6.0
7.1
1.3
5.3
5.9
2.9
2.8
VDD1 undervoltage detection
threshold
VDD1UV
VDD2UV
V
V
VDD1 falling
VDD2 rising
2.2
2.65
2.2
VDD2 undervoltage detection
threshold
VDD2 falling
1.85
3.0 V < VDD1 < 3.6 V, SHTDN = low
4.5 V < VDD1 < 5.5 V, SHTDN = low
SHTDN = VDD1
8.4
mA
µA
IDD1
High-side supply current
Low-side supply current
9.7
3.0 V < VDD2 < 3.6 V
4.5 V < VDD2 < 5.5 V
7.2
8.1
IDD2
mA
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) The typical value is at VDD1 = 3.3 V.
(4) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
(5) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(6) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
Output signal rise time
Output signal fall time
TEST CONDITIONS
MIN
TYP
1.3
MAX
UNIT
µs
tr
tf
1.3
µs
VDD1 step to 3.0 V with VDD2 ≥3.0 V,
to VOUTP, VOUTN valid, 0.1% settling
tAS
Analog settling time
50
100
µs
tEN
Device enable time
SHTDN high to low
SHTDN low to high
50
3
100
10
µs
µs
tSHTDN
Device shutdown time
6.11 Timing Diagram
2 V
IN
0 V
tr
tf
OUTP
OUTN
VCMout
50% - 10%
50% - 50%
50% - 90%
图6-1. Rise, Fall, and Delay Time Definition
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6.12 Insulation Characteristics Curves
500
1600
1400
1200
1000
800
600
400
200
0
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
400
300
200
100
0
0
50
100
TA (°C)
150
200
0
50
100
TA (èC)
150
200
D001
D002
图6-2. Thermal Derating Curve for Safety-Limiting 图6-3. Thermal Derating Curve for Safety-Limiting
Current per VDE
Power per VDE
1E+11
1E+10
1E+9
1E+8
1E+7
1E+6
1E+5
1E+4
1E+3
1E+2
1E+1
Safety Margin Zone: 1200 VRMS, 40 Years
Operating Zone: 1000 VRMS, 31 Years
30%
20%
500
1500
2500
3500
4500
Stress Voltage (VRMS
5500
)
6500
7500
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1000 VRMS, operating lifetime = 31 years
图6-4. Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
2.5
2
1.5
vs VDD1
vs VDD2
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
Device 1
Device 2
Device 3
-1.5
-2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D006
D005
VDD1 = 5 V
图6-6. Input Offset Voltage vs Temperature
图6-5. Input Offset Voltage vs Supply Voltage
2.5
2
14
12
10
8
Device 1
Device 2
Device 3
1.5
1
0.5
0
6
-0.5
-1
4
-1.5
-2
2
-2.5
-40 -25 -10
0
100
5
20 35 50 65 80 95 110 125
Temperature (°C)
1000
fIN (kHz)
10000
D007
D009
VDD1 = 3.3 V
图6-7. Input Offset Voltage vs Temperature
图6-8. Input Capacitance vs Input Signal Frequency
15
12
9
15
12
9
6
6
3
3
0
0
-3
-6
-9
-12
-15
-3
-6
-9
-12
-15
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD1 (V)
5
5.25 5.5
D011
D010
图6-10. Input Bias Current vs Temperature
图6-9. Input Bias Current vs High-Side Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
0.3
0.2
0.1
0
Device 1
Device 2
Device 3
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
VDD1
VDD2
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D014
D016
图6-11. Gain Error vs Supply Voltage
图6-12. Gain Error vs Temperature
5
0
50
0
-5
-50
-10
-15
-20
-25
-30
-35
-40
-100
-150
-200
-250
-300
-350
-400
1
10
100
1000
0.01
0.1
1
10
100
1000
fIN (kHz)
fIN (kHz)
D04034
D044
图6-13. Normalized Gain vs Input Frequency
图6-14. Output Phase vs Input Frequency
0.04
0.03
0.02
0.01
0
5
4.5
4
VOUTP
VOUTN
3.5
3
2.5
2
-0.01
-0.02
-0.03
-0.04
1.5
1
0.5
0
-0.2
0
0.2 0.4 0.6 0.8 1
VIN (V)
1.2 1.4 1.6 1.8
2
-0.1
0.3
0.7
1.1
1.5
1.9
2.3
2.7
D020
VIN (V)
D018
图6-16. Nonlinearity vs Input Voltage
图6-15. Output Voltage vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
0.04
0.03
0.02
0.01
0
0.04
0.03
0.02
0.01
0
vs VDD1
vs VDD2
-0.01
-0.02
-0.03
-0.04
-0.01
-0.02
-0.03
-0.04
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D022
D021
图6-18. Nonlinearity vs Temperature
图6-17. Nonlinearity vs Supply Voltage
-70
-75
-70
-75
vs VDD1
vs VDD2
-80
-80
-85
-85
-90
-90
Device 1
Device 2
Device 3
-95
-95
-100
-100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D024
D023
图6-20. Total Harmonic Distortion vs Temperature
图6-19. Total Harmonic Distortion vs Supply Voltage
1000
72.5
70
67.5
65
100
10
1
62.5
60
57.5
55
52.5
50
47.5
45
0.1
42.5
0.1
1
10
Frequency (kHz)
100
1000
0
0.2 0.4 0.6 0.8
1
VIN (V)
1.2 1.4 1.6 1.8
2
D025
D026
图6-21. Input-Referred Noise Density vs Frequency
图6-22. Signal-to-Noise Ratio vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
80
77.5
75
80
77.5
75
vs VDD1
vs VDD2
72.5
70
72.5
70
67.5
65
67.5
65
Device 1
Device 2
Device 3
62.5
60
62.5
60
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D028
D027
图6-24. Signal-to-Noise Ratio vs Temperature
图6-23. Signal-to-Noise Ratio vs Supply Voltage
0
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
-20
-40
-60
-80
-100
-120
VDD1
VDD2
1.39
0.1
1
10
Ripple Frequency (kHz)
100
1000
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
D029
D031
100-mV ripple
图6-25. Power-Supply Rejection Ratio vs Ripple Frequency
图6-26. Output Common-Mode Voltage vs Low-Side Supply
Voltage
300
290
280
270
260
250
240
230
220
210
200
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
1.39
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D033
D032
图6-28. Output Bandwidth vs Low-Side Supply Voltage
图6-27. Output Common-Mode Voltage vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
300
290
280
270
260
250
240
230
220
210
200
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
IDD1 vs VDD1
IDD2 vs VDD2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDDx (V)
5
5.25 5.5
D034
D035
图6-29. Output Bandwidth vs Temperature
图6-30. Supply Current vs Supply Voltage
8.5
8
4
3.5
3
7.5
7
2.5
2
6.5
6
5.5
5
1.5
1
4.5
4
IDD1
IDD2
0.5
0
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
D036
D037
图6-31. Supply Current vs Temperature
图6-32. Output Rise and Fall Time vs Low-Side Supply Voltage
4
3.5
3
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
1
2.5
2
1.5
1
0.5
0
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.25 3.5 3.75
4
4.25 4.5 4.75
VDD2 (V)
5
5.25 5.5
D038
D040
图6-33. Output Rise and Fall Time vs Temperature
图6-34. IN to OUTP, OUTN Signal Delay vs Low-Side Supply
Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D042
图6-35. IN to OUTP, OUTN Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1211-Q1 is a precision, single-ended input, isolated amplifier with a high input impedance and wide
input voltage range. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The
modulator converts the analog input signal into a digital bitstream that is transferred across the isolation barrier
and separates the high-side from the low-side. On the low-side, the received bitstream is processed by a fourth-
order analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application note. The digital modulation used in the AMC1211-
Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics, result in high reliability
and high common-mode transient immunity.
7.2 Functional Block Diagram
VDD1
VDD2
OUTP
OUTN
GND2
AMC1211-Q1
Analog Filter
IN
ΔΣ Modulator
SHTDN
GND1
7.3 Feature Description
7.3.1 Analog Input
The single-ended, high-impedance input stage of the AMC1211-Q1 feeds a second-order, switched-capacitor,
feed-forward ΔΣmodulator. The modulator converts the analog signal into a bitstream that is transferred across
the isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signal IN. First, if the input voltage VIN exceeds the range specified
in the Absolute Maximum Ratings table, the input current must be limited to the absolute maximum value
because the electrostatic discharge (ESD) protection turns on. Secondly, the linearity and parametric
performance of the device is ensured only when the analog input voltage remains within the linear full-scale
range (VFSR) as specified in the Recommended Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC1211-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to
represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1211-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the
input to the fourth-order analog filter. The AMC1211-Q1 transmission channel is optimized to achieve the highest
level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-
frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC1211-Q1 provides a differential analog output on the OUTP and OUTN pins. For input voltages of VIN in
the range from –0.1 V to +2 V, the device provides a linear response with a nominal gain of 1. For example, for
an input voltage of 2 V, the differential output voltage (VOUTP – VOUTN) is 2 V. At zero input (IN shorted to
GND1), both pins output the same common-mode output voltage VCMout, as specified in the Electrical
Characteristics table. For input voltages greater than 2 V but less than approximately 2.5 V, the differential
output voltage continues to increase but with reduced linearity performance. The outputs saturate at a differential
output voltage of VCLIPout, as shown in 图7-2, if the input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VFAILSAFE
VOUTN
VCLIPout
VOUTP
VCMout
0
2.516 V
Input Voltage (VIN
)
2 V
图7-2. Output Behavior of the AMC1211-Q1
The AMC1211-Q1 output offers a fail-safe feature that simplifies diagnostics on a system level. 图 7-2 shows the
fail-safe mode, in which the AMC1211-Q1 outputs a negative differential output voltage that does not occur
under normal operating conditions. The fail-safe output is active in three cases:
• When the high-side supply VDD1 of the AMC1211-Q1 device is missing
• When the high-side supply VDD1 falls below the undervoltage threshold VDD1UV
• When the SHTDN pin is pulled high
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for fail-
safe detection on a system level.
7.4 Device Functional Modes
The AMC1211-Q1 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The high input impedance, low input bias current, low AC and DC errors, and low temperature drift make the
AMC1211-Q1 a high-performance solution for automotive applications where voltage sensing in the presence of
high common-mode voltage levels is required.
8.2 Typical Application
图 8-1 shows an OBC that uses the AMC1211-Q1 to monitor the DC bus voltage that can be as high as 600 V.
The DC bus voltage is divided down to an approximate 2-V level across the bottom resistor (RSNS) of a high-
impedance resistive divider that is sensed by the AMC1211-Q1. The output of the AMC1211-Q1 is a differential
analog output voltage of the same value as the input voltage but is galvanically isolated from the high-side by a
basic isolation barrier.
The isolation barrier and high common-mode transient immunity (CMTI) of the AMC1211-Q1 ensure reliable and
accurate operation in harsh and high-noise environments.
+ DC-Bus
DC-Link
Number of unit resistors depends
on design requirements.
See design examples for details.
DC/DC
EMI
Filter
PFC
Contactor
SW
RX1
RX2
L1
L2
L3
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
SW
SW
100 nF 1 uF
AMC1211-Q1
VDD1
VDD2
ICROSS
RSNS
IN
OUTP
OUTN
GND2
ADC
SHTDN
GND1
SW
N
1 uF 100 nF 100 pF
N
DC-Bus
图8-1. Using the AMC1211-Q1 for DC Bus Voltage Sensing in an OBC
8.2.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
VALUE
600 V (maximum)
3.3 V or 5 V
3.3 V or 5 V
100 V
DC bus voltage
High-side supply voltage
Low-side supply voltage
Maximum resistor operating voltage
Voltage drop across the sense resistor (RSNS) for a linear response
Current through the resistive divider, ICROSS
2 V (maximum)
100 μA
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8.2.2 Detailed Design Procedure
The 100-μA, cross-current requirement at the maximum DC bus voltage (600 V) determines that the total
impedance of the resistive divider is 6 MΩ. The impedance of the resistive divider is dominated by the top
portion (shown exemplary as RX1 and RX2 in 图 8-1) and the voltage drop across RSNS can be neglected for a
moment. The maximum allowed voltage drop per unit resistor is specified as 100 V; therefore, the minimum
number of unit resistors in the top portion of the resistive divider is 600 V / 100 V = 6. The calculated unit value is
6 MΩ/ 6 = 1 MΩand matches a value from the E96 series.
RSNS is sized such that the voltage drop across the resistor at the maximum DC-bus voltage (600 V) equals the
linear full-scale range input voltage (VFSR) of the AMC1211-Q1, which is 2 V. The value of RSNS is calculated as
RSNS = VFSR / (VDC-Bus, max –VFSR) × RTOP, where RTOP is the total value of the top resistor string (6 × 1 MΩ=
6 MΩ). RSNS is calculated as 20.07 kΩ. The next closest, lower value from the E96 series is 20 kΩ.
表8-2 summarizes the design of the resistive divider.
表8-2. Resistor Value Example
PARAMETER
VALUE
1 MΩ
Unit resistor value, RX
Number of unit resistors
Sense resistor value, RSNS
Total resistance value
6
20 kΩ
6.02 MΩ
99.7 μA
1.993 V
9.9 mW
59.8 mW
Resulting current through resistive divider, ICROSS
Resulting full-scale voltage drop across sense resistor RSNS
Power dissipated in unit resistor RX
Total power dissipated in resistive divider
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8.2.2.1 Input Filter Design
Placing an RC filter in front of the isolated amplifier improves signal-to-noise performance of the signal path. In
practice, however, the impedance of the resistor divider is high and only a small-value filter capacitor can be
used to not limit the signal bandwidth to an unacceptable low value. Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the internal ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In this case, a single capacitor (as shown in 图8-2) is sufficient to filter the input signal.
VDC
R1
AMC1211-Q1
R2
VDD1
VDD2
OUTP
OUTN
GND2
100 pF
IN
RSNS
SHTDN
GND1
图8-2. Input Filter
8.2.2.2 Differential to Single-Ended Output Conversion
图 8-3 shows an example of a TLV900x-Q1-based signal conversion and filter circuit for systems using single-
ended input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ
and C1 = C2 = 330 pF yields good performance.
C1
AMC1211-Q1
R2
VDD1
VDD2
OUTP
OUTN
GND2
R1
R3
IN
–
+
ADC
To MCU
SHTDN
GND1
TLV9001-Q1
C2
R4
VREF
图8-3. Connecting the AMC1211-Q1 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the
18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
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8.2.3 Application Curve
One important aspect of system design is the effective detection of an overvoltage condition to protect switching
devices and passive components from damage. To power off the system quickly in the event of an overvoltage
condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale step
response of the AMC1211-Q1.
VOUTP
VOUTN
VIN
图8-4. Step Response of the AMC1211-Q1
8.3 Best Design Practices
Do not leave the analog input (IN pin) of the AMC1211-Q1 unconnected (floating) when the device is powered up
on the high-side. If the device input is left floating, the bias current may generate a negative input voltage that
exceeds the specified input voltage range, causing the output of the device to be invalid.
Do not connect protection diodes to the input (IN pin) of the AMC1211-Q1. Diode leakage current can introduce
significant measurement error especially at high temperatures. The input pin is protected against high voltages
by the ESD protection circuit and the high impedance of the external restive divider.
8.4 Power Supply Recommendations
In a typical application, the high-side (VDD1) of the AMC1211-Q1 is powered from an already existing, high-side,
ground-referenced, 3.3-V or 5-V power supply in the system. Alternatively, the high-side supply can be
generated from the low-side supply (VDD2) by an isolated DC/DC converter. A low-cost solution is based on the
push-pull driver SN6501-Q1 and a transformer that supports the desired isolation voltage ratings.
The AMC1211-Q1 does not require any specific power-up sequencing. The high-side power supply (VDD1) is
decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side
power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. 图 8-5 shows
the proper decoupling layout for the AMC1211-Q1.
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VDC
VDD1
VDD2
R1
C2 1 µF
C4 1 µF
AMC1211-Q1
C1 100 nF
C3 100 nF
R2
VDD1
VDD2
OUTP
OUTN
GND2
IN
to RC filter / ADC
to RC filter / ADC
C5 100 pF
RSNS
SHTDN
GND1
图8-5. Decoupling of the AMC1211-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
8.5 Layout
8.5.1 Layout Guidelines
图 8-6 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1211-Q1 supply pins) and placement of the other components required by the device. For
best performance, place the sense resistor close to the device input pin (IN).
8.5.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C4
C3
C2
C1
to RC filter / ADC
to RC filter / ADC
OUTP
OUTN
GND2
INP
AMC1211-Q1
Top Metal
Inner or Bottom Layer Metal
Via
图8-6. Recommended Layout of the AMC1211-Q1
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application note
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application note
• Texas Instruments, TLV900x-Q1 Low-Power, RRIO, 1-MHz Automotive Operational Amplifier data sheet
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, AMC1311EVM Users Guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1211AQDWVQ1
AMC1211AQDWVRQ1
ACTIVE
ACTIVE
SOIC
SOIC
DWV
DWV
8
8
64
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
1211AQ1
1211AQ1
Samples
Samples
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1211AQDWVRQ1
SOIC
DWV
8
1000
330.0
16.4
12.15
6.2
3.05
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DWV
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
AMC1211AQDWVRQ1
8
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DWV SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
AMC1211AQDWVQ1
8
64
505.46
13.94
4826
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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