AMC1351-Q1 [TI]
汽车类 0-5V 输入、精密电压检测增强型隔离式放大器;
| 型号： | AMC1351-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 0-5V 输入、精密电压检测增强型隔离式放大器 放大器 |
| 文件： | 总34页 (文件大小：1951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC1351-Q1
ZHCSNE9 – DECEMBER 2021
具有 5V 输入电压的 AMC1351-Q1 汽车精密增强型隔离放大器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准：
– 温度等级 1：–40°C 至 +125°C，TA
提供功能安全
AMC1351-Q1 是一款隔离式精密放大器，此放大器的
输出与输入电路由抗电磁干扰性能极强的隔离栅隔开。
该隔离栅经认证可提供高达 5kVRMS 的增强型电隔离，
符合 VDE V 0884-11 和 UL1577 标准，并且可支持最
高 1.5kVRMS 的工作电压。
•
– 可帮助进行功能安全系统设计的文档
线性输入电压范围：-0.25 V 至 5 V
高输入阻抗：1.25mΩ（典型值）
固定增益：0.4 V/V
•
•
•
•
该隔离栅可将系统中以不同共模电压电平运行的各器件
隔开，并保护低压侧免受可能有害的电压冲击。
低直流误差：
AMC1351-Q1 的高阻抗输入针对与高阻抗电阻分压
器或具有高输出电阻的其他电压信号源的连接进行了优
化。具有出色的精度和低温漂，可支持精确的直流电压
检测，适用于直流/直流转换器、变频器、电机驱动或
其他必须支持高共模电压的应用。
– 失调电压误差 ±1.5mV（最大值）
– 温漂：±15µV/°C（最大值）
– 增益误差：±0.2%（最大值）
– 增益漂移：±35ppm/°C（最大值）
– 非线性 ±0.02%（最大值）
高侧和低侧运行电压：3.3V 或 5V
高 CMTI：100kV/µs（最小值）
失效防护输出
•
•
•
•
AMC1351-Q1 采用宽体 8 引脚 SOIC 封装，符合面
向汽车应用的 AEC-Q100 标准，并支持 –40°C 至
+125°C 的温度范围。
安全相关认证：
器件信息(1)
– 7070-VPK 增强型隔离，符合 DIN VDE V
器件型号
封装
封装尺寸（标称值）
0884-11：2017-01
AMC1351-Q1
SOIC (8)
5.85mm × 7.50mm
– 符合 UL1577 标准且长达 1 分钟的 5000VRMS
隔离
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
可用于以下应用的隔离式电压感应：
– 牵引逆变器
– 车载充电器
– 直流/直流转换器
– 混合动力汽车/电动汽车直流充电器
VDC
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
R1
AMC1351-Q1
VDD1
IN
VDD2
OUTP
R2
0..5V
RSNS
VCMout
2 V
ADC
GND1
GND1
OUTN
GND2
典型应用
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAB4
AMC1351-Q1
ZHCSNE9 – DECEMBER 2021
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics.............................................8
6.10 Switching Characteristics........................................10
6.11 Timing Diagram.......................................................10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................12
7 Detailed Description......................................................19
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
8.3 What To Do and What Not To Do..............................25
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Documentation Support.......................................... 28
11.2 接收文档更新通知................................................... 28
11.3 支持资源..................................................................28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 术语表..................................................................... 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
December 2021
REVISION
NOTES
*
Initial Release
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5 Pin Configuration and Functions
VDD1
IN
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
GND1
GND1
Not to scale
图 5-1. DWV Package, 8-Pin SOIC (Top View)
表 5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
2
VDD1
IN
High-side power
Analog input
High-side power supply(1)
Analog input
High-side analog ground reference for input amplifier. Connect to pin 4. Do not leave
unconnected.
3
GND1
High-side ground
4
5
6
7
8
GND1
GND2
OUTN
OUTP
VDD2
High-side ground
Low-side ground
Analog output
High-side analog ground
Low-side analog ground
Inverting analog output
Noninverting analog output
Low-side power supply(1)
Analog output
Low-side power
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
High-side VDD1 to GND1
6.5
Power-supply voltage
V
Low-side VDD2 to GND2
–0.3
6.5
Analog input voltage
Analog output voltage
Input current
IN
–1
15
VDD2 + 0.5
10
V
V
OUTP, OUTN
GND2 – 0.5
–10
Continuous, any pin except power-supply pins
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
,
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011,
CDM ESD classification level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD1
VDD2
High-side power-supply
Low-side power-supply
VDD1 to GND1
VDD2 to GND2
3
3
5
5.5
5.5
V
V
3.3
ANALOG INPUT
VClipping Input voltage before clipping output
VFSR Specified linear full-scale voltage
ANALOG OUTPUT
6.25
V
V
–0.25
5
On OUTP or OUTN to GND2
OUTP to OUTN
500
250
1
CLOAD
Capacitive load
pF
kΩ
RLOAD
TEMPERATURE RANGE
TA Specified ambient temperature
Resistive load
On OUTP or OUTN to GND2
10
–40
125
°C
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6.4 Thermal Information
AMC1351-Q1
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
84.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
28.3
RθJB
ψJT
Junction-to-board thermal resistance
41.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.9
ψJB
39.1
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VALUE
96
UNIT
PD
Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5 V
mW
VDD1 = 3.6 V
Maximum power dissipation (high-side)
VDD1 = 5.5 V
29
PD1
mW
mW
51
VDD2 = 3.6 V
Maximum power dissipation (low-side)
VDD2 = 5.5 V
26
PD2
45
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UNIT
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
≥ 8.5
≥ 8.5
mm
mm
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double
insulation
DTI
CTI
Distance through insulation
≥ 0.021
mm
V
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 600
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage category
per IEC 60664-1
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01
Maximum repetitive peak
isolation voltage
VIORM
At AC voltage
2120
VPK
At AC voltage (sine wave)
1500
2120
7070
8480
VRMS
VDC
Maximum-rated isolation
working voltage
VIOWM
At DC voltage
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
isolation voltage
VIOTM
VPK
VPK
Maximum surge
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
VIOSM
8000
≤ 5
isolation voltage(2)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤ 5
qpd
Apparent charge(3)
pC
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875
× VIORM, tm = 1 s
≤ 5
Barrier capacitance,
input to output(4)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
~1.5
pF
Ω
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(4)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):
2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition
Reinforced insulation
Single protection
Certificate number: pending
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
over-heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 84.6°C/W, VDDx = 5.5 V,
TJ = 150°C, TA = 25°C
270
IS
Safety input, output, or supply current
mA
RθJA = 84.6°C/W, VDDx = 3.6 V,
TJ = 150°C, TA = 25°C
410
PS
TS
Safety input, output, or total power
Maximum safety temperature
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C
1480
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, IN =
–0.25 V to +5 V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT
TA = 25°C, IN = GND1,
–1.5
–2.5
±0.3
–0.8
1.5
mV
2.5
4.5 V ≤ VDD1 ≤ 5.5 V(1)
VOS
Offset voltage(2)
TA = 25°C, IN = GND1,
3.0 V ≤ VDD1 ≤ 5.5 V(3)
ΔVOS
Offset voltage long-term stability
Offset voltage thermal drift(5)
10 years at TA = 55℃
0(7)
±3
mV
TCVOS
IN = GND1
–15
1
15 µV/°C
Offset voltage thermal drift
long-term stability
10 years at TA = 55℃,
IN = GND1
ΔTCVOS
0(7)
mV/°C
RIN
Input resistance
1.25
0(7)
5
1.5
MΩ
ppm
ΔRIN
TCRIN
CIN
Input resistance long-term stability 10 years at TA = 55℃
Input resistance thermal drift
Input capacitance
–40℃ ≤ TA ≤ 85℃
ppm/°C
pF
fIN = 275 kHz
4
ANALOG OUTPUT
Nominal gain
0.40
±0.05%
0(7)
V/V
EG
Gain error(1)
TA = 25℃
–0.2%
–35
0.2%
ΔEG
TCEG
Gain error long-term stability
Gain error thermal drift(1) (6)
10 years at TA = 55℃
±10
35 ppm/°C
ppm/°C
Gain error thermal drift
long-term stability
ΔTCEG
10 years at TA = 55℃
0(7)
Nonlineartity(1)
–0.02%
±0.003%
0.2
0.02%
Nonlinearity thermal drift
ppm/°C
dB
VIN = 5 VPP, fIN = 10 kHz,
BW = 100 kHz
THD
SNR
Total harmonic distortion(4)
–82
79
VIN = 5 VPP, fIN = 1 kHz,
BW = 10 kHz
75
Signal-to-noise ratio
Output noise
dB
VIN = 5 VPP, fIN = 10 kHz,
BW = 100 kHz
69
IN = GND1, BW = 100 kHz
PSRR vs VDD1, DC
250
–67
–80
µVrms
PSRR vs VDD2, DC
Power-supply rejection ratio(2)
dB
PSRR vs VDD1 with 10-kHz,
100-mV ripple
PSRR
–65
PSRR vs VDD2 with 10-kHz,
100-mV ripple
–64
1.44
2.49
VCMout
Output common-mode voltage
1.39
275
1.49
–2.5
V
V
VOUT = (VOUTP – VOUTN),
VIN > VClipping
VCLIPout
Clipping differential output voltage
VFail-safe
BW
Fail-safe differential output voltage VDD1 undervoltage or VDD1 missing
Output bandwidth
–2.57
300
V
kHz
Ω
ROUT
Output resistance
On OUTP or OUTN
< 0.2
On OUTP or OUTN, sourcing or sinking,
IN = GND1, outputs shorted to
either GND or VDD2
Output short-circuit current
14
mA
CMTI
Common-mode transient immunity
100
150
kV/µs
POWER SUPPLY
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, IN =
–0.25 V to +5 V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
2.7
2.6
2.45
2.0
6.0
7.0
5.3
5.9
MAX UNIT
VDD1 rising
2.5
2.9
V
2.8
VDD1 undervoltage detection
threshold
VDD1UV
VDD2UV
IDD1
VDD1 falling
2.4
VDD2 rising
2.2
2.65
V
2.2
VDD2 undervoltage detection
threshold
VDD2 falling
1.85
3.0 V < VDD1 < 3.6 V
4.5 V < VDD1 < 5.5 V
3.0 V < VDD2 < 3.6 V
4.5 V < VDD2 < 5.5 V
8.1
mA
9.3
High-side supply current
Low-side supply current
7.2
mA
8.1
IDD2
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) The typical value is at VDD1 = 3.3 V.
(4) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(5) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (VOS,MAX - VOS,MIN) / TempRange where VOS,MAX and VOS,MIN refer to the maximum and minimum VOS values measured
within the temperature range (–40 to 125℃).
(6) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %)
measured within the temperature range (–40 to 125℃).
(7) Value is below measurement capability.
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
1.3
1
MAX
UNIT
µs
tr
tf
Output signal rise time
Output signal fall time
µs
IN to OUTx signal delay (50% – 10%)
IN to OUTx signal delay (50% – 50%)
IN to OUTx signal delay (50% – 90%)
Unfiltered output
Unfiltered output
Unfiltered output
1.5
2.1
3
µs
1.6
2.5
µs
µs
VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to
VOUTP and VOUTN valid, 0.1% settling
tAS
Analog settling time
500
800
µs
6.11 Timing Diagram
5 V
IN
2.5 V
0 V
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90%
图 6-1. Rise, Fall, and Delay Time Definition
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6.12 Insulation Characteristics Curves
600
1800
1600
1400
1200
1000
800
600
400
200
0
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
500
400
300
200
100
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
D070
D069
图 6-3. Thermal Derating Curve for Safety-Limiting Power per
图 6-2. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1500 VRMS, operating lifetime = 135 years
图 6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
0.1
TA = -40 C
0.08
TA = 25 C
TA = 125 C
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
-1
0
1
2
3
4
5
6
7
VIN (V)
D074
Total uncalibrated output error is defined as:
(VOUT – VIN × G) / (VClipping × G), where G is the nominal gain
of the device (0.4 V/V) and VClipping is 6.25 V
图 6-6. Total Uncalibrated Output Error vs Input Voltage
图 6-5. Output Voltage vs Input Voltage
2.5
2
2.5
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-2.5
3
3.5
4
4.5
VDD1 (V)
5
5.5
3
3.5
4
4.5
VDD2 (V)
5
5.5
D027
D027b
图 6-7. Input Offset Voltage vs High-Side Supply Voltage
图 6-8. Input Offset Voltage vs Low-Side Supply Voltage
2.5
1.25
Device 1
Device 2
2
Device 3
1.24
1.23
1.22
1.21
1.2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
D073
D026
图 6-10. Input Impedance vs Temperature
图 6-9. Input Offset Voltage vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
0.3
0.2
0.1
0
0.3
0.2
0.1
0
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
3
3.5
4
4.5
VDD1 (V)
5
5.5
3
3.5
4
4.5
VDD2 (V)
5
5.5
D020
D020b
图 6-11. Gain Error vs High-Side Supply Voltage
图 6-12. Gain Error vs Low-Side Supply Voltage
0.02
0.3
0.2
0.1
0
Device 1
Device 2
Device 3
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.1
-0.2
-0.3
-1
0
1
2
3
4
5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
D028
Temperature (°C)
D021
图 6-14. Nonlinearity vs Input Voltage
图 6-13. Gain Error vs Temperature
0.02
0.02
0.015
0.01
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
0.015
0.01
0.005
0
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.005
-0.01
-0.015
-0.02
3
3.5
4
4.5
VDD1 (V)
5
5.5
3
3.5
4
4.5
VDD2 (V)
5
5.5
D029
D029b
图 6-15. Nonlinearity vs High-Side Supply Voltage
图 6-16. Nonlinearity vs Low-Side Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
-60
-65
-70
-75
-80
-85
-90
-95
-100
Device 1
Device 2
Device 3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VIN (V)
D049
图 6-17. Nonlinearity vs Temperature
图 6-18. Total Harmonic Distortion vs Input Voltage
-60
-65
-70
-75
-80
-85
-90
-95
-100
-60
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
-65
-70
-75
-80
-85
-90
-95
-100
3
3.5
4
4.5
VDD1 (V)
5
5.5
3
3.5
4
4.5
VDD2 (V)
5
5.5
D056
D056b
图 6-19. Total Harmonic Distortion vs High-Side Supply Voltage 图 6-20. Total Harmonic Distortion vs Low-Side Supply Voltage
-60
-65
-70
-75
-80
-85
-90
-95
-100
80
75
70
65
60
55
50
45
40
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Temperature (°C)
D059
VIN (V)
D032
图 6-21. Total Harmonic Distortion vs Temperature
图 6-22. Signal-to-Noise Ratio vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
75
74
73
72
71
70
69
68
67
66
65
75
74
73
72
71
70
69
68
67
66
65
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
3
3.5
4
4.5
VDD1 (V)
5
5.5
3
3.5
4
4.5
VDD2 (V)
5
5.5
D034
D034b
图 6-23. Signal-to-Noise Ratio vs High-Side Supply Voltage
图 6-24. Signal-to-Noise Ratio vs Low-Side Supply Voltage
75
1000
Device 1
Device 2
74
Device 3
73
100
10
1
72
71
70
69
68
67
66
65
0.1
0.1
1
10
100
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Frequency (kHz)
D017
Temperature (°C)
D035
图 6-26. Input-Referred Noise Density vs Frequency
图 6-25. Signal-to-Noise Ratio vs Temperature
-66
-68
-70
-72
-74
-76
0
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
-20
-40
-60
-80
-100
0.01
0.1
1
10
100
1000
3
3.5
4
4.5
VDD1 (V)
5
5.5
fIN (kHz)
D038
D037
图 6-28. Common-Mode Rejection Ratio vs Input Frequency
图 6-27. Common-Mode Rejection Ratio vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
-66
-68
-70
-72
-74
-76
0
Device 1
Device 2
Device 3
-20
-40
-60
-80
VDD1
VDD2
-100
0.01
0.1
1
10
100
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ripple Frequency (kHz)
Temperature (°C)
D041
D039
fIN = 10 kHz
图 6-30. Power-Supply Rejection Ratio vs Ripple Frequency
图 6-29. Common-Mode Rejection Ratio vs Temperature
0
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
VDD1
VDD2
-20
-40
-60
-80
-100
1.39
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.5
4
4.5
VDD2 (V)
5
5.5
Temperature (°C)
D042
D009
fRipple = 10 kHz
图 6-31. Power-Supply Rejection Ratio vs Temperature
图 6-32. Common-Mode Output Voltage vs Supply Voltage
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
5
0
-5
-10
-15
-20
-25
-30
-35
-40
1.39
-40 -25 -10
5
20 35 50 65 80 95 110 125
1
10
100
1000
Temperature (°C)
fIN (kHz)
D010
D007
图 6-33. Common-Mode Output Voltage vs Temperature
图 6-34. Normalized Gain vs Input Frequency
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
0°
-45°
320
310
300
290
280
Device 1
Device 2
Device 3
-90°
-135°
-180°
-225°
-270°
-315°
-360°
1
10
100
1000
3
3.5
4
4.5
VDD1 (V)
5
5.5
fIN (kHz)
D008
D011
图 6-35. Output Phase vs Input Frequency
Device 1
图 6-36. Bandwidth vs Supply Voltage
320
310
300
290
280
8
7.5
7
Device 2
Device 3
6.5
6
5.5
5
4.5
4
IDD1 vs VDD1
IDD2 vs VDD2
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.5
4
4.5
VDDx (V)
5
5.5
Temperature (°C)
D012
D043
图 6-37. Bandwidth vs Temperature
图 6-38. Supply Current vs Supply Voltage
8
7.5
7
3
2.5
2
6.5
6
1.5
1
5.5
5
0.5
0
4.5
4
IDD1
IDD2
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.5
4
4.5
VDD2 (V)
5
5.5
Temperature (°C)
D044
D065
图 6-39. Supply Current vs Temperature
图 6-40. Output Rise and Fall Time vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, IN = 0 V to 5 V, and fIN = 10 kHz (unless otherwise noted)
3
2.5
2
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
1.5
1
0.5
0
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.5
4
4.5
VDD2 (V)
5
5.5
Temperature (°C)
D066
D067
图 6-41. Output Rise and Fall Time vs Temperature
图 6-42. Input to Output Signal Delay vs Supply Voltage
3.8
3.4
3
50% - 90%
50% - 50%
50% - 10%
2.6
2.2
1.8
1.4
1
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D068
图 6-43. Input to Output Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1351-Q1 is a single-ended input, precision, isolated amplifier with a high input-impedance and wide
input-voltage range. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The
modulator converts the analog input signal into a digital bitstream that is transferred across the isolation barrier
that separates the high-side from the low-side. On the low-side, the received bitstream is processed by a
fourth-order analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input
signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described
in the ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the
AMC1351-Q1 to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in
high reliability and common-mode transient immunity.
7.2 Functional Block Diagram
VDD1
INP
VDD2
OUTP
OUTN
GND2
Diagnostics
Modulator
Analog Filter
GND1
GND1
AMC1351-Q1
7.3 Feature Description
7.3.1 Analog Input
The single-ended, high-impedance input stage of the AMC1351-Q1 feeds a second-order, switched-capacitor,
feed-forward ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred across
the isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signal IN. First, if the input voltage VIN exceeds the range
specified in the Absolute Maximum Ratings table, the input current must be limited to the absolute maximum
value because the electrostatic discharge (ESD) protection turns on. In addition, the linearity and parametric
performance of the device is ensured only when the analog input voltage remains within the linear full-scale
range (VFSR) as specified in the Recommended Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC1351-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the
Functional Block Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier
to represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC1351-Q1 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides
the input to the fourth-order analog filter. The AMC1351-Q1 transmission channel is optimized to achieve the
highest level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the
high-frequency carrier and RX, TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图 7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC1351-Q1 provides a differential analog output on the OUTP and OUTN pins. For input voltages (VIN)
in the range from –0.25 V to 5 V, the device provides a linear response with a nominal gain of 0.4 V/V. For
example, for an input voltage of 5 V, the differential output voltage (VOUTP – VOUTN) is 2 V. At zero input (IN
shorted to GND1), both pins output the same common-mode output voltage VCMout, as specified in the Electrical
Characteristics table. For input voltages greater than 5 V but less than approximately 6.25 V, the differential
output voltage continues to increase but with reduced linearity performance. The outputs saturate at a differential
output voltage of VCLIPout, as shown in 图 7-2, if the input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VFail-safe
VOUTN
VCLIPout
VOUTP
VCMout
0
6.25 V
Input Voltage (VIN
)
5 V
图 7-2. Output Behavior of the AMC1351-Q1
The AMC1351-Q1 output offers a fail-safe feature that simplifies diagnostics on a system level. 图 7-2 shows the
behavior in fail-safe mode, in which the AMC1351-Q1 outputs a negative differential output voltage that does not
occur under normal operating conditions. The fail-safe output is active:
•
•
When the high-side supply VDD1 of the AMC1351-Q1 device is missing
When the high-side supply VDD1 falls below the undervoltage threshold VDD1UV
Use the maximum VFail-safe voltage specified in the Electrical Characteristics table as a reference value for
fail-safe detection on a system level.
7.4 Device Functional Modes
The AMC1351-Q1 is operational when the power supplies VDD1 and VDD2 are applied as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The high input impedance, low input bias current, excellent accuracy, and low temperature drift make the
AMC1351-Q1 a high-performance solution for automotive applications where voltage sensing in the presence of
high common-mode voltage levels is required.
8.2 Typical Application
Isolated amplifiers are widely used for voltage measurements in high-voltage applications that must be isolated
from a low-voltage domain. A typical application is the sensing of the DC bus voltage in a frequency inverter.
With its wide, 5-V input voltage range, the AMC1351-Q1 is designed for isolated DC voltage-sensing
applications where accurate voltage monitoring is required in high-noise environments.
图 8-1 shows a simplified schematic of the AMC1351-Q1 in a typical motor drive application. The DC bus voltage
is divided down to an approximate 5-V level across the bottom resistor (RSNS) of a high-impedance resistor
divider that is sensed by the AMC1351-Q1. The AMC1351-Q1 digitizes the analog input signal on the high-side,
transfers the data across the isolation barrier to the low-side, and reconstructs an analog signal that is presented
as a differential voltage on the output pins.
The high-impedance input and the high common-mode transient immunity (CMTI) of the AMC1351-Q1 ensure
reliable and accurate operation even in high-noise environments.
+ DC Link
Number of unit resistors depends
on design requirements.
See design examples for details.
R1
LS Gate Driver Supply
Low-side supply
(3.3 V or 5 V)
M
3~
R2
100 nF 1 uF
AMC1351-Q1
VDD1
VDD2
OUTP
OUTN
GND2
IN
ADC
GND1
GND1
1 uF 100 nF
RSNS
DC Link
图 8-1. Using the AMC1351-Q1 for DC Link Voltage Sensing in Frequency Inverters
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8.2.1 Design Requirements
表 8-1 lists the parameters for this typical application.
表 8-1. Design Requirements
PARAMETER
190-VDC LINE VOLTAGE
120 VRMS ±10%, 60 Hz
190 V
360-VDC LINE VOLTAGE
230 VRMS ±10%, 50 Hz
360 V
System input voltage
DC bus voltage (max)
High-side supply voltage
Low-side supply voltage
3.3 V or 5 V
3.3 V or 5 V
3.3 V or 5 V
3.3 V or 5 V
Maximum resistor operating voltage
75 V
75 V
Voltage drop across the sense resistor (RSNS) for a linear response
5 V (maximum)
100 μA
5 V (maximum)
100 μA
Current through the resistive divider (ICROSS
)
8.2.2 Detailed Design Procedure
This discussion covers the 360-VDC example. The procedure for calculating the resistive divider for the 190-VDC
use case is identical.
The 100-μA, cross-current requirement at peak input voltage (360 V) determines that the total impedance of
the resistive divider is 3.6 MΩ. The impedance of the resistive divider is dominated by the top resistors (shown
exemplary as R1 and R2 in 图 8-1) and the voltage drop across RSNS can be neglected for a short time. The
maximum allowed voltage drop per unit resistor is specified as 75 V; therefore, the total minimum number of unit
resistors in the top portion of the resistive divider is 360 V / 75 V = 5. The calculated unit value is 3.6 MΩ / 5 =
720 kΩ and the next closest value from the E96 series is 715 kΩ.
The effective sense resistor value RSNSEFF is the parallel combination of the external resistor RSNS and the
input impedance of the AMC1351-Q1, RIN. RSNSEFF is sized such that the voltage drop across the impedance at
maximum input voltage (360 V) equals the linear full-scale input voltage (VFSR) of the AMC1351-Q1 (that is, 5 V).
RSNSEFF is calculated as RSNSEFF = VFSR / (VPeak – VFSR) × RTOP, where RTOP is the total value of top resistor
string (5 × 715 kΩ = 3575 kΩ). The resulting value for RSNSEFF is 9.96 kΩ. In a final step, RSNS is calculated as
RSNS = RIN × RSNSEFF / (RIN – RSNSEFF). With RIN = 1.25 MΩ (typical), RSNS equals 52.47 kΩ and the next
closest value from the E96 series is 52.3 kΩ.
表 8-2 summarizes the design of the resistive divider.
表 8-2. Resistor Value Examples
PARAMETER
190-VDC LINE VOLTAGE
360-VDC LINE VOLTAGE
Unit resistor value (RTOP
)
634 kΩ
3
715 kΩ
5
Number of unit resistors in RTOP
Sense resistor value (RSNS)
51.1 kΩ
1953.1 kΩ
97.3 μA
4.971 V
6 mW
49.9 kΩ
3624.9 kΩ
99.3 μA
4.956 V
7.1 mW
35.8 mW
Total resistance value (RTOP + RSNS)
Resulting current through resistive divider (ICROSS
)
Resulting full-scale voltage drop across sense resistor RSNS
Peak power dissipated in RTOP unit resistors
Total peak power dissipated in resistive divider
18.5 mW
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8.2.2.1 Input Filter Design
Placing an RC filter in front of the isolated amplifier improves signal-to-noise performance of the signal path. In
practice, however, the impedance of the resistor divider is so high that adding a filter capacitor on the IN pin
limits the signal bandwidth to an unacceptable low limit, such that the filter capacitor is omitted. When used,
design the input filter such that:
•
•
The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the internal ΔΣ modulator
The input bias current does not generate significant voltage drop across the DC impedance of the input filter
Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In that case, no additional resistor is needed and a single capacitor (as shown in 图 8-2)
is sufficient to filter the input signal.
VDC
R1
AMC1351-Q1
R2
VDD1
VDD2
OUTP
OUTN
GND2
1 nF
IN
RSNS
GND1
GND1
图 8-2. Input Filter
8.2.2.2 Differential to Single-Ended Output Conversion
图 8-3 shows an example of a TLVx313-Q1-based signal conversion and filter circuit for systems using single-
ended input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage
equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ
and C1 = C2 = 330 pF yields good performance.
C1
AMC1351-Q1
R2
VDD1
VDD2
OUTP
OUTN
GND2
R1
R3
IN
–
+
ADC
To MCU
GND1
GND1
TLV313-Q1
C2
R4
VREF
图 8-3. Connecting the AMC1351-Q1 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
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8.2.3 Application Curve
One important aspect of system design is the effective detection of an overvoltage condition to protect switching
devices and passive components from damage. To power off the system quickly in the event of an overvoltage
condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale step
response of the AMC1351-Q1.
VOUTP
VOUTN
VIN
图 8-4. Step Response of the AMC1351-Q1
8.3 What To Do and What Not To Do
Do not leave the analog input (IN) of the AMC1351-Q1 unconnected (floating) when the device is powered up on
the high-side. If the device input is left floating, the bias current may generate a positive or negative input voltage
and the output of the device is undetermined.
Do not connect protection diodes to the input (IN) of the AMC1351-Q1. Diode leakage current can introduce
significant measurement error especially at high temperatures. The input pin is protected against high voltages
by its ESD protection circuit and the high impedance of the external restive divider
Connect both GND1 pins to the high-side ground potential. Do not leave one of the GND1 pins unconnected.
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9 Power Supply Recommendations
In a typical application, the high-side power supply (VDD1) for the AMC1351-Q1 is generated either from a
gate-driver supply on the high-side (as shown in 图 8-1), or from the low-side supply (VDD2) by an isolated
DC/DC converter. A low-cost solution is based on the push-pull driver SN6501 and a transformer that supports
the desired isolation voltage ratings.
The AMC1351-Q1 does not require any specific power-up sequencing. The high-side power supply (VDD1)
is decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side
power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible.
VDC
VDD1
VDD2
R1
R2
C2 1 µF
C4 1 µF
AMC1351-Q1
C1 100 nF
C3 100 nF
VDD1
VDD2
OUTP
OUTN
GND2
IN
to RC filter / ADC
to RC filter / ADC
RSNS
GND1
GND1
图 9-1. Decoupling of the AMC1351-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
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10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1351-Q1 supply pins) and placement of the other components required by the device. For
best performance, place the sense resistor close to the device input pin (IN).
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
C2
C1
C4
C3
to RC filter / ADC
to RC filter / ADC
IN
OUTP
OUTN
GND2
AMC1351-Q1
Top Metal
Inner or Bottom Layer Metal
Via
图 10-1. Recommended Layout of the AMC1351-Q1
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
•
•
Texas Instruments, Isolation Glossary application report
Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
Texas Instruments, TLVx313-Q1 Low-Power, Rail-to-Rail In/Out, 750-μV Typical Offset, 1-MHz Operational
Amplifier for Cost-Sensitive Systems data sheet
•
•
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
•
•
Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
Texas Instruments, Best in Class Radiated Emissions EMI Performance with the AMC1300B-Q1 Isolated
Amplifier technical white paper
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1351QDWVRQ1
ACTIVE
SOIC
DWV
8
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
AMC1351Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC1351-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2022
Catalog : AMC1351
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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