AMC1411DWLR [TI]
具有高 CMTI 的 2V 输入、精密电压检测增强型隔离式放大器
| DWL | 8 | -40 to 125;型号: | AMC1411DWLR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有高 CMTI 的 2V 输入、精密电压检测增强型隔离式放大器 | DWL | 8 | -40 to 125 放大器 |
文件: | 总32页 (文件大小:1608K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AMC1411
ZHCSN86A –MAY 2021 –REVISED SEPTEMBER 2021
采用15mm 扩展型SOIC 封装的
AMC1411 高阻抗2V 输入增强型隔离放大器
1 特性
3 说明
• 优化了2V 高阻抗输入电压范围,可实现隔离式电
压测量
• 固定增益:1.0 V/V
• 低直流误差:
AMC1411 是一款隔离式精密放大器,此放大器的输出
与输入电路由抗电磁干扰性能极强的电容隔离层隔开。
该隔离层经认证可提供高达 7.5kVRMS 的增强型电隔
离,符合 VDE V 0884-11 和 UL1577 标准,并且可支
持最高1600VRMS 的工作电压。
– 失调电压误差±1.5mV(最大值)
– 温漂:±10µV/°C(最大值)
– 增益误差:±0.2%(最大值)
– 增益漂移:±30ppm/°C(最大值)
– 非线性0.04%(最大值)
该隔离层可将系统中以不同共模电压电平运行的各器件
隔开,防止高电压冲击导致低压侧器件电气损坏或对操
作员造成伤害。
AMC1411 的高阻抗输入针对与高阻抗电阻分压器或其
他高阻抗电压信号源的连接进行了优化。出色的直流精
度和低温漂移支持精确的电压检测,适用于直流/直流
转换器、太阳能或风力涡轮机逆变器、交流电机驱动器
或其他必须在高电压、高海拔或高度污染环境下运行的
应用。
• 高侧和低侧以3.3V 或5V 电压运行
• 高侧电源缺失检测功能
• 高CMTI:100kV/µs(最小值)
• ≥15.7mm 爬电距离,扩展型SOIC 封装
• 增强隔离型:
– 10600-VPK 增强型隔离,符合DIN VDE V
AMC1411 的工业工作温度范围为 –40°C 至
+125°C,支持低至-55°C 的工作温度。
0884-11:2017-01
– 符合UL1577 标准且长达1 分钟的7500VRMS
隔离
器件信息(1)
• 可在工业级工作温度范围内正常工作:–40°C 至
封装尺寸(标称值)
器件型号
AMC1411
封装
SOIC (8)
+125°C
6.4 mm × 14.0 mm
2 应用
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 可用于以下应用的隔离式电压感应:
– 电机驱动器
– 变频器
– 光伏逆变器
– 风力涡轮机逆变器
– 铁路运输系统
VDC
High-Side Supply
(3.3 V or 5 V)
Low-Side Supply
(3.3 V or 5 V)
R1
AMC1411
VDD1
VDD2
OUTP
R2
IN
0..2 V
RSNS
VCMout
2 V
ADC
SHTDN
GND1
OUTN
GND2
典型应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBASAA7
AMC1411
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ZHCSN86A –MAY 2021 –REVISED SEPTEMBER 2021
Table of Contents
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
8.3 What To Do and What Not To Do..............................25
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 Electrostatic Discharge Caution..............................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .......................................10
6.11 Timing Diagram.......................................................10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................12
7 Detailed Description......................................................18
7.1 Overview...................................................................18
Information.................................................................... 27
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2021) to Revision A (September 2021)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
VDD1
IN
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
SHTDN
GND1
Not to scale
图5-1. DWL Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions
PIN
NAME
TYPE
DESCRIPTION
NO.
1
2
3
4
5
6
7
8
VDD1
INP
High-side power
Analog input
High-side power supply(1)
Analog input
SHTDN
GND1
GND2
OUTN
OUTP
VDD2
Digital input
Shutdown input, active high, with internal pullup resistor (typical value: 100 kΩ)
High-side analog ground
High-side ground
Low-side ground
Analog output
Analog output
Low-side power
Low-side analog ground
Inverting analog output
Noninverting analog output
Low-side power supply(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
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6 Specifications
6.1 Absolute Maximum Ratings
see(1)
MIN
–0.3
MAX
UNIT
High-side VDD1 to GND1
6.5
6.5
Power-supply voltage
Input voltage
V
Low-side VDD2 to GND2
–0.3
IN
VDD1 + 0.5
VDD1 + 0.5
VDD2 + 0.5
10
GND1 –6
GND1 –0.5
GND2 –0.5
–10
V
SHTDN
Output voltage
Input current
OUTP, OUTN
V
Continuous, any pin except power-supply pins
mA
Junction, TJ
Storage, Tstg
150
Temperature
°C
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
High-side power supply
Low-side power supply
ANALOG INPUT
VDD1 to GND1
VDD2 to GND2
3
3
5
5.5
5.5
V
V
3.3
VClipping
VFSR
DIGITAL INPUT
Input voltage
TEMPERATURE RANGE
Operating ambient temperature
Input voltage before clipping output
IN to GND1
IN to GND1
2.516
V
V
Specified linear full-scale voltage
2
–0.1
SHTDN to GND1
0
VDD1
V
125
125
–55
–40
TA
°C
Specified ambient temperature
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6.4 Thermal Information
AMC1411
THERMAL METRIC(1)
DWL (SOIC)
8 PINS
63.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
26.1
RθJB
ψJT
Junction-to-board thermal resistance
28.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
7.8
26.8
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD1 = VDD2 = 3.6 V
VALUE
56
UNIT
PD
Maximum power dissipation (both sides)
mW
VDD1 = VDD2 = 5.5 V
VDD1 = 3.6 V
98
30
PD1
Maximum power dissipation (high-side)
Maximum power dissipation (low-side)
mW
mW
VDD1 = 5.5 V
53
VDD2 = 3.6 V
26
PD2
VDD2 = 5.5 V
45
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UNIT
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6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Distance through insulation
Comparative tracking index
Material group
Shortest pin-to-pin distance through air
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double insulation
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
mm
mm
mm
V
≥14.7
≥15.7
≥0.021
≥600
I
CPG
DTI
CTI
I-IV
Rated mains voltage ≤600 VRMS
Overvoltage category
per IEC 60664-1
I-III
Rated mains voltage ≤1000 VRMS
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01
Maximum repetitive peak isolation
voltage
VIORM
At AC voltage
2260
VPK
At AC voltage (sine wave)
1600
2260
VRMS
VDC
Maximum-rated isolation
working voltage
VIOWM
At DC voltage
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
10600
12720
Maximum transient
VIOTM
VPK
VPK
isolation voltage
Maximum surge
VIOSM
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
≤5
≤5
≤5
~1.5
isolation voltage(2)
Method a, after input/output safety test subgroups 2 and 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(3)
pC
Method b1, at routine test (100% production) and preconditioning (type
test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(4)
CIO
VIO = 0.5 VPP at 1 MHz
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(4)
RIO
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 7500 VRMS or 10600 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 9000 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
7500
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: pending
File number: E181974
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-
heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 63.2°C/W, VDDx = 3.6 V,
550
TJ = 150°C, TA = 25°C
θJA = 63.2°C/W, VDDx = 5.5 V,
TJ = 150°C, TA = 25°C
θJA = 63.2°C/W, TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
mA
R
360
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1980
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.
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6.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VIN
= –0.1 V to 2 V, and SHTDN = GND1 = 0 V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V,
and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT
VOS
TCVOS
RIN
Input offset voltage
Input offset thermal drift(1) (2) (4)
Input resistance
TA = 25°C(1) (2)
±0.1
±3
1
1.5
mV
–1.5
–10
10 µV/°C
TA = 25℃
GΩ
IIB
Input bias current
3.5
7
15
nA
pF
IN = GND1, TA = 25℃
fIN = 275 kHz
–15
CIN
Input capacitance
ANALOG OUTPUT
Nominal gain
1
±0.05
±5
V/V
%
EG
Gain error(1)
0.2
TA = 25℃
–0.2
–30
TCEG
Gain error drift(1) (5)
Nonlineartity(1)
30 ppm/°C
0.04%
±0.01%
–0.04%
VIN = 2 VPP, VIN > 0 V,
fIN = 10 kHz, BW = 10 kHz
THD
SNR
Total harmonic distortion(3)
dB
–87
VIN = 2 VPP, fIN = 1 kHz, BW = 10 kHz
VIN = 2 VPP, fIN = 10 kHz, BW = 100 kHz
VIN = GND1, BW = 100 kHz
vs VDD1, at DC
79
82.6
70.9
220
Signal-to-noise ratio
Output noise
dB
µVrms
–80
–85
–65
–70
1.44
vs VDD2, at DC
PSRR
Power-supply rejection ratio(2)
dB
vs VDD1, 10 kHz / 100-mV ripple
vs VDD2, 10 kHz / 100-mV ripple
VCMout
Output common-mode voltage
1.39
220
1.49
V
V
VOUT = (VOUTP –VOUTN);
VIN > VClipping
VCLIPout
Clipping differential output voltage
2.49
SHTDN = high, or VDD1 undervoltage,
or VDD1 missing
VFAILSAFE Failsafe differential output voltage
V
–2.6
–2.5
BW
Output bandwidth
Output resistance
275
kHz
ROUT
On OUTP or OUTN
<0.2
Ω
On OUTP or OUTN, sourcing or sinking,
IN = GND1, outputs shorted to
either GND or VDD2
Output short-circuit current
14
mA
CMTI
Common-mode transient immunity
100
150
kV/µs
DIGITAL INPUT
IIN
Input current
1
µA
pF
SHTDN pin, GND1 ≤SHTDN ≤VDD1
–70
CIN
Input capacitance
SHTDN pin
5
0.7 ×
VDD1
VIH
VIL
High-level input voltage
V
V
0.3 ×
VDD1
Low-level input voltage
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6.9 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VIN
= –0.1 V to 2 V, and SHTDN = GND1 = 0 V (unless otherwise noted); typical specifications are at TA = 25°C, VDD1 = 5 V,
and VDD2 = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
VDD1 rising
2.5
2.4
2.7
2.6
2.45
2.0
6.0
7.1
1.3
5.3
5.9
2.9
V
VDD1 undervoltage detection
threshold
VDD1UV
VDD2UV
VDD1 falling
2.8
VDD2 rising
2.2
2.65
V
2.2
VDD2 undervoltage detection
threshold
VDD2 falling
1.85
3.0 V < VDD1 < 3.6 V
4.5 V < VDD1 < 5.5 V, SHTDN = low
SHTDN = VDD1
8.4
mA
9.7
IDD1
High-side supply current
Low-side supply current
µA
3.0 V < VDD2 < 3.6 V
4.5 V < VDD2 < 5.5 V
7.2
mA
8.1
IDD2
(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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6.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.3
1.3
1
MAX
UNIT
µs
tr
tf
Output signal rise time
Output signal fall time
µs
Unfiltered output
Unfiltered output
Unfiltered output
1.5
2.1
3
µs
IN to OUTx signal delay (50% –10%)
IN to OUTx signal delay (50% –50%)
IN to OUTx signal delay (50% –90%)
1.6
2.5
µs
µs
VDD1 step to 3.0 V with VDD2 ≥3.0 V,
to VOUTP, VOUTN valid, 0.1% settling
tAS
Analog settling time
50
100
µs
tEN
Device enable time
SHTDN high to low
SHTDN low to high
50
3
100
10
µs
µs
tSHTDN
Device shutdown time
6.11 Timing Diagram
2 V
IN
0 V
tf
tr
OUTN
OUTP
VCMout
50% - 10%
50% - 50%
50% - 90%
图6-1. Rise, Fall, and Delay Time Definition
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6.12 Insulation Characteristics Curves
600
2250
2000
1750
1500
1250
1000
750
VDD1 = VDD2 = 3.6 V
VDD1 = VDD2 = 5.5 V
500
400
300
200
100
0
500
250
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
图6-3. Thermal Derating Curve for Safety-Limiting Power per
图6-2. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1600 VRMS, projected insulation lifetime = 98 years
图6-4. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
1.5
1
0.5
0
-0.5
-1
Device 1
Device 2
Device 3
-1.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD1 = 5 V
图6-6. Input Offset Voltage vs Temperature
图6-5. Input Offset Voltage vs Supply Voltage
2.5
15
12
9
Device 1
Device 2
Device 3
2
1.5
1
6
0.5
0
3
0
-0.5
-1
-3
-6
-9
-12
-15
-1.5
-2
-2.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDD1 (V)
5
5.5
VDD1 = 3.3 V
图6-7. Input Offset Voltage vs Temperature
图6-8. Input Bias Current vs High-Side Supply Voltage
15
12
9
14
12
10
8
6
3
0
6
-3
-6
-9
-12
-15
4
2
0
100
1000
fIN (kHz)
10000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-10. Input Capacitance vs Input Signal Frequency
图6-9. Input Bias Current vs Temperature
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
5
4.5
4
5
0
OUTP
OUTN
-5
3.5
3
-10
-15
-20
-25
-30
-35
-40
2.5
2
1.5
1
0.5
0
1
10
100
1000
-0.1
0.3
0.7
1.1
VIN (V)
1.5
1.9
2.3
2.7
fIN (kHz)
图6-12. Normalized Gain vs Input Frequency
图6-11. Output Voltage vs Input Voltage
0.2
0°
0.15
0.1
-45°
-90°
0.05
0
-135°
-180°
-225°
-270°
-315°
-360°
-0.05
-0.1
-0.15
-0.2
VDD1
VDD2
3
3.5
4
4.5
VDDx (V)
5
5.5
1
10
100
1000
fIN (kHz)
图6-14. Gain Error vs Supply Voltage
图6-13. Output Phase vs Input Frequency
0.2
0.15
0.1
Device 1
Device 2
Device 3
0.05
0
-0.05
-0.1
-0.15
-0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-15. Gain Error vs Temperature
图6-16. Nonlinearity vs Input Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
0.04
0.03
0.02
0.01
0
0.04
0.03
0.02
0.01
0
vs VDD1
vs VDD2
-0.01
-0.02
-0.03
-0.04
-0.01
-0.02
-0.03
-0.04
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDDx (V)
5
5.5
图6-18. Nonlinearity vs Temperature
图6-17. Nonlinearity vs Supply Voltage
-70
-75
-70
-75
VDD1
VDD2
-80
-80
-85
-85
-90
-90
Device 1
Device 2
Device 3
-95
-95
-100
-100
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDDx (V)
5
5.5
图6-20. Total Harmonic Distortion vs Temperature
图6-19. Total Harmonic Distortion vs Supply Voltage
80
72.5
70
VDD1
VDD2
77.5
75
67.5
65
62.5
60
72.5
70
57.5
55
67.5
65
52.5
50
62.5
60
47.5
45
3
3.5
4
4.5
VDDx (V)
5
5.5
42.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VIN (V)
图6-21. Signal-to-Noise Ratio vs Input Voltage
图6-22. Signal-to-Noise Ratio vs Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
1000
100
10
80
77.5
75
72.5
70
67.5
65
1
Device 1
Device 2
Device 3
62.5
60
0.1
0.1
1
10
100
1000
Frequency (kHz)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-24. Input-Referred Noise Density vs Frequency
图6-23. Signal-to-Noise Ratio vs Temperature
0
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
-20
-40
-60
-80
-100
VDD1
VDD2
-120
1.39
0.1
1
10
100
1000
3
3.5
4
4.5
VDD2 (V)
5
5.5
Ripple Frequency (kHz)
100-mV ripple
图6-25. Power-Supply Rejection Ratio vs Ripple Frequency
图6-26. Output Common-Mode Voltage vs Low-Side Supply
Voltage
1.49
1.48
1.47
1.46
1.45
1.44
1.43
1.42
1.41
1.4
300
290
280
270
260
250
240
230
220
210
200
1.39
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDD2 (V)
5
5.5
图6-27. Output Common-Mode Voltage vs Temperature
图6-28. Output Bandwidth vs Low-Side Supply Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
300
290
280
270
260
250
240
230
220
210
200
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
IDD1 vs VDD1
IDD2 vs VDD2
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
3
3.5
4
4.5
VDDx (V)
5
5.5
图6-29. Output Bandwidth vs Temperature
图6-30. Supply Current vs Supply Voltage
4
8.5
8
3.5
3
7.5
7
2.5
2
6.5
6
1.5
1
5.5
5
4.5
4
0.5
0
IDD1
IDD2
3
3.5
4
4.5
VDD2 (V)
5
5.5
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-31. Supply Current vs Temperature
图6-32. Output Rise and Fall Time vs Low-Side Supply Voltage
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0.2
3
3.5
4
4.5
VDD2 (V)
5
5.5
图6-33. Output Rise and Fall Time vs Temperature
图6-34. IN to OUTP, OUTN Signal Delay vs Low-Side Supply
Voltage
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6.13 Typical Characteristics (continued)
at VDD1 = 5 V, VDD2 = 3.3 V, SHTDN = 0 V, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)
3.8
50% - 90%
50% - 50%
50% - 10%
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0.2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
图6-35. IN to OUTP, OUTN Signal Delay vs Temperature
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7 Detailed Description
7.1 Overview
The AMC1411 is a precision, single-ended input, isolated amplifier with a high input-impedance and wide input
voltage range. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The modulator
converts the analog input signal into a digital bitstream that is transferred across the isolation barrier and
separates the high-side from the low-side. On the low-side, the received bitstream is processed by a fourth-order
analog filter that outputs a differential signal at the OUTP and OUTN pins proportional to the input signal.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application report. The digital modulation used in the AMC1411
to transmit data across the isolation barrier, and the isolation barrier characteristics itself, result in high reliability
and common-mode transient immunity.
7.2 Functional Block Diagram
VDD1
VDD2
OUTP
OUTN
GND2
AMC1411
Analog Filter
IN
ΔΣ Modulator
SHTDN
GND1
7.3 Feature Description
7.3.1 Analog Input
The single-ended, high-impedance input stage of the AMC1411 feeds a second-order, switched-capacitor, feed-
forward ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred across the
isolation barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signal IN. First, if the input voltage VIN exceeds the range specified
in the Absolute Maximum Ratings table, the input current must be limited to the absolute maximum value,
because the electrostatic discharge (ESD) protection turns on. In addition, the linearity and parametric
performance of the device is ensured only when the analog input voltage remains within the linear full-scale
range (VFSR) as specified in the Recommended Operating Conditions table.
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7.3.2 Isolation Channel Signal Transmission
The AMC1411 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-1, to transmit the modulator
output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) shown in the Functional Block
Diagram transmits an internally-generated, high-frequency carrier across the isolation barrier to represent a
digital one and does not send a signal to represent a digital zero. The nominal frequency of the carrier used
inside the AMC1411 is 480 MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides the
input to the fourth-order analog filter. The AMC1411 transmission channel is optimized to achieve the highest
level of common-mode transient immunity (CMTI) and lowest level of radiated emissions caused by the high-
frequency carrier and RX/TX buffer switching.
Internal Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-1. OOK-Based Modulation Scheme
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7.3.3 Analog Output
The AMC1411 provides a differential analog output on the OUTP and OUTN pins. For input voltages VIN in the
range from –0.1 V to +2 V, the device provides a linear response with a nominal gain of 1. For example, for an
input voltage of 2 V, the differential output voltage (VOUTP – VOUTN) is 2 V. At zero input (IN shorted to GND1),
both pins output the same common-mode output voltage VCMout, as specified in the Electrical Characteristics
table. For input voltages greater than 2 V but less than approximately 2.5 V, the differential output voltage
continues to increase but with reduced linearity performance. The outputs saturate at a differential output voltage
of VCLIPout, as shown in 图7-2, if the input voltage exceeds the VClipping value.
Maximum input range before clipping (VClipping
)
Linear input range (VFSR
)
VFAILSAFE
VOUTN
VCLIPout
VOUTP
VCMout
0
2.516 V
Input Voltage (VIN
)
2 V
图7-2. Output Behavior of the AMC1411
The AMC1411 output offers a fail-safe feature that simplifies diagnostics on system level. 图 7-2 shows the fail-
safe mode, in which the AMC1411 outputs a negative differential output voltage that does not occur under
normal operating conditions. The fail-safe output is active in three cases:
• When the high-side supply VDD1 of the AMC1411 device is missing
• When the high-side supply VDD1 falls below the undervoltage threshold VDD1UV
• When the SHTDN pin is pulled high
Use the maximum VFAILSAFE voltage specified in the Electrical Characteristics table as a reference value for fail-
safe detection on a system level.
7.4 Device Functional Modes
The AMC1411 is operational when the power supplies VDD1 and VDD2 are applied as specified in the
Recommended Operating Conditions table.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The high input impedance, low input bias current, excellent accuracy, and low temperature drift make the
AMC1411 a high-performance solution for industrial applications where voltage sensing in the presence of high
common-mode voltage levels is required.
8.2 Typical Application
Reinforced isolated amplifiers are commonly offered in SOIC packages with less than 9 mm of clearance and
creepage specification. Equipment with working voltages greater than 850 V, impulse voltage requirements
greater than 8000 V, systems designed for altitudes greater than 2000 m or for environments with pollution
degree 2 or higher, may require clearance and creepage distances greater than 9 mm depending on the
overvoltage category the system is designed for. Examples are 690-V unearthed (IT) 3-phase power network for
high-reliability industrial applications or corner-earthed, 690-V, 3-phase systems commonly used for high-power
AC motor drives.
The AMC1411 comes in a SOIC package with greater than 15 mm of creepage distance and is specifically
designed for use in high-voltage systems that require accurate voltage monitoring and reinforced isolation
between high-voltage and low-voltage parts of the system.
图 8-1 shows a 3-phase motor-drive application that uses the AMC1411 to monitor the 1200-V, DC-link voltage.
The DC-link voltage is divided down to an approximate 2-V level across the bottom resistor (RSNS) of a high-
impedance resistive divider that is sensed by the AMC1411. The output of the AMC1411 is a differential analog
output voltage of the same value as the input voltage but is galvanically isolated from the high-side by a
reinforced isolation barrier.
The wide creepage and clearance, high isolation voltage rating, and high common-mode transient immunity
(CMTI) of the AMC1411 ensure reliable and accurate operation in harsh and high-noise environments.
+ DC Bus
Number of unit resistors depends
on design requirements.
See design examples for details.
RX1
High-side supply
(3.3 V or 5 V)
Low-side supply
(3.3 V or 5 V)
100 nF 1 uF
RX2
AMC1411
Load
VDD1
VDD2
10
10
10 nF
ICROSS
RSNS
IN
OUTP
OUTN
GND2
ADC
SHTDN
GND1
1 uF 100 nF
IGBT module
DC Bus
图8-1. Using the AMC1411 for DC Link Voltage Sensing in Frequency Inverters
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8.2.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
System input voltage
VALUE
3-phase, 690 V, 50 Hz, IT system
III
Overvoltage category
Altitude
≤2000 m
DC-link voltage
1200 V (maximum)
3.3 V or 5 V
High-side supply voltage
Low-side supply voltage
3.3 V or 5 V
Maximum resistor operating voltage
Voltage drop across the sense resistor (RSNS) for a linear response
Current through the resistive divider, ICROSS
75 V
2 V (maximum)
300 μA
8.2.2 Detailed Design Procedure
The 300-μA cross-current requirement at the maximum DC-link voltage (1200 V) determines that the total
impedance of the resistive divider is 4 MΩ. The impedance of the resistive divider is dominated by the top
portion (shown exemplary as RX1 and RX2 in 图 8-1) and the voltage drop across RSNS can be neglected for a
moment. The maximum allowed voltage drop per unit resistor is specified as 75 V; therefore, the minimum
number of unit resistors in the top portion of the resistive divider is 1200 V / 75 V = 16. The calculated unit value
is 4 MΩ/ 16 = 250 kΩand the next closest value from the E96 series is 249 kΩ.
RSNS is sized such that the voltage drop across the resistor at the maximum DC-link voltage (1200 V) equals
the linear full-scale range input voltage (VFSR) of the AMC1411 that is 2 V. This voltage is calculated as RSNS =
V
FSR / (VDC-link, max – VFSR) x RTOP, where RTOP is the total value of the top resistor string (16 x 249 kΩ = 3984
kΩ). RSNS is calculated as 6.65 kΩand matches a value from the E96 series.
表8-2 summarizes the design of the resistive divider.
表8-2. Resistor Value Example
PARAMETER
VALUE
249 kΩ
16
Unit resistor value, RX
Number of unit resistors
Sense resistor value, RSNS
6.65 kΩ
3990.65 kΩ
300.7 µA
2.000 V
22.5 mW
361 mW
Total resistance value
Resulting current through resistive divider, ICROSS
Resulting full-scale voltage drop across sense resistor RSNS
Power dissipated in unit resistor RX
Total power dissipated in resistive divider
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8.2.2.1 Insulation Coordination
In this example of a motor drive application, isolation between the high-voltage and low-voltage parts of the
system must be checked against the requirements of the IEC61800-5-1 standard for electrical power drive
systems. Isolation must be designed to withstand the rated impulse voltage, temporary overvoltage, and the
working voltage. In addition, the physical distance between exposed metal parts on the high- and low-voltage
side must meet the minimum creepage and clearance requirements.
Table B.1 of the IEC60664-1 standard defines the impulse voltage for a 690-V, 3-phase, unearthed system (such
as an IT system, OVC III) as 8000 V. This value matches the VIOSM (8000 VPK) rating of the AMC1411.
Table B.1 of the IEC60664-1 standard also defines the system voltage of a 690-V, 3-phase IT system as 1000 V.
According to table 7 of the IEC61800-5-1 standard, the temporary overvoltage for a system voltage of 1000 V is
3110 VPK, which is lower than the VIOTM (10500 V) of the AMC1411.
The working voltage in this example is 1200 VDC and is also lower than VIOWM (2260 VDC) of the AMC1411.
The minimum clearance for a 8000-V impulse voltage according the IEC61800-5-1, table 9, is 14 mm for
reinforced isolation. The AMC1411 provides a minimum clearance of 14.7 mm and meets the requirement.
Finally, the minimum creepage distance for a working voltage of 1200 VDC, insulating material group I, pollution
degree 2, reinforced isolation is 2 × 6.04 mm = 12.08 mm according to IEC61800-5-1 table 10. 6.04 mm is the
interpolated value between the 1000 VRMS and 1250 VRMS and is doubled for reinforced isolation. The AMC1411
provides a minimum creepage of 15.7 mm and provides significant margin against the minimum requirement.
8.2.2.2 Input Filter Design
Placing an RC filter in front of the isolated amplifier improves signal-to-noise performance of the signal path. In
practice, however, the impedance of the resistor divider is so high that adding a filter capacitor on the IN pin
limits the signal bandwidth to an unacceptable low limit, such that the filter capacitor is omitted. When used,
design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency
(20 MHz) of the internal ΔΣmodulator
• The input bias current does not generate significant voltage drop across the DC impedance of the input filter
Most voltage-sensing applications use high-impedance resistor dividers in front of the isolated amplifier to scale
down the input voltage. In this case, a single capacitor (as shown in 图8-2) is sufficient to filter the input signal.
VDC
R1
AMC1411
R2
VDD1
VDD2
OUTP
OUTN
GND2
1 nF
IN
RSNS
SHTDN
GND1
图8-2. Input Filter
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8.2.2.3 Differential-to-Single-Ended Output Conversion
图8-3 shows an example of a TLV6001-based signal conversion and filter circuit for systems using single-ended
input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage equals
(VOUTP –VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the system and
use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩand C1 = C2
= 330 pF yields good performance.
C1
AMC1411
R2
VDD1
VDD2
OUTP
OUTN
GND2
R1
R3
IN
–
+
ADC
To MCU
SHTDN
GND1
TLV6001
C2
R4
VREF
图8-3. Connecting the AMC1411 Output to a Single-Ended Input ADC
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see the
18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.
8.2.3 Application Curve
One important aspect of system design is the effective detection of an overvoltage condition to protect switching
devices and passive components from damage. To power off the system quickly in the event of an overvoltage
condition, a low delay caused by the isolated amplifier is required. 图 8-4 shows the typical full-scale step
response of the AMC1411.
VOUTP
VOUTN
VIN
图8-4. Step Response of the AMC1411
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8.3 What To Do and What Not To Do
Do not leave the analog input (IN) of the AMC1411 unconnected (floating) when the device is powered up on the
high-side. If the device input is left floating, the bias current may generate a negative input voltage that exceeds
the specified input voltage range and the output of the device is invalid.
Do not connect protection diodes to the input (IN) of the AMC1411. Diode leakage current can introduce
significant measurement error especially at high temperatures. The input pin is protected against high voltages
by its ESD protection circuit and the high impedance of the external restive divider.
9 Power Supply Recommendations
In a typical application, the high-side (VDD1) of the AMC1411 is powered from an already existing, high-side-
ground referenced 3.3-V or 5-V power supply in the system. Alternatively, the high-side supply can be generated
from the low-side supply (VDD2) by an isolated DC/DC converter. A low-cost solution is based on the push-pull
driver SN6501 and a transformer that supports the desired isolation voltage ratings.
The AMC1411 does not require any specific power-up sequencing. The high-side power supply (VDD1) is
decoupled with a low-ESR, 100-nF capacitor (C1) parallel to a low-ESR, 1-μF capacitor (C2). The low-side
power supply (VDD2) is equally decoupled with a low-ESR, 100-nF capacitor (C3) parallel to a low-ESR, 1-μF
capacitor (C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. 图 9-1 shows
the proper decoupling layout for the AMC1411.
VDC
VDD1
VDD2
R1
R2
C2 1 µF
C4 1 µF
AMC1411
C1 100 nF
C3 100 nF
VDD1
VDD2
OUTP
OUTN
GND2
IN
to RC filter / ADC
to RC filter / ADC
RSNS
SHTDN
GND1
图9-1. Decoupling of the AMC1411
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of their
nominal capacitance under real-world conditions and this factor must be taken into consideration when selecting
these capacitors. This problem is especially acute in low-profile capacitors, in which the dielectric field strength is
higher than in taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves
that greatly simplify component selection.
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Product Folder Links: AMC1411
AMC1411
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ZHCSN86A –MAY 2021 –REVISED SEPTEMBER 2021
10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors (as close as
possible to the AMC1411 supply pins) and placement of the other components required by the device. For best
performance, place the sense resistor close to the device input pin (IN).
10.2 Layout Example
Clearance area, to be kept free
of any conductive materials.
C2
C1
C4
C3
to RC filter / ADC
to RC filter / ADC
IN
OUTP
OUTN
GND2
AMC1411
SHTDN
Top Metal
Inner or Bottom Layer Metal
Via
图10-1. Recommended Layout of the AMC1411
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AMC1411
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ZHCSN86A –MAY 2021 –REVISED SEPTEMBER 2021
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, TLV600x Low-Power, Rail-to-Rail In/Out, 1-MHz Operational Amplifier for Cost-Sensitive
Systems data sheet
• Texas Instrument, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
design guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC1411DWLR
ACTIVE
SOIC
DWL
8
500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
1411
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DWL0008A
SOIC - 4.034 mm max height
S
C
A
L
E
1
.
2
5
0
PLASTIC SMALL OUTLINE
C
SEATING PLANE
17.4
17.1
A
PIN 1 ID AREA
0.1 C
6X 1.27
8
5
1
6.5
6.3
NOTE 3
2X
3.81
4
0.51
0.31
8X
(3.634)
14.1
13.9
NOTE 4
B
0.25
A B C
4.034 MAX
0.33
0.13
TYP
SEE DETAIL A
(1.625)
0.25
GAGE PLANE
0.3
0.1
1.1
0.6
0 -8
DETAIL A
TYPICAL
4224743/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.
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EXAMPLE BOARD LAYOUT
DWL0008A
SOIC - 4.034 mm max height
PLASTIC SMALL OUTLINE
(14.25)
SYMM
(14.6)
8X (1.875)
8X (2)
SYMM
8X (0.6)
8X (0.6)
1
1
4
8
5
8
5
SYMM
SYMM
4
(R0.05)
TYP
(R0.05)
TYP
6X
(1.27)
6X
(1.27)
(16.475)
(16.25)
LAND PATTERN EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
EXPOSED METAL SHOWN
SCALE:3X
LAND PATTERN EXAMPLE
STANDARD
EXPOSED METAL SHOWN
SCALE:3X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224743/A 01/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWL0008A
SOIC - 4.034 mm max height
PLASTIC SMALL OUTLINE
8X (2)
SYMM
1
4
8
SYMM
8X (0.6)
5
6X (1.27)
(16.25)
SOLDER PASTE EXAMPLE
STANDARD
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
SYMM
8X (1.875)
8X (0.6)
1
4
8
5
SYMM
6X (1.27)
(16.475)
SOLDER PASTE EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4224743/A 01/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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