AMC3336-Q1 [TI]
具有集成直流/直流的汽车类 ±1V 输入、精密电压检测增强型隔离式调制器;
| 型号： | AMC3336-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成直流/直流的汽车类 ±1V 输入、精密电压检测增强型隔离式调制器 |
| 文件： | 总40页 (文件大小：2405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC3336-Q1
ZHCSM49 –APRIL 2021
AMC3336-Q1 具有集成直流/直流转换器的高精度、±1V 输入
增强型隔离式Δ-Σ 调制器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
AMC3336-Q1 是一款精密的隔离式 Δ-Σ 调制器，针
对高阻抗交流电压测量进行了优化。这款完全集成的隔
离式直流/直流转换器可实现器件低侧的单电源运行，
使该器件成为空间受限应用的独特解决方案。增强型电
容式隔离栅已通过 VDE V 0884-11 和 UL1577 认证，
并支持高达1.2kVRMS 的工作电压。
– 温度等级1：–40°C 至+125°C，TA
• 3.3V 或5V 单电源，具有集成直流/直流转换器
• ±1V 输入电压范围，针对电压测量进行了优化
• 输入电阻：1GΩ（典型值）
• 低直流误差：
– 失调电压误差：±0.3mV（最大值）
– 温漂±4µV/°C（最大值）
该隔离栅可将系统中以不同共模电压电平运行的各器件
隔开，并保护电压较低的器件免受高电压冲击。
– 增益误差：±0.2%（最大值）
– 增益漂移：±40ppm/°C（最大值）
• 高CMTI：90kV/µs（最小值）
• 系统级诊断功能
• 低EMI：符合CISPR-11 和CISPR-25 标准
• 安全相关认证：
AMC3336-Q1 的输入针对直接连接电阻器网络或其他
高阻抗电压信号源进行了优化。出色的直流精度和低温
漂支持在 –40°C 至 +125°C 的工业级工作温度范围内
进行精确的电压测量。
通过使用数字滤波器（例如 sinc3 滤波器）来抽取位
流，该器件可在 78kSPS 数据速率下实现 16 位分辨率
和85dB 的动态范围。
– 符合DIN VDE V 0884-11 标准的6000VPEAK 增
强型隔离
– 符合UL1577 标准且长达1 分钟的4250VRMS
隔离
器件信息(1)
封装尺寸（标称值）
器件型号
封装
SOIC (16)
AMC3336-Q1
10.30mm x 7.50mm
2 应用
• 可用于以下应用的隔离式电压感应：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– HEV/EV 车载充电器(OBC)
– HEV/EV 直流/直流转换器
– HEV/EV 牵引逆变器
Low-side supply
(3.3 V or 5 V)
DCDC_OUT
DCDC_HGND
HLDO_IN
DCDC_IN
DCDC_GND
Isolated
Power
Isolated
Power
DIAG
NC
LDO_OUT
VDD
HLDO_OUT
MCU
INP
CLKIN
DOUT
GND
+1.0 V
0 V
Isolated
ûꢀ-ADC
INN
œ1.0 V
HGND
AMC3336-Q1
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASA83
AMC3336-Q1
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Table of Contents
7.1 Overview...................................................................19
7.2 Functional Block Diagram.........................................19
7.3 Feature Description...................................................20
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................30
10 Layout...........................................................................32
10.1 Layout Guidelines................................................... 32
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 Device Support........................................................33
11.2 Documentation Support.......................................... 33
11.3 接收文档更新通知................................................... 33
11.4 支持资源..................................................................33
11.5 Trademarks............................................................. 33
11.6 Electrostatic Discharge Caution..............................33
11.7 Glossary..................................................................33
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Power Ratings ............................................................5
6.6 Insulation Specifications ............................................ 6
6.7 Safety-Related Certifications ..................................... 7
6.8 Safety Limiting Values ................................................7
6.9 Electrical Characteristics ............................................8
6.10 Switching Characteristics .......................................10
6.11 Timing Diagrams..................................................... 10
6.12 Insulation Characteristics Curves............................11
6.13 Typical Characteristics............................................12
7 Detailed Description......................................................19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
April 2021
*
Initial Release
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5 Pin Configuration and Functions
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCDC_IN
DCDC_GND
DIAG
LDO_OUT
VDD
HLDO_OUT
INP
CLKIN
INN
DOUT
HGND
GND
Not to scale
图5-1. DWE Package, 16-Pin SOIC, Top View
表5-1. Pin Functions
PIN
NAME
DCDC_OUT
TYPE
DESCRIPTION
High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin.(1)
NO.
1
Power
2
3
DCDC_HGND High-side power ground High-side ground reference for the DC/DC converter; connect this pin to the HGND pin.
HLDO_IN
NC
Power
Input of the high-side LDO; connect this pin to the DCDC_OUT pin.(1)
No internal connection. Connect this pin to the high-side ground or leave unconnected
(floating).
4
5
6
—
HLDO_OUT
INP
Power
Output of the high-side LDO.(1)
Noninverting analog input. Either INP or INN must have a DC current path to HGND to
define the common-mode input voltage.(2)
Analog input
Inverting analog input. Either INP or INN must have a DC current path to HGND to define
the common-mode input voltage.(2)
7
INN
Analog input
8
HGND
GND
High-side signal ground High-side analog signal ground; connect this pin to the DCDC_HGND pin.
Low-side signal ground Low-side analog signal ground; connect this pin to the DCDC_GND pin.
9
10
11
12
DOUT
CLKIN
VDD
Digital output
Digital input
Modulator data output.
Modulator clock input with internal pull-down resistor (typical value: 1.5 MΩ).
Low-side power supply.(1)
Low-side power
Output of the low-side LDO; connect this pin to the DCDC_IN pin. The output of the LDO
must not be loaded by external circuitry.(1)
13
14
LDO_OUT
DIAG
Power
Active-low, open-drain status indicator output; connect this pin to the pullup supply (for
example, VDD) using a resistor or leave this pin floating if not used.
Digital output
15
16
DCDC_GND
DCDC_IN
Low-side power ground Low-side ground reference for the DC/DC converter; connect this pin to the GND pin.
Power
Low-side input of the DC/DC converter; connect this pin to the LDO_OUT pin.(1)
(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.
(2) See the Layout section for details.
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6 Specifications
6.1 Absolute Maximum Ratings
see (1)
MIN
–0.3
MAX
UNIT
Power-supply voltage
Analog input voltage
Digital input voltage
VDD to GND
6.5
V
V
V
INP, INN
HLDO_OUT + 0.5
HGND –6
GND –0.5
GND –0.5
GND –0.5
–10
CLKIN
VDD + 0.5
VDD + 0.5
6.5
DOUT
Digital output voltage
Input current
V
DIAG
Continuous, any pin except power-supply pins
10
mA
°C
Junction, TJ
Storage, Tstg
150
Temperature
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1), HBM ESD classification Level 2
Charged-device model (CDM), per AEC Q100-011, CDM ESD classification Level C6
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
3.3
MAX
UNIT
POWER SUPPLY
VDD
Low-side power supply
VDD to GND
3
5.5
V
ANALOG INPUT
VClipping Differential input voltage before clipping output
±1.25
V
V
V
V
VIN = VINP –VINN
VFSR
Specified linear differential full-scale voltage
Absolute common-mode input voltage (1)
Operating common-mode input voltage
1
VHLDO_OUT
0.6
VIN = VINP –VINN
–1
–2
(VINP + VINN) / 2 to HGND
(VINP + VINN) / 2 to HGND
VCM
DIGITAL I/O
–0.8
VIO
Digital input / output voltage
0
9
VDD
21
V
fCLKIN
Input clock frequency
Input clock duty cycle
20
MHz
40%
50%
60%
9 MHz ≤fCLKIN ≤21 MHz
TEMPERATURE RANGE
TA Specified ambient temperature
125
°C
–40
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
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6.4 Thermal Information
AMC3336-Q1
THERMAL METRIC(1)
DWE (SOIC)
16 PINS
73.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
31
RθJB
ψJT
Junction-to-board thermal resistance
44
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.7
42.8
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
VDD = 5.5 V
VALUE
231
UNIT
PD
Maximum power dissipation
mW
VDD = 3.6 V
151
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UNIT
6.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
GENERAL
CLR
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance through air
mm
mm
≥8
≥8
≥21
≥120
≥600
I
CPG
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance - capacitive signal isolation)
Minimum internal gap (internal clearance - transformer power isolation)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
CTI
Distance through the insulation
µm
V
Comparative tracking index
Material group
According to IEC 60664-1
I-III
Rated mains voltage ≤600 VRMS
Overvoltage category
per IEC 60664-1
I-II
Rated mains voltage ≤1000 VRMS
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
Maximum repetitive peak isolation
voltage
VIORM
At AC voltage (bipolar)
1700
1200
VPK
At AC voltage (sine wave); time-dependent dielectric breakdown (TDDB)
test
VRMS
Maximum-rated isolation
working voltage
VIOWM
At DC voltage
1700
6000
7200
VDC
VPK
VPK
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
VIOTM
isolation voltage
Maximum surge
VIOSM
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK (qualification)
6250
≤5
≤5
VPK
isolation voltage(3)
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and preconditioning (type
test),
≤5
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
VIO = 0.5 VPP at 1 MHz
~4.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(5)
RIO
VIO = 500 V at 100°C ≤TA ≤125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL1577
VTEST = VISO = 4250 VRMS or 6000 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO, t = 1 s (100% production test)
VISO
Withstand isolation voltage
4250
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings must be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Certificate pending
Single protection
Certificate pending
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-
heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
θJA = 73.5°C/W, VDD = 5.5 V,
309
TJ = 150°C, TA = 25°C
θJA = 73.5°C/W, VDD = 3.6 V,
TJ = 150°C, TA = 25°C
θJA = 73.5°C/W, TJ = 150°C, TA = 25°C
IS
Safety input, output, or supply current
mA
R
472
PS
TS
Safety input, output, or total power
Maximum safety temperature
R
1700
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum low-side voltage.
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6.9 Electrical Characteristics
all minimum and maximum specifications are at TA = –40°C to 125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, INN = 0 V,
and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20 MHz, VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
RIN
RIND
IIB
Single-ended input resistance
Differential input resistance
Input bias current
INN = HGND
0.06
0.06
–10
–5
1
1
GΩ
GΩ
nA
INP = INN = HGND; IIB = (IIBP + IIBN) / 2
10
5
IIO
Input offset current(1)
±0.5
2
nA
IIO = IIBP –IIBN
INN = HGND; fIN = 310 kHz, fCLKIN = 20
MHz
CIN
Single-ended input capacitance
Differential input capacitance
pF
pF
CIND
fIN = 310 kHz, fCLKIN = 20 MHz
2
ACCURACY
EO
Offset error(1)
INP = INN = HGND, TA = 25°C
±0.04
0.3
4
mV
–0.3
–4
TCEO
EG
Offset error thermal drift(4)
Gain error
µV/°C
TA = 25°C
0.2%
40
–0.2%
–40
TCEG
DNL
Gain error thermal drift(5)
Differential nonlinearity
ppm/°C
LSB
Resolution: 16 bits
0.99
–0.99
Differential measurement; Resolution: 16
bits
4
6
–4
–6
INL
Integral nonlinearity
LSB
Single-ended measurement; Resolution:
16 bits
SNR
Signal-to-noise ratio
fIN = 1 kHz
80
77
84
84
dB
dB
dB
dB
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion(3)
Spurious-free dynamic range
fIN = 1 kHz
VIN = 2 VPP, fIN = 1 kHz
VIN = 2 VPP, fIN = 1 kHz
–93
96
–80
SFDR
79
INP = INN, fIN = 0 Hz, VCM min ≤VCM
VCM max
≤
–104
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
INP = INN, fIN = 10 kHz, –0.5 V ≤VIN ≤
0.5 V
–89
–109
–104
VDD from 3.0 V to 5.5 V, at dc
INP = INN = HGND, VDD from 3.0 V to
5.5 V, 10 kHz / 100 mV ripple
DIGITAL I/O
IIN
Input leakage current
Input capacitance
7
GND ≤VIN ≤VDD
μA
pF
V
CIN
VIH
4
High-level input voltage
Low-level input voltage
Output load capacitance
0.7 × VDD
VDD + 0.3
0.3 × VDD
30
VIL
V
–0.3
CLOAD
15
pF
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
IOL = 4 mA
VDD –0.1
VDD –0.4
VOH
High-level output voltage
V
0.1
0.4
VOL
Low-level output voltage
V
CMTI
Common-mode transient immunity
90
150
kV/μs
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6.9 Electrical Characteristics (continued)
all minimum and maximum specifications are at TA = –40°C to 125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, INN = 0 V,
and sinc3 filter with OSR = 256 (unless otherwise noted); typical values are at TA = 25°C, CLKIN = 20 MHz, VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
no external load on HLDO
28.5
30.5
42.5
44.5
2.9
IDD
Low-side supply current
mA
V
1 mA external load on HLDO
VDD rising
VDD analog undervoltage detection
threshold
VDDUV
VDDPOR
VDD falling
2.8
VDD rising
2.5
VDD digital reset threshold
DC/DC output voltage
V
VDD falling
2.4
VDCDC_OUT
VDCDCUV
VHLDO_OUT
VHLDOUV
DCDC_OUT to HGND
3.1
2.1
3.5
4.65
V
V
DC/DC output undervoltage detection
threshold voltage
VDCDC_OUT falling
2.25
HLDO_OUT to HGND,
High-side LDO output voltage
3
3.2
2.6
3.4
V
V
up to 1 mA external load (2)
High-side LDO output undervoltage
detection threshold voltage
VHLDO_OUT falling
2.4
Load connected from HLDOout to HGND;
High-side supply current for auxiliary
circuitry
IH
1
mA
ms
non-switching; –40℃≤TA ≤85℃(2)
tSTART
Device startup time
VDD step from 0 to 3.0 V to bitstrem valid
0.6
1.1
(1) The typical value includes one standard deviation (sigma) at nominal operating condition.
(2) High-side LDO supports full external load (IH) only up to TA = 85℃. See the Isolated DC/DC Converter section for more details.
(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (ValueMAX - ValueMIN) / TempRange
(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106
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6.10 Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
tH
tD
DOUT hold time after rising edge of CLKIN CLOAD = 15 pF; CLKIN 50% to DOUT 10% / 90%
3.5
Rising edge of CLKIN to DOUT valid delay CLOAD = 15 pF; CLKIN 50% to DOUT 10% / 90%
15
6
ns
2.5
3.2
2.2
2.9
10% to 90%, 3.0 V ≤VDD ≤3.6 V, CLOAD = 15 pF
DOUT rise time
tr
tf
ns
ns
6
10% to 90%, 4.5 V ≤VDD ≤5.5 V, CLOAD = 15 pF
6
10% to 90%, 3.0 V ≤VDD ≤3.6 V, CLOAD = 15 pF
DOUT fall time
6
10% to 90%, 4.5 V ≤VDD ≤5.5 V,CLOAD = 15 pF
6.11 Timing Diagrams
tCLKIN
tHIGH
CLKIN
50%
tLOW
tH
tD
tr / tf
90%
10%
DOUT
图6-1. Digital Interface Timing
VDD
CLKIN
DOUT
tSTART
Bitstream not valid (analog settling)
Valid bitstream
图6-2. Device Startup Timing
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6.12 Insulation Characteristics Curves
500
1800
1600
1400
1200
1000
800
600
400
200
0
VDD = 3.6 V
VDD = 5.5 V
400
300
200
100
0
0
25
50
75
TA (°C)
100
125
150
0
25
50
75
TA (°C)
100
125
150
图6-4. Thermal Derating Curve for Safety-Limiting Power per
图6-3. Thermal Derating Curve for Safety-Limiting Current per
VDE
VDE
TA up to 150°C, stress-voltage frequency = 60 Hz, isolation working voltage = 1200 VRMS, operating lifetime = 76 years
图6-5. Reinforced Isolation Capacitor Lifetime Projection
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6.13 Typical Characteristics
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
10
8
10
8
6
6
4
4
2
2
0
0
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
3
3.5
4
4.5
5
5.5
-1.4
-1
-0.6
-0.2
0.2
VCM (V)
0.6
1
1.4
VDD (V)
图6-7. Input Bias Current vs Supply Voltage
图6-6. Input Bias Current vs Common-Mode Input Voltage
10
8
0.3
0.2
0.1
0
6
4
2
0
-2
-4
-6
-8
-10
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
图6-8. Input Bias Current vs Temperature
图6-9. Offset Error vs Clock Frequency
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
图6-10. Offset Error vs Supply Voltage
图6-11. Offset Error vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
3
3.5
4
4.5
5
5.5
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
VDD (V)
图6-13. Gain Error vs Supply Voltage
图6-12. Gain Error vs Clock Frequency
0.3
0.2
0.1
0
2
1.5
1
0.5
0
-0.5
-1
-0.1
-0.2
-0.3
Device 1
Device 2
Device 3
-1.5
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
VIN (V)
图6-14. Gain Error vs Temperature
图6-15. Integral Nonlinearity vs Input Voltage
6
5
4
3
2
1
6
5
4
3
2
1
0
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
0
3
3.5
4
4.5
5
5.5
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
VDD (V)
图6-17. Integral Nonlinearity vs Supply Voltage
图6-16. Integral Nonlinearity vs Clock Frequency
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
6
5
4
3
2
1
0
100
90
80
70
60
50
40
Device 1
Device 2
Device 3
SNR
SINAD
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VIN (VPP
)
图6-18. Integral Nonlinearity vs Temperature
图6-19. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
vs Input Signal Amplitude
90
89
88
87
86
85
84
83
82
81
80
90
SNR
SINAD
SNR
SINAD
89
88
87
86
85
84
83
82
81
80
0.01
0.1
1
10
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
fIN (kHz)
图6-20. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
图6-21. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
vs Input Signal Frequency
vs Clock Frequency
90
90
SNR
SNR
89
88
87
86
85
84
83
82
81
80
89
88
87
86
85
84
83
82
81
80
SINAD
SINAD
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
图6-22. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
图6-23. Signal-to-Noise Ratio and Signal-to-Noise + Distortion
vs Supply Voltage
vs Temperature
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
-70
-75
-70
-75
Device 1
Device 2
Device 3
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
Device 1
Device 2
Device 3
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0.01
0.1
1
10
VIN (VPP
)
fIN (kHz)
图6-24. Total Harmonic Distortion vs Input Signal Amplitude
图6-25. Total Harmonic Distortion vs Input Signal Frequency
-70
-70
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
-75
-80
-75
-80
-85
-90
-85
-90
-95
-95
-100
-105
-110
-100
-105
-110
3
3.5
4
4.5
5
5.5
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
VDD (V)
图6-27. Total Harmonic Distortion vs Supply Voltage
图6-26. Total Harmonic Distortion vs Clock Frequency
-70
120
115
110
105
100
95
Device 1
Device 2
Device 3
-75
-80
-85
-90
90
-95
85
-100
-105
-110
80
Device 1
Device 2
Device 3
75
70
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
VIN (VPP
)
图6-28. Total Harmonic Distortion vs Temperature
图6-29. Spurious-Free Dynamic Range vs Input Signal
Amplitude
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
110
105
100
95
110
105
100
95
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
90
90
85
85
80
80
0.01
0.1
1
10
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
fIN (kHz)
图6-30. Spurious-Free Dynamic Range vs Input Signal
图6-31. Spurious-Free Dynamic Range vs Clock Frequency
Frequency
110
110
Device 1
Device 2
Device 3
Device 1
Device 2
Device 3
105
100
95
105
100
95
90
90
85
85
80
80
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD (V)
图6-32. Spurious-Free Dynamic Range vs Supply Voltage
图6-33. Spurious-Free Dynamic Range vs Temperature
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
50
Frequency (kHz)
sinc3, OSR = 256, VIN = 2 VPP
sinc3, OSR = 1; Frequency bin-width equals 1 Hz
图6-35. Frequency Spectrum With 1-kHz Input Signal
图6-34. Noise Density With Both Inputs Shorted to HGND
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
0
-20
0
-20
OSR = 8
OSR = 256
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
0.1
1
10
50
0.01
0.1
1
10
100
1000
Frequency (kHz)
fIN (kHz)
sinc3, OSR = 256, VIN = 2 VPP
图6-36. Frequency Spectrum With 10-kHz Input Signal
图6-37. Common-Mode Rejection Ratio vs Input Signal
Frequency
32
30
28
26
24
22
0
OSR = 8
OSR = 256
-20
-40
-60
-80
-100
-120
-140
3
3.5
4
4.5
5
5.5
0.01
0.1
1
10
100
1000
VDD (V)
fRipple (kHz)
图6-39. Supply Current vs Supply Voltage
图6-38. Power-Supply Rejection Ratio vs Ripple Frequency
32
30
28
26
24
22
32
30
28
26
24
22
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
9
10 11 12 13 14 15 16 17 18 19 20 21
fCLKIN (MHz)
图6-41. Supply Current vs Temperature
图6-40. Supply Current vs Clock Frequency
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6.13 Typical Characteristics (continued)
at VDD = 3.3 V, INP = –1 V to 1 V , INN = AGND, fCLKIN = 20 MHz, sinc3 filter with OSR = 256, and 16-bit resolution (unless
otherwise noted)
3.4
3.35
3.3
1.25
1
3.25
3.2
0.75
0.5
0.25
0
3.15
3.1
3.05
3
3
3.5
4
4.5
5
5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VDD (V)
TA°(C)
图6-42. High-Side LDO Output Voltage vs Supply Voltage
图6-43. IH Derating vs Ambient Temperature
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7 Detailed Description
7.1 Overview
The AMC3336-Q1 is a fully differential, precision, isolated modulator with an integrated DC/DC converter that
can supply the high-side of the device from a single 3.3-V or 5-V voltage supply on the low side. The input stage
of the device drives a second-order, delta-sigma (ΔΣ) modulator. The modulator converts the analog input
signal into a digital bitstream that is transferred across the isolation barrier and separates the high-side from the
low-side. The isolated data output DOUT of the modulator provides a stream of digital ones and zeros that is
synchronous to the externally-provided clock source at the CLKIN pin. The time average of this serial bitstream
output is proportional to the analog input voltage. The external clock input simplifies the synchronization of
multiple measurement channels on the system level.
The signal path is isolated by a double capacitive silicon dioxide (SiO2) insuation barrier, whereas power
isolation uses an on-chip transformer separated by a thin-film polymer as the insulating material.
7.2 Functional Block Diagram
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
Resonator
And
Driver
Rectifier
Diagnostics
LDO_OUT
VDD
LDO
LDO
HLDO_OUT
INP
CLKIN
Digital
Interface
ΔΣ Modulator
INN
DOUT
AMC3336-Q1
GND1
GND2
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7.3 Feature Description
7.3.1 Analog Input
The high-impedance input stage of the AMC3336-Q1 feeds a second-order, switched-capacitor, feed-forward
ΔΣ modulator. The modulator converts the analog signal into a bitstream that is transferred over the isolation
barrier, as described in the Isolation Channel Signal Transmission section. The high-impedance, and low bias-
current input makes the AMC3336-Q1 suitable for isolated, high-voltage-sensing applications that typically
employ high impedance resistor dividers.
For reduced offset and offset drift, the input buffer is chopper-stabilized with the chopping frequency set at
fCLKIN / 32. Quantization Noise Shaping shows the spur at 625 kHz that is generated by the chopping frequency
for a modulator clock of 20 MHz.
0
-20
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
1000
10000
Frequency (kHz)
sinc3 filter, OSR = 1, fCLKIN = 20 MHz, fIN = 1 kHz
图7-1. Quantization Noise Shaping
There are two restrictions on the analog input signals (INP and INN). First, if the input voltage exceeds the input
range specified in the Absolute Maximum Ratings table, the input current must be limited to 10 mA because the
device input electrostatic discharge (ESD) diodes turn on. Second, the linearity and noise performance of the
device are ensured only when the differential analog input voltage remains within the specified linear full-scale
range VFSR and within the specified input common-mode voltage range VCM as specified in the Recommended
Operating Conditions table.
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7.3.2 Modulator
图 7-2 conceptualizes the second-order, switched-capacitor, feed-forward ΔΣ modulator implemented in the
AMC3336-Q1. The analog input voltage VIN and the output V5 of the 1-bit digital-to-analog converter (DAC) are
differentiated, providing an analog voltage V1 at the input of the first integrator stage. The output of the first
integrator feeds the input of the second integrator stage, resulting in an output voltage V3 that is differentiated
with the input signal VIN and the output of the first integrator V2. Depending on the polarity of the resulting
voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the next clock pulse
by changing the associated analog output voltage V5, causing the integrators to progress in the opposite
direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
V2
V3
V4
VIN
Integrator 1
DAC
Integrator 2
+
–
Σ
Σ
DOUT
0 V
V5
图7-2. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as depicted in Quantization Noise Shaping.
Therefore, use a low-pass digital filter at the output of the device to increase the overall performance. This filter
is also used to convert the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate
(decimation). TI's C2000™ and Sitara™ microcontroller families offer a suitable programmable, hardwired filter
structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC3336-Q1. Alternatively, a
field-programmable gate array (FPGA) or complex programmable logic device (CPLD) can be used to implement
the filter.
7.3.3 Isolation Channel Signal Transmission
The AMC3336-Q1 uses an on-off keying (OOK) modulation scheme, as shown in 图 7-3, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) illustrated in the
Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to
represent a digital one and does not send a signal to represent a digital zero. The nominal frequency of the
carrier used inside the AMC3336-Q1 is 480 MHz.
图7-3 shows the concept of the on-off keying scheme.
Clock
Modulator Bitstream
on High-side
Signal Across Isolation Barrier
Recovered Sigal
on Low-side
图7-3. OOK-Based Modulation Scheme
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7.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 1 V produces a stream of ones and zeros that are high 90% of the time. With 16 bits of
resolution, that percentage ideally corresponds to code 58982. A differential input of –1 V produces a stream of
ones and zeros that are high 10% of the time and ideally results in code 6553 with 16-bit resolution. These input
voltages are also the specified linear range of the AMC3336-Q1. If the input voltage value exceeds this range,
the output of the modulator shows nonlinear behavior as the quantization noise increases. The output of the
modulator clips with a stream of only zeros with an input less than or equal to –1.25 V or with a stream of only
ones with an input greater than or equal to 1.25 V. In this case, however, the AMC3336-Q1 generates a single 1
(if the input is at negative full-scale) or 0 (if the input is at positive full-scale) every 128 clock cycles to indicate
proper device function (see the Output Behavior in Case of a Full-Scale Input section for more details). 图 7-4
shows the input voltage versus the output modulator signal.
+ FS (Analog Input)
Modulator Output
– FS (Analog Input)
Analog Input
图7-4. Analog Input vs Modulator Output
The density of ones in the output bitstream for any input voltage value can be calculated using 方程式1 (with the
exception of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN + VClipping
2ì VClipping
(1)
7.3.4.1 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC3336-Q1 (that is, |VIN| ≥VClipping), as shown in 图7-5, the device
generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being
sensed. In this way, detecting a valid full-scale input signal and differentiating it from a missing high-side supply
is possible on the system level.
CLKIN
DOUT
DOUT
VIN –1.25 V
VIN ≥ 1.25 V
127 CLKIN cycles
127 CLKIN cycles
图7-5. Full-Scale Output of the AMC3336-Q1
7.3.4.2 Output Behavior in Case of a High-Side Supply Failure
The AMC3336-Q1 provides a fail-safe output that ensures that the output DOUT of the device offers a constant
bitstream of logic 0's in case the integrated DC/DC converter output voltage is below the undervoltage detection
threshold. See the Diagnostic Output section for more information.
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7.3.5 Isolated DC/DC Converter
The AMC3336-Q1 offers a fully integrated isolated DC/DC converter stage that includes the following
components illustrated in the Functional Block Diagram:
• Low-dropout regulator (LDO) on the low-side to stabilize the supply voltage VDD that drives the low-side of
the DC/DC converter. This circuit does not output a constant voltage and is not intended for driving any
external load.
• Low-side full-bridge inverter and drivers
• Laminate-based, air-core transformer for high immunity to magnetic fields
• High-side full-bridge rectifier
• High-side LDO to stabilize the output voltage of the DC/DC converter for high analog performance of the
signal path. The high-side LDO outputs a constant voltage and can provide a limited amount of current to
power external circuitry.
The DC/DC converter uses a spread-spectrum clock generation technique to reduce the spectral density of the
electromagnetic radiation. The resonator frequency is synchronized to the operation of the ΔΣ modulator to
minimize interference with data transmission and support the high analog performance of the device.
The architecture of the DC/DC converter is optimized to drive the high-side circuitry of the AMC3336-Q1 and can
source up to IH of additional DC current for an optional auxiliary circuit such as an active filter, preamplifier, or
comparator. As shown in 图 7-6, IH is specified up to an ambient temperature of 85°C and derates linearly at
higher temperatures.
1.25
1
0.75
0.5
0.25
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA (èC)
D00458
图7-6. Derating of IH at Ambient Temperatures >85°C
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7.3.6 Diagnostic Output
As shown in 图 7-7, the open-drain DIAG pin can be monitored to confirm the device is operational, and the
output data are valid. During power-up, the DIAG pin is actively held low until the high-side supply is in regulation
and the modulator starts outputting data. The DIAG pin is actively pulled low if:
• The low-side does not receive data from the high-side (for example, because of a loss of power on the high-
side). The modulator itself outputs a constant bitstream of logic 0's in this case, that is, the DOUT pin is
permanently low.
• The high-side DC/DC output voltage (DCDC_OUT) or the high-side LDO output voltage (HLDO_OUT) drop
below their respective undervoltage detection thresholds (brown-out). In this case, the low-side may still
receive data from the high-side but the data may not be valid. However, the modulator itself outputs a
constant bitstream of logic 0's in this case, meaning that the DOUT pin is permanently low.
CLKIN
DOUT
Normal
Operation
Normal
Operation
DIAG
Power-up
High-side supply undervoltage
图7-7. DIAG and Output under Different Operating Conditions
7.4 Device Functional Modes
The digital interface, including the open-drain DIAG pin are functional as soon as VDD rises above the VDDPOR
threshold. Analog functions, including the circuitry on the high-side, are enabled as soon as VDD rises above the
analog under voltage lockout threshold VDDUV
.
At power-down, analog functions are disabled as VDD falls below the VDDUV (falling) voltage level. The digital
interface, including the open-drain DIAG pin remain functional until VDD drops below the VDDPOR (falling)
voltage level. 图7-8 shows the different enable thresholds for the AMC3336-Q1.
VDDUV, rising
VDDUV, falling
VDDPOR, rising
VDDPOR, falling
VDD
no analog functionality
full analog functionality
no analog functionality
Digital Interface &
DIAG pin not functional
Digital Interface &
DIAG pin functional
Digital Interface &
DIAG pin not functional
图7-8. AMC3336-Q1 Enable Thresholds
Below the VDDPOR voltage level the digital output pins are not actively driven, that is they are in a high-
impedance state but clamped to one diode-voltage above the VDD supply.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The very high input impedance, low AC and DC errors, and low temperature drift make the AMC3336-Q1 a high-
performance solution for voltage-sensing applications. The integrated DC/DC converter simplifies the system
design and allows for measuring signals independent from any high-side supply that is required with
conventional isolated modulators.
8.1.1 Digital Filter Usage
The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, as calculated by 方程
式2, built with minimal effort and hardware, is a sinc3-type filter:
3
-OSR
≈
’
1- z
H z =
( )
∆
∆
÷
÷
1- z-1
«
◊
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-
order modulator. All characterization in this document is done with a sinc3 filter with an oversampling ratio (OSR)
of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of bits
(ENOB) as a function of the OSR is illustrated in 图8-3 or the Typical Application section.
An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an
FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for
download at www.ti.com.
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8.2 Typical Application
8.2.1 On-Board Charger Application
Isolated modulators are widely used for voltage measurements in high-voltage applications that must be isolated
from a low-voltage domain. Typical applications are AC line voltage measurements at the input of a power factor
correction (PFC) stage of an onboard charger (OBC), DC measurements at the output of a PFC stage or DC/DC
converter, or phase voltage measurements in traction inverters. The AMC3336-Q1 integrates an isolated power
supply for the high-voltage side and therefore is particularly easy to use in applications that do not have a high-
side supply readily available or where a high-side supply is referenced to a different ground potential than the
signal to be measured.
图 8-1 shows a simplified schematic of the AMC3336-Q1 in an OBC where the AC phase voltage on the grid-
side must to be measured. At that location in the system, there is no supply readily available for powering the
isolated modulator. The integrated isolated power supply, together with its bipolar input voltage range, makes the
AMC3336-Q1 ideally suited for AC line-voltage sensing.
At the output of the PFC stage a second AMC3336-Q1 is used for sensing the DC-link voltage. This example
also shows the proper connection for implementing a differential measurement that typically results in best
measurement accuracy and linearity.
DC-Link
VBUS
PFC
DC/DC
RDC1
L1
L2
L3
RDCSNS1
To Battery Management System
RDCSNS2
RDC2
N
– VBUS
N
RL11
AMC3336-Q1
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
RL1SNS
DCDC_GND
DIAG
47 k
to uC (optional)
RL12
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
N
N
N
HLDO_OUT
INP
3.3 V / 5 V supply
from uC
1 nF
CLKIN
INN
DOUT
to uC
HGND
GND
GND
AMC3336-Q1
1 µF 1 nF
100 nF
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
47 k
to uC (optional)
100 nF
LDO_OUT
VDD
1 nF 100 nF
1 nF 1 µF
HLDO_OUT
INP
3.3 V / 5 V supply
from uC
1 nF
CLKIN
INN
DOUT
to uC
HGND
GND
GND
图8-1. The AMC3336-Q1 in a Typical Application
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8.2.1.1 Design Requirements
表8-1 lists the parameters for this typical application.
表8-1. Design Requirements
PARAMETER
120-VRMS LINE VOLTAGE
120 V ±10%, 60 Hz
3.3 V or 5 V
230-VRMS LINE VOLTAGE
230 V ±10%, 50 Hz
3.3 V or 5 V
System input voltage
Low-side supply voltage
Maximum resistor operating voltage
75 V
75 V
Voltage drop across the sense resistor (RSNS) for a linear response
Current through the resistive divider, ICROSS
±1 V (maximum)
100 μA
±1 V (maximum)
100 μA
8.2.1.2 Detailed Design Procedure
This discussion covers the 230-VRMS example. The procedure for calculating the resistive divider for the 120-
VRMS use case is identical.
The 100-μA crosscurrent requirement at peak input voltage (360 V) determines that the total impedance of the
resistive divider is 3.6 MΩ. The impedance of the resistive divider is dominated by the top and bottom resistors
(shown exemplary as RL11 and RL12 in 图 8-1) and the voltage drop across RL1SNS can be neglected for a
moment. The maximum allowed voltage drop per unit resistor is specified as 75 V, therefore the total, minimum
number of unit resistors in the top and bottom portion of the resistive divider is 360 V / 75 V = 5. The calculated
unit value is 3.6 MΩ/ 5 = 720 kΩand the next closest value from the E96-series is 715 kΩ.
RL1SNS is sized such that the voltage drop across the resistor at maximum input voltage (360 V) equals the
linear full-scale range input voltage (VFSR) of the AMC3336-Q1 that is +1 V. This voltage is calculated as
RL1SNS = VFSR / (VPeak –VFSR) x (RTOP + RBOT), where (RTOP + RBOT) is the total value of the RL11 and RL12
resistor strings (5 x 715 kΩ = 3575 kΩ). RL1SNS is calculated as 9.96 kΩ and the next closest value from the
E96-series is 10 kΩ.
表8-2 summarizes the design of the resistive divider.
表8-2. Resistor Value Examples
PARAMETER
120-VRMS LINE VOLTAGE
230-VRMS LINE VOLTAGE
Peak voltage
190 V
634 kΩ
1
360 V
715 kΩ
2
Unit resistor value, RL11Xand RL12X
Number of unit resistors in RL11
Number of unit resistors in RL12
2
3
Sense resistor value, RL1SNS
10 kΩ
1912 kΩ
99.4 μA
0.994 V
6.3mW
18.9 mW
10 kΩ
3585 kΩ
100.4 μA
1.004 V
7.2 mW
36.2 mW
Total resistance value
Resulting current through resistive divider, ICROSS
Resulting full-scale voltage drop across sense resistor RL1SNS
Peak power dissipated in unit resistor RL11X and RL12X
Peak power dissipated in resistive divider
The AMC3336-Q1 requires a single 3.3-V or 5-V supply on its low-side. The high-side supply is internally
generated by an integrated DC/DC converter, as explained in the Isolated DC/DC Converter section.
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8.2.1.2.1 Input Filter Design
TI recommends placing an RC filter in front of the isolated amplifier to improve signal-to-noise performance of
the signal path. Design the input filter such that:
• The cutoff frequency of the filter is at least one order of magnitude lower than the sampling frequency (fCLKIN
)
of the internal ΔΣmodulator
• The DC impedance of the filter does not generate significant voltage drop in the analog input lines
• The source impedance of the analog inputs are equal
Most voltage-sensing applications use high-impedance resistive dividers in front of the isolated amplifier to scale
down the input voltage. In this case, a single capacitor (as shown in 图8-2) is sufficient to filter the input signal.
AMC3336-Q1
DCDC_OUT
DCDC_HGND
HLDO_IN
NC
DCDC_IN
DCDC_GND
DIAG
LDO_OUT
VDD
HLDO_OUT
INP
1 nF
CLKIN
INN
DOUT
HGND
GND
图8-2. Input Filter
8.2.1.2.2 Bitstream Filtering
For modulator output bitstream filtering, a device from TI's C2000™ or Sitara™ microcontroller families is
recommended. These families support up to eight channels of dedicated hardwired filter structures that
significantly simplify system level design by offering two filtering paths per channel: one providing high-accuracy
results for the control loop and one fast-response path for overcurrent detection.
A delta-sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and
selecting the right OSR and filter-order to achieve the desired output resolution and filter response time.
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8.2.1.3 Application Curve
The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators.
图 8-3 shows the ENOB of the AMC3336-Q1 with different oversampling ratios. By using 方程式 3, this number
can also be calculated from the SINAD:
SINAD = 1.76 dB + 6.02 dB x ENOB
(3)
16
14
12
10
8
sinc3
sinc2
sinc1
6
4
2
0
1
10
100
1000
OSR
图8-3. Measured Effective Number of Bits vs Oversampling Ratio
8.2.2 What To Do and What Not To Do
Do not leave the inputs of the AMC3336-Q1 unconnected (floating) when the device is powered up. If both
modulator inputs are left floating, the modulator outputs a bitstream that is undefined.
Connect the high-side ground (HGND) to INN, either directly or through a resistive path. A DC current path
between INN and HGND is required to define the input common-mode voltage. Take care not to exceed the input
common-mode range, as specified in the Recommended Operating Conditions table.
The high-side LDO can source a limited amount of current (IH) to power external circuitry. Take care not to over-
load the high-side LDO and be aware of the drating of IH at high temperatures as explined in the Isolated DC/DC
Converter section.
The low-side LDO does not output a constant voltage and is not intended for powering any external circuitry. Do
not connect any external load to the HLDO_OUT pin.
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9 Power Supply Recommendations
The AMC3336-Q1 is powered from the low-side power supply (VDD) with a nominal value of 3.3 V (or 5 V). TI
recommends a low ESR decoupling capacitor of 1 nF (C8 in 图 9-1) placed as close as possible to the VDD pin,
followed by a 1-µF capacitor (C9) to filter this power-supply path.
The low-side of the DC/DC converter is decoupled with a low-ESR, 100-nF capacitor (C4) positioned close to the
device between the DCDC_IN and DCDC_GND pins. Use a 1-µF capacitor (C2) to decouple the high-side in
addition to a low-ESR, 1-nF capacitor (C3) placed as close as possible to the device and connected to the
DCDC_OUT and DCDC_HGND pins.
For the high-side LDO, use low-ESR capacitors of 1-nF (C6), placed as close as possible to the AMC3336-Q1,
followed by a 100-nF decoupling capacitor (C5).
The ground reference for the high-side (HGND) is derived from the terminal of the sense resistor that is
connected to the negative input (INN) of the device. IIN and HGND can be shorted together directly at the device
pins. The high-side DC/DC ground terminal (DCDC_HGND) is also shorted to HGND directly at the device pins.
C2 C3
1 µF 1 nF
C4
100 nF
AMC3336-Q1
DCDC_OUT
DCDC_IN
DCDC_GND
DIAG
DCDC_HGND
HLDO_IN
NC
R1
47 k
C1 100 nF
C6
to uC (optional)
LDO_OUT
VDD
C5
C8 C9
1 nF 1 µF
100 nF 1 nF
HLDO_OUT
INP
3.3 V / 5 V supply
from uC
C10
1 nF
CLKIN
INN
DOUT
to uC
HGND
GND
图9-1. Decoupling the AMC3336-Q1
Capacitors must provide adequate effective capacitance under the applicable DC bias conditions they
experience in the application. MLCC capacitors typically exhibit only a fraction of their nominal capacitance
under real-world conditions and this factor must be taken into consideration when selecting these capacitors.
This problem is especially acute in low-profile capacitors, in which the dielectric field strength is higher than in
taller components. Reputable capacitor manufacturers provide capacitance versus DC bias curves that greatly
simplify component selection.
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表 9-1 lists components suitable for use with the AMC3336-Q1. This list is not exhaustive. Other components
may exist that are equally suitable (or better), however these listed components have been validated during the
development of the AMC3336-Q1.
表9-1. Recommended External Components
DESCRIPTION
PART NUMBER
MANUFACTURER
SIZE (EIA, L x W)
VDD
C8
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
12065C102KAT2A
12063C105KAT2A
AVX
AVX
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C9
DC/DC CONVERTER
C4
100 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C0603C102K5RACTU
Kemet
Kemet
TDK
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
0603, 1.6 mm x 0.8 mm
C3
1 nF ± 10%, X7R, 50 V
1 µF ± 10%, X7R, 25 V
C2
CGA3E1X7R1E105K080AC
HLDO
C1
100 nF ± 10%, X7R, 50 V
100 nF ± 5%, NP0, 50 V
1 nF ± 10%, X7R, 50 V
C0603C104K5RACAUTO
C3216NP01H104J160AA
12065C102KAT2A
Kemet
TDK
0603, 1.6 mm x 0.8 mm
1206, 3.2 mm x 1.6 mm
1206, 3.2 mm x 1.6 mm
C5
C6
AVX
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10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation with the critical placement of the decoupling capacitors. The same
reference designators are used as in the Power Supply Recommendations section. Decoupling capacitors are
placed as close as possible to the AMC3336-Q1 supply pins. For best performance, place the sense resistor
close to the INP and INN inputs of the AMC3336-Q1 and keep the layout of both connections symmetrical.
This layout is used on the AMC3336-Q1 EVM and supports CISPR-11 compliant electromagnetic radiation
levels.
10.2 Layout Example
Clearance area, to be
kept free of any
conductive materials.
DIAG To MCU I/O (optional)
AMC3336-Q1
VDD 3.3-V or 5-V supply
INP
INN
CLKIN From MCU
DOUT To MCU
GND
HGND
Top Metal
Inner or Bottom Layer Metal
Via
图10-1. Recommended Layout of the AMC3336-Q1
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 Isolation Glossary
See the Isolation Glossary
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, Delta Sigma Modulator Filter Calculator design tool
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
C2000™, Sitara™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC3336QDWERQ1
ACTIVE
SOIC
DWE
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
AMC3336Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF AMC3336-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2021
Catalog : AMC3336
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DWE0016A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4223098/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223098/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWE0016A
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
8
14X (1.27)
8
9
9
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4223098/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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