AMC7812BSPAPR [TI]
用于模拟监控和控制的集成多通道 ADC 和 DAC | PAP | 64 | -40 to 125;
| 型号： | AMC7812BSPAPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于模拟监控和控制的集成多通道 ADC 和 DAC | PAP | 64 | -40 to 125 监控 |
| 文件： | 总95页 (文件大小：4017K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMC7812B
www.ti.com.cn
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
具有多通道模数转换器 (ADC)，数模转换器 (DAC) 和温度传感器的
12 位模拟监视和控制解决方案
查询样品: AMC7812B
1
特性
说明
2345
•
具有可编程输出的 12 个 12 位 DAC：
AMC7812B 是一款完整的模拟监视和控制解决方案，
此解决方案包括一个 16 通道，12 位模数转换器
(ADC)，十二个 12 位数模转换器 (DAC)，8 个通用输
入输出 (GPIO)，以及两个远程和一个本地温度传感器
通道。
–
–
0V 至 5V
0V 至 12.5V
•
•
DAC 关断至用户定义电平
具有 16 个输入的 12 位，500 每秒千次采样
(kSPS) ADC：
此器件具有一个内部 +2.5V 基准，可将 DAC 输出电压
配置在 0V 至 +5V 或 0V 至 +12.5V 的范围内。也可使
用一个外部基准。 典型功率耗散为
–
16 个单端或
两个差分 + 12 个单端
•
•
两个远程温度传感器：
±2°C 精度，–40°C 至 +150°C
一个内部温度传感器：
±2.5°C 精度，–40°C 至 +125°C
95mW。 AMC7812B 非常适合于电路板空间、尺寸和
低功耗都十分关键的多通道应用。
–
此器件采用 QFN-64 或 HTQFP-64 PowerPAD™ 封
装，在 -40°C 至 +105°C 的温度范围内完全额定运
行，并且在 -40°C 至 +125°C 的完全温度范围内可
用。
–
•
•
•
•
范围外输入警报
2.5V 内部基准
八个通用输入和输出
可配置兼容 I2C 和 SPI™ 接口，此接口具有 5V 和
3V 逻辑电平
对于那些要求一个不同的通道数、额外的特性、或者转
换器解决方案的应用，德州仪器 (TI) 提供一个模拟监
视器和控制 (AMC) 产品的完整系列产品。 更多信息请
参考www.ti.com/amc。
•
•
省电模式
宽工作温度范围：
-40℃ 至 +125℃
•
小型封装：9mm × 9mm 四方扁平无引线 (QFN)-
64，和 10mm × 10mm 带散热片薄型四方扁平封
装 (HTQFP)-64
ADC-REF-IN/CMP
AMC7812B
CH0
CH1
CH2
CH3
CH4
Reference
(2.5V)
CH5
REF-OUT
CH6
CH7
CH8
CH9
REF-DAC
CH10
CH11
CH12
CH13
CH14
CH15
应用范围
Trigger
DAC-0
DAC0-OUT
ADC
DAC1-OUT
•
•
•
•
基站中的射频 (RF) 功率放大器控制
DAC2-OUT
D1+
GPIO-5
Control/Limits/Status
Registers
DAC3-OUT
DAC4-OUT
测试和测量
DAC5-OUTDAC6-OUT
DAC7-OUTDAC8-OUT
DAC9-OUTDAC10-OUT
DAC11-OUT
GPIO-4
GPIO-7
D1-
Local
Temperature
Sensor
Remote
Temperature
Sensor
工业控制
D2+
Driver
普通模拟监视和控制
GPIO-6
D2-
DAC-11
GPIO-3
GPIO Controller
GPIO-0
ALARM
LOAD-DAC
Out-of-Range
Alarms
DAC-CLR-0
DAC-CLR-1
DACs Clear Logic
RESET
DAV
Serial Interface Register and Control
(SPI/I2C)
Control
Logic
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
5
PowerPAD is a trademark of Texas Instruments, Incorporated.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SBAS625
AMC7812B
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
–0.3 to +6
UNIT
V
AVDD to GND
DVDD to GND
–0.3 to +6
V
IOVDD to GND
–0.3 to +6
V
AVCC to GND
–0.3 to +18
–0.3 to +6
V
DVDD to DGND
V
Analog input voltage to GND
ALARM, GPIO-0, GPIO-1, GPIO-2, GPIO-3, SCLK/SCL, and SDI/SDA to GND
D1+/GPIO-4, D1–/GPIO-5, D2+/GPIO-6, D2–/GPIO-7 to GND
Digital input voltage to DGND
SDO and DAV to GND
–0.3 to AVDD + 0.3
–0.3 to +6
V
V
–0.3 to AVDD + 0.3
–0.3 to IOVDD + 0.3
–0.3 to IOVDD + 0.3
–40 to +125
–40 to +150
+150
V
V
V
Operating temperature range
Storage temperature range
Junction temperature range (TJ max)
°C
°C
°C
kV
kV
Human body model (HBM)
2.5
Electrostatic discharge (ESD)
ratings
Charged device model (CDM)
1.0
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
THERMAL INFORMATION
AMC7812B
THERMAL METRIC(1)
RGC (QFN)
64 PINS
24.1
PAP (HTQFP)
UNITS
64 PINS
33.7
9.5
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
θJCtop
θJB
8.1
3.2
9.0
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
0.3
ψJB
3.3
8.9
θJCbot
0.6
0.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2013, Texas Instruments Incorporated
AMC7812B
www.ti.com.cn
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V,
internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC PERFORMANCE
DAC DC ACCURACY
Resolution
12
Bits
TA = –40°C to +105°C, measured by line passing
through codes 020h and FFFh
±1
±1.25
±1
LSB
INL
Relative accuracy
TA = –40°C to +125°C, measured by line passing
through codes 020h and FFFh
LSBs
LSB
TA = –40°C to +125°C, measured by line passing
through codes 020h and FFFh
DNL
TUE
Differential nonlinearity
Total unadjusted error
±0.3
TA = +25°C, DAC output = 5.0 V
TA = +25°C, DAC output = 12.5 V
±10
±30
mV
mV
TA = +25°C, DAC output = 0 V to +5 V,
code 020h
±2
±5
mV
Offset error
TA = +25°C, DAC output = 0 V to +12.5 V,
code 020h
mV
Offset error temperature coefficient
Gain error
±1
ppm/°C
%FSR
TA = –40°C to +125°C, external reference,
output = 0 V to +5 V
±0.025
±0.15
±0.3
TA = –40°C to +125°C, external reference,
output = 0 V to +12.5 V
–0.15
±2
%FSR
Gain temperature coefficient
ppm/°C
DAC OUTPUT CHARACTERISTICS
TA = –40°C to +125°C, VREF = 2.5 V, gain = 2
TA = –40°C to +125°C, VREF = 2.5 V, gain = 5
0
0
5
V
V
Output voltage range(1)
12.5
DAC output = 0 V to +5 V, code 400h to C00h,
to 1/2 LSB, from CS rising edge, RL = 2 kΩ,
CL = 200 pF
Output voltage settling time(2)
3
µs
Slew rate(2)
Short-circuit current(2)
1.5
30
V/µs
mA
mA
mA
Full-scale current shorted to ground
Source within 200 mV of supply, TA = +25°C
Sink within 300 mV of supply, TA = +25°C
+10
–10
Load current
DAC output = 0 V to +5 V, code B33h. Source and
sink with voltage drop < 25 mV,
TA = –40°C to +95°C
±8
10
mA
Capacitive load stability(2)
DC output impedance(2)
Power-on overshoot
RL = infinite
nF
Ω
Code 800h
0.3
5
AVCC 0 V to 5 V, 2-ms ramp
Code changes from 7FFh to 800h, 800h to 7FFh
Device is not accessed
mV
nV-s
nV-s
Digital-to-analog glitch energy
Digital feedthrough
0.15
0.15
TA = +25°C, at 1 kHz, code 800h, gain = 2,
excludes reference
81
8
nV/√Hz
Output noise
f = 0.1 Hz to 10 Hz, excludes reference
µVPP
DAC REFERENCE INPUT
Reference voltage input range
Input current(2)
TA = –40°C to +125°C, REF-DAC pin
VREF = 2.5 V
1
2.6
V
170
µA
(1) The output voltage must not be greater than AVCC. See the DAC Output section for further details.
(2) Sampled during initial release to ensure compliance; not subject to production testing.
Copyright © 2013, Texas Instruments Incorporated
3
AMC7812B
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V,
internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.505
25
UNIT
INTERNAL REFERENCE
Output voltage
TA = +25°C, REF-OUT pin
2.495
2.5
0.4
10
V
Ω
Output impedance
Reference temperature coefficient
Output current (sourcing and sinking)
TA = –40°C to +125°C
ppm/°C
mA
±5
TA = +25°C, f = 1 kHz
f = 0.1 Hz to 10 Hz
260
13
nV/√Hz
µVPP
Output voltage noise
ADC PERFORMANCE
ADC DC ACCURACY (for AVDD = 5 V)
Resolution
12
±0.5
±0.5
Bits
LSB
LSB
INL
Integral nonlinearity
TA = –40°C to +125°C
TA = –40°C to +125°C
±1
±1
DNL
Differential nonlinearity
Single-Ended Mode
Offset error
±1
±0.4
±1
±3
±5
LSB
LSB
LSB
LSB
Offset error match
Gain error
External reference
Gain error match
±0.4
Differential Mode
External reference, 0 V to (2 × VREF) mode,
VCM = 2.5 V
±2
±1
±5
±5
LSB
LSB
Gain error
External reference, 0 V to VREF mode,
VCM = 1.25 V
Gain error match
Zero code error
±0.5
±1
LSB
LSB
0 V to (2 × VREF) mode, VCM = 2.5 V
±3
±3
External reference, 0 V to VREF mode,
VCM = 1.25 V
±1
LSB
Zero code error match
±0.5
67
LSB
dB
Common-mode rejection
At dc, 0 V to (2 × VREF) mode
SAMPLING DYNAMICS
External single analog channel, auto mode
External single analog channel, direct mode
External single analog channel
500
167
2
kSPS
kSPS
µs
Conversion rate
Conversion time(3)
Autocycle update rate(3)
Throughput rate
All 16 single-ended inputs enabled
32
µs
SPI clock, 12 MHz or greater, single channel
500
kSPS
ANALOG INPUT(4)
TA = –40°C to +125°C, single-ended, 0 V to VREF
TA = –40°C to +125°C, single-ended,
0
0
VREF
V
V
2 × VREF
0 V to (2 × VREF
)
Full-scale input voltage
TA = –40°C to +125°C, VIN+ – VIN–, fully-differential,
0 V to VREF
–VREF
+VREF
V
V
TA = –40°C to +125°C, VIN+ – VIN–, fully-differential,
–2 × VREF
GND – 0.2
2 × VREF
0 V to (2 × VREF
)
Absolute input voltage
Input capacitance(3)
TA = –40°C to +125°C
0 V to VREF mode
AVDD + 0.2
V
118
73
pF
pF
µA
0 V to (2 × VREF) mode
Unselected ADC input
DC input leakage current
±10
ADC REFERENCE INPUT
Reference input voltage range
Input current
TA = –40°C to +125°C
VREF = 2.5 V
1.2
AVDD
V
145
µA
(3) Sampled during initial release to ensure compliance; not subject to production testing.
(4) VIN+ or VIN– must remain within GND – 0.2 V and AVDD + 0.2 V; see the Analog Inputs section.
4
Copyright © 2013, Texas Instruments Incorporated
AMC7812B
www.ti.com.cn
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V,
internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted.
PARAMETER
INTERNAL ADC REFERENCE BUFFER
Offset
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = +25°C
±5
mV
INTERNAL TEMPERATURE SENSOR
Operating range
–40
+125
±2.5
±1.5
°C
°C
°C
°C
ms
AVDD = 5 V, TA = –40°C to +125°C
AVDD = 5 V, TA = 0°C to +100°C
Per LSB
±1.25
Accuracy
Resolution
0.125
15
Conversion rate
External temperature sensors are disabled
EXTERNAL TEMPERATURE SENSOR (Using 2N3906 external transistor)
Operating range
Limited by external diode
–40
+150
±1.5
°C
°C
AVDD = 5 V, TA = 0°C to +100°C,
TD = –40°C to +150°C
Accuracy(5)(6)
AVDD = 5 V, TA = –40°C to +100°C,
TD = –40°C to +150°C
±2
°C
°C
ms
Resolution
Per LSB
0.125
93
With resistance cancellation
(RC bit = '1')
72
33
100
47
Conversion rate per sensor
DIGITAL LOGIC: GPIO(7)(8) and ALARM
Without resistance cancellation
(RC bit = '0')
44
ms
IOVDD = +5 V
2.1
2.2
0.3 + IOVDD
V
V
V
V
V
VIH
VIL
Input high voltage
Input low voltage
TA = –40°C to +125°C, IOVDD = +3.3 V
IOVDD = +5 V
0.3 + IOVDD
–0.3
–0.3
0.8
0.7
0.4
TA = –40°C to +125°C, IOVDD = +3.3 V
TA = –40°C to +125°C, IOVDD = +5 V, sinking 5 mA
VOL
Output low voltage
TA = –40°C to +125°C, IOVDD = +3.3 V,
sinking 2 mA
0.4
V
High-impedance leakage
5
µA
pF
High-impedance output capacitance
10
DIGITAL LOGIC: All Except SCL, SDA, ALARM, and GPIO
IOVDD = +5 V
2.1
2.2
0.3 + IOVDD
V
V
VIH
VIL
Input high voltage
Input low voltage
TA = –40°C to +125°C, IOVDD = +3.3 V
IOVDD = +5 V
0.3 + IOVDD
–0.3
–0.3
0.8
0.7
±1
5
V
TA = –40°C to +125°C, IOVDD = +3.3 V
V
Input current
µA
pF
V
Input capacitance
IOVDD = +5 V, sourcing 3 mA
IOVDD = +3.3 V, sourcing 3 mA
IOVDD = +5 V, sinking 3 mA
IOVDD = +3.3 V, sinking 3 mA
4.8
2.9
VOH
Output high voltage
Output low voltage
V
0.4
0.4
±5
V
VOL
V
High-impedance leakage
µA
pF
High-impedance output capacitance
10
(5) TD is the external diode temperature.
(6) Auto conversion mode disabled.
(7) For pins GPIO0 to GPIO3, the external pull-up resistor must be connected to a voltage less than or equal to 5.5 V.
(8) For pins GPIO4 to GPIO7, the external pull-up resistor must be connected to a voltage less than or equal to AVDD
.
Copyright © 2013, Texas Instruments Incorporated
5
AMC7812B
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AVCC = +15 V, AGND = DGND = 0 V, IOVDD = 2.7 V to 5.5 V,
internal 2.5-V reference, and the DAC output span = 0 V to 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL LOGIC: SDA, SCL (I2C-Compatible Interface)
IOVDD = +5 V
2.1
2.2
0.3 + IOVDD
V
V
VIH
VIL
Input high voltage
Input low voltage
TA = –40°C to +125°C, IOVDD = +3.3 V
IOVDD = +5 V
0.3 + IOVDD
–0.3
–0.3
0.8
0.7
±5
5
V
TA = –40°C to +125°C, IOVDD = +3.3 V
V
Input current
µA
pF
V
Input capacitance
IOVDD = +5 V, sinking 3 mA
0
0
0.4
VOL
Output low voltage
TA = –40°C to +125°C, IOVDD = +3.3 V,
sinking 3 mA
0.4
V
High-impedance leakage
±5
10
µA
pF
High-impedance output capacitance
TIMING REQUIREMENTS
From AVDD , DVDD ≥ 2.7 V and AVCC ≥ 4.5 V to
normal operation
Power-on delay
100
100
250
µs
Power-down recovery time
From CS rising edge
70
µs
µs
ns
ns
Reset delay
Convert pulse width
Reset pulse width
Delay to normal operation from any reset
250
20
20
POWER-SUPPLY REQUIREMENTS
AVDD
AVDD must be ≥ (VREF + 1.2 V)
+2.7
+5.5
12.5
V
TA = –40°C to +125°C, AVDD and DVDD combined,
normal operation, no DAC load
7.9
1.6
mA
AIDD
IVCC
AVCC
mA
V
+4.5
+18
6.5
AVCC, no load, DACs at code 800h
mA
TA = –40°C to +125°C, normal operation(9)
AVDD = DVDD = 5 V, AVCC = 15 V
,
Power dissipation
95
120
mW
DVDD
IOVDD
+2.7
+2.7
+5.5
+5.5
V
V
TEMPERATURE RANGE
Specified performance
Operating range
–40
–40
+105
+125
°C
°C
(9) No DAC load, all DACs at 800h and both ADCs at the fastest auto conversion rate.
6
Copyright © 2013, Texas Instruments Incorporated
AMC7812B
www.ti.com.cn
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
ADC-REF-IN/CMP
AMC7812B
CH0
CH1
CH2
CH3
CH4
CH5
CH6
Reference
(2.5V)
REF-OUT
REF-DAC
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
Trigger
DAC0-OUT
DAC-0
ADC
DAC1-OUT
DAC2-OUT
D1+
GPIO-5
DAC3-OUT
Control/Limits/Status
Registers
DAC4-OUT
DAC5-OUTDAC6-OUT
DAC7-OUTDAC8-OUT
DAC9-OUTDAC10-OUT
DAC11-OUT
GPIO-4
GPIO-7
D1-
Local
Temperature
Sensor
Remote
Temperature
Sensor
D2+
Driver
GPIO-6
D2-
DAC-11
GPIO-3
GPIO Controller
GPIO-0
ALARM
LOAD-DAC
Out-of-Range
Alarms
DAC-CLR-0
DAC-CLR-1
DACs Clear Logic
RESET
DAV
Serial Interface Register and Control
(SPI/I2C)
Control
Logic
Copyright © 2013, Texas Instruments Incorporated
7
AMC7812B
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
PIN CONFIGURATIONS
RGC PACKAGE
QFN-64
(TOP VIEW)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RESET
DAV
CH15
CH14
CH13
CH12
CH11
CH10
CH9
3
CNVT
4
SDI/SDA
SCLK/SCL
DGND
IOVDD
5
6
7
8
DVDD
CH8
9
CS/A0
CH7
10
11
12
13
14
15
16
SDO/A1
A2
CH6
CH5
SPI/I2C
GPIO-0
GPIO-1
GPIO-2
GPIO-3
CH4
CH3
CH2
CH1
CH0
PAP PACKAGE
HTQFP-64
(TOP VIEW)
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RESET
DAV
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
3
CNVT
4
SDI/SDA
SCLK/SCL
DGND
IOVDD
5
6
7
8
DVDD
9
CS/A0
10
11
12
13
14
15
16
SDO/A1
A2
SPI/I2C
GPIO-0
GPIO-1
GPIO-2
GPIO-3
8
Copyright © 2013, Texas Instruments Incorporated
AMC7812B
www.ti.com.cn
ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
PIN DESCRIPTIONS
NAME
A2
NO.
11
DESCRIPTION
Slave address selection A2 for I2C when the SPI/I2C pin is low.
ADC ground. Must be connected to AGND.
ADC-GND
32
External ADC reference input when external VREF is used to drive the ADC. A compensation capacitor connection
(connect a 4.7-µF capacitor between this pin and AGND) when internal VREF is used to drive the ADC.
ADC-REF-IN/CMP
31
AGND1
AGND2
AGND3
AGND4
54
55
22
21
Analog ground
Analog ground
Analog ground
Analog ground
Global alarm. Open-drain output. An external 10-kΩ, pull-up resistor is required. This pin goes low (active) when one
(or more) analog channels are out of range.
ALARM
AVCC1
AVCC2
62
56
23
Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, and DAC11-OUT, must be tied
to AVCC2
Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, and DAC5-OUT, must be tied to
AVCC1
AVDD1
AVDD2
49
50
Positive analog power supply
Positive analog power supply
Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be programmed as
differential or single-ended.
CH0 to CH15
33-48
CNVT
3
External conversion trigger, active low. The falling edge initiates the sampling and conversion of the ADC.
Chip-select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I2C when the SPI/I2C pin is low.
CS/A0
9
D1–/GPIO4
D1+/GPIO-5
D2–/GPIO-6
D2+/GPIO-7
DAC0-OUT
DAC1-OUT
DAC2-OUT
DAC3-OUT
DAC4-OUT
DAC5-OUT
DAC6-OUT
DAC7-OUT
DAC8-OUT
DAC9-OUT
DAC10-OUT
DAC11-OUT
29
30
27
28
26
25
24
20
19
18
51
52
53
59
60
61
Remote sensor D1 negative input when D1 is enabled; GPIO-6 when D1 is disabled. Pull-up resistor required for output.
Remote sensor D1 positive input when D1 is enabled; GPIO-7 when D1 is disabled. Pull-up resistor required for output.
Remote sensor D2 negative input when D2 is enabled; GPIO-6 when D2 is disabled. Pull-up resistor required for output.
Remote sensor D2 positive input when D2 is enabled; GPIO-7 when D2 is disabled. Pull-up resistor required for output.
DAC channel 0 output
DAC channel 1 output
DAC channel 2 output
DAC channel 3 output
DAC channel 4 output
DAC channel 5 output
DAC channel 6 output
DAC channel 7 output
DAC channel 8 output
DAC channel 9 output
DAC channel 10 output
DAC channel 11 output
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter a clear
state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DAC-
data register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous
data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit.
When this pin is high, the DACs are in normal operation.
DAC-CLR-0
17
DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter a clear
state, the DAC latch is loaded with a predefined code, and the output is set to the corresponding level. However, the DAC-
data register does not change. When the DAC goes back to normal operation, the DAC latch is loaded with the previous
data from the DAC-data register and the output returns to the previous level, regardless of the status of the SLDAC-n bit.
When this pin is high, the DACs are in normal operation.
DAC-CLR-1
DAV
63
2
Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion ends. In
auto mode, a 1-µs pulse (active low) appears on this pin when a conversion cycle completes (see the Primary ADC
Operation and Registers sections for details). DAV stays high when deactivated.
DGND
DGND2
DVDD
6
Digital ground
Digital ground
64
8
Digital power supply (+3 V to +5 V). Must be the same value as AVDD
.
GPIO-0
GPIO-1
GPIO-2
GPIO-3
13
14
15
16
General-purpose digital inputs and outputs. These pins are bidirectional open-drain, digital input and output pins, and
require an external pull-up resistor. See the General Purpose Input/Output Pins section for more details.
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
PIN DESCRIPTIONS (continued)
NAME
IOVDD
NO.
7
DESCRIPTION
Interface power supply
DAC reference Input
Internal reference output
REF-DAC
REF-OUT
RESET
58
57
1
Reset input, active low. A logic low on this pin causes the device to perform a hardware reset.
Serial clock input of the main serial interface. This pin functions as the SPI clock when the SPI/I2C pin is high. This pin
functions as the I2C clock when the SPI/I2C pin is low.
SCLK/SCL
5
Serial interface data. This pin functions as SDI for the serial peripheral interface (SPI) when the SPI/I2C pin (pin 12) is
high. This pin functions as SDA for the I2C interface when the SPI/I2C pin is low.
SDI/SDA
SDO/A1
SPI/I2C
4
SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I2C when the SPI/I2C pin is low.
10
12
Interface selection pin; digital input. When this pin is tied to IOVDD, the SPI is enabled and the I2C interface is disabled.
When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled.
10
Copyright © 2013, Texas Instruments Incorporated
AMC7812B
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
I2C-COMPATIBLE TIMING DIAGRAMS
S
Sr
P
S
SDA
tSU, STA
tSU, DAT
tBUF
tHD, STA
tHD, DAT
tLOW
tSU, STO
SCL
tHD,STA
tHIGH
tR
tF
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
= Resistor Pull-Up
Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus
TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes(1)
At –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 2.7 V to 5.5 V, unless otherwise
noted.
STANDARD MODE
FAST MODE
PARAMETER
SCL clock frequency
MIN
0
MAX
100
—
MIN
0
MAX
400
—
UNIT
kHz
µs
(2)
fSCL
tLOW
Low period of the SCL clock
4.7
4.0
4.7
1.3
0.6
0.6
tHIGH
High period of the SCL clock
—
—
µs
tSU, STA
Set-up time for a repeated start condition
—
—
µs
Hold time (repeated) start condition. After this
period, the first clock pulse is generated
tHD, STA
4.0
—
0.6
—
µs
tSU, DAT
tHD, DAT
tSU, STO
tR
Data set-up time
Data hold time for I2C-bus devices
250
0
—
3.45
—
100
0
—
0.9
—
ns
µs
µs
ns
ns
µs
pF
ns
Set-up time for stop condition
4.0
—
0.6
(3)
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Bus-free time between a stop and start condition
Capacitive load for each bus line
Pulse duration of spike suppressed
1000 20 + 0.1 CB
300 20 + 0.1 CB
300
300
—
(3)
tF
—
tBUF
4.7
—
—
400
N/A
1.3
—
0
CB
400
50
tSP
N/A
(1) All values refer to VIHmin and VILmax levels.
(2) An SCL operating frequency of at least 1 kHz is recommended to avoid activating the I2C timeout function. See the Timeout Function
section for details.
(3) CB = total capacitance of one bus line in pF.
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
www.ti.com.cn
Sr
Sr
P
tFDA
tRDA
SDA
tHD, DAT
tSU, STO
tSU, STA
tHD, STA
tSU, DAT
SCL
tFCL
tLOW
(1)
(1)
tRCL1
tRCL
tLOW
tRCL1
tHIGH
tHIGH
= Current Source Pull-Up
= Resistor Pull-Up
Sr = Repeated START Condition
P = STOP Condition
(1) First rising edge of the SCL signal after Sr and after each acknowledge bit.
Figure 2. Timing for High-Speed (Hs) Mode Devices on the I2C Bus
TIMING CHARACTERISTICS: SDA and SCL for Hs Mode(1)
At –40°C to +105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 2.7 V to 5.5 V, unless
otherwise noted.
CB = 10 pF to 100 pF
CB = 400 pF
PARAMETER
SCL clock frequency
MIN
0
MAX
MIN
0
MAX
1.7
—
UNIT
MHz
ns
(2)
fSCL
3.4
—
—
—
—
—
70
40
tSU, STA
tHD, STA
tLOW
Setup time for (repeated) start condition
Hold time (repeated) start condition
Low period of the SCL clock
High period of the SCL clock
Data setup time
160
160
160
60
160
160
320
120
10
—
ns
—
ns
tHIGH
—
ns
tSU, DAT
tHD, DAT
tRCL
10
—
ns
Data hold time
0
0
150
80
ns
Rise time of SCL signal
10
20
ns
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit
tRCL1
10
80
20
160
ns
tFCL
Fall time of SCL signal
10
10
10
160
10
0
40
80
20
20
20
160
—
80
160
160
—
ns
ns
ns
ns
pF
ns
tRDA
Rise time of SDA signal
tFDA
Fall time of SDA signal
80
tSU, STO
Set-up time for stop condition
Capacitive load for SDA and SCL lines
Pulse width of spike suppressed
—
(3)
CB
100
10
400
10
tSP
0
(1) All values refer to VIHmin and VILmax levels.
(2) An SCL operating frequency of at least 1 kHz is recommended to avoid activating the I2C timeout function. See the Timeout Function
section for details.
(3) For bus line loads where CB is between 100 pF and 400 pF, the timing parameters must be linearly interpolated.
12
Copyright © 2013, Texas Instruments Incorporated
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
SPI TIMING DIAGRAMS
t8
t10
t4
CS
t1
t7
t3
SCLK
t2
tF
tR
t5
t6
SDI
Bit 23
Bit 1
Bit 0
--
Don’t Care
Bit 23 = MSB
Figure 3. SPI Single-Chip Write Operation
t1
t7
t4
CS
t1
t3
SCLK
t2
tF
tR
t5
t6
Bit 23
Bit 22
Read Command
Bit 0
Bit 23
t9
Bit 22
Bit 1
Bit 0
SDI
Any Command
SDO
Bit 23
Bit 22
Bit 1
Bit 0
Data Read from the Register Selected
in the Previous Read Operation
Figure 4. SPI Single-Chip Read Operation
t8
t4
CS
t1
t7
t3
t2
SCLK
SDI
tF
tR
t5
t6
(Command to B)
(Command to A)
Bit 23 (A)
Bit 0 (A)
Bit 23 (B)
Bit 0 (B)
Bit 0 (A)
t9
Bit 23 (A)
SDO
Figure 5. Daisy-Chain Operation: Two Devices
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www.ti.com.cn
TIMING CHARACTERISTICS: SPI Bus(1)(2)
At –40°C to +105°C, AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, and IOVDD = 3.0 V to 5.5 V, unless otherwise
noted.
LIMIT AT TMIN, TMAX
PARAMETER
Clock frequency, TA = –40°C to +105°C
Clock frequency, TA = –40°C to +125°C
SCLK cycle time
MIN
MAX
50
UNIT
MHz
MHz
ns
fSCLK
25
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
20
8
SCLK high time
ns
SCLK low time
8
ns
CS falling edge to SCLK rising edge setup time
Input data setup time
5
ns
5
ns
Input data hold time
4
ns
SCLK falling edge to CS rising edge
Minimum CS high time
10
30
3
ns
ns
Output data valid time
20
ns
CS rising to next SCLK rising edge
3
ns
(1) Specified by design; not production tested.
(2) SDO loaded with 10-pF load capacitance for SDO timing specifications, tR = tF ≤ 5 ns.
14
Copyright © 2013, Texas Instruments Incorporated
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: DAC
At +25°C, unless otherwise noted.
1
0.8
1
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−0.2
−0.4
−0.6
−0.8
−1
TA = −40°C
Gain = 2
VREF = 2.5V, Internal
TA = −40°C
Gain = 2
VREF = 2.5V, Internal
−1
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 6. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 7. LINEARITY ERROR vs CODE
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
−0.4
−0.6
−0.8
−1
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
0
512 1024 1536 2048 2560 3072 3584 4096
Code
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 8. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 9. LINEARITY ERROR vs CODE
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
−0.4
−0.6
−0.8
−1
TA = +105°C
Gain = 2
VREF = 2.5V, Internal
TA = +105°C
Gain = 2
VREF = 2.5V, Internal
0
512 1024 1536 2048 2560 3072 3584 4096
Code
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 10. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 11. LINEARITY ERROR vs CODE
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www.ti.com.cn
TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
TA = +25°C
Gain = 5
VREF = 2.5V, Internal
TA = +25°C
Gain = 5
VREF = 2.5V, Internal
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 12. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 13. LINEARITY ERROR vs CODE
1
0.8
0.6
1
0.8
INL Max
0.6
0.4
0.4
DNL Max
0.2
0
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
DNL Min
−0.4
−0.6
INL Min
Gain = 2
VREF = 2.5V, Internal
Gain = 2
−0.8
−1
VREF = 2.5V, Internal
−40 −25 −10
5
20
35
50
65
80
95 110
−40 −25 −10
5
20
35
50
65
80
95 110
TA (°C)
TA (°C)
Figure 14. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
Figure 15. LINEARITY ERROR vs TEMPERATURE
1
0.8
1
0.8
INL Max
0.6
0.6
0.4
0.4
DNL Max
DNL Min
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
INL Min
Gain = 5
VREF = 2.5V, Internal
Gain = 5
VREF = 2.5V, Internal
−40 −25 −10
5
20
35
50
65
80
95 110
−40 −25 −10
5
20
35
50
65
80
95 110
TA (°C)
TA (°C)
Figure 16. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
Figure 17. LINEARITY ERROR vs TEMPERATURE
16
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
1
1
0.8
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
Ch9
Ch10
Ch11
Ch0
Ch1
Ch2
Ch3
Ch4
Ch5
Ch6
Ch7
Ch8
Ch9
Ch10
Ch11
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 18. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 19. LINEARITY ERROR vs CODE
50
60
50
40
30
20
10
0
TA = +25°C
TA = +25°C
Gain = 5
10368 Channels
Gain = 2
10884 Channels
40
30
20
10
0
Gain Error (%FSR)
Gain Error (%FSR)
Figure 20. GAIN ERROR
Figure 21. GAIN ERROR
0.15
0.1
0.3
0.2
Gain = 5
VREF = 2.5V, Internal
0.05
0
0.1
0
−0.05
−0.1
−0.2
−0.3
−0.1
Gain = 2
VREF = 2.5V, Internal
−0.15
−40 −25 −10
5
20
35
50
65 80 95 110
−40 −25 −10
5
20
35
50
65
80
95 110
TA (°C)
TA (°C)
Figure 22. GAIN ERROR vs TEMPERATURE
Figure 23. GAIN ERROR vs TEMPERATURE
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www.ti.com.cn
TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
0.15
0.3
0.2
TA = +25°C
Gain = 5
VREF = 2.5V, Internal
0.1
0.05
0
0.1
0
−0.05
−0.1
−0.15
−0.1
−0.2
−0.3
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
4.5
6
7.5
9
10.5 12 13.5 15 16.5 18
AVCC (V)
12
13
14
15
16
17
18
AVCC (V)
Figure 24. GAIN ERROR vs SUPPLY
Figure 25. GAIN ERROR vs SUPPLY
35
30
25
20
15
10
5
35
30
25
20
15
10
5
TA = +25°C
TA = +25°C
Gain = 5
VREF = 2.5V, Internal
Gain = 2
VREF = 2.5V, Internal
Code = 020h
Code = 020h
2220 Channels
10884 Channels
0
0
Offset Error (mV)
Offset Error (mV)
Figure 26. OFFSET VOLTAGE
Figure 27. OFFSET VOLTAGE
2
1.5
1
5
4
3
2
0.5
0
1
0
−1
−2
−3
−4
−5
−0.5
−1
Gain = 2
VREF = 2.5V, Internal
Code = 020h
Gain = 5
VREF = 2.5V, Internal
Code = 020h
−1.5
−2
−40 −25 −10
5
20
35
50
65 80
95 110
−40 −25 −10
5
20
35
50
65 80
95 110
TA (°C)
TA (°C)
Figure 28. OFFSET VOLTAGE vs TEMPERATURE
Figure 29. OFFSET VOLTAGE vs TEMPERATURE
18
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ZHCSBJ9A –SEPTEMBER 2013–REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
3
5
3
2
1
1
0
−1
−3
−5
−1
−2
−3
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
Code = 020h
TA = +25°C
Gain = 5
VREF = 2.5V, Internal
Code = 020h
4.5
6
7.5
9
10.5 12 13.5 15 16.5 18
AVCC (V)
12
13
14
15
16
17
18
AVCC (V)
Figure 30. OFFSET VOLTAGE vs SUPPLY VOLTAGE
Figure 31. OFFSET VOLTAGE vs SUPPLY VOLTAGE
3
5
TA = +25°C
AVCC = 15V
Gain = 2
VREF = 2.5V, Internal
FFFh
FF0h
FE0h
FC0h
F80h
2.9
4.95
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
Code = 800h
4.9
4.85
4.8
TA = +25°C
AVCC = 5V
Gain = 2
4.75
4.7
VREF = 2.5V, Internal
−40
−30
−20
−10
0
10
20
30
40
0
2
4
6
8
10
12
ILOAD (mA)
ILOAD (mA)
Figure 32. OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 33. OUTPUT VOLTAGE vs
SOURCE CURRENT CAPABILITY
350
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
3.3
080h
040h
020h
010h
000h
300
250
200
150
100
50
TA = +25°C
AVCC = 15V
Gain = 2
TA = +25°C
Gain = 2
VREF = 2V, External
VREF = 2.5V, Internal
Code = 800h
0
−12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1
0
4.5
6
7.5
9
10.5 12 13.5 15 16.5 18
AVCC (V)
ILOAD (mA)
Figure 34. OUTPUT VOLTAGE vs
SINK CURRENT CAPABILITY
Figure 35. DAC SUPPLY CURRENT vs
DAC SUPPLY VOLTAGE
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TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
6.5
6
5.5
5
6.1
5.8
5.4
5.1
4.7
4.4
4
4.5
4
All DAC Channels
TA = +25°C
Gain = 2
3.7
3.4
3
Gain = 2
VREF = 2.5V, Internal
Code = 800h
3.5
3
VREF = 2.5V, Internal
0
512 1024 1536 2048 2560 3072 3584 4096
Code
−40 −25 −10
5
20
35
50
65
80
95 110
TA (°C)
Figure 36. SUPPLY CURRENT vs DAC CODE
Figure 37. SUPPLY CURRENT vs TEMPERATURE
60
50
40
30
20
10
0
1400
1200
1000
800
600
400
200
0
TA = +25°C
30 Units
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
10
100
1k
10k
100k
1M
Frequency (Hz)
AICC (mA)
Figure 38. DAC SUPPLY CURRENT
Figure 39. DAC NOISE VOLTAGE vs FREQUENCY
2
1.5
1
16
20
15
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
RL= 2KΩ, CL = 250pF
DAC Out SS
DAC Out LS
CS
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
Code = 800h
14
12
10
8
10
0.5
0
5
0
−0.5
6
−5
−10
−15
−20
−1
−1.5
−2
4
2
0
−3
0
3
6
9
12
Time (µs)
0
4
8
12
16
20
Time (s)
Figure 40. DAC NOISE (0.1 Hz to 10 Hz)
Figure 41. SETTLING TIME RISING EDGE
20
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TYPICAL CHARACTERISTICS: DAC (continued)
At +25°C, unless otherwise noted.
2
1.5
1
16
TA = +25°C
Gain = 2
VREF = 2.5V, Internal
RL= 2KΩ, CL = 250pF
DAC Out SS
DAC Out LS
CS
14
12
10
8
0.5
0
−0.5
−1
6
4
−1.5
−2
2
0
−3
0
3
6
9
12
Time (µs)
Figure 42. SETTLING TIME FALLING EDGE
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TYPICAL CHARACTERISTICS: ADC
At +25°C, unless otherwise noted.
1
0.8
1
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
TA = +25°C
0V to VREF Mode
VREF = 2.5V, Internal
Single−Ended Mode
TA = +25°C
0V to VREF Mode
VREF = 2.5V, Internal
Single−Ended Mode
−0.6
−0.8
−1
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 43. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 44. LINEARITY ERROR vs CODE
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
−0.4
TA = +25°C
TA = +25°C
−0.6
−0.8
−1
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
0
512 1024 1536 2048 2560 3072 3584 4096
Code
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 45. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 46. LINEARITY ERROR vs CODE
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
−0.4
TA = +25°C
TA = +25°C
−0.6
−0.8
−1
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0
512 1024 1536 2048 2560 3072 3584 4096
Code
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 47. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 48. LINEARITY ERROR vs CODE
22
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TYPICAL CHARACTERISTICS: ADC (continued)
At +25°C, unless otherwise noted.
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
TA = +25°C
TA = +25°C
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 49. DIFFERENTIAL LINEARITY ERROR vs CODE
Figure 50. LINEARITY ERROR vs CODE
1
1
0.8
0.8
0.6
0.6
DNL Max
DNL Max
0.4
0.4
0.2
0
0.2
0
−0.2
−0.2
−0.4
−0.6
−0.8
−1
−0.4
DNL Min
DNL Min
−0.6
−0.8
−1
0V to VREF Mode
VREF = 2.5V, Internal
Single−Ended Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
Figure 51. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
Figure 52. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
1
0.8
1
0.8
0.6
0.6
DNL Max
DNL Max
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
DNL Min
DNL Min
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
Figure 53. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
Figure 54. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
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TYPICAL CHARACTERISTICS: ADC (continued)
At +25°C, unless otherwise noted.
1
1
0.8
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
0.8
0.6
0.6
INL Max
INL Max
0.4
0.2
0.4
0.2
0
0
−0.2
−0.4
−0.2
−0.4
−0.6
−0.8
−1
INL Min
−0.6
0V to VREF Mode
VREF = 2.5V, Internal
Single−Ended Mode
INL Min
−0.8
−1
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
Figure 55. LINEARITY ERROR vs TEMPERATURE
Figure 56. LINEARITY ERROR vs TEMPERATURE
1
0.8
1
0.8
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Differential Mode
INL Max
0.6
0.6
INL Max
0.4
0.4
0.2
0.2
0
0
−0.2
−0.4
−0.6
−0.8
−1
−0.2
−0.4
−0.6
−0.8
−1
INL Min
INL Min
0V to VREF Mode
VREF = 2.5V, Internal
Differential Mode
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
Figure 57. LINEARITY ERROR vs TEMPERATURE
Figure 58. LINEARITY ERROR vs TEMPERATURE
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−2
−1.5
−2
TA = +25°C
VREF = 2.5V, Internal
Single−Ended Mode
0V to VREF Mode
0V to (2 VREF) Mode
0V to VREF Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
−2.5
−2.5
−3
2.7
−3
3.1
3.5
3.9
4.3
4.7
5.1
5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
AVDD (V)
Figure 59. GAIN ERROR vs SUPPLY
Figure 60. GAIN ERROR vs TEMPERATURE
24
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TYPICAL CHARACTERISTICS: ADC (continued)
At +25°C, unless otherwise noted.
20
15
10
5
5
972 Units
0V to VREF Mode
0V to (2 VREF) Mode
VREF = 2.5V, Internal
Single−Ended Mode
4
3
2
1
0
−1
−2
−3
−4
−5
0
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (dB)
Conversion Frequency (kHz)
Figure 61. OFFSET vs TEMPERATURE
Figure 62. CONVERSION FREQUENCY
540
530
520
510
500
490
480
470
460
540
530
520
510
500
490
480
470
460
TA = +25°C
5.1 5.5
2.7
3.1
3.5
3.9
4.3
4.7
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
AVDD (V)
Figure 63. CONVERSION FREQUENCY vs SUPPLY
Figure 64. CONVERSION FREQUENCY vs TEMPERATURE
12
12
11
10
9
11
10
9
8
7
8
6
TA = +25°C
5.1 5.5
5
2.7
7
3.1
3.5
3.9
4.3
4.7
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
AVDD (V)
Figure 65. SUPPLY CURRENT vs SUPPLY VOLTAGE
Figure 66. SUPPLY CURRENT vs TEMPERATURE
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TYPICAL CHARACTERISTICS: ADC (continued)
At +25°C, unless otherwise noted.
50
40
30
20
10
0
8
TA = +25°C
864 Units
7
6
5
4
3
2
Auto Convert Mode
Direct Mode With Nap
Direct Mode Without Nap
1
0
Single Channel
all DACs at code 800h
0
100
200
300
400
500
Frequency (kHz)
)
AIDD (mA)
Figure 67. SUPPLY CURRENT vs CONVERSION RATE
Figure 68. COMBINED AVDD AND DVDD SUPPLY CURRENT
26
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TYPICAL CHARACTERISTICS: INTERNAL REFERENCE
At +25°C, unless otherwise noted.
2.505
2.503
2.501
2.499
2.497
2.495
2.501
10 Units
2.5005
2.5
2.4995
2.499
TA = +25°C
5.1 5.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
2.7
3.1
3.5
3.9
4.3
4.7
AVDD (V)
Figure 69. OUTPUT VOLTAGE vs TEMPERATURE
Figure 70. OUTPUT VOLTAGE vs SUPPLY
50
40
30
20
10
0
2.505
2.503
2.501
2.499
2.497
2.495
TA = -40°C to +105°C
30 Units
TA = +25°C
−10 −8
−6
−4
−2
0
2
4
6
8
10
)
ILOAD (mA)
Temperature Drift (ppm/°C
Figure 71. OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 72. OUTPUT VOLTAGE DRIFT
1000
20
15
TA = +25°C
Gain = 2
TA = +25°C
VREF = 2.5V, Internal
800
600
400
200
0
10
5
0
−5
−10
−15
−20
100
1k
10k
100k
1M
0
4
8
12
16
20
Frequency (Hz)
Time (s)
Figure 73. INTERNAL REFERENCE NOISE vs FREQUENCY
Figure 74. INTERNAL REFERENCE NOISE (0.1 Hz to 10 Hz)
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TYPICAL CHARACTERISTICS: TEMPERATURE SENSOR
At +25°C, unless otherwise noted.
2.5
10 Units
QFN Package
10 Units
QFN Package
Auto Conversion Mode Disabled
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−2
−1.5
−2
−2.5
−2.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C )
T
(°C )
G001
A
Figure 75. LOCAL TEMPERATURE ERROR vs
TEMPERATURE
Figure 76. REMOTE TEMPERATURE ERROR vs
TEMPERATURE
2.5
2.5
16 units
TQFP Package
16 units
TQFP Package
Auto Conversion Mode Disabled
2
1.5
1
2.0
1.5
1.0
0.5
0
0.5
0.0
−0.5
−1
−0.5
−1.0
−1.5
−2.0
−2.5
−1.5
−2
−2.5
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
TA (°C)
G000
G000
Figure 77. LOCAL TEMPERATURE ERROR vs
TEMPERATURE
Figure 78. REMOTE TEMPERATURE ERROR vs
TEMPERATURE
TYPICAL CHARACTERISTICS: DIGITAL INPUTS
At +25°C, unless otherwise noted.
1.8
1.6
1.4
1.2
1
TA = +25°C
Digital Input = CS
IOVDD = 2.7V
IOVDD = 5V
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Logic Input Voltage (V)
Figure 79. SUPPLY CURRENT vs INPUT VOLTAGE
28
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THEORY OF OPERATION
ADC OVERVIEW
The AMC7812B has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary
ADC features a 16-channel multiplexer, an on-chip track-and-hold, and a successive approximation register
(SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at 500 kSPS and converts
the analog channel inputs, CH0 to CH15. The analog input range for the device can be selected as 0 V to VREF
or 0 V to (2 × VREF). The analog input can be configured for either single-ended or differential signals. The device
has an on-chip 2.5-V reference that can be disabled when an external reference is preferred. If the internal ADC
reference is to be used elsewhere in the system, the output must first be buffered. The various monitored and
uncommitted input signals are multiplexed into the ADC. The secondary ADC is a part of the temperature-
sensing function that converts the analog temperature signals.
ANALOG INPUTS
The device has 16 uncommitted analog inputs; 12 of these inputs (CH4 to CH15) are single-ended. The inputs
for CH0 to CH3 can be configured as four single-ended inputs or two fully-differential channels, depending on the
setup of the ADC channel registers, ADC Channel Register 0 and ADC Channel Register 1. See the Registers
section for details. Figure 80 shows the device equivalent input circuit. The (peak) input current through the
analog inputs depends on the sample rate, input voltage, and source impedance. The current into the device
charges the internal capacitor array during the sample period. After this capacitance is fully charged, there is no
further input current. The source of the analog input voltage must be able to charge the input capacitance to a
12-bit settling level within the acquisition time. When the converter goes into hold mode, the input impedance is
greater than 1 GΩ.
AVDD
40pF
40W
50W
50W
50W
CH0
CH3
CH4
AVDD
AVDD
Device in Hold Mode
AVDD
50W
50W
CH15
40pF
40W
ADC-GND
Figure 80. Equivalent Input Circuit
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Single-Ended Analog Input
In applications where the signal source has high impedance, TI recommends buffering the analog input before
applying it to the ADC. The analog input range can be programmed to be either 0 V to VREF or 0 V to (2 × VREF).
In 2 × VREF mode, the input is effectively divided by two before the conversion takes place. Note that the voltage
with respect to GND on the ADC analog input pins cannot exceed AVDD
.
Fully-Differential Input
When the device is configured as a differential input, the differential signal is defined as VDM, as shown in
Figure 81(a). The differential signal is the equivalent of the difference between the V1 and V2 signals, as shown
in Figure 81(b). The common-mode input VCOMMON is equal to (V1 + V2) / 2.
When the conversion occurs, only the differential mode voltage (VDM) is converted; the common-mode voltage
(VCOMMON) is rejected. This process results in a virtually noise-free signal with a maximum amplitude of –VREF to
+VREF for the VREF range, or (–2 × VREF) to (+2 × VREF) for the (2 × VREF) range. The results are stored in straight
binary or twos complement format.
VIN+
VIN+
VDM
2
V1
V2
VDM
2
VCOMMON
VIN
-
VIN
(b)
-
(a)
Figure 81. Fully-Differential Analog Input
PRIMARY ADC OPERATION
This section describes the operation of the primary ADC.
ADC Trigger Signals (see AMC configuration register 0)
The ADC can be triggered externally by the falling edge of the external trigger CNVT, or internally by writing to
the ICONV bit in AMC Configuration Register 0. The ADC channel registers specify which external analog
channel is converted.
When a new trigger activates, the ADC stops any existing conversion immediately and starts a new cycle. For
example, the ADC is programmed to sample channel 0 to channel 3 repeatedly (auto-mode). During the
conversion of channel 1, an external trigger is activated. The ADC stops converting channel 1 immediately and
starts converting channel 0 again, instead of proceeding to convert channel 2.
30
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Conversion Mode
Two types of ADC conversions are available: direct mode and auto mode. The conversion mode (CMODE) bit of
the AMC configuration 0 register specifies the conversion mode.
In direct mode, each analog channel within the specified group is converted a single time. After the last channel
is converted, the ADC enters an idle state and waits for a new trigger.
Auto mode is a continuous operation. In auto mode, each analog channel within the specified group is converted
sequentially and repeatedly.
The flow chart of the ADC conversion sequence in Figure 82 shows the conversion process.
Start
(Reset)
Wait for
ADC Trigger
First
Conversion
New
Trigger Occurred
Yes
or CMODE
Changed?
No
Has
Input Channel
Stop Current
Conversion
Yes
Yes
Yes
Register been
Rewritten?
No
Has
Input Threshold
Register been
Rewritten?
No
Is this the
Last
Conversion?
No
Convert
Next Channel
Direct
Mode?
Yes
No
Figure 82. ADC Conversion Sequence
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The current conversion cycle stops immediately if:
•
•
•
•
A new trigger is issued.
The conversion mode changes.
Either ADC channel register is rewritten.
Any of the analog input threshold registers are rewritten.
When a new external or internal trigger activates, the ADC starts a new conversion cycle. The internal trigger
should not be issued at the same time the conversion mode is changed. If a '1' is simultaneously written to the
ICONV bit when changing the CMODE bit to '0' or '1', the current conversion stops and immediately returns to
the wait for ADC trigger state.
Double-Buffered ADC Data Registers
The host can access all 16, double-buffered ADC data registers, as shown in Figure 83. The conversion result
from the analog input with channel address n (where n = 0 to 15) is stored in the ADC-n-data register. When the
conversion of an individual channel completes, the data are immediately transferred into the corresponding ADC-
n temporary (TMPRY) register, the first stage of the data buffer. When the conversion of the last channel
completes, all data in the ADC-n TMPRY registers are simultaneously transferred into the corresponding ADC-n-
data registers, the second stage of the data buffer. However, if a data transfer is in progress between any ADC-
n-data register and the AMC shift register, no ADC-n-data registers are updated until the data transfer is
complete. The conversion result from channel address n is stored in the ADC-n-data register. For example, the
result from channel 0 is stored in the ADC-0-data register, and the result from channel 3 is stored in the ADC-3-
data register.
CH0
Out-of-Limit
Alarm
CH1
CH2
CH3
CH4
CH5
CH6
ADC-0
Temporary
ADC-0
Data
To Shift
Register
ADC
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
Input
Range
Selection
ADC-7
Temporary
ADC-7
Data
ICONV
(Internal
Trigger)
OR
ADC-15
Temporary
ADC-15
Data
CONVERT
(External Trigger)
DAVF Bit
DAV Pin
Figure 83. Double-Buffered ADC Structure
32
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ADC Data Format
For a single-ended input, the conversion result is stored in straight binary format. For a differential input, the
results are stored in twos complement format.
SCLK Clock Noise Reduction
To avoid noise caused by the bus clock, TI recommends that no bus clock activity occur for at least the
conversion process time immediately after the ADC conversion starts.
Programmable Conversion Rate
The maximum conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 1. The
conversion rate is programmable through the CONV-RATE-[1:0] bits of the AMC configuration register 1. When
more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC
channel register 0 and ADC channel register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual
conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The
actual conversion rate in direct mode is determined by the rate of the conversion trigger. Note that when a trigger
is issued, there may be a delay of up to 4 µs to internally synchronize and initiate the start of the sequential
channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value
other than the maximum rate ('00'), nap mode is activated between conversions. By activating nap mode, the
AIDD supply current is reduced; see Figure 67.
Table 1. ADC Conversion Rate
tACQ
(µs)
tCONV
(µs)
NAP
ENABLED
THROUGHPUT
(Single-Channel Auto Mode)
CONV-RATE-1
CONV-RATE-0
0
0
1
1
0
1
0
1
0.375
2.375
6.375
14.375
1.625
1.625
1.625
1.625
No
500 kSPS (default)
250 kSPS
Yes
Yes
Yes
125 kSPS
62.5 kSPS
Handshaking with the Host (see AMC configuration register 0)
The DAV pin and the DAVF (data available flag) bit in AMC configuration register 0 provide handshaking with the
host. Pin and bit status depend on the conversion mode (direct or auto); see Figure 84 and Figure 85. In direct
mode, after ADC-n-data registers of all selected channels are updated, the DAVF bit in AMC configuration
register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data are available. By
reading the ADC-n-data register or restarting via the external CNVT pin, the ADC clears the DAVF bit to '0' and
deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new ADC conversion,
an ADC-n-data register must be read after the current conversion completes before a new conversion can be
started in order to reset the DAV status.
In auto-mode, after the ADC-n-data registers of the selected channels are updated, a pulse of 1 µs (low) appears
on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in auto-
mode.
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a) Internal Trigger, Direct Mode:
a) External Trigger, Direct Mode:
SS
CNVT
First
Internal
Trigger
Second
Internal
Trigger
Set ICONV
bit to ‘1’
Set ICONV
bit to ‘1’
First
Trigger
Second
Trigger
Third
Trigger
Read Data
DATA
Read Data
DATA
SDI
DAV
DAV
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion of
the Channels Specified in
the ADC Channel Register
Third Conversion of
the Channels Specified in
the ADC Channel Register
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion of
the Channels Specified in
the ADC Channel Register
b) External Trigger, Auto Mode:
b) Internal Trigger, Auto Mode:
CNVT
First
Trigger
1ms
SS
Set ICONV
bit to ‘1’
Internal
Trigger
DAV
SDI
1ms
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion of
the Channels Specified in
the ADC Channel Register
Third Conversion of
the Channels Specified in
the ADC Channel Register
DAV
First Conversion of
the Channels Specified in
the ADC Channel Register
Second Conversion
Third Conversion
Figure 85. ADC External Trigger
Figure 84. ADC Internal Trigger
Data Available Pin (DAV)
DAV is an output pin that indicates the completion of ADC conversions. The DAVF bit in AMC configuration
register 0 determines the status of the DAV pin. In direct mode, after the selected group of input channels are
converted and the ADC is stopped, the DAVF bit is set to '1' and the DAV pin is driven to logic low (active). In
ADC auto mode, each time the group of input channels are sequentially converted, a 1-µs pulse (low) appears
on the DAV pin.
Convert Pin (CNVT)
CNVT is the input pin for the external ADC trigger signal. ADC channel conversions begin on the falling edge of
the CNVT pulse. If a CNVT pulse occurs when the ADC is already converting, then the ADC continues
converting the current channel. After the current channel completes, the existing conversion cycle finishes and a
new conversion cycle starts. The selected channels specified in the ADC channel registers are converted
sequentially in order of enabled channels.
Analog Input Out-of-Range Detection (see the Analog Input Out-of-Range Alarm Section)
The CH0 to CH3 analog inputs and the temperature inputs are implemented with out-of-range detection. When
any of these inputs is out of the preset range, the corresponding alarm flag in the status register is set. If any
inputs are out of range, the global out-of-range pin (ALARM) goes low. To avoid a false alarm, the device is
implemented with false-alarm protection. See the Alarm Operation section for more details.
Full-Scale Range of the Analog Input
The gain bit of the ADC gain register determines the full-scale range of the analog input. Full-scale range is VREF
when ADGn = 0, or (2 × VREF) when ADGn = 1. If a channel pair is configured for differential operation, the input
ranges are either ±VREF or ±(2 × VREF). In (2 × VREF) mode, the input is effectively divided by two before the
conversion takes place. Each input must not exceed the supply value of AVDD + 0.2 V or AGND – 0.2 V. When
the REF-OUT pin is connected to the REF-ADC pin, the internal reference is used as the ADC reference. When
an external reference voltage is applied to the REF-ADC pin, the external reference is used as the ADC
reference.
34
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SECONDARY ADC AND TEMPERATURE SENSOR OPERATION
The AMC7812B contains one local and two remote temperature sensors. The temperature sensors continuously
monitor the three temperature inputs, and new readings are automatically available every cycle. The on-chip
integrated temperature sensor (shown in Figure 86) is used to measure the device temperature. Two remote
diode sensor inputs are used to measure the two external temperatures. All analog signals are converted by the
secondary ADC that runs in the background at a lower speed. The measurement relies on the characteristics of
a semiconductor junction operation at a fixed current level. The forward voltage of the diode (VBE) depends on
the current passing through the diode and the ambient temperature. The change in VBE when the diode operates
at two different currents (a low current of ILOW and a high current of IHIGH) is shown in Equation 1:
IHIGH
hkT
q
VBE_HIGH - VBE_LOW
=
ln
ILOW
where:
•
•
•
•
k is Boltzmann's constant,
q is the charge of the carrier,
T is the absolute temperature in Kelvin (K), and
η is the ideality of the transistor as a sensor.
(1)
ILOW
IHIGH
SW1
SW2
Local
Temperature
Registers
Second ADC
and Signal
Processing
LPF and Signal
Conditioning
Mux
Diode
Temperature
Sensor
Figure 86. Integrated Local Temperature Sensor
The remote sensing transistor can be a discrete, small-signal type transistor or a substrate transistor built within
the microprocessor. This architecture is shown in Figure 87. An internal voltage source biases the D– terminal
above ground to prevent the ground noise from interfering with measurement. An external capacitor (up to 330
pF) may be placed between D+ and D– to further reduce noise interference.
Remote
Temperature
Registers
ILOW
IHIGH
SW1
SW2
Second ADC
and Signal
Processing
D+
LPF and Signal
Conditioning
Mux
D-
VBIAS
Figure 87. Remote Temperature Sensor
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The device has three temperature sensors: two remote (D1 and D2) and one on-chip (LT). If any sensor is not
used, it can be disabled by clearing the corresponding enable bit (bits D2EN, D1EN, and LTEN of the
temperature configuration register). When disabled, the sensors are not converted. The device continuously
monitors the selected temperature sensors in the background, leaving the user free to perform conversions on
the other channels. When one monitor cycle finishes, a signal passes to the control logic to automatically initiate
a new conversion.
The analog sensing signal is preprocessed by a low-pass filter and signal-conditioning circuitry, and then
digitized by the ADC. The resulting digital signal is further processed by the digital filter and processing unit. The
final result is stored in the LT-temperature-data register, the D1-temperature-data register, and the D2-
temperature-data register, respectively. The format of the final result is in twos complement, as shown in Table 2.
Note that the device measures the temperature from –40°C to +150°C.
Table 2. Temperature Data Format
TEMPERATURE (°C)
DIGITAL CODE
011111111111
010010110000
001100100000
000110010000
000011001000
000000001000
000000000000
111111111000
111100111000
111001110000
110011100000
101101010000
100000000000
+255.875
+150
+100
+50
+25
+1
0
–1
–25
–50
–100
–150
–256
36
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Remote Sensing Diode
Errors in remote temperature sensor readings are typically the consequence of the ideality factor and current
excitation used by the device versus the manufacturer-specified operating current for a given transistor. Some
manufacturers specify a low-level (ILOW) and high-level (IHIGH) current for the temperature-sensing substrate
transistors. The AMC7812B uses 6 μA for ILOW and 120 μA for IHIGH. The device is designed to function with
discrete transistors, such as the 2N3904 and 2N3906. If an alternative transistor is used, the device operates as
specified, as long as the following conditions are met:
1. Base-emitter voltage is greater than 0.25 V at 6 μA, at the highest sensed temperature.
2. Base-emitter voltage is less than 0.95 V at 120 μA, at the lowest sensed temperature.
3. Base resistance is less than 100 Ω.
4. Tight control of VBE characteristics indicated by small variations in hFE (that is, 50 to 150).
Ideality Factor
The ideality factor (η) is a measured characteristic of a remote temperature sensor diode as compared to an
ideal diode. The device allows for different η-factor values, according to Table 3. The device is trimmed for a
power-on reset (POR) value of η = 1.008. If η is different, the η-factor correction register can be used. The value
(NADJUST) written in this register must be in twos complement format, as shown in Table 3. This value is used to
adjust the effective η-factor according to Equation 2 and Equation 3.
Table 3. η-Factor Range (Single Byte)
NADJUST
BINARY
0111 1111
0000 1010
0000 1000
0000 0110
0000 0100
0000 0010
0000 0001
0000 0000
1111 1111
1111 1110
1111 1100
1111 1010
1111 1000
1111 0110
1000 0000
HEX
7F
0A
08
DECIMAL
ηEFF
127
10
8
1.747977
1.042759
1.035616
1.028571
1.021622
1.014765
1.011371
1.008
06
6
04
4
02
2
01
1
00
0
FF
FE
FC
FA
F8
F6
80
–1
–2
–4
–6
–8
–10
–128
1.004651
1.001325
0.994737
0.988235
0.981818
0.975484
0.706542
1.008 ´ 300
heff
=
300 - NADJUST
(2)
300 ´ 1.008
heff
NADJUST = 300 -
where:
•
•
ηEFF is the actual ideality of the transistor used and
NADJUST is the corrected ideality used in the calculation.
(3)
37
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Filtering
Figure 88(a) and Figure 88(b) show the connection of recommended NPN or PNP transistors, respectively.
Remote junction temperature sensors are usually implemented in a noisy environment. Noise is most often
created by fast digital signals, and can corrupt measurements. The AMC7812B has a built-in 65-kHz filter on the
D+ and D– inputs to minimize the effects of noise. However, a bypass capacitor placed differentially across the
inputs of the remote temperature sensor can make the application more robust against unwanted coupled
signals. If filtering is required, the capacitance between D+ and D– should be limited to 330 pF or less for
optimum measurement performance. This capacitance includes any cable capacitance between the remote
temperature sensor and the device.
2N3906
2N3904
D+
D+
D-
D-
(a) NPN
(b) PNP
Figure 88. Remote Temperature Sensor Using Transistor
Series Resistance Cancellation
Parasitic resistance (in series with the remote diode) to the D+ and D– inputs of the device is caused by a variety
of factors, including printed circuit board (PCB) trace resistance and trace length. This series resistance appears
as a temperature offset in the remote sensor temperature measurement, and causes more than 0.45°C error per
ohm. The device implements a technology to automatically cancel out the effect of this series resistance, thus
providing a more accurate result without requiring user characterization of this resistance. With this technology,
the device is able to reduce the effects of series resistance to typically less than 0.0075°C per ohm. The
resistance cancellation is disabled when the RC bit in the temperature configuration register is cleared ('0').
Reading Temperature Data
Temperature is always read as 12-bit data. When the conversion finishes, the temperature is sent to the
corresponding temperature-data register. However, if a data transfer is in progress between the temperature-data
register and the AMC shift register, the temperature-data register is frozen until data transfer completes.
Conversion Time
The conversion time depends on the type of sensor and configuration, as shown in Table 4.
Table 4. Conversion Times
MONITORING
CYCLE TIME (ms)
PROGRAMMABLE
DELAY RANGE (s)
TEMPERATURE SENSOR
Local sensor is active, remote sensors are disabled or in power-down
15
0.48 to 3.84
One remote sensor is active and RC = 0, local sensor and one remote sensor are disabled
or in power-down
44
1.40 to 11.2
One remote sensor is active and RC = 1, local sensor and one remote sensor are disabled
or in power-down
93
59
2.97 to 23.8
1.89 to 15.1
3.45 to 27.65
One remote sensor and local sensor are active and RC = 0, one remote sensor is disabled
or in power-down
One remote sensor and local sensor are active and RC = 1, one remote sensor is disabled
or in power-down
108
Two remote sensors are active and RC = 0, local sensor is disabled or in power-down
Two remote sensors are active and RC = 1, local sensor is disabled or in power-down
All sensors are active and RC is '0'
88
2.81 to 22.5
5.95 to 47.6
3.92 to 26.38
6.43 to 51.45
186
103
201
All sensors are active and RC is '1'
38
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REFERENCE OPERATION
This section describes the operation of the internal and external references.
Internal Reference
The device includes a 2.5-V internal reference. The internal reference is externally available at the REF-OUT pin.
A 100-pF to 10-nF capacitor is recommended between the reference output and GND for noise filtering. The
internal reference is a bipolar transistor-based, precision band-gap voltage reference. The output current is
limited by design to approximately 100 mA.
The internal reference drives all temperature sensors. When connecting the REF-OUT pin to the REF-DAC pin,
the internal reference functions as the DAC reference.
The ADC-REF-IN/CMP pin has a dual function. When an external reference is connected to this pin, the external
reference is used as the ADC reference. When a compensation capacitor (4.7 µF, typical) is connected between
this pin and AGND, the internal reference is used as the ADC reference. When using an external reference to
drive the ADC, the ADC-REF-INT bit in AMC configuration register 0 must be cleared ('0') to turn off the ADC
reference buffer. When using the internal reference to drive the ADC, the ADC-REF-INT bit in AMC configuration
register 0 must be set to '1' to turn on the ADC reference buffer.
External Reference
Figure 89 shows how the external reference is used as the DAC reference when applied on the DAC-REF pin,
and as the ADC reference when applied on the ADC-REF pin. Figure 90 shows the use of the internal reference.
CH0
CH1
CH0
CH1
ADC
ADC
CH14
CH15
CH14
CH15
ADC-REF-IN/CMP
ADC-REF-IN/CMP
Ext.
Ref.
Control Logic: Bit
ADC-REF-INT = ‘0’
Control Logic: Bit
ADC-REF-INT = ‘1’
C > 470nF
(Minimize
Inductance
to Pin)
REF-OUT
REF-DAC
REF-OUT
REF-DAC
Reference
(2.5V)
Reference
(2.5V)
Control Logic:
Bit PREF = ‘0’
Control Logic:
Bit PREF = ‘1’
Ext.
Ref.
DAC0-OUT
DAC0-OUT
DAC-0
DAC-0
Figure 89. Use of the External Reference
Figure 90. Use of the Internal Reference
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DAC OPERATION
The device contains 12 DACs that provide digital control with 12 bits of resolution using an internal or external
reference. The DAC core is a 12-bit string DAC and output buffer. The DAC drives the output buffer to provide an
output voltage. Refer to the DAC configuration register for details. Figure 91 shows a function block diagram of
the DAC architecture. The DAC latch stores the code that determines the output voltage from the DAC string.
The code is transferred from the DAC-n-data register to the DAC latch when the internal DAC-load signal is
generated.
DAC
Data
Register
12-Bit
Resistor
String
DAC
Latch
VOUT
DAC Load(1)
Gain
Gain Logic
Gain Bits
(1) Internal DAC load is generated by writing '1' to the ILDAC bit in synchronous mode. In asynchronous mode, the DAC
latch is transparent.
Figure 91. DAC Block Diagram
Resistor String
The resistor string structure is shown in Figure 92. The resistor string consists of a string of resistors, each of
value R. The code loaded to the DAC latch determines at which node on the string the voltage is tapped off to be
fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the
amplifier. This architecture is inherently monotonic, voltage out, and low glitch. The resistor string architecture is
also linear because all the resistors are of equal value.
R
R
To Output
Amplifier
R
R
R
Figure 92. Resistor String
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DAC Output
The output range is programmable from 0 V to (2 × VREF) or from 0 V to (5 × VREF), depending on the gain bits in
the DAC gain register. The maximum output is AVCC. The output buffer amplifier is capable of generating rail-to-
rail voltages on its output, giving an output range of 0 V to AVCC. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics. The slew rate is 1.5 V/μs with a typical 1/4 to 3/4 scale
settling time of 3 μs with the output unloaded.
Double-Buffered DAC Data Registers
There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data are initially written to an individual DAC-n-data register and then transferred to the corresponding
DAC-n latch. When the DAC-n latch is updated, the output of DAC-n changes to the newly set value. When the
host reads the register memory map location labeled DAC-n-data, the value held in the DAC-n latch is returned
(not the value held in the input DAC-n-data register).
Full-Scale Output Range
The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain
of the DAC output buffer (VREF × gain). The gain bits of the DAC gain register set the output range of the
individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum
output from the DAC must not be greater than AVCC, and the minimum output must not be less than AGND.
DAC Output After Power-On Reset
After power-on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DACx-
OUT (where x = 0 to 11) output pin connects to the analog ground through an internal 10-kΩ resistor. After
power-on or a hardware reset, all DAC-n-data registers, DAC-n latches, and the DAC output are set to default
values (000h).
Load DAC Latch
See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-n latch determine
the output level of the DAC-n pin. After writing to the DAC-n-data register, the DAC latch can be loaded either in
asynchronous or synchronous mode.
In asynchronous mode (SLDAC-n bit = '0'), data are loaded into the DAC-n latch immediately after the write
operation. In synchronous mode (SLDAC-n bit = '1'), the DAC latch updates when the synchronous DAC loading
signal occurs. Setting the ILDAC bit in AMC configuration register 0 generates the loading signal.
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Synchronous Load, Asynchronous Load, and Output Updating
The SLDA-n (synchronous load) bit of the DAC configuration register determines the DAC updating mode, as
shown in Table 5. When SLDA-n is cleared to '0', asynchronous mode is active, the DAC latch updates
immediately after writing to the DAC-n-data register, and the output of DAC-n changes accordingly.
Table 5. DAC-n Output Update Summary for Manual Mode Update
SLDA-n BIT
WRITING TO ILDAC BIT
OPERATION
Update DAC-n individually. The DAC-n latch and DAC-n output are immediately
updated after writing to the DAC-n-data register.
0
Don't care
Simultaneously update all DACs by internal trigger. Writing '1' to the ILDAC bit
generates an internal load DAC trigger signal that updates the DAC-n latches and
DAC-n outputs with the contents of the corresponding DAC-n-data register.
1
1
When the SLDA-n bit is set to '1', synchronous mode is selected. The value of the DAC-n-data register is
transferred to the DAC-n latch only after an active DAC synchronous loading signal (ILDAC) occurs, which
immediately updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n-data
register changes only the value in that register, but not the content of DAC-n latch nor the output of DAC-n, until
the synchronous load signal occurs.
The DAC synchronous load is triggered by writing '1' to the ILDAC bit in AMC configuration register 0. When this
DAC synchronous load signal occurs, all DACs with the SLDA-n bit set to '1' are simultaneously updated with the
value of the corresponding DAC-n-data register. By setting the SLDA-n bit properly, several DACs can be
updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1
to '1' first, and then write the proper values into the DAC-0-data and DAC-1-data registers, respectively. After this
presetting, set the ILDAC bit to '1' to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1
change at the same time.
The device updates the DAC latch only if the latch was accessed from the last time ILDAC was issued, thereby
eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded again. When
the DAC latch is updated, the corresponding output changes to the new level immediately.
NOTE
When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC
latch is loaded with the predefined value of the DAC-n-CLR-setting register and the output
is set to the corresponding level immediately, regardless of the SLDA-n bit value.
However, the DAC data register does not change.
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Clear DACs
DAC-n can be cleared with hardware or software, as shown in Figure 93. When DAC-n goes to a clear state, it is
immediately loaded with predefined code in the DAC-n-CLR-setting register, and the output is set to the
corresponding level to shut down the external LDMOS device. However, the DAC-n-data register does not
change. When the DAC goes back to normal operation, DAC-n is immediately loaded with the previous data from
the DAC-n-data register and the output of DACn-OUT is set back to the previous level to restore LDMOS to the
status before shutdown, regardless of the SLDAC-n bit status.
DAC
Data Register
DAC
Latch
0
1
DAC
DAC
CLR-Setting
Register
DAC-CLR-n Pin
CLR-n Bit in HW-DAC-CLR-n Register
CLR-n Bit in SW-DAC-CLR-n Register
ACLR-n Bit
Alarm Source
Figure 93. Clearing DAC-n
The device is implemented with two external control lines, the DAC-CLR-0 and DAC-CLR-1 pins, to clear the
DACs. When either pin goes low, the corresponding user-selected DACs are in a cleared state. The HW_DAC-
CLR-0 register determines which DAC is cleared when the DAC-CLR-0 pin is low. The register contains 12 clear
bits (CLR-n), one per DAC. If the CLR-n bit is '1', DAC-n is in a cleared state when the DAC-CLR-0 pin is low.
However, if the CLR-n bit is '0', DAC-n does not change when the pin is low. Likewise, the HW-DAC-CLR-1
register determines which DAC is cleared when the DAC-CLR-1 pin is low.
Writing directly to the SW_DAC_CLR register puts the selected DACs in a cleared state. DACs can also be
forced into a clear state by alarm events. The AUTO-DAC-CLR-SOURCE register specifies which alarm events
force the DACs into a clear state, and the AUTO-DAC-CLR-EN register defines which DACs are forced into a
clear state. Refer to the AUTO-DAC-CLR-SOURCE register and AUTO-DAC-CLR-EN register for further details.
DAC Output Thermal Protection
A significant amount of power can be dissipated in the DAC outputs. The AMC7812B is implemented with a
thermal protection circuit that sets the THERM-ALR bit in the status register if the die temperature exceeds
+150°C. The THERM-ALR bit can be used in combination with THERM-ALR-CLR (bit 2 in the AUTO-DAC-CLR-
SOURCE register) and ACLR-n (bits[14:3] in the AUTO-DAC-CLR-EN register) to set the DAC output to a
predefined code when this condition occurs. Note that this feature is disabled when the local temperature sensor
powers down.
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Alarm Operation
The device continuously monitors all analog inputs and temperatures in normal operation. When any input is out
of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit in
the status register is set ('1'). The global alarm bit (GALR) in AMC configuration register 0 is the OR of individual
alarms, see Figure 94. When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the alarm is
latched. The global alarm bit (GALR) maintains '1' until the corresponding error conditions subside and the alarm
status is read. The alarm bits are referred to as being latched because they remain set until read by software.
This design ensures that out-of-limit events cannot be missed if the software is polling the device periodically. All
bits are cleared when reading the status register, and all bits are reasserted if the out-of limit condition still exists
on the next monitoring cycle, unless otherwise noted.
CH0-ALR
Alarm
Status
Bits
GALR Bit
THERM-ALR
Figure 94. Global Alarm Bit
When the ALARM-LATCH-DIS bit in the alarm control register is set ('1'), the alarm bit is not latched. The alarm
bit in the status register goes to '0' when the error condition subsides, regardless of whether the bit is read or not.
When GALR is '1', the ALARM pin goes low. When the GALR bit is '0', the ALARM is high (inactive).
44
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Analog Input Out-of-Range Alarm
The device provides out-of-range detection for four individual analog inputs (CH0, CH1, CH2, and CH3), as
shown in Figure 95. When the measurement is out-of-range, the corresponding alarm bit in the status register is
set to '1' to flag the out-of-range condition. The value in the high-threshold register defines the upper bound
threshold of the Nth analog input, while the value in the low-threshold register defines the lower bound. These
two bounds specify a window for the out-of-range detection.
High-Threshold-n
Register
(upper bound)
CHn-ALR Bit
nth Analog Input
(n = 0 to 3)
Low-Threshold-n
Register
(lower bound)
Figure 95. CHn Out-of-Range Alarm
The device also has high-limit or low-limit detection for the temperature sensors (D1, D2, and LT), as shown in
Figure 96. To implement single, upper-bound threshold detection for analog input CHn, the host processor can
set the upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lower-
bound threshold detection, the host processor can set the lower-bound threshold to the desired value and the
upper-bound threshold to the default value. Note that the value of the high-threshold register must not be less
than the value of the low-threshold register; otherwise, ALR-n is always set to '1' and the alarm indicator is
always active. Each temperature sensor has two alarm bits: High-ALR (high-limit alarm) and Low-ALR (low-limit
alarm).
High-Threshold
(upper bound)
High-ALR Bit
Temperature Data
(D1, D2, LT)
Low-ALR Bit
Low-Threshold
(lower bound)
Figure 96. Temperature Out-of-Range Alarm
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ALARM pin
The ALARM pin is a global alarm indicator. ALARM is an open-drain pin, as Figure 97 illustrates; an external
pull-up resistor is required. When the pin is activated, it goes low. When the pin is inactive, it is in Hi-Z status.
The ALARM pin functions as an interrupt to the host so that it may query the status register to determine the
alarm source. Any alarm event (including analog inputs, temperatures, diode status, and device thermal
condition) activates the pin if the alarm is not masked (the corresponding EALR bit in the alarm control register is
'1'). When the alarm pin is masked (EN-ALARM bit is '0'), the occurrence of the event sets the corresponding
status bit in status register to '1', but does not activate the ALARM pin.
CH0-ALR Bit
ALARM
EALR-CH0 Bit
G1
D2-FAIL-ALR Bit
EALR-D2-FAIL Bit
THERM-ALR Bit
EN-ALARM Bit
Figure 97. ALARM Pin
When the ALARM-LATCH-DIS bit in the alarm control register is cleared ('0'), the alarm is latched. Reading the
status register clears the alarm status bit. Whenever an alarm status bit is set, indicating an alarm condition, the
bit remains set until the event that caused the alarm is resolved and the status register is read. The alarm bit can
only be cleared by reading the status register after the event is resolved, or by a hardware reset, software reset,
or power-on reset (POR). All bits are cleared when reading the status register, and all bits are reasserted if the
out-of-limit condition still exists after the next conversion cycle, unless otherwise noted. When the ALARM-
LATCH-DIS bit in the alarm control register is set ('1'), the ALARM pin is not latched. The alarm bit clears to '0'
when the error condition subsides, regardless of whether the bit is read or not.
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Hysteresis
The device continuously monitors the analog input channels and temperatures. If any alarms are out of range
and the alarm is enabled, the alarm bit is set ('1'). However, the alarm condition is cleared only when the
conversion result returns to a value of at least hys below the value of the high threshold register, or hys above
the value of low threshold register. The hysteresis registers store the value for each analog input (CH0, CH1,
CH2, and CH3) and temperature (D1, D2, and LT). hys is the value of hysteresis that is programmable: 0 LSB to
127 LSB for analog inputs, and 0°C to +31°C for temperatures. For the THERM-ALR bit, the hysteresis is fixed at
8°C. The hysteresis behavior is shown in Figure 98.
High Threshold
Hysteresis
Input
Hysteresis
Low Threshold
Over High Alarm
Below Low Alarm
Figure 98. Hysteresis
False-Alarm Protection
As noted previously, the device continuously monitors all analog inputs and temperatures in normal operation.
When any input is out of the specified range in N consecutive conversions, the corresponding alarm bit is set
('1'). If the input returns to the normal range before N consecutive times, the alarm bit remains clear ('0'). This
design avoids false alarms.
The number N is programmable by the CH-FALR-CT-[2:0] bits in AMC configuration register 1 for analog input
CHn as shown in Table 6, or by the TEMP-FALR-CT-[1:0] bits for temperature monitors as shown in Table 7.
Table 6. Consecutive Sample Number for False Alarm Protection for CHn
N CONSECUTIVE SAMPLES
CH-FALR-CT-2
CH-FALR-CT-1
CH-FALR-CT-0
BEFORE ALARM IS SET
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
4
8
16 (default)
32
64
128
256
Table 7. Consecutive Sample Number for False Alarm Protection for Temperature Channels
TEMP-FALR-CT-1
TEMP-FALR-CT-0
N CONSECUTIVE SAMPLES BEFORE ALARM IS SET
0
0
1
1
0
1
0
1
1
2
4 (default)
8
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GENERAL-PURPOSE INPUT AND OUTPUT PINS (GPIO-0 to GPIO-7)
The device has eight GPIO pins. The GPIO-0, -1, -2 and -3 pins are dedicated to general, bidirectional, digital I/O
signals. GPIO-4, GPIO-5, GPIO-6, and GPIO-7 are dual-function pins and can be programmed as either
bidirectional digital I/O pins or remote temperature sensors D1 and D2. When D1 or D2 is disabled, the pins
function as GPIOs. These pins can receive an input or produce an output. When the GPIO-n pin functions as an
output, it has an open-drain and the status is determined by the corresponding GPIO-n bit of the GPIO register.
The output state is high impedance when the GPIO-n bit is set to '1', and is logic low when the GPIO-n bit is
cleared ('0'). Note that a 10-kΩ pull-up resistor is required when using the GPIO-n pin as an output, see
Figure 99. The dual-function GPIO-4, -5, -6, and -7 pins should not be tied to a pull-up voltage that exceeds the
AVDD supply. The dedicated GPIO-0, -1, -2, and -3 pins are only restricted by the absolute maximum voltage. To
use the GPIO-n pin as an input, the corresponding GPIO-n bits in the GPIO register must be set to '1'. When the
GPIO-n pin functions as an input, the digital value on the pin is acquired by reading the corresponding GPIO-n
bit. After a power-on reset or any forced hardware or software reset, all GPIO-n bits are set to '1', and the GPIO-
n pin goes to a high-impedance state.
V+
GPIO-n
ENABLE
GPIO-n Bit
(when writing)
GPIO-n Bit
(when reading)
Figure 99. GPIO Pins
HARDWARE RESET
Pulling the RESET pin low performs a hardware reset. When the RESET pin is low, the device enters a reset
state and all registers are set to the default values (including the power-down register). Therefore, all function
blocks (except the internal temperature sensor) are in power-down mode. On the RESET rising edge, the device
returns to the normal operating mode. After returning to this mode, all registers remain set to the default value
until a new value is written. Note that after reset, the power-down register must be properly written in order to
activate the device. Hardware reset should only be issued when DVDD reaches the minimum specification of 2.7
V or above.
SOFTWARE RESET
Software reset returns all register settings to their default values and can be performed by writing to the software
reset register. In the case of I2C communication, any value written to this register results in a reset condition. In
the case of SPI communications, only writing the specific value of 6600h to this register resets the device. See
the Registers section for details. During reset, all communication is blocked. After issuing the reset, wait at least
30 µs before attempting to resume communication.
POWER-ON RESET (POR)
When powered on, the internal POR circuit invokes a power-on reset, which performs the equivalent function of
the RESET pin. To ensure a POR, DVDD must start from a level below 750 mV.
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POWER-SUPPLY SEQUENCE
The preferred (not required) order for applying power is IOVDD, DVDD/AVDD, and then AVCC. All registers
initialize to the default values after these supplies are established. Communication with the device is valid after a
250-µs maximum power-on reset delay. The default state of all analog blocks is off as determined by the power-
down register (6Bh). Before writing to this register, a hardware reset should be issued to ensure specified device
operation. Device communication is valid after a maximum 250-µs reset delay from the RESET rising edge. If
DVDD falls below 2.7 V, the minimum supply value of DVDD, either issue a hardware or power-on reset in order
to resume proper operation.
To avoid activating the device ESD protection diodes, do not apply the GPIO-4, GPIO-5, GPIO-6, and GPIO-7
inputs before the AVDD is established. Also, if using the external reference configuration of the ADC, do not
apply ADC-REF-IN/CMP before AVDD.
PRIMARY COMMUNICATION INTERFACE
The device communicates with the system controller through the primary communication interface, which can be
configured as either an I2C-compatible two-wire bus or an SPI bus. When the SPI/I2C pin is tied to ground, the
I2C interface is enabled and the SPI is disabled. When the SPI/I2C pin is tied to IOVDD, the I2C interface is
disabled and the SPI is enabled.
I2C-Compatible Interface
This device uses a two-wire serial interface compatible with the I2C-bus specification, version 2.1. The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA
and SCL. A master device, usually a microcontroller or a digital signal processor (DSP), controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the start and stop of data transfers. A slave device receives and transmits data on the
bus under control of the master device. The AMC7812B functions as a slave and supports the following data
transfer modes, as defined in the I2C-bus specification: standard mode (100 kbps), fast mode (400 kbps), and
high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same;
therefore, they are referred to as F/S mode in this document. The protocol for high-speed mode is different from
the F/S mode, and is referred to as Hs mode. The device supports 7-bit addressing. However 10-bit addressing
and general-call addressing are not supported. The device slave address is determined by the status of pins A0,
A1, and A2, as shown in Table 8.
Table 8. Slave Addresses
A0
A1
A2
SLAVE ADDRESS
1100001
GND
GND
GND
GND
GND
IOVDD
GND
0101100
GND
IOVDD
IOVDD
GND
1100100
GND
IOVDD
GND
0101110
IOVDD
IOVDD
IOVDD
IOVDD
1100010
GND
IOVDD
GND
0101101
IOVDD
IOVDD
1100101
IOVDD
0101111
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F/S-Mode Protocol
The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high; see Figure 2. All I2C-compatible devices must recognize a
start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read or write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition
requires that the SDA line is stable during the entire high period of the clock pulse (see Figure 2). All devices
recognize the address sent by the master and compare the address to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. When this acknowledge is detected, the master recognizes
that a communication link is established with a slave.
The master generates further SCL cycles to either transmit data to the slave (R/W bit is '1') or receive data from
the slave (R/W bit is '0'). In either case, the receiver must acknowledge the data sent by the transmitter.
Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which
one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue
as long as necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-to-
high while the SCL line is high (see Figure 2). This action releases the bus and stops the communication link
with the addressed slave. All I2C-compatible devices must recognize the stop condition. When a stop condition is
received, all devices recognize that the bus is released and wait for a start condition followed by a matching
address.
Hs-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx. This
transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the Hs
master code, but all devices must recognize the Hs master code and switch their internal setting to support 3.4
Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as for F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all internal settings of the slave
devices to support F/S mode. Note that instead of using a stop condition, repeated start conditions are used to
secure the bus in Hs mode.
Address Pointer
The AMC7812B address pointer register is an 8-bit register. Each register has an address and, when accessed,
the address pointer points to the register address. All AMC7812B registers are 16 bits, consisting of a high byte
(D[15:8]) and a low byte (D[7:0]). The high byte is always accessed first, and the low byte accessed second.
When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During
a write operation, the new content does not take effect until the low byte is written. In read operation, the whole
register value is frozen until the low byte is read.
The address pointer does not change after the current register is accessed. To change the pointer, the master
issues a slave address byte with the R/W bit low, followed by the pointer register byte; no additional data are
required.
Timeout Function
The device resets the serial interface if either SCL or SDA are held low for 32.8 ms (typical) between a START
and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START
condition. To avoid activating the timeout function, a communication speed of at least 1 kHz for the SCL
operating frequency must be maintained.
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Device Communication Protocol for I2C
The device uses the following I2C protocols: writing a single word of data to a 16-bit register, writing multiple
words to different registers, reading a single word from any register, and reading the same register multiple
times. This section discusses these I2C protocols.
Writing a Single Word of Data to a 16-Bit Register (Figure 100)
Figure 100 shows a diagram of this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends a data byte of the high byte of the register (D[15:8]).
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master sends a data byte of the low byte of the register (D[7:0]).
9. The AMC7812B asserts an acknowledge signal on SDA.
10. The master asserts a stop condition to end the transaction.
Register Pointer
(Register Address)
High Byte to
Device Register
Low Byte to
Device Register
Device
Slave Address
S
0
A
A
A
A
P
A = Acknowledge
From Master to Slave
From Slave to Master
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 100. Write Single Byte
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Writing Multiple Words to Different Registers (Figure 101)
A complete word must be written to a register (high byte and low byte) for proper operation, as shown in
Figure 101. Steps for this process are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends the first register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends the high byte of the data word to the first register.
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master sends the low byte of the data word to the first register.
9. The AMC7812B asserts an acknowledge signal on SDA.
10. The master sends a second register address.
11. The AMC7812B asserts an acknowledge signal on SDA.
12. The master then sends the high byte of the data word to the second register.
13. The AMC7812B asserts an acknowledge on SDA.
14. The master sends the low byte of the data word to the second register.
15. The AMC7812B asserts an acknowledge signal on SDA.
16. The master and the AMC7812B repeat steps 4 to 15 until the last data are transferred.
17. The master then asserts a stop condition to end the transaction.
Register Pointer
(1st Register Address)
High Byte of Data to
1st Register
Low Byte of Data to
1st Register
Device
Slave Address
S
0
A
A
A
A
A
A
A
A
A
A
Register Pointer
(2nd Register Address)
High Byte of Data to
2nd Register
Low Byte of Data to
2nd Register
Register Pointer
(Last Register Address)
High Byte of Data to
Last Register
Low Byte of Data to
Last Register
P
A = Acknowledge
From Master to Slave
From Slave to Master
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 101. Write to Multiple 16-Bit Registers
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Reading a Single Word from Any Register (Figure 102)
Figure 102 shows a diagram of this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master device asserts a restart condition.
7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a
read operation.
8. The AMC7812B asserts an acknowledge signal on SDA.
9. The AMC7812B then sends the high byte of the register (D[15:8]).
10. The master asserts an acknowledge signal on SDA.
11. The AMC7812B sends the low byte of the register (D[7:0]).
12. The master asserts a not acknowledge signal on SDA.
13. The master then asserts a stop condition to end the transaction.
Register Pointer
(Register Address)
Device
Slave Address
Device
Slave Address
S
0
A
A
Sr
1
From High Byte of
Device Register
From Low Byte of
Device Register
A
A
N
P
A = Acknowledge
From Master to Slave
From Slave to Master
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 102. Read a Single Word
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Reading the Same Register Multiple Times (Figure 103 and Figure 104)
Figure 103 and Figure 104 illustrate the process for this protocol. Steps for this protocol are:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends a register address.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master device asserts a restart condition.
7. The master then sends the 7-bit AMC7812B slave address followed by a '1' for the direction bit, indicating a
read operation.
8. The AMC7812B asserts an acknowledge signal on SDA.
9. The AMC7812B then sends the high byte of the register (D[15:8]).
10. The master asserts an acknowledge signal on SDA.
11. The AMC7812B sends the low byte of the register (D[7:0]).
12. The master asserts an acknowledge signal on SDA.
13. The AMC7812B and the master repeat steps 9 to 12 until the low byte of last reading is transferred.
14. After receiving the low byte of the last register, the master asserts a not acknowledge signal on SDA.
15. The master then asserts a stop condition to end the transaction.
Register Pointer
(Register Address)
Device
Slave Address
Device
Slave Address
S
0
A
A
A
A
Sr
1
High Byte of Register;
1st Reading
Low Byte of Register;
1st Reading
A
A
N
High Byte of Register;
Last Reading
Low Byte of Register;
Last Reading
P
A = Acknowledge
From Master to Slave
From Slave to Master
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 103. Read Multiple Words
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Register Pointer
(1st Register Address)
Device
Slave Address
Device
Slave Address
S
S
S
0
0
0
A
A
A
A
A
A
A
A
A
A
A
A
Sr
Sr
Sr
1
P
1
High Byte of
1st Register
Low Byte of
1st Register
N
N
N
Register Pointer
(2nd Register Address)
Device
Slave Address
Device
Slave Address
High Byte of
2nd Register
Low Byte of
2nd Register
P
1
Register Pointer
(Last Register Address)
Device
Slave Address
Device
Slave Address
High Byte of the Last
Register being Read
Low Byte of the Last
Register being Read
P
A = Acknowledge
From Master to Slave
From Slave to Master
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
Figure 104. Read Multiple Registers Using the Reading Single Word from Any Register Method
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Serial Peripheral Interface (SPI)
The AMC7812B can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50
MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication
command consists of a read or write (R/W) bit, seven register address bits, and 16 data bits (as shown in
Table 9), for a total of 24 bits. The timing for this operation is shown in the SPI timing diagrams (Figure 3,
Figure 4, and Figure 5).
SPI Shift Register
The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control
of the serial clock input, SCLK. The CS falling edge starts the communication cycle. Data are latched into the SPI
shift register on the SCLK falling edge, while CS is low. When CS is high, the SCLK and SDI signals are blocked
out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded into the
device internal register on the CS rising edge (with delay). During the transfer, the command is decoded and new
data are transferred into the proper registers.
The serial interface functions with both a continuous and non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock to
latch the data.
AMC7812B Communications Command for SPI
The AMC7812B is entirely controlled by registers. Reading from and writing to these registers is accomplished by
issuing a 24-bit operation word shown in Table 9.
Table 9. 24-Bit Word Structure for Read/Write Operation
OPERATION
I/O
BIT 23 (MSB)
BIT22:BIT16
BIT15:BIT0
SDI
0 (R/W)
Addr[6:0]
Data to be written
Write
Undefined or data depending on the
previous frame
SDO
SDI
Data are undefined
1 (R/W)
Data are undefined
Addr[6:0]
Don't care
Read frame 1
Read frame 2
Undefined or data depending on the
previous frame
SDO
Data are undefined
Data are undefined
SDI
1 (R/W)
Addr[6:0]
Don't care
SDO
Data are undefined
Data are undefined
Data for address specified in frame 1
Bit 23
R/W. Indicates a read from or a write to the addressed register.
0 = The write operation is set and data are written to the specified register
1 = A read operation where bits Addr[6:0] select the register to be read. The remaining bits are don't care. Data read from
the selected register appear on the SDO pin in the next SPI cycle.
Bits[22:16]
Bits[15:0]
Addr6:Addr0. Register address; specifies which register is accessed.
DATA. 16-bit data bits.
In a write operation, these bits are written to bits[15:0] of the register with the address of (Addr[6:0]).
In a read operation, these bits are determined by the previous operation. If the previous operation is a read, these bits are
from bits[15:0] of the internal register specified in previous read operation. If the previous operation is a write, these data
bits are don’t care (undefined). Data read from the current read operation appear on SDO in the next operation cycle.
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Standalone Operation
In standalone mode, as shown in Figure 105, each device has its own SPI bus. The serial clock can be
continuous or gated. The first CS falling edge starts the operation cycle. Exactly 24 falling clock edges must be
applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than
24 SCLK falling edges are applied before CS is brought high, then the input data are incorrect. The device input
register is updated from the shift register on the CS rising edge, and data are automatically transferred to the
addressed registers as well. In order for another serial transfer to occur, CS must be brought low again.
Figure 106 and Figure 107 show write and read operations in standalone mode.
Figure 105. Standalone Operation
CS
SDI
W0
W1
W2
W3
SDO
XX
XX
XX
XX
Wn = Write Command for Register N
XX = Don’t care, undefined
Figure 106. Write Operation in Standalone Mode
CS
Any Command
D3
SDI
R0
R3
R1
R2
XX
D0
D1
D2
SDO
Rn = Read Command for Register N
Dn = Data from Register N
XX = Don’t care, undefined
Figure 107. Read Operation in Standalone Mode
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Daisy-Chain Operation
For systems that contain several AMC7812Bs, the SDO pin can be used to daisy-chain multiple devices
together. This daisy-chain feature is useful in reducing the number of serial interface lines. The first CS falling
edge starts the operation cycle. SCLK is continuously applied to the input shift register when CS is low.
If more than 24 clock pulses are applied, data ripple out of the shift register and appear on the SDO line. These
data are clocked out on the SCLK rising edge and are valid on the falling edge. By connecting the SDO output of
the first device to the SDI input of the next device in the chain, a multiple-device interface is constructed. Each
device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N,
where N is the total number of AMC7812Bs in the daisy chain. When the serial transfer to all devices is
complete, CS is taken high. This action transfers data from the SPI shifter registers to the internal register of
each AMC7812B in the daisy-chain and prevents any further data from being clocked in. The serial clock can be
continuous or gated. A continuous SCLK source can only be used if CS is held low for the correct number of
clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and
CS must be taken high after the final clock in order to latch the data. Figure 108 to Figure 111 illustrate the daisy-
chain operation.
C
B
A
SDI
SDI-C
SDO-C
SDI-B
SDO-B
SDI-A
SDO-A
SDO
CS
SCLK
Figure 108. Three AMC7812Bs in a Daisy-Chain Configuration
Cycle 0
Cycle 1
Cycle 2
Cycle 3
CS
SDI-C
SDO-C
SDI-B
RA0
XX
XX
XX
XX
XX
RB0
RA0
RA0
XX
RC0
RB0
RB0
RA0
RA0
XX
RA1
CD0
CD0
BD0
BD0
AD0
RB1
RA1
RA1
CD0
CD0
BD0
RC1
RB1
RB1
RA1
RA1
CD0
RA2
CD1
CD1
BD1
BD1
AD1
RB2
RA2
RA2
CD1
CD1
BD1
RC2
RB2
RB2
RA2
RA2
CD1
RA3
CD2
CD2
BD2
BD2
AD2
RB3
RA3
RA3
CD2
CD2
BD2
RC3
RB3
RB3
RA3
RA3
CD2
SDO-B
SDI-A
XX
XX
SDO-A
RAn (RBn, RCn) = Read Command for Register N of device A (B,C)
ADn (BDn, CDn) = Data from Register N of device A (B, C)
XX = Don’t care, undefined
Figure 109. Reading Multiple Registers
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Cycle 0
Cycle 1
Cycle 2
Cycle 3
CS
SDI-C
SDO-C
SDI-B
RA0
XX
XX
XX
XX
XX
WB0
RA0
RA0
XX
RC0
WB0
WB0
RA0
RA0
XX
RA1
CD0
CD0
XX
WB1
RA1
RA1
CD0
CD0
XX
WC1
WB1
WB1
RA1
RA1
CD0
RA2
XX
RB2
RA2
RA2
XX
RC2
RB2
RB2
RA2
RA2
XX
RA3
CD2
CD2
BD2
BD2
AD2
RB3
RA3
RA3
CD2
CD2
BD2
RC3
RB3
RB3
RA3
RA3
CD2
XX
SDO-B
SDI-A
XX
XX
XX
XX
XX
SDO-A
AD0
XX
AD1
XX
WBn (WCn) = Write Command for Register N of device A (B,C)
RAn (RBn, RCn) = Read Command for Register N of device A (B, C)
ADn (BDn, CDn) = Data from Register N of device A (B, C)
XX = Don’t care, undefined
Figure 110. Mixed Operation: Reading Devices A and C, and Writing to Device B; then Reading A, and
Writing to B and C; then Reading A, B, and C Twice
Cycle 0
Cycle 1
Cycle 2
Cycle 3
CS
SDI-C
WA0
XX
WB0
WA0
WA0
XX
RC0
WB0
WB0
WA0
WA0
XX
WA1
CD0
CD0
XX
WB1
WA1
WA1
CD0
CD0
XX
RC1
WB1
WB1
WA1
WA1
CD0
WA2
CD1
CD1
XX
WB2
WA2
WA2
CD1
CD1
XX
RC2
WB2
WB2
WA2
WA2
CD1
WA3
CD2
CD2
XX
WB3
WA3
WA3
CD2
CD2
XX
RC3
WB3
WB3
WA3
WA3
CD2
SDO-C
SDI-B
SDO-B
SDI-A
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
SDO-A
Figure 111. Writing to Devices A and B, and Reading Device C
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REGISTERS
REGISTER MAP
The AMC7812B has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8-
bit register pointer points to the proper register. The pointer does not change after an operation. Table 10 lists
the registers for the AMC7812B. Note that the default values are for SPI operation; see the Register Descriptions
section for I2C default values.
Table 10. Register Map
ADDRESS
(HEX)
DEFAULT
(HEX)
ADDRESS
(HEX)
DEFAULT
(HEX)
R/W
R
REGISTER
LT-temperature-data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
REGISTER
DAC-6-CLR-setting
00
01
02
0A
0B
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
0000
0000
0000
003C(1)
0007(1)
0000(1)
0000(1)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
7C
0000
0000
0000
0000
0000
0000
00FF
2000
0070
0000
0000
0000
0000
FFFF
0004
0000
0000
0000
0000
0000
0000
0FFF
0000
0FFF
0000
0FFF
0000
0FFF
0000
07FF
0800
07FF
0800
07FF
0800
0810
0810
2108
0000
1221
N/A
R
D1-temperature-data
D2-temperature-data
Temperature configuration
Temperature conversion rate
η-factor correction (for D1)
η-factor correction (for D2)
ADC-0-data
DAC-7-CLR-setting
DAC-8-CLR-setting
DAC-9-CLR-setting
DAC-10-CLR-setting
DAC-11-CLR-setting
GPIO
R
R/W
R/W
R/W
R/W
R
AMC configuration 0
AMC configuration 1
Alarm control
R
ADC-1-data
R
ADC-2-data
R
ADC-3-data
Status
R
ADC-4-data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
ADC channel 0
R
ADC-5-data
ADC channel 1
R
ADC-6-data
ADC gain
R
ADC-7-data
AUTO-DAC-CLR-SOURCE
AUTO-DAC-CLR-EN
SW-DAC-CLR
R
ADC-8-data
R
ADC-9-data
R
ADC-10-data
HW-DAC-CLR-EN-0
HW-DAC-CLR-EN-1
DAC configuration
DAC gain
R
ADC-11-data
R
ADC-12-data
R
ADC-13-data
R
ADC-14-data
Input-0-high-threshold
Input-0-low-threshold
Input-1-high-threshold
Input-1-low-threshold
Input-2-high-threshold
Input-2-low-threshold
Input-3-high-threshold
Input-3-low-threshold
LT-high-threshold
LT-low-threshold
D1-high-threshold
D1-low-threshold
D2-high-threshold
D2-low-threshold
Hysteresis-0
R
ADC-15-data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAC-0-data
DAC-1-data
DAC-2-data
DAC-3-data
DAC-4-data
DAC-5-data
DAC-6-data
DAC-7-data
DAC-8-data
DAC-9-data
DAC-10-data
DAC-11-data
DAC-0-CLR-setting
DAC-1-CLR-setting
DAC-2-CLR-setting
DAC-3-CLR-setting
DAC-4-CLR-setting
DAC-5-CLR-setting
Hysteresis-1
Hysteresis-2
Power-down
Device ID
R/W
Software reset
(1) See register descriptions for I2C default values.
60
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REGISTER DESCRIPTIONS
Temperature Data Registers (Read-Only)
In twos complement format, 0.125°C/LSB.
LT-Temperature-Data Register (Address = 00h, Default 0000h, 0°C)
Store the local temperature sensor reading in twos complement data format.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
LT-4
BIT 7
LT-3
BIT 6
LT-2
BIT 5
LT-1
BIT 4
LT-0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
LT-11 LT-10 LT-9 LT-8 LT-7 LT-6 LT-5
0
D1-Temperature-Data Register (Address = 01h, Default 0000h, 0°C)
Store the remote temperature sensor D1 reading in twos complement data format.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
D1-4
BIT 7
D1-3
BIT 6
D1-2
BIT 5
D1-1
BIT 4
D1-0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
D1-11 D1-10 D1-9 D1-8 D1-7 D1-6 D1-5
0
D2-Temperature-Data Register (Address = 02h, Default 0000h, 0°C)
Store the remote temperature sensor D2 reading in twos complement data format.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
D2-4
BIT 7
D2-3
BIT 6
D2-2
BIT 5
D2-1
BIT 4
D2-0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
D2-11 D2-10 D2-9 D2-8 D2-7 D2-6 D2-5
0
Temperature Configuration Register (Read or Write, Address = 0Ah)
When using the SPI, the following bit configuration must be used; default = 003Ch.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
0
BIT 6
0
BIT 5
BIT 4
BIT 3
BIT 2
RC
BIT 1
0
BIT 0
0
0
0
0
0
0
0
D2EN D1EN LTEN
0
When using the I2C interface, the following bit configuration must be used; default = 3CFFh.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
1
BIT 6
1
BIT 5
1
BIT 4
1
BIT 3
1
BIT 2
1
BIT 1
1
BIT 0
0
0
D2EN D1EN LTEN RC
0
1
Bit descriptions for this register are shown in Table 11.
Table 11. Temperature Configuration Register Bit Descriptions
NAME
DEFAULT
R/W
DESCRIPTION
Remote temperature sensor D2 enable.
D2EN
1
R/W
0 = D2 is disabled
1 = D2 is enabled
Remote temperature sensor D1 enable.
0 = D1 is disabled
1 = D1 is enabled
D1EN
LTEN
RC
1
1
1
R/W
R/W
R/W
Local temperature sensor enable.
0 = LT is disabled
1 = LT is enabled
Resistance correction enable.
0 = Correction is disabled
1 = Correction is enabled
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Temperature Conversion Rate Register (Read or Write, Address = 0Bh)
When using the SPI, the following bit configuration must be used; default = 0007h.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
R2
BIT 1
R1
BIT 0
0
0
0
0
0
0
0
R0
When using the I2C interface, the following bit configuration must be used; default = 07FFh.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
R0
BIT 7
1
BIT 6
1
BIT 5
1
BIT 4
1
BIT 3
1
BIT 2
1
BIT 1
1
BIT 0
0
0
0
0
0
R2 R1
1
Bit descriptions for this register are shown in Table 12.
Table 12. Temperature Conversion Time
R2
0
R1
0
R0
0
CONVERSION TIME
128x minimum
64x minimum
32x minimum
16x minimum
8x minimum
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
4x minimum
1
1
0
2x minimum
1
1
1
Minimum cycle time
Table 13. Temperature Monitoring Cycle Time
MONITORING
TEMPERATURE SENSOR STATUS
CYCLE TIME (ms)
Local sensor is active, remote sensors are disabled or in power-down.
15
44
One remote sensor is active and RC is '0', local sensor and one remote sensor are disabled or in power-down.
One remote sensor is active and RC is '1', local sensor and one remote sensor are disabled or in power-down.
One remote sensor and local sensor are active and RC is '0', one remote sensor is disabled or in power-down.
One remote sensor and local sensor are active and RC is '1', one remote sensor is disabled or in power-down.
Two remote sensors are active and RC is '0', local sensor is disabled or in power-down.
Two remote sensors are active and RC is '1', local sensor is disabled or in power-down.
All sensors are active and RC is '0'.
93
59
108
88
186
103
201
All sensors are active and RC is '1'.
62
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η-Factor Correction Register (Read or Write, Addresses = 21h and 22h)
Only the low byte is used; the high byte is ignored.
When using the SPI interface, the following bit configuration must be used; default = 0000h.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
NADJUST
When using the I2C, the following bit configuration must be used; default = 00FFh.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
1
BIT 6
1
BIT 5
1
BIT 4
1
BIT 3
1
BIT 2
1
BIT 1
1
BIT 0
NADJUST
1
The NADJUST value for ideality correction is stored as shown in Table 14. ηEFF is the actual ideality of the
transistor being used. Refer to the Ideality Factor section for further details.
Table 14. NADJUST and ηEFF Values
NADJUST
BINARY
HEX
7F
0A
08
DECIMAL
ηEFF
1.747977
1.042759
1.035616
1.028571
1.021622
1.014765
1.011371
1.008 (default)
1.004651
1.001325
0.994737
0.988235
0.981818
0.975484
0.706542
0111 1111
0000 1010
0000 1000
0000 0110
0000 0100
0000 0010
0000 0001
0000 0000
1111 1111
1111 1110
1111 1100
1111 1010
1111 1000
1111 0110
1000 0000
127
10
8
06
6
04
4
02
2
01
1
00
0
FF
FE
FC
FA
F8
F6
80
–1
–2
–4
–6
–8
–10
–128
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ADC-n-Data Registers (Read-Only, Addresses = 23h to 32h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
A8
BIT 7
A7
BIT 6
A6
BIT 5
A5
BIT 4
A4
BIT 3
A3
BIT 2
A2
BIT 1
A1
BIT 0
0
0
0
0
A11
A10
A9
A0
Bits[11:0]
ADC data.
Four ADC data registers are available. The ADC-n-data registers (where n = 0 to 15) store the conversion results
of the corresponding analog channel-n, as shown in Table 15.
Table 15. ADC Data Register Definitions
CONVERSION RESULT
INPUT CHANNEL
Channel 0
INPUT TYPE
Single-ended
Single-ended
Single-ended
Single-ended
Differential
STORED IN
FORMAT
Straight binary
Straight binary
Straight binary
Straight binary
Twos complement
Twos complement
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
Straight binary
ADC-0-data register
ADC-1-data register
ADC-2-data register
ADC-3-data register
ADC-0-data register
ADC-2-data register
ADC-4-data register
ADC-5-data register
ADC-6-data register
ADC-7-data register
ADC-8-data register
ADC-9-data register
ADC-10-data register
ADC-11-data register
ADC-12-data register
ADC-13-data register
ADC-14-data register
ADC-15-data register
Channel 1
Channel 2
Channel 3
CH0+ or CH1–
CH2+ or CH3–
Channel 4
Differential
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
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DAC-n-Data Registers (Read or Write, Addresses = 33h to 3Eh, Default 0000h)
Each DAC has a DAC data register to store the data (DAC[11:0]) that are loaded into the DAC latches.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
D8
BIT 7
D7
BIT 6
D6
BIT 5
D5
BIT 4
D4
BIT 3
D3
BIT 2
D2
BIT 1
D1
BIT 0
0
0
0
0
D11
D10
D9
D0
Bits[11:0]
DAC data.
DAC-n-CLR-Setting Registers (Read or Write, Addresses = 3Fh to 4Ah, Default 0000h)
Each DAC has a DAC-CLR-setting register to store the data to be loaded into the DAC latch when the DAC is
cleared.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
GPIO Register (Read or Write, Address = 4Bh, Default = 00FFh)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIO- GPIO- GPIO- GPIO- GPIO- GPIO- GPIO- GPIO-
7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
For write operations, the GPIO pin operates as an output. Writing a '0' sets the GPIO-n pin to logic low. An
external pull-up resistor is required when using the GPIO pin as an output. Writing a '1' to the GPIO-n bit sets the
GPIO-n pin to high impedance.
For read operations, the GPIO pin operates as an input. Read the GPIO-n bit to receive the status of the GPIO-n
pin. Reading a '0' indicates that the GPIO-n pin is low; reading a '1' indicates that the GPIO-n pin is high.
After power-on reset, or any forced hardware or software reset, the GPIO-n bit is set to '1' and is in a high-
impedance state.
When D1 is enabled, GPIO-4 and GPIO-5 are ignored.
When D2 is enabled, GPIO-6 and GPIO-7 are ignored.
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AMC Configuration Register 0 (Read or Write, Address = 4Ch, Default = 2000h)
Table 16. AMC Configuration Register 0
BIT
15
NAME
—
DEFAULT
R/W
R
DESCRIPTION
0
0
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
14
—
R
ADC conversion mode bit. This bit selects between the two operating conversion modes
(direct or auto).
0 = Direct mode. The analog inputs specified in the ADC channel registers are converted
sequentially (see the ADC channel registers) one time. When one set of conversions are
complete, the ADC is idle and waits for a new trigger.
13
CMODE
1
R/W
1 = Auto mode. The analog inputs specified in the AMC channel registers are converted
sequentially and repeatedly (see the ADC channel registers). When one set of conversions
are complete, the ADC multiplexer returns to the first channel and repeats the process.
Repetitive conversions continue until the CMODE bit is cleared ('0').
Internal conversion bit.
12
11
ICONV
ILDAC
0
0
R/W Set this bit to '1' to start the ADC conversion internally. The bit is automatically cleared ('0')
after the ADC conversion starts.
Load DAC bit.
Set this bit to '1' to synchronously load the DAC data registers, which are programmed for
synchronous update mode (SLDAC-n = 1). The AMC7812B updates the DAC latch only if
R/W the ILDAC bit is set ('1'), thereby eliminating any unnecessary glitches. Any DAC channels
that are not accessed are not reloaded. When the DAC latch is updated, the corresponding
output changes to the new level immediately. This bit is cleared ('0') after the DAC data
register is updated.
ADC VREF select bit.
0 = The internal reference buffer is off and the external reference drives the ADC.
R/W
10
ADC-REF-INT
0
1 = The internal buffer is on and the internal reference drives the ADC. Note that a
compensation capacitor is required.
Enable ALARM pin bit.
9
8
EN-ALARM
—
0
0
R/W
R
0 = The ALARM pin is disabled
1 = The ALARM pin is enabled
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
ADC Data available flag bit. For direct mode only. Always cleared (set to '0') in Auto mode.
0 = The ADC conversion is in progress (data are not ready) or the ADC is in auto mode.
1 = The ADC conversions are complete and new data are available.
In direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF is '1', and goes
high when DAVF is '0'.
In auto mode, DAVF is always cleared to '0'. However, a 1-µs pulse (active low) appears
on the DAV pin when the last input specified in the ADC channel registers is converted.
DAVF is cleared to '0' in one of three ways: by reading the ADC data register, by starting a
new ADC conversion, or by writing '0' to this bit. Reading the status register does not clear
this bit.
7
DAVF
R
Global alarm bit.
This bit is the OR function of all individual alarm bits of the status register. This bit is set
('1') when any alarm condition occurs, and remains '1' until the status register is read. This
bit is cleared ('0') after reading the status register.
6
GALR
0
R
5
4
3
2
1
0
—
—
—
—
—
—
0
0
0
0
0
0
R
R
R
R
R
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
66
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AMC Configuration Register 1 (Read or Write, Address = 4Dh, Default = 0070h)
Table 17. AMC Configuration Register 1
BIT
15
14
13
12
11
10
9
NAME
DEFAULT
R/W
R
DESCRIPTION
—
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
—
R
—
R
—
R
—
—
R
R
CONV-RATE-1
CONV-RATE-0
CH-FALR- CT-2
CH-FALR- CT-1
CH-FALR- CT-0
TEMP-FALR- CT-1
TEMP-FALR- CT-0
—
R/W ADC conversion rate bit. See Table 18.
8
R/W ADC conversion rate bit. See Table 18.
7
R/W False alarm protection bit for CH0 to CH3. See Table 19.
R/W False alarm protection bit for CH0 to CH3. See Table 19.
R/W False alarm protection bit for CH0 to CH3. See Table 19.
R/W False alarm protection bit for temperature monitor. See Table 20.
R/W False alarm protection bit for temperature monitor. See Table 20.
6
5
4
3
2
R
R
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
1
—
0
—
Table 18. CONV-RATE-[1:0] Bit Settings
CONV-RATE-1
CONV-RATE-0
ADC CONVERSION RATE
500 kSPS, the specified rate (default)
1/2 of the specified rate
0
0
1
1
0
1
0
1
1/4 of the specified rate
1/8 of the specified rate
Table 19. CH-FALR-CT-[2:0] Bit Settings
N CONSECUTIVE SAMPLES
CH-FALR-CT-2
CH-FALR-CT-1
CH-FALR-CT-0
BEFORE ALARM IS SET
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
4
8
16 (default for CH0 to CH3)
32
64
128
256
Table 20. TEMP-FALR-CT-[1:0] Bit Settings
TEMP-FALR-CT-1
TEMP-FALR-CT-0
N CONSECUTIVE SAMPLES BEFORE ALARM IS SET
0
0
1
1
0
1
0
1
1
2
4 (default)
8
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Alarm Control Register (Read or Write, Address = 4Eh, Default = 0000h)
The alarm control register determines whether the ALARM pin is accessed when a corresponding alarm event
occurs. However, this register does not affect the status bit in the status register. Note that the thermal alarm is
always enabled. When the THERM_ALR bit is '1', the ALARM pin goes low if the pin is enabled.
Table 21. Alarm Control Register
BIT
NAME
DEFAULT
R/W
DESCRIPTION
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CH0 and (CH0+, CH1–) alarm enable bit.
15
—
0
R
0 = The alarm is masked. When the input of CH0 or (CH0+, CH1–) is out of range, the
ALARM pin does not go low, but the CH0-ALR bit is set.
1 = The alarm is enabled, the CH0-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH0 or (CH0+, CH1–) is out of range.
14
13
12
11
10
9
EALR-CH0
EALR-CH1
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CH1 alarm enable bit.
0 = The alarm is masked. When the input of CH1 is out of range, the ALARM pin does not
go low, but the CH1-ALR bit is set.
1 = The alarm is enabled, the CH1-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH1 is out of range.
CH2 and (CH2+, CH3–) alarm enable bit.
0 = The alarm is masked. When the input of CH2 or (CH2+, CH3–) is out of range, the
ALARM pin does not go low, but the CH2-ALR bit is set.
1 = The alarm is enabled, the CH2-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH2 or (CH2+, CH3–) is out of range.
EALR-CH2
CH3 alarm enable bit.
0 = The alarm is masked. When the input of CH3 is out of range, the ALARM pin does not
go low, but the CH3-ALR bit is set.
1 = The alarm is enabled, the CH3-ALR bit is set, and the ALARM pin goes low (if enabled)
when the input of CH3 is out of range.
EALR-CH3
Local sensor low alarm enable bit.
0 = The LT-Low alarm is masked. When LT is below the specified range, the ALARM pin
does not go low, but the LT-Low-ALR bit is set.
1 = The LT-Low alarm is enabled. When LT is below the specified range, the LT-Low-ALR
bit is set ('1') and the ALARM pin goes low (if enabled).
EALR-LT-Low
EALR-LT-High
EALR-D1-Low
EALR-D1-High
EALR-D2-Low
EALR-D2-High
Local sensor high alarm enable bit.
0 = The LT-High alarm is masked. When LT is above the specified range, the ALARM pin
does not go low, but the LT-High-ALR bit is set.
1 = The LT-High alarm is enabled. When LT is above the specified range, the LT-High-ALR
bit is set ('1') and the ALARM pin goes low (if enabled).
D1 low alarm enable bit.
0 = The D1-Low alarm is masked. When D1 is below the specified range, the ALARM pin
does not go low, but the D1-Low-ALR bit is set.
1 = The D1-Low alarm is enabled. When D1 is below the specified range, the D1-Low-ALR
bit is set ('1'), and the ALARM pin goes low (if enabled).
8
D1 high alarm enable bit.
0 = The D1-High alarm is masked. When D1 is above the specified range, the ALARM pin
does not go low, but the D1-High-ALR bit is set.
1 = The D1-High alarm is enabled. When D1 is above the specified range, the D1-High-
ALR bit is set ('1'), and the ALARM pin goes low (if enabled).
7
D2 low alarm enable bit.
0 = The D2-Low alarm is masked. When D2 is below the specified range, the ALARM pin
does not go low, but the D2-Low-ALR bit is set.
1 = The D2-Low alarm is enabled. When D2 is below the specified range, the D2-Low-ALR
bit is set ('1'), and the ALARM pin goes low (if enabled).
6
D2 high alarm enable bit.
0 = The D2-High alarm is masked. When D2 is above the specified range, the ALARM pin
does not go low, but the D2-High-ALR bit is set.
5
1 = The D2-High alarm is enabled. When D2 is above the specified range, the D2-High-
ALR bit is set ('1'), and the ALARM pin goes low (if enabled).
68
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Table 21. Alarm Control Register (continued)
BIT
NAME
DEFAULT
R/W
DESCRIPTION
D1 fail alarm enable bit.
0 = The D1-FAIL alarm is masked. When D1 fails, the ALARM pin does not go low, but the
D1-FAIL-ALR bit is set.
1 = The D1-Fail alarm is enabled. When D1 fails, the D1-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
4
EALR-D1-FAIL
EALR-D2-FAIL
0
R/W
D2 fail alarm enable bit.
0 = The D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the
D2-FAIL-ALR bit is set.
1 = The D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is set ('1'), the
ALARM pin goes low (if enabled).
3
2
0
0
R/W
R/W
Alarm latch disable bit.
0 = The status register bits are latched. When an alarm occurs, the corresponding alarm bit
is set ('1'). The alarm bit remains '1' until the error condition subsides and the status
register is read. Before reading, the alarm bit is not cleared ('0') even if the alarm condition
disappears.
ALARM-
LATCH-DIS
1 = The status register bits are not latched. When the alarm condition subsides, the alarm
bits are cleared regardless of whether the status register is read or not.
1
0
—
—
0
0
R
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
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Status Register (Read-Only, Address = 4Fh, Default = 0000h)
The AMC7812B continuously monitors all analog inputs and temperatures during normal operation. When any
input is out of the specified range for N consecutive times, the corresponding alarm bit is set ('1'). If the input
returns to the normal range before N consecutive times, the corresponding alarm bit remains clear ('0'). This
configurations avoids any false alarms.
When an alarm status occurs, the corresponding alarm bit is set ('1'). When the ALARM-LATCH-DIS bit in the
alarm control register is cleared ('0'), the ALARM pin is latched. Whenever an alarm status bit is set, that bit
remains set until the event that caused the alarm is resolved and the status register is read. Reading the status
registers clears the alarm status bit. The alarm bit can only be cleared by reading the status register after the
event is resolved, or by hardware reset, software reset, or power-on reset. All alarm status bits are cleared when
reading the status register, and all these bits are reasserted if the out-of-limit condition still exists after the next
conversion cycle, unless otherwise noted.
When the ALARM-LATCH-DIS bit in the alarm control register is set ('1'), the ALARM pin is not latched. The
alarm bit goes to '0' when the error condition subsides, regardless of whether the bit is read or not.
Table 22. Status Register
BIT
NAME
DEFAULT
R/W
DESCRIPTION
15
—
0
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
0 = The analog input is not out of the specified range.
14
13
12
11
CH0-ALR
CH1-ALR
CH2-ALR
CH3-ALR
0
0
0
0
R
R
R
R
1 = The single-ended channel 0 or differential input pair (CH0+, CH1–) is out of the range
defined by the corresponding threshold registers.
0 = The analog input is not out of the specified range.
1 = The single-ended channel 1 is out of the range defined by the corresponding threshold
registers.
0 = The analog input is not out of the specified range.
1 = The single-ended channel 2 or differential input pair (CH2+, CH3–) is out of the range
defined by the corresponding threshold registers.
0 = The analog input is not out of the specified range.
1 = The single-ended channel 3 is out of the range defined by the corresponding threshold
registers.
Local temperature underrange flag.
0 = The local temperature is not less than the range.
1 = The local temperature is less than the low-bound threshold.
This bit is only checked when LT is enabled (EN-LT is '1'); this bit is ignored when EN-LT is
'0'.
10
9
LT-Low-ALR
LT-High-ALR
D1-Low-ALR
D1-High -ALR
D2-Low-ALR
0
0
0
0
0
R
R
R
R
R
Local temperature overrange flag.
0 = The local temperature is not greater than the range.
1 = The local temperature is greater than the high-bound threshold.
This bit is only checked when LT is enabled (EN-LT is '1'); this bit is ignored when EN-LT is
'0'.
Remote temperature reading of D1 when less than the range flag.
0 = The local temperature is not less than the range.
1 = The local temperature is less than the low-bound threshold.
This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is
'0'.
8
Remote temperature reading of D1 when greater than the range flag.
0 = The local temperature is not greater than the range.
1 = The local temperature is greater than the high-bound threshold.
This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is
'0'.
7
Remote temperature reading of D2 when less than the range flag.
0 = The local temperature is not less than the range.
1 = The local temperature is less than the low-bound threshold.
This bit is only checked when D2 is enabled (EN-D2 is '1'); this bit is ignored when EN-D2 is
'0'.
6
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Table 22. Status Register (continued)
BIT
NAME
DEFAULT
R/W
DESCRIPTION
Remote temperature reading of D2 when greater than the range flag.
0 = The local temperature is not greater than the range.
1 = The local temperature is greater than the high-bound threshold.
This bit is only checked when D2 is enabled (EN-D2 is '1'); this bit is ignored when EN-D2 is
'0'.
5
D2-High -ALR
D1-FAIL-ALR
0
R
Remote sensor D1 failure flag.
0 = The sensor is in a normal condition.
1 = The sensor is an open-circuit or short-circuit.
4
0
R
This bit is only checked when D1 is enabled (EN-D1 is '1'); this bit is ignored when EN-D1 is
'0'.
Remote sensor D2 failure flag.
0 = The sensor is in a normal condition.
1 = The sensor is an open-circuit or short-circuit.
This bit is only checked when D2 is enabled (EN-D2 is '1'); this is ignored when EN-D2 is
'0'.
3
2
D2-FAIL-ALR
THERM-ALR
0
0
R
R
Thermal alarm flag.
When the die temperature is equal to or greater than +150°C, the bit is set ('1') and the
THERM-ALR flag activates. The on-chip temperature sensor (LT) monitors the die
temperature. If LT is disabled, the THERM-ALR bit is always '0'. The hysteresis of this alarm
is 8°C.
1
0
—
—
0
0
R
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
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ADC Channel Register 0 (Read or Write, Address = 50h, Default = 0000h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DF
DF
0
SE0
SE1
(CH0+,
CH1–)
SE2
SE3
(CH2+,
CH3–)
SE4 SE5 SE6 SE7 SE8 SE9 SE10 SE11 SE12
These bits specify the external analog auxiliary input channels (CH0 to CH12) to be converted. The specified
channels are accessed sequentially in order from bit 14 to bit 0. The input is converted when the corresponding
bit is set ('1').
Bit 15
Reserved
Writing to this bit causes no change. Reading this bit returns '0'.
Bits 14, 13, 11, 10, 8:0
Bit 12
SE0 to SE12
External single-ended analog input for CHn. The result is stored in ADC-n-data register in straight binary format.
DF (CH0+, CH1–)
External analog differential input pair, CH0 and CH1, with CH0 as positive and CH1 as negative. The difference
of (CH0 – CH1) is converted and the result is stored in the ADC-0-data register in twos complement format.
Bit 9
DF(CH2+, CH3-)
External analog differential input pair, CH2 and CH3, with CH2 as positive and CH3 as negative. The difference
of (CH2 – CH3) is converted and the result is stored in the ADC-2-data register in twos complement format.
Table 23. CH0 and CH1 Bit Settings
BIT 14
BIT 13
BIT 12
DESCRIPTION
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
CH0 and CH1 are both accessed as single-ended inputs. Bit 12 is ignored.
CH0 is accessed as a single-ended input. CH1 is not accessed. Bit 12 is ignored.
CH1 is accessed as a singled-ended. CH0 is not accessed. Bit 12 is ignored.
Differential input pair CH0 + and CH1– is accessed as a differential input.
CH0, CH1, and differential pair CH0+, CH1– are not accessed.
Table 24. CH2 and CH3 Bit Settings
BIT 11
BIT 10
BIT 9
DESCRIPTION
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
CH2 and CH3 are both accessed as single-ended inputs. Bit 9 is ignored.
CH2 is accessed as a single-ended input. CH3 is not accessed. Bit 9 is ignored.
CH3 is accessed as a singled-end input. CH2 is not accessed. Bit 9 is ignored.
Differential input pair CH2+ and CH3– is accessed as a differential input.
CH2, CH3, and differential pair CH2+, CH3– are not accessed.
Table 25. CH4 to CH12 Bit Settings
BIT 8
BIT 7
—
BIT 6
BIT 5
—
BIT 4
—
BIT 3
—
BIT 2
—
BIT 1
—
BIT 0
—
DESCRIPTION
1
—
—
1
CH4 is accessed as a single-ended input
CH5 is accessed as a single-ended input
CH6 is accessed as a single-ended input
CH7 is accessed as a single-ended input
CH8 is accessed as a single-ended input
CH9 is accessed as a single-ended input
CH10 is accessed as a single-ended input
CH11 is accessed as a single-ended input
CH12 is accessed as a single-ended input
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
1
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ADC Channel Register 1 (Read or Write, Address = 51h, Default = 0000h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
0
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
SE13 SE14 SE15
0
0
0
0
These bits specify the external analog auxiliary input channels (CH13, CH14, and CH15) to be converted. The
specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC channel register 0, and then bit
14 to bit 12 of ADC channel register 1. The input is converted when the corresponding bit is set ('1').
Bits[14:12]
SEn
External single-ended analog input CHn. The result is stored in the ADC-n-data register in straight binary format.
ADC Gain Register (Read or Write, Address = 52h, Default = FFFFh)
MSB
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
LSB
BIT 0
BIT 9 BIT 8 BIT 7 BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9 ADG10 ADG11 ADG12 ADG13 ADG14 ADG15
Bit 15
ADG0
0 = The analog input range of single-ended input CH0 (SE0) is 0 V to VREF or differential input pair DF (CH0+, CH1–) is
–VREF to +VREF
1 = The analog input range of single-ended input CH0 (SE0) is 0 V to (2 × VREF) or differential input pair DF (CH0+,
CH1–) is (–2 × VREF) to (+2 × VREF
)
Bit 14
Bit 13
ADG1
0 = The analog input range of single-ended input CH1 (SE1) is 0 V to VREF
1 = The analog input range is 0 V to (2 × VREF
)
ADG2
0 = The analog input range of single-ended input CH2 (SE2) is 0 V to VREF or differential input pair DF (CH2+, CH3–) is
–VREF to +VREF
1 = The analog input range of single-ended input CH2 (SE2) is 0 V to (2 × VREF) or differential input pair DF (CH2+,
CH3–) is (–2 × VREF) to (+2 × VREF
)
Bit 12
ADG3
0 = The analog input range of single-end input CH3 (SE3) is 0 V to VREF
1 = The analog input range is 0 V to (2 × VREF
)
Bit[11:0]
ADG4 to ADG15
0 = The analog input range of CHn (where n = 4 to 15) is 0 V to VREF
1 = The analog input range is 0 V to (2 × VREF
)
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AUTO-DAC-CLR-SOURCE Register (Read or Write, Address = 53h, Default = 0004h)
This register selects which alarm forces the DAC into a clear state, regardless of which DAC operation mode is
active, auto, or manual.
Table 26. AUTO-DAC-CLR-SOURCE Register
BIT
NAME
DEFAULT
R/W
DESCRIPTION
15
—
0
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
CH0 alarm clear bit.
0 = CH1-ALR goes to '1' and does not force any DAC to a clear status
1 = DAC-n is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the CH0-ALR bit in the status register are set ('1')
14
13
12
11
10
9
CH0-ALR-CLR
CH1-ALR-CLR
CH2-ALR-CLR
CH3-ALR-CLR
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CH1 alarm clear bit.
0 = CH1-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the CH1-ALR bit in the status register are set ('1')
CH2 alarm clear bit.
0 = CH2-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the CH2-ALR bit in the status register are set ('1')
CH3 alarm clear bit.
0 = CH3-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the CH3-ALR bit in the status register are set ('1')
Local temperature sensor low alarm clear bit.
LT-Low-ALR-
CLR
0 = LT-Low-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the LT-Low-ALR bit in the status register are set ('1')
Local temperature sensor high alarm clear bit.
LT-High-ALR-
CLR
0 = LT-High-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the LT-High-ALR bit in the status register are set ('1')
Remote temperature sensor D1 low alarm clear bit.
D1-Low-ALR-
CLR
0 = D1-Low-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D1-Low-ALR bit in the status register are set ('1')
8
Remote temperature sensor D1 high alarm clear bit.
D1-High-ALR-
CLR
0 = D1-High-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D1-High-ALR bit in the status register are set ('1')
7
Remote temperature sensor D2 low alarm clear bit.
D2-Low-ALR-
CLR
0 = D2-Low-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D2-Low-ALR bit in the status register are set ('1')
6
Remote temperature sensor D2 high alarm clear bit.
D2-High-ALR-
CLR
0 = D2-High-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D2-High-ALR bit in the status register are set ('1')
5
D1 fail alarm clear bit.
0 = D1-FAIL-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D2-FAIL-ALR bit in the status register are set ('1')
4
D1-FAIL-CLR
D2-FAIL-CLR
D2 fail alarm clear bit.
0 = D2-FAIL-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the D2-FAIL-ALR bit in the status register are set ('1')
3
Thermal alarm clear bit.
THERM-ALR-
CLR
0 = THERM-ALR goes to '1' and does not force any DAC to a clear status
1 = DACn is forced to a clear status if both the ACLRn bit in the AUTO-DAC-CLR-EN
register and the THERM-ALR bit in the status register are set ('1')
2
1
0
—
—
0
0
R
R
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
Reserved. Writing to this bit causes no change. Reading this bit returns '0'.
74
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AUTO-DAC-CLR-EN Register (Read or Write, Address = 54h, Default = 0000h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0
BIT 1
0
BIT 0
ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[14:3]
ACLRn
Auto clear DAC-n enable bit.
0 = DAC-n is not forced to a clear state when the alarm occurs (default)
1 = DAC-n is forced to a clear state when the alarm occurs
NOTE
ACLRn is always ignored when an alarm occurs for a temperature greater than +150°C
(THERM-ALR is '1'). If an alarm activates for a temperature greater than +150°C, and if
the THERM-ALR-CLR bit in the AUTO-DAC-CLR-SOURCE register is set ('1'), all DACs
are forced into a clear status. However, if THERM-ALR-CLR is cleared ('0'), the over
+150°C alarm does not force any DAC to a clear status.
SW-DAC-CLR Register (Read or Write, Address = 55h, Default = 0000h)
This register uses software to force the DAC into a clear state.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
0
BIT 1
0
BIT 0
ICLR
11
ICLR
10
ICLR
9
ICLR
8
ICLR
7
ICLR
6
ICLR
5
ICLR
4
ICLR
3
ICLR
2
ICLR
1
ICLR
0
0
0
Bits[14:3]
ICLRn
Software clear DACn bit.
0 = DACn is restored to normal operation
1 = DACn is forced into a clear state
HW-DAC-CLR-EN 0 Register (Read or Write, Address = 56h, Default = 0000h)
This register determines which DAC is in a clear state when the DAC-CLR-0 pin goes low.
MSB
BIT
LSB
BIT BIT BIT
15
BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR
11 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
2
1
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Bits[14:3]
H0CLRn: Hardware clear DAC-n enable 1 bit.
If H0CLRn = '1', DAC-n is forced into a clear state when the DAC-CLR-0 pin goes low.
If H0CLRn = '0', pulling the DAC-CLR-0 pin low does not effect the state of DAC-n.
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HW-DAC-CLR-EN 1 Register (Read or Write, Address = 57h, Default = 0000h)
This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.
MSB
BIT
LSB
BIT BIT BIT
15
BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
2
1
0
H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[14:3]
H1CLRn
Hardware clear DAC-n enable 1 bit.
0 = Pulling the DAC-CLR-1 pin low does not effect the state of DAC-n
1 = DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low
DAC Configuration Register (Read or Write, Address = 58h, Default = 0000h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA
11 10
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Bits[11:0]
SLDA-n
DAC synchronous load enable bit.
0 = Asynchronous load is enabled. A write command to the DAC-n-data register immediately updates the DAC-n latch
and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default value of SLDA-n
is '0'. The device updates the DAC latch only if the ILDAC bit is set ('1'), thereby eliminating unnecessary glitches. Any
DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output
changes to the new level immediately. Note that the SLDA-n bit is ignored in auto mode (DAC-n mode bits do not equal
'00'). In auto mode, the DAC latch is always updated asynchronously.
1 = Synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n latch is loaded with the value
of the corresponding DACn-data register, and the output of DAC-n is updated immediately. The internal load DAC signal
ILDAC is generated by writing a '1' to the ILDAC bit in the AMC configuration register. In synchronous load, a write
command to the DAC-n-data register updates that register only, and does not change the DAC-n output.
NOTE
The DACs can be forced to a clear state immediately by the external DAC-CLR-n signal,
by alarm events, and by writing to the SW-DAC-CLR register. In these cases, the SLDA-n
bit is ignored.
DAC Gain Register (Read or Write, Address = 59h, Default = 0000h)
The DACn GAIN bits specify the output range of DACn.
MSB
LSB
BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
DAC11 DAC10 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN
0
0
0
0
Bits[11:0]
DACnGAIN: DACn gain bits.
1 = Gain is 5 and the output is 0 V to 5 × VREF
0 = Gain is 2 and the output is 0 V to 2 × VREF
76
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Analog Input Channel Threshold Registers (Read or Write, Addresses = 5Ah to 61h)
Four analog auxiliary inputs (CH0, CH1, CH2, and CH3) and three temperature sensors (LT, D1, and D2)
implement an out-of-range alarm function. Threshold-High-n and Threshold-Low-n (where n = 0, 1, 2, 3) define
the upper bound and lower bound of the nth analog input range, as shown in Table 27. This window determines
whether the nth input is out-of-range. When the input is outside the window, the corresponding CH-ALR-n bit in
the status register is set to '1'.
For normal operation, the value of Threshold-High-n must be greater than the value of Threshold-Low-n;
otherwise, CH-ALR-n is always set to '1' and an alarm is always indicated. Note that when the analog channel is
accessed as single-ended input, its threshold is in a straight binary format. However, when the channel is
accessed as a differential pair, its threshold is in twos complement format.
Table 27. Threshold Coding
INPUT CHANNEL
INPUT TYPE
THRESHOLD STORED IN
FORMAT
Input-0-Threshold-High-Byte
Input-0-Threshold-Low-Byte
Channel 0
Single-ended
Straight binary
Input-1-Threshold-High-Byte
Input-1-Threshold-Low-Byte
Channel 1
Channel 2
Single-ended
Single-ended
Single-ended
Differential
Straight binary
Straight binary
Input-2-Threshold-High-Byte
Input-2-Threshold-Low-Byte
Input-3-Threshold-High-Byte
Input-3-Threshold-Low-Byte
Channel 3
Straight binary
Input-0-Threshold-High-Byte
Input-0-Threshold-Low-Byte
CH0+, CH1–
CH2+, CH3–
Twos complement
Twos complement
Input-2-Threshold-High-Byte
Input-2-Threshold-Low-Byte
Differential
Input-n-High-Threshold Register (where n = 0, 1, 2, 3) (Read or Write, Default = 0FFFh)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12]
Bits[11:0]
Reserved
These bits are '0' when read back. Writing to these bits has no effect.
THRHn
Data bits of the upper-bound threshold of the nth analog input.
Input-n-Low-Threshold Register (where n = 0, 1, 2, 3) (Read or Write, Default = 0000h)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL
11 10
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Bits[15:12]
Bits[11:0]
Reserved
These bits are '0' when read back. Writing to these bits has no effect.
THRLn
Data bits of the lower-bound threshold of the nth analog input.
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Temperature Threshold Registers
LT-High-Threshold Register (Read or Write, Address = 62h, Default = 07FFh, +255.875°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are ‘0' when read back. Writing these bits causes no change
LT-Low-Threshold Register (Read or Write, Address = 63h, Default = 0800h, –256°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are reserved. Writing to these bits causes no change. Reading these bits returns '0'.
D1-High-Threshold Register (Read or Write, Address = 64h, Default = 07FFh, +255.875°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are ‘0' when read back. Writing these bits causes no change.
D1-Low-Threshold Register (Read or Write, Address = 65h, Default = 0800h, –256°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are ‘0' when read back. Writing these bits causes no change.
D2-High-Threshold Register (Read or Write, Address = 66h, Default = 07FFh, +255.875°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are ‘0' when read back. Writing these bits causes no change.
D2-Low-Threshold Register (Read or Write, Address = 67h, Default = 0800h, –256°C)
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL
11 10
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Bits[15:12] are ‘0' when read back. Writing these bits causes no change.
78
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Hysteresis Registers
The hysteresis registers define the hysteresis in the alarm detection of an individual alarm.
Hysteresis Register 0 (Read or Write, Address = 68h, Default = 0810h, 8 LSB)
This register contains the hysteresis values for CH0 and CH1.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
CH0-
BIT 7
CH1-
BIT 6
CH1-
BIT 5
CH1-
BIT 4
CH1-
BIT 3
CH1-
BIT 2
CH1-
BIT 1
CH1-
BIT 0
CH0- CH0- CH0- CH0- CH0- CH0-
0
0
HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0
Bits[14:8]
Bits[7:1]
CH0-HYS-n
Hysteresis of CH0, 1 LSB per step.
CH1-HYS-n
Hysteresis of CH1, 1 LSB per step.
Hysteresis Register 1 (Read or Write, Address = 69h, Default = 0810h, 8 LSB)
This register contains the hysteresis values for CH2 and CH3.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
CH2-
BIT 7
CH3-
BIT 6
CH3-
BIT 5
CH3-
BIT 4
CH3-
BIT 3
CH3-
BIT 2
CH3-
BIT 1
CH3-
BIT 0
CH2- CH2- CH2- CH2- CH2- CH2-
0
0
HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0
Bits[14:8]
Bits[7:1]
CH2-HYS-n
Hysteresis of CH2, 1 LSB per step.
CH3-HYS-n
Hysteresis of CH3, 1 LSB per step.
Hysteresis Register 2 (Read or Write, Address = 6Ah, Default = 2108h, 8°C)
This register contains the hysteresis values for D2, D1, and LT. The range is 0°C to +31°C.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
D1-
BIT 7
D1-
BIT 6
D1-
BIT 5
D1-
BIT 4
LT-
BIT 3
LT-
BIT 2
LT-
BIT 1
LT-
BIT 0
D2- D2- D2- D2- D2- D1-
LT-
0
HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3
Bits[14:10]
Bits[9:5]
Bits[4:0]
D2-HYS-n
Hysteresis of D2, 1°C per step. Note that bits D2-HYS-[2:0] are always '0'.
D1-HYS-n
Hysteresis of D1, 1°C per step. Note that bits D1-HYS-[2:0] are always '0'.
LT-HYS-n
Hysteresis of LT, 1°C per step. Note that bits LT-HYS-[2:0] are always '0'.
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Power-Down Register (Read or Write, Address = 6Bh, Default = 0000h)
After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled
by this register are either powered-down or off. The Power-Down Register allows the host to manage the
AMC7812B power dissipation. When not required, the ADC, the reference buffer amplifier, and any of the DACs
can be put into an inactive low-power mode to reduce current drain from the supply. The bits in the Power-Down
Register control this power-down function. Set the respective bit to '1' to activate the corresponding function.
MSB
LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC
10 11
0
PADC PREF
0
0
1
2
3
4
5
6
7
8
9
Bit 14
PADC
Power-down mode control bit.
0 = The ADC is inactive in low-power mode.
1 = The ADC is in normal operating mode.
Bit 13
PREF
Internal reference in power-down mode control bit.
0 = The reference buffer amplifier is inactive in low-power mode.
1 = The reference buffer amplifier is powered on.
Bits[12:1]
PDACn
DACn power-down control bit.
0 = DACn is inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of DACn is
internally switched from the buffer output to the analog ground through an internal resistor.
1 = DACn is in normal operating mode.
Device ID Register (Read-Only, Address = 6Ch, Default = 1221h)
Model and revision information.
Software Reset Register (Read or Write, Address = 7Ch, Default = NA)
The software reset register resets all registers to the default values, except for the DAC data register, DAC latch,
and DAC clear register. The software reset is similar to a hardware reset, which resets all registers including the
DAC data register, DAC latch, and DAC clear register. After a software reset, make sure that the DAC data
register, DAC latch, and DAC clear register are set to the desired values before the DAC is powered on.
SPI Mode
In SPI Mode, writing 6600h to this register forces the device reset.
I2C Mode
Writing to this register (with any data) forces the device to perform a software reset. Reading this register returns
an undefined value that must be ignored. Note that this register is 8-bit, instead of 16-bit. Both reading from and
writing to this register are single-byte operations. Writing data to the software reset register in I2C mode is
described in the following steps:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends register address 7Ch.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends a data byte.
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master asserts a stop condition to end the transaction.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2013) to Revision A
Page
•
Changed 器件状态改为生产数据 .......................................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AMC7812BSPAP
AMC7812BSPAPR
AMC7812BSRGCR
AMC7812BSRGCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
VQFN
PAP
PAP
RGC
RGC
64
64
64
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AMC7812B
1000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
AMC7812B
AMC7812B
AMC7812B
VQFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC7812BSPAPR
AMC7812BSRGCR
AMC7812BSRGCT
HTQFP
VQFN
VQFN
PAP
RGC
RGC
64
64
64
1000
2000
250
330.0
330.0
180.0
24.4
16.4
16.4
13.0
9.3
13.0
9.3
1.5
1.1
1.1
16.0
12.0
12.0
24.0
16.0
16.0
Q2
Q2
Q2
9.3
9.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
AMC7812BSPAPR
AMC7812BSRGCR
AMC7812BSRGCT
HTQFP
VQFN
VQFN
PAP
RGC
RGC
64
64
64
1000
2000
250
367.0
367.0
210.0
367.0
367.0
185.0
55.0
38.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
AMC7812BSPAP
PAP
HTQFP
64
160
8 X 20
150
322.6 135.9 7620 15.2
13.1
13
Pack Materials-Page 3
GENERIC PACKAGE VIEW
PAP 64
10 x 10, 0.5 mm pitch
HTQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226442/A
www.ti.com
PACKAGE OUTLINE
TM
PAP0064G
PowerPAD TQFP - 1.2 mm max height
SCALE 1.300
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
16
33
17
32
A
0.27
64X
60X 0.5
0.17
0.08
C A B
4X 7.5
C
SEATING PLANE
1.2 MAX
(0.127)
TYP
SEE DETAIL A
17
32
0.25
GAGE PLANE
(1)
33
16
0.15
0.05
0.08 C
0 -7
0.75
0.45
65
7.00
5.99
DETAIL A
A
17
TYPICAL
1
48
49
64
4218924/A 01/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
PAP0064G
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
8)
NOTE 8
(
7)
SYMM
SOLDER MASK
49
64
DEFINED PAD
64X (1.5)
(R0.05)
TYP
1
48
64X (0.3)
65
(11.4)
SYMM
(1.3 TYP)
60X (0.5)
33
16
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
17
32
SEE DETAILS
(1.3 TYP)
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218924/A 01/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
PAP0064G
PowerPAD TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
7)
BASED ON 0.125
THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
64
49
64X (1.5)
1
48
64X (0.3)
(R0.05) TYP
SYMM
65
(11.4)
60X (0.5)
33
16
METAL COVERED
BY SOLDER MASK
17
32
(11.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
7.83 X 7.83
7.0 X 7.0 (SHOWN)
6.39 X 6.39
0.125
0.15
0.175
5.92 X 5.92
4218924/A 01/2022
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
9.15
8.85
A
B
9.15
8.85
PIN 1 INDEX AREA
(0.2)TYP
(0.1)TYP
DETAIL 'A'
DETAIL 'A'
OPTION1
OPTION2
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X
7.5
EXPOSED
7.25±0.1
THERMAL PAD
32
17
16
33
SEE DETAIL 'A'
60X
0.5
SYMM
65
2X
7.5
0.3
0.18
64X
0.1
C A B
C
48
1
0.05
PIN1 ID
64
49
(OPTIONAL)
SYMM
0.5
0.3
64X
4219009/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X(8.8)
2X(7.5)
SEE SOLDER MASK
DETAIL
64X(0.6)
(
7.25)
64
49
1
48
64X(0.24)
60X(0.5)
65
SYMM
2X
2X(7.5)
(8.8)
4X
(1.14)
2X
(1.1)
(0.05)
(TYP)
33
16
45X (Ø0.2)
(TYP) VIA
4X
(1.14)
SYMM
32
17
2X
(1.1)
LAND PATTERN EXAMPLE
SCALE: 10X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219009/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X (8.8)
2X(7.5)
SYMM
36X
(0.94)
64x(0.6)
64
49
1
48
65
64X(0.24)
60X(0.5)
2X(0.57)
2X(8.8)
SYMM
2X(7.5)
4X(1.14)
(R0.05)
TYP
33
16
EXPOSED METAL
17
32
4X(1.14)
2X(0.57)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
60% PRINTED COVERAGE BY AREA
SCALE: 12X
4219009/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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