AVCE6467TZUTL1 [TI]
Digital Media System-on-Chip;
| 型号： | AVCE6467TZUTL1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Digital Media System-on-Chip |
| 文件： | 总352页 (文件大小：2060K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCE6467T, AVCE6467T
www.ti.com
SPRS690–MARCH 2011
VCE6467T, AVCE6467T
Digital Media System-on-Chip
Check for Samples: VCE6467T, AVCE6467T
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
Set-Associative)
– 128K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
• High-Performance Digital Media SoC
– 1-GHz C64x+™ Clock Rate
– 500-MHz ARM926EJ-S™ Clock Rate
– Eight 32-Bit C64x+ Instructions/Cycle
– 8000 C64x+ MIPS
– Fully Software-Compatible With C64x /
ARM9™
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
– Industrial Temperature Devices Available
• Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
• ARM9 Memory Architecture
•
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
•
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
• Video Communications Engine Software
– Point-to-Point SIP Video Calling
– Up to 720p30 Resolution and Frame Rate
– Low-Latency and A/V Synchronization
– Integrated Bandwidth Management Control
– Basic Package Included [AVCE6467T Only]
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Forward Error Correction (FEC) [AVCE6467T
Only]
– Audio Codecs
– Additional C64x+™ Enhancements
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Operation
•
•
G.711
G.722 [AVCE6467T Only]
•
– Video Codecs
•
•
H.264 AVC
H.264 SVC (Scalable Video Coding)
[AVCE6467T Only]
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
• Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Dual Programmable High-Definition Video
Image Co-Processor (HDVICP) Engines
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex
Multiplies
– Supports a Range of Encode, Decode, and
Transcode Operations
• C64x+ L1/L2 Memory Architecture
– 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
– 32K-Byte L1D Data RAM/Cache (2-Way
•
H.264, MPEG2, VC1, MPEG4 SP/ASP
• 108-MHz Video Port Interface (VPIF)
– Two 8-Bit SD (BT.656), Single 16-Bit HD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
VCE6467T, AVCE6467T
SPRS690–MARCH 2011
www.ti.com
(BT.1120), or Single Raw (8-/10-/12-Bit) Video
Capture Channels
• 32-Bit, 66-MHz, 3.3 V Peripheral Component
Interconnect (PCI) Master/Slave Interface
– Two 8-Bit SD (BT.656) or Single 16-Bit HD
(BT.1120) Video Display Channels
• Video Data Conversion Engine (VDCE)
– Horizontal and Vertical Downscaling
– Chroma Conversion (4:2:2↔4:2:0)
– Conforms to PCI Specification 2.3
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Three Configurable UART/IrDA/CIR Modules
(One With Modem Control Signals)
• Two Transport Stream Interface (TSIF) Modules
(One Parallel/Serial and One Serial Only)
– Supports up to 1.8432 Mbps UART
– SIR and MIR (0.576 MBAUD)
– TSIF for MPEG Transport Stream
– Simultaneous Synchronous or
– CIR With Programmable Data Encoding
Asynchronous Input/Output Streams
– Absolute Time Stamp Detection
– PID Filter With 7 PID Filter Tables
– Corresponding Clock Reference Generator
(CRGEN) Modules for System Time-Clock
Recovery
• One Serial Peripheral Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C Bus™)
• Two Multichannel Audio Serial Ports (McASPs)
– One Four Serializer Transmit/Receive Port
– One Single DIT Transmit Port for S/PDIF
• 32-Bit Host Port Interface (HPI)
• External Memory Interfaces (EMIFs)
– Up to 400-MHz 32-Bit DDR2 SDRAM Memory
Controller With 512M-Byte Address Space
(1.8-V I/O)
– Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
• VLYNQ™ Interface (FPGA Interface)
• Two Pulse Width Modulator (PWM) Outputs
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
• Up to 33 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• On-Chip ARM ROM Bootloader (RBL)
• Individual Power-Saving Modes for ARM/DSP
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
• 529-Pin Pb-Free BGA Package
(ZUT Suffix), 0.8-mm Ball Pitch
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.3-V Internal
• Applications:
•
Flash Memory Interfaces
–
–
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
– Programmable Default Burst Size
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant (3.3-V I/O Only)
– Supports MII and GMII Media Independent
Interfaces
– Management Data I/O (MDIO) Module
• USB Port With Integrated 2.0 PHY
– USB 2.0 High-/Full-Speed Client
– Video Encode/Decode/Transcode/Transrate
– Digital Media
– Networked Media Encode/Decode
– Video Imaging
– USB 2.0 High-/Full-/Low-Speed Host
(Mini-Host, Supporting One External
Device)
– Video Infrastructure
– Video Conferencing
2
Digital Media System-on-Chip (DMSoC)
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1.2 Description
The VCE6467T, AVCE6467T, which are part of the TMS320DM646x™ DMSoC Platform, leverages TI’s
DaVinci™ technology to meet the networked media encode and decode digital media processing needs of
next-generation embedded devices.
Throughout this document, unless otherwise noted, VCE6467T, refers to the VCE6467T and AVCE6467T
devices.
The VCE6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, high processing performance, and long battery life through the
maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the VCE6467T provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core incorporates:
•
•
•
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the
TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation
high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas
Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a
code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of
the C64x+ DSP with added functionality and an expanded instruction set.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x+
core offers solutions to high-performance DSP programming challenges. The DSP core possesses the
operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The VCE6467T also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The VCE6467T core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
Copyright © 2011, Texas Instruments Incorporated
Digital Media System-on-Chip (DMSoC)
3
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The peripheral set includes: a configurable video port; a 10/100/1000 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; a 4-bit transfer/4-bit receive VLYNQ interface; an
inter-integrated circuit (I2C) Bus interface; a multichannel audio serial port (McASP0) with 4 serializers; a
secondary multichannel audio serial port (McASP1) with a single transmit serializer; 2 64-bit
general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a
configurable 32-bit host port interface (HPI); up to 33-pins of general-purpose input/output (GPIO) with
programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART/IrDA/CIR
interfaces with modem interface signals on UART0; 2 pulse width modulator (PWM) peripherals; an
ATA/ATAPI-6 interface; a 66-MHz peripheral component interface (PCI); and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the VCE6467T and
the network. The VCE6467T EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)
and 100 Mbps in either half- or full-duplex mode; and 1000Base-TX (1 Gbps) in full-duplex mode with
hardware flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the
MDIO module transparently monitors its link state by reading the PHY status register. Link change events
are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link
status of the device without continuously performing costly MDIO accesses.
The PCI, HPI, I2C, SPI, USB2.0, and VLYNQ ports allow the VCE6467T to easily control peripheral
devices and/or communicate with host processors.
The VCE6467T also includes a High-Definition Video/Imaging Co-processor (HDVICP) and Video Data
Conversion Engine (VDCE) to offload many video and imaging processing tasks from the DSP core,
making more DSP MIPS available for common video and imaging algorithms. For more information on the
HDVICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales
representative.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The VCE6467T has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
4
Digital Media System-on-Chip (DMSoC)
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
JTAG Interface
System Control
ARM Subsystem
DSP Subsystem
High Definition
Video-Imaging
Coprocessor
(HDVICP0)
Input
Clock(s)
PLLs/Clock
Generator
ARM926EJ-S CPU
C64x™ DSP CPU
128 KB L2 RAM
16 KB
I-Cache
8 KB
D-Cache
Power/Sleep
Controller
High Definition
Video-Imaging
Coprocessor
(HDVICP1)
32 KB
L1 Pgm
32 KB
L1 Data
32 KB RAM
8 KB ROM
Pin
Multiplexing
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
System
General-
Purpose
Timer
Watchdog
Timer
EDMA
I2C
SPI
McASP
PWM
UART
CRGEN
VDCE
Connectivity
Program/Data Storage
EMAC
With
MDIO
DDR2
Mem Ctlr
(16b/32b)
Async EMIF/
NAND/
SmartMedia
USB 2.0
PHY
Video
Port I/F
PCI
(66 MHz)
VLYNQ
HPI
ATA
TSIF
Figure 1-1. VCE6467T Functional Block Diagram
Copyright © 2011, Texas Instruments Incorporated
Digital Media System-on-Chip (DMSoC)
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1
Digital Media System-on-Chip (DMSoC) ............ 1
1.1 Features .............................................. 1
1.2 Description ........................................... 3
1.3 Functional Block Diagram ............................ 5
Device Overview ........................................ 7
6.1 Parameter Information ............................ 141
6.2
Recommended Clock and Control Signal Transition
Behavior ........................................... 142
6.3 Power Supplies .................................... 143
6.4
External Clock Input From DEV_MXI/DEV_CLKIN
2
and AUX_MXI/AUX_CLKIN Pins .................. 151
6.5 Clock PLLs ........................................ 155
2.1 Device Characteristics ............................... 7
6.6
Enhanced Direct Memory Access (EDMA3)
2.2 Device Compatibility ................................. 9
2.3 ARM Subsystem ..................................... 9
2.4 DSP Subsystem .................................... 13
2.5 VCE Software APIs ................................. 18
2.6 Memory Map Summary ............................. 21
2.7 Pin Assignments .................................... 25
2.8 Terminal Functions ................................. 32
2.9 Device Support ..................................... 80
2.10 Documentation Support ............................ 82
2.11 Community Resources ............................. 82
Device Configurations ................................ 83
Controller .......................................... 163
6.7 Reset .............................................. 183
6.8 Interrupts .......................................... 194
6.9 External Memory Interface (EMIF) ................ 200
6.10 DDR2 Memory Controller ......................... 207
6.11 Video Port Interface (VPIF) ....................... 220
6.12 Transport Stream Interface (TSIF) ................ 228
6.13 Clock Recovery Generator (CRGEN) ............. 238
6.14 Video Data Conversion Engine (VDCE) .......... 241
6.15 Peripheral Component Interconnect (PCI) ........ 244
6.16 Ethernet MAC (EMAC) ............................ 250
6.17 Management Data Input/Output (MDIO) .......... 260
6.18 Host-Port Interface (HPI) Peripheral .............. 262
6.19 USB 2.0 [see Note] ............................... 270
6.20 ATA Controller ..................................... 280
3
3.1 System Module Registers .......................... 83
3.2 Power Considerations .............................. 85
3.3 Clock Considerations ............................... 88
3.4 Boot Sequence ..................................... 95
3.5 Configurations At Reset ........................... 101
3.6 Configurations After Reset ........................ 104
3.7 Multiplexed Pin Configurations .................... 112
3.8 Debugging Considerations ........................ 134
6.21 VLYNQ ............................................ 295
6.22 Multichannel Audio Serial Port (McASP0/1)
Peripherals ........................................ 300
6.23 Serial Peripheral Interface (SPI) .................. 312
6.24 Universal Asynchronouse Receiver/Transmitter
(UART) ............................................ 327
4
5
System Interconnect ................................ 136
Device Operating Conditions ...................... 137
6.25 Inter-Integrated Circuit (I2C) ...................... 334
6.26 Pulse Width Modulator (PWM) .................... 338
6.27 Timers ............................................. 340
6.28 General-Purpose Input/Output (GPIO) ............ 343
6.29 IEEE 1149.1 JTAG ................................ 346
Mechanical Packaging and Orderable
Information ............................................ 349
7.1 Thermal Data for ZUT ............................. 349
7.2 Packaging Information ............................ 349
5.1
Absolute Maximum Ratings Over Operating Case
Temperature Range (Unless Otherwise Noted)
..................................................... 137
5.2 Recommended Operating Conditions ............. 138
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
7
Temperature (Unless Otherwise Noted) .......... 139
Peripheral Information and Electrical
Specifications ......................................... 141
6
6
Contents
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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the VCE6467T SoC. The table shows significant features of the device,
including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+
DSP, and the package type with pin count.
Table 2-1. Characteristics of the VCE6467T Processor
HARDWARE FEATURES
VCE6467T
DDR2 Memory Controller
DDR2 (Up to 400-MHz, 16/32-bit bus width)
Asynchronous (8/16-bit bus width) RAM, Flash
(NOR, NAND)
Asynchronous EMIF (EMIFA)
EDMA
64 independent channels
8 QDMA channels
2 64-Bit General Purpose (each configurable as 2
separate 32-bit timers)
Timers
UART
1 64-Bit Watchdog
3 (with SIR, MIR, CIR support and RTS/CTS flow
control)
(UART0 Supports Modem Interface)
SPI
I2C
1 (supports 2 slave devices)
1 (Master/Slave)
2 (one transmit/receive with 4 serializers,
one DIT transmit only with 1 serializer for S/PDIF
output)
Multichannel Audio Serial Port (McASP)
10/100/1000 Ethernet MAC with Management Data
Input/Output (MDIO)
1 (with MII/GMII Interface)
Peripherals
VLYNQ
1
Up to 33 pins
Not all peripherals pins are
available at the same time
(for more detail, see the
Device Configurations
section).
General-Purpose Input/Output Port (GPIO)
PWM
ATA
PCI
2 outputs
1 (ATA/ATAPI-6)
1 (32-bit, 66 MHz)
1 (16-/32-bit multiplexed address/data)
HPI
1 [horizontal and vertical downscaling,
chroma conversion (4:2:2↔4:2:0)]
VDCE
Clock Recovery Generator (CRGEN)
Power Sleep Controller (PSC)
1
1 (peripheral/module clock gating)
2 8-bit BT.656 capture channels or
1 16-bit Y/C capture channel or
108-MHz Configurable Video Port Interface (VPIF)
1 8-/10-/12-bit raw video capture channel and
2 8-bit BT.656 display channels or
1 16-bit Y/C display channel
MPEG transport stream interface
1 with 8-bit parallel or serial input and output
Transport Stream Interface (TSIF)
1 with serial-only input and output
Each with corresponding clock recovery generator
(CRGEN) for external VCXO control.
High- and Full-Speed Device
High-, Full-, and Low-Speed Host
(1)
USB 2.0
(1) USB2.0 is not supported on -1G parts that are dated prior to May 1, 2010. See the TMS320DM6467T Silicon Errata (Literature Number:
SPRZ307) for more details on how to decode the date from package markings.
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Device Overview
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Table 2-1. Characteristics of the VCE6467T Processor (continued)
HARDWARE FEATURES
VCE6467T
Size (Bytes)
248KB RAM, 8KB ROM
DSP
•
•
•
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
On-Chip Memory
Organization
ARM
•
•
•
•
16KB I-cache
8KB D-cache
32KB RAM
8KB ROM
CPU ID + CPU Rev ID
Control Status Register (CSR.[31:16])
0x1000
0x0000
C64x+ Megamodule
Revision
Revision ID Register (MM_REVID[15:0])
(address location: 0x0181 2000)
JTAGID Register
(address location: 0x01C4 0028)
See Section 6.29.1, JTAG ID (JTAGID) Register
JTAG BSDL_ID
CPU Frequency
Description(s)
DSP 1 GHz (-1G)
ARM926 500 MHz(-1G)
DSP 1.0 ns (-1G)
ARM926 2.0 ns (-1G)
1.3 V (-1G)
MHz
ns
Cycle Time
Voltage
Core (V)
I/O (V)
1.8 V, 3.3 V (-1G)
DEV_CLKIN frequency multiplier (PLLC1)
(Between 27 – 35-MHz range)
x1 (Bypass), x14 to x32 (-1G)
x1 (Bypass), x14 to x32 (-1G)
PLL Options
DEV_CLKIN frequency multiplier (PLLC2)
(Between 27 – 35-MHz range)
AUX_CLKIN frequency
19 x 19 mm
μm
24/48-MHz reference
529-Pin BGA (ZUT)
0.09 μm
BGA Package
Process Technology
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(2)
PD
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8
Device Overview
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2.2 Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the
C64xT DSP family.
2.3 ARM Subsystem
The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem,
the VPSS Subsystem, and a majority of the peripherals and external memories.
The ARM Subsystem includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit) instruction set
Little endian operation
Co-Processor 15 (CP15)
MMU
16KB Instruction cache
8KB Data cache
Write Buffer
32KB Internal Tightly-Coupled Memory (TCM) RAM (32-bit wide access)
8KB Internal ROM (ARM bootloader for non-EMIFA boot options)
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
ARM Interrupt Controller
PLL Controller
Power and Sleep Controller (PSC)
System Module
2.3.1 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data Caches
Write buffer
Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
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Device Overview
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For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
2.3.2 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.
2.3.3 MMU
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux®,
Windows® CE, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is
used to control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables. The MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
2.3.4 Caches and Write Buffer
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
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2.3.5 Tightly Coupled Memory (TCM)
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM
and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides
for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the
D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be
stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM
sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to
the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to
the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. The instruction
region at 0x0000 and data region at 0x10000 map to the same physical 32-KB TCM RAM. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
2.3.6 Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the VCE6467T also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The VCE6467T trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
2.3.8 ARM Memory Mapping
The ARM memory map is shown in Section 2.6, Memory Map Summary of this document. The ARM has
access to memories shown in the following sections.
2.3.8.1 ARM Internal Memories
The ARM has access to the following ARM internal memories:
•
32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
•
8KB ARM Internal ROM
2.3.8.2 External Memories
The ARM has access to the following external memories:
•
•
•
DDR2 Synchronous DRAM
Asynchronous EMIF / NOR Flash / NAND Flash
ATA
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2.3.8.3 DSP Memories
The ARM has access to the following DSP memories:
L2 RAM
L1P RAM
L1D RAM
•
•
•
2.3.8.4 ARM-DSP Integration
VCE6467T ARM and DSP integration features are as follows:
•
•
•
DSP visibility from ARM’s memory map, see Section 2.6, Memory Map Summary, for details
Boot Modes for DSP - see Device Configurations section, Section 3.4.1, DSP Boot, for details
ARM control of DSP boot / reset - see Device Configurations section, Section 3.4.2.4, ARM Boot, for
details
•
•
ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for
details
ARM & DSP Interrupts - see Section 6.8.1, ARM CPU Interrupts, and Section 6.8.2, DSP Interrupts, for
details
2.3.9 Peripherals
The ARM9 has access to all of the peripherals on the VCE6467T device.
2.3.10 PLL Controller (PLLC)
The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for
configuring VCE6467T’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following
configuration and control:
•
•
•
•
•
PLL Bypass Mode
Set PLL multiplier parameters
Set PLL divider parameters
PLL power down
Oscillator power down
The PLLs are briefly described in this document in the Clocking section. For more detailed information on
the PLLs and PLL Controller register descriptions, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number SPRUEP9).
2.3.11 Power and Sleep Controller (PSC)
The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more
detailed information and complete register descriptions for the PSC, see the TMS320DM646x DMSoC
ARM Subsystem Reference Guide (literature number SPRUEP9).
2.3.12 ARM Interrupt Controller (AINTC)
The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
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2.3.13 System Module
The ARM Subsystem includes the System module. The System module consists of a set of registers for
configuring and controlling a variety of system functions. For details and register descriptions for the
System module, see Section 3, Device Configurations and see the TMS320DM646x DMSoC ARM
Subsystem Reference Guide (literature number SPRUEP9).
2.3.14 Power Management
VCE6467T has several means of managing power consumption. There is extensive use of clock gating,
which reduces the power used by global device clocks and individual peripheral clocks. Clock
management can be utilized to reduce clock frequencies in order to reduce switching power. For more
details on power management techniques, see Section 3, Device Configurations, Section 6, Peripheral
and Electrical Specifications, and see the TMS320DM646x DMSoC ARM Subsystem Reference Guide
(literature number SPRUEP9).
VCE6467T gives the programmer full flexibility to use any and all of the previously mentioned capabilities
to customize an optimal power management strategy. Several typical power management scenarios are
described in the following sections.
2.4 DSP Subsystem
The DSP Subsystem includes the following features:
•
•
•
•
•
C64x+ DSP CPU
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
Little endian
2.4.1 C64x+ DSP CPU Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.
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The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
TMS320C64x Technical Overview (literature number SPRU395)
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Even
register
file A
(A0, A2,
A4...A30)
src1
src2
Odd
register
file A
(A1, A3,
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
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2.4.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.6, Memory Map Summary. Configuration of the control
registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to
memories shown in the following sections.
2.4.2.1 ARM Internal Memories
The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).
2.4.2.2 External Memories
The DSP has access to the following External memories:
•
•
•
DDR2 Synchronous DRAM
Asynchronous EMIF / NOR Flash
ATA
2.4.2.3 DSP Internal Memories
The DSP has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
2.4.2.4 C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P)
consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 Data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way
set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB RAM memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache, or a
combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
Table 2-2. C64x+ Cache Registers
HEX ADDRESS RANGE
0x0184 0000
REGISTER ACRONYM
L2CFG
DESCRIPTION
L2 Cache configuration register
0x0184 0020
L1PCFG
L1PCC
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
0x0184 0024
0x0184 0040
L1DCFG
L1DCC
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
-
EDMAWEIGHT
-
L2 EDMA access control register
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
0x0184 2004
L2 allocation register 1
0x0184 2008
L2 allocation register 2
0x0184 200C
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
0x0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
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Table 2-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
L2IWC
DESCRIPTION
0x0184 401C
0x0184 4020
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
0x0184 4024
0x0184 4030
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0x0184 4034
0x0184 4038
0x0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D Block Writeback
0x0184 4044
L1D Block Writeback
0x0184 4048
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
-
L1P Global Invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
MAR0 - MAR15
L1D Global Writeback
0x0184 5044
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
Reserved (corresponds to byte address 0x0000 0000 - 0x0FFF FFFF)
0x0184 5048
0x0184 8000 - 0x0184 803C
Memory Attribute Registers for ARM TCM (corresponds to byte address
0x1000 0000 - 0x10FF FFFF)
0x0184 8040
MAR16
0x0184 8044 - 0x0184 80FC
0x0184 8100
MAR17 - MAR63
MAR64
Reserved (corresponds to byte address 0x1100 0000 - 0x3FFF FFFF)
Reserved (corresponds to byte address 0x4000 0000 - 0x40FF FFFF)
Reserved (corresponds to byte address 0x4100 0000 - 0x41FF FFFF)
0x0184 8104
MAR65
Memory Attribute Registers for EMIFA (corresponds to byte address 0x4200
0000 - 0x49FF FFFF)
0x0184 8108 - 0x0184 8124
0x0184 8128 - 0x0184 812C
0x0184 8130 - 0x0184 813C
0x0184 8140 - 0x0184 81FC
0x0184 8200 - 0x0184 82FC
0x0184 8300 - 0x0184 83FC
MAR66 - MAR73
MAR74 - MAR75
MAR76 - MAR79
MAR80 - MAR127
MAR128 - MAR191
MAR192 - MAR255
Reserved (corresponds to byte address 0x4A00 0000 - 0x4BFF FFFF)
Memory Attribute Registers for VLYNQ (corresponds to byte address
0x4C00 0000 - 0x4FFF FFFF)
Reserved (corresponds to byte address 0x5000 0000 - 0x7FFF FFFF)
Memory Attribute Registers for DDR2 (corresponds to byte address 0x8000
0000 - 0xBFFF FFFF)
Reserved (corresponds to byte address 0xC000 0000 - 0xFFFF FFFF)
2.4.3 Peripherals
The DSP has access/controllability of the following peripherals:
•
•
•
•
HDVICP0/1
EDMA
McASP0/1
2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers
2.4.4 DSP Interrupt Controller
The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s
available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts
section. For more detailed on the DSP Interrupt Controller, see the TMS320C64x+ DSP Megamodule
Reference Guide (literature number SPRU871).
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2.5 VCE Software APIs
Figure 2-2 shows the software block diagram of the device.
Customer Application
VoIP Client Framework
Media Engine
Call Control
Driver
Abstraction
Layer
Signaling Protocols
A-RTP
CODECS
Drivers
Common Core
VCE6467T Hardware Platform and Operating System
Figure 2-2. Software Block Diagram
The Texas Instruments (TI) VCE6467T takes advantage of the RADVISION® software infrastructure built
around BeeHD. The VCE6467T utilizes a software library to set-up and establish a two-way video
communications channel. Table 2-3 lists the APIs used to configure the VCE6467T and handle the various
protocols necessary.
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Table 2-3. VCE6467T Software APIs
API NAME
DESCRIPTION
VCE6467T Client
RvV2oipClientAdminToolsExecuteOnSlave
RvV2oipClientAdminToolsPutFileOnSlave
RvV2oipClientConstruct
This function sends a command to execute from Master to Slave.
This function sends a file from the Master ARM processor to the Slave processor.
This API is called to construct a new VCE6467T Client instance and set its configuration to
the default values.
This should be the first API to be called when the VCE6467T Client is initialized.
RvV2oipClientDestruct
RvV2oipClientRefresh
This API is called to destruct a VCE6467T Client.
This API is called to initiate a Refresh procedure of the VCE6467T Client. A Refresh
procedure drops all calls from the VCE6467T Client, unregisters, reconfigures the VCE6467T
Client module, and re-registers to the server. In a Refresh procedure only partial
reconfiguration is allowed, since the system (including the VCE6467T Client, MTF, SIP, and
H.323 modules) does not restart and the same local IP address is bound. The configuration
buffer supplied by the application must not be released until the Refresh procedure is
completed (i.e., RvV2oipClientRegisteredEv is called). During the Refresh configuration
process, the parameters that are not reconfigured will remain as before.
RvV2oipClientRegister
This API is called to start a registration process of the VCE6467T Client to the configured
registrar/proxy in SIP.
RvV2oipClientRegisteredEv
RvV2oipClientRestart
This event is called when a registration to network process was completed.
This API is called to initiate a Restart procedure of the VCE6467T Client. In a Restart
procedure, the VCE6467T Client is stopped (including the MTF and SIP modules) and the
local IP address is unbound. The VCE6467T Client then reconfigures, and after 2 seconds,
starts again with the new configuration and re-registers to the server. In a Restart procedure,
the VCE6467T Client can be fully reconfigured. The RvV2oipClientRestart can be called only
when the VCE6467T Client is not registered to the server. The configuration buffer supplied
by the application must not be released until the Restart procedure is completed (i.e.,
RvV2oipClientRegisteredEv is called). During the Restart configuration process, the
parameters that are not reconfigured will be set to their default values.
RvV2oipClientSetClientCallbacks
RvV2oipClientSetClientCallbacksByIndex
RvV2oipClientSetScreenResolution
RvV2oipClientStart
This API is called to set the client callbacks in the client object.
This API is called to set the client with more than one set of callbacks in the client object.
This API is called to set the configuration parameters of the screen resolution.
This API is called to start the VCE6467T Client process. All modules of the VCE6467T Client
(including MTF, SIP, and the media module interface) are initialized here. In this API, the
VCE6467T Client starts listening on the local IP address with the configured ports for SIP.
Only after this API is completed successfully, the VCE6467T Client can register to a
server/gatekeeper and make or receive calls.
RvV2oipClientGetStatus
This API is called to get the current client status.
RvV2oipClientTroubleNotifierEv
This event is called to notify the application about a problem that has occurred in the
VCE6467T Client. The application can use the notification string to help the user
troubleshoot the problem.
RvV2oipClientUnRegister
This API is called to start an un-registration process of the VCE6467T Client from the
registrar/proxy. Calling this API will cause all calls in the VCE6467T Client to be dropped.
RvV2oipClientUnregisteredEv
This event is called when an un-registration process has ended.
RvV2oipClientRegistrationProcessComplete This event is called when the registration process to MTF and networks is completed. After
dEv
the registration process was successfully completed, the user can start to make and receive
calls.
RvV2oipClientUnRegistrationProcessComple This event is called when the un-registration process from MTF and networks is completed.
tedEv
HV2OIP
Handle to a VCE6467T Client object.
HV2OIPAPP
Application handle to a VCE6467T Client object. This handle can be used as an application
context.
HV2OIPCALL
Handle to a VCE6467T Client call object.
HV2OIPCALLAPP
Application handle to a VCE6467T Client call object. This handle can be used as an
application context for the call.
HV2OIPWINAPP
Application handle to a VCE6467T Client window object.
RV_V2OIP_NOTIFICATION_CODE
These definitions define error numbers in the VCE6467T Client that the VCE6467T Client
uses to specify the problem to the application.
RvV2oipClientCallbacks
This structure specifies the VCE6467T Client callbacks.
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Table 2-3. VCE6467T Software APIs (continued)
API NAME
RvV2oipClientNotifierData
DESCRIPTION
This structure defines the meta data provided by the Troubleshooting Notifier.
This enumeration defines the severity of the notification.
RvV2oipClientNotifierSeverityType
RvV2oipClientNotifierUserType
This enumeration defines the type of user to whom the notification is addressed.
RvV2oipClientNotifierGetnotificationsBuffer
This API is called to get a buffer in XML format of the last numLastEnries notifications. If
numLastEnries is set to "0", the buffer will contain the last 100 notifications. Each notification
requires 200 bytes; therefore, the size of pBuf should be at least numLastEnries*200 bytes.
RvV2oipClientPermissionType
RvV2oipAutoAnswerMode
RvV2oipRegType
This enumeration defines the level of permissions to change configuration parameters.
This enumeration defines the mode of the automatic answer: (ON/OFF/ON+MIC Mute).
This enumeration defines the type of registration (SIP).
RvV2oipRegistrationState
RvV2oipRegistrationStateReason
RvV2oipClientStatus
This enumeration reflects the registration state of a terminal.
This enumeration reflects the reason for a registration state of a terminal.
This structure defines the client status information.
VCE6467T Client Call
RvV2oipClientCallAnswer
This API is called to accept an incoming call with the given configuration. This API should be
called when or after the RvV2oipClientCallStateOffering state is notified if the user accepts
the call.
RvV2oipClientCallChangeAudioSettings
RvV2oipClientCallConstruct
This API is called to change the volume level of the speakers.
This API is called to construct a call object in the VCE6467T Client with default initial
parameters. This API is the first API to be called on a call.
RvV2oipClientCallDestruct
RvV2oipClientCallDial
This API is called to destruct a call object in the VCE6467T Client. This API should be called
when or after the RvV2oipClientCallStateChangedEv event is called with
RvV2oipClientCallStateDisconnected state.
This API is called to initiate an outgoing call to the given remote party and with a given call
configuration. This function can be called only after a call object was constructed using
RvV2oipClientCallConstruct().
RvV2oipClientCallDrop
This API is called to drop a call.
RvV2oipClientCallDtmfEv
Indicates a DTMF signal from the remote.
RvV2oipClientCallGetClientInstanceHandles This API is called to retrieve the VCE6467T Client and application handles of the VCE6467T
Client object from a call object.
RvV2oipClientCallGetInfo
RvV2oipClientCallMute
This API is called to retrieve the current context and information from a call object.
This API is called to mute a call. Calling this API will stop the media of the specified type
from being transmitted to the remote party.
RvV2oipClientCallMuteEv
RvV2oipClientCallNewEv
RvV2oipClientCallReject
This event is called when an incoming media channel of the call is muted (a mute indication
is received from the remote party), or when a local outgoing channel is muted.
This event is called when a new incoming call is received. In this event, the application
should construct the call object using the RvV2oipClientCallConstruct() API function.
This API is called to reject an incoming call with the given reason. This API should be called
when or after the RvV2oipClientCallStateOffering state is notified if the user rejects the call.
RvV2oipClientCallRejectedEv
This callback is called when an incoming call was automatically rejected by the engine.
RvV2oipClientCallResolutionChangeEv
This callback is called when the resolution of the incoming video stream is discovered (once
at the beginning of the stream and once for every change in the incoming resolution).
RvV2oipClientCallSendDTMF
This API is called to send a DTMF digit.
RvV2oipClientCallSetCallCallbacks
This API is called to set the VCE6467T Client call-related callbacks in the VCE6467T Client
object.
RvV2oipClientCallSetCallCallbacksByIndex
RvV2oipClientCallStateChangedEv
This API is called to set more than one set of VCE6467T Client call-related callbacks in the
V2oIP Client object.
This event is called when a call state in the VCE6467T Client is changed. This event can be
used by the application for call management and as an indication for the GUI about the
current call state.
RvV2oipClientCallUnmute
This API is called to unmute a muted channel of the specified type.
RvV2oipClientCallUnmuteEv
This event is called when an incoming muted media channel of the call is unmuted (an
unmute indication is received from the remote party), or when a local outgoing muted media
channel is unmuted.
RvV2oipCallDropReason
This structure defines the application’s reason for dropping a call.
20
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Table 2-3. VCE6467T Software APIs (continued)
API NAME
DESCRIPTION
This structure specifies the call information.
RvV2oipCallInfo
RvV2oipCallMediaInfo
RvV2oipCallMediaStreamType
RvV2oipCallNWQuality
RvV2oipCallProtocol
This structure specifies the call media information.
This enumeration defines the media stream types.
This enumeration defines the network quality.
This enumeration defines the signaling protocol used for this call.
Note: Only SIP will be available.
RvV2oipCallRejectReason
RvV2oipCallType
This structure defines the application’s reason for rejecting a call
This enumeration specifies the different supported call types (Audio, Video )
This structure specifies the VCE6467T Client call events
This enumeration defines the state of a VCE6467T call.
This structure contains additional information related to the state of a VCE6467T call.
This enumeration defines the reason for the state of a V2oIP call.
This enumeration defines the reason a call was locally rejected.
This structure specifies the incoming call information.
RvV2oipClientCallCallbacks
RvV2oipClientCallState
RvV2oipClientCallStateReason
RvV2oipClientCallMtfStateReason
RvV2oipCallRejectReasonType
RvV2oipIncomingCallParams
RvV2oipMsgHandle
This is a handle to a message object.
VCE6467T Client Configuration
RvV2oipClientGetAppCfgParamsEv
This event is called to get the application configuration parameters when
RvV2oipClientGetConfig is called.
RvV2oipClientGetCfgParam
RvV2oipClientGetConfig
This API is called to retrieve one configuration parameter.
This API is called to get the current configuration of the VCE6467T Client. The configuration
is returned in a text buffer in the same format as the configuration file.
RvV2oipClientSetAppCfgParamEv
This event is called to set an application configuration parameter. The application can add its
own configuration parameters to the configuration file of the VCE6467T Client, under the
group name APPLICATION or any other group name unknown to the VCE6467T Client. This
event will be called for each such parameter.
RvV2oipClientSetCfgCallbacks
RvV2oipClientSetConfig
This API is called to set the configuration module events in the VCE6467T Client object.
This API is called to configure the VCE6467T Client and application. Configuration
parameters that are not in the configuration buffer will keep their current value. If the caller of
the API is not authorized a WRITE permission on one or more parameters in the file, the API
will not change the current configuration and will return with an error code.
RvV2oipClientSetConfigParam
This API is called to set a specific configuration parameter. If the configuration fails for
permission or state reasons, this function will return an error value.
RvV2oipClientRemoveCfgParam
RvV2oipCfgGroupType
This API is called to remove a parameter from a given configuration buffer.
This enumeration defines the configuration group types.
This structure defines the configuration parameter object.
This structure specifies the VCE6467T Client configuration events
VCE6467T Client Logs
RvV2oipCfgParamObj
RvV2oipClientCfgCallbacks
RvV2oipClientLogApplMsg
This API is called when the application wants to log its own messages in the log file under
the APPL log source. The application messages will be logged to the log file only if the
IPP_USERAPP log source is set under IppLogOptions in the configuration file.
RvV2oipClientLogFuncT
RvV2oipClientSetLogCB
This is the type definition for the logging event function.
This API is called to set the callback function that is called when logging messages are being
written.
RvV2oipClientlogErrorType
This enumeration defines the logging type of an application log message.
2.6 Memory Map Summary
Table 2-4 shows the memory map address ranges of the device. Table 2-5 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
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Table 2-4. Memory Map Summary
MASTER PERIPHERAL ACCESSIBILITY(1)
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
EDMA/
C64x+
ARM
Video
Port
TSIF
(0/1)
PERIPHERAL
VDCE
EMAC HPI
PCI
USB VLYNQ ATA
0x0000 0000
0x0000 4000
0x0000 3FFF
0x0000 7FFF
16K ARM RAM0
(Instruction)
16K ARM RAM1
(Instruction)
0x0000 8000
0x0001 0000
0x0001 4000
0x0001 8000
0x0002 0000
0x0010 0000
0x0040 0000
0x0050 0000
0x0060 0000
0x0070 0000
0x0080 0000
0x0081 0000
0x0081 8000
0x0083 8000
0x0090 0000
0x0093 0000
0x0000 FFFF
0x0001 3FFF
0x0001 7FFF
0x0001 FFFF
0x000F FFFF
0x003F FFFF
0x004F FFFF
0x005F FFFF
0x006F FFFF
0x007F FFFF
0x0080 FFFF
0x0081 7FFF
0x0083 7FFF
0x008F FFFF
0x0092 FFFF
0x009F FFFF
32K ARM ROM (Instruction)
16K ARM RAM0 (Data)
16K ARM RAM1 (Data)
32K ARM ROM (Data)
Reserved
Reserved
896K
3M
1M
1M
1M
Reserved
1M
64K
32K Reserved
128K
Hole (MPPA Disable)(2) Reserved
L2 RAM/Cache
800K
Reserved
192K
832K
0x00A0 0000 0x00DF FFFF
4M
Reserved
32K
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x0180 0000
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
L1P RAM/Cache
Reserved
992K
32K
L1D RAM/Cache
Reserved
Reserved
0x017F FFFF 9184K
0x01BB FFFF 3840K
0x01BC 0000 0x01BC 0FFF
0x01BC 1000 0x01BC 17FF
0x01BC 1800 0x01BC 18FF
0x01BC 1900 0x01BC 1BFF
0x01BC 1C00 0x01BF FFFF
0x01C0 0000 0x0FFF FFFF
4K
2K
ARM ETB Memory
ARM ETB Registers
CFG Space
256 ARM IceCrusher
768 Reserved
249K
228M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals
x(3)
x(3)
x(3)
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
64K
16K
16K
32K
Reserved
ARM RAM0 (Data)
ARM RAM1 (Data)
ARM ROM (Data)
ARM RAM0 (Data)
ARM RAM1 (Data)
ARM ROM (Data)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x10FF FFFF 16256K
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
4M
1M
1M
1M
1M
64K
Reserved
Reserved
Reserved
32K Reserved
128K L2 RAM/Cache
800K Reserved
5M
Hole (MPPA Disable)(2) Reserved
L2 RAM/Cache
Reserved
L2 RAM/Cache
x
x
x
x
x
x
x
x
x
x
x
Reserved
32K L1P RAM/Cache
992K Reserved
L1P RAM/Cache
Reserved
L1P RAM/Cache
Reserved
(1) These peripherals have their own DMA engine or master port interface to the DMSoC system bus and do not use the EDMA for data
transfers. The x symbol indicates that the peripheral has a valid connection through the device switch fabric to the memory region
identified in the EDMA access column.
(2) MPPA should be used to disable the hole. For more information on MPPA, see the TMS320C64x+ DSP Megamodule Reference Guide
(SPRU871).
(3) The HPI's, PCI's, and VLYNQ's access to the configuration bus peripherals is limited, see Table 2-5, Configuration Memory Map
Summary for the details.
22
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Table 2-4. Memory Map Summary (continued)
MASTER PERIPHERAL ACCESSIBILITY(1)
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
EDMA/
PERIPHERAL
ARM
C64x+
Video
Port
TSIF
(0/1)
VDCE
EMAC HPI
PCI
USB VLYNQ ATA
0x11F0 0000
0x11F0 8000
0x1200 0000
0x2000 0000
0x11F0 7FFF
0x11FF FFFF
0x1FFF FFFF
0x2000 7FFF
32K L1D RAM/Cache
992K Reserved
224M
L1D RAM/Cache
Reserved
L1D RAM/Cache
Reserved
x
x
x
x
x
32K DDR2 Control
Registers
DDR2 Control
Registers
DDR2 Control
Registers
x
0x2000 8000
0x2001 0000
0x2000 FFFF
0x2001 7FFF
32K EMIFA Control
Registers
EMIFA Registers
VLYNQ Registers
Reserved
EMIFA Registers
VLYNQ Registers
Reserved
32K VLYNQ Control
Registers
0x2001 8000
0x2010 0000
0x3000 0000
0x4000 0000
0x4040 0000
0x4044 0000
0x4048 0000
0x404C 0000
0x4050 0000
0x4060 0000
0x4064 0000
0x4068 0000
0x406C 0000
0x4070 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x200F FFFF
0x2FFF FFFF
0x3FFF FFFF
0x403F FFFF
0x4043 FFFF
0x4047 FFFF
0x404B FFFF
0x404F FFFF
0x405F FFFF
0x4063 FFFF
0x4067 FFFF
0x406B FFFF
0x406F FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
928K Reserved
255M
256M PCI Data
PCI Data
Reserved
4M
Reserved
Reserved
256K
256K
256K
256K
1M
256K Reserved
256K
Reserved
Reserved
256K
256K
25M
32M EMIFA Data (CS2)(4)
32M EMIFA Data (CS3)(4)
32M EMIFA Data (CS4)(4)
32M EMIFA Data (CS5)(4)
32M Reserved
EMIFA Data (CS2)(4)
EMIFA Data (CS3)(4)
EMIFA Data (CS4)(4)
EMIFA Data (CS5)(4)
Reserved
EMIFA Data (CS2)(4)
EMIFA Data (CS3)(4)
EMIFA Data (CS4)(4)
EMIFA Data (CS5)(4)
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x4A00 0000 0x4BFF FFFF
0x4C00 0000 0x4FFF FFFF
64M VLYNQ (Remote Data) VLYNQ (Remote Data) VLYNQ (Remote Data)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x5000 0000
0x8000 0000
0x7FFF FFFF
0x9FFF FFFF
768M Reserved
Reserved
Reserved
512M DDR2 Memory
DDR2 Memory
Reserved
DDR2 Memory
Reserved
x
x
0xA000 0000 0xBFFF FFFF 512M Reserved
0xC000 0000 0xFFFF FFFF 1G Reserved
Reserved
Reserved
(4) EMIFA CS0 and CS1 are not functionally supported on the VCE6467T, and therefore, are not pinned out.
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Table 2-5. Configuration Memory Map Summary
MASTER PERIPHERAL
ACCESSIBILITY
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
ARM/EDMA
C64x+
HPI
PCI
VLYNQ
0x0180 0000
0x0181 0000
0x0181 1000
0x0181 2000
0x0182 0000
0x0183 0000
0x0184 0000
0x0185 0000
0x01BC 0000
0x01BC 0100
0x01BC 0200
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01C0 0000
0x01C1 0000
0x01C1 0400
0x01C1 0800
0x01C1 0C00
0x01C1 1000
0x01C1 2000
0x01C1 2400
0x01C1 2800
0x01C1 3000
0x01C1 3400
0x01C1 3800
0x01C1 A000
0x01C1 A800
0x01C2 0000
0x01C2 0400
0x01C2 0800
0x01C2 0C00
0x01C2 1000
0x01C2 1400
0x01C2 1800
0x01C2 1C00
0x01C2 2000
0x01C2 2400
0x01C2 2800
0x01C2 6000
0x01C2 6400
0x01C2 6800
0x01C4 0000
0x01C4 0800
0x01C4 0C00
0x01C4 1000
0x01C4 2000
0x01C4 8000
0x01C4 8400
0x01C6 4000
0x0180 FFFF
0x0181 0FFF
0x0181 1FFF
0x0181 2FFF
0x0182 FFFF
0x0183 FFFF
0x0184 FFFF
0x01BB FFFF
0x01BC 00FF
0x01BC 01FF
0x01BC 0FFF
0x01BC 17FF
0x01BC 18FF
0x01BF FFFF
0x01C0 FFFF
0x01C1 03FF
0x01C1 07FF
0x01C1 0BFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 23FF
0x01C1 27FF
0x01C1 2FFF
0x01C1 33FF
0x01C1 37FF
0x01C1 9FFF
0x01C1 A7FF
0x01C1 FFFF
0x01C2 03FF
0x01C2 07FF
0x01C2 0BFF
0x01C2 0FFF
0x01C2 13FF
0x01C2 17FF
0x01C2 1BFF
0x01C2 1FFF
0x01C2 23FF
0x01C2 27FF
0x01C2 5FFF
0x01C2 63FF
0x01C2 67FF
0x01C3 FFFF
0x01C4 07FF
0x01C4 0BFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 7FFF
0x01C4 83FF
0x01C6 3FFF
0x01C6 5FFF
64K
4K
C64x+ Interrupt Controller
C64x+ Powerdown Controller
C64x+ Security ID
C64x+ Revision ID
C64x+ EMC
4K
4K
Reserved
64K
64K
64K
3520K
256
256
3.5K
2K
Reserved
C64x+ Memory System
Reserved
ARM ETB Memory
Reserved
ARM ETB Registers
ARM Ice Crusher
256
255744 Reserved
64K
1K
EDMA CC
EDMA TC0
EDMA TC1
EDMA TC2
EDMA TC3
Reserved
EDMA CC
EDMA TC0
EDMA TC1
EDMA TC2
EDMA TC3
Reserved
1K
1K
1K
4K
1K
Video Port
Reserved
1K
Reserved
2K
VDCE
1K
TSIF0
1K
TSIF1
26K
2K
Reserved
Reserved
Reserved
PCI Control Registers
Reserved
22K
1K
UART0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1K
UART1
1K
UART2
1K
Reserved
Reserved
1K
I2C
1K
Timer0
Timer0
Timer1
1K
Timer1
1K
Timer2 (Watchdog)
PWM0
1K
1K
PWM1
14K
1K
Reserved
Reserved
CRGEN0
1K
CRGEN1
102K
2K
Reserved
Reserved
System Module
PLL Controller 1
PLL Controller 2
Power and Sleep Controller
Reserved
System Module
1K
1K
4K
Power and Sleep Controller
Reserved
24K
1K
ARM Interrupt Controller
Reserved
Reserved
111K
8K
Reserved
USB2.0 Registers / RAM
24
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Table 2-5. Configuration Memory Map Summary (continued)
MASTER PERIPHERAL
ACCESSIBILITY
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
ARM/EDMA
C64x+
HPI
x
PCI
x
VLYNQ
0x01C6 6000
0x01C6 6800
0x01C6 7000
0x01C6 7800
0x01C6 8000
0x01C8 0000
0x01C8 1000
0x01C8 2000
0x01C8 4000
0x01C8 4800
0x01D0 1000
0x01D0 1400
0x01D0 1800
0x01D0 1C00
0x01D0 2000
0x01E0 0000
0x0200 0000
0x0220 0000
0x0240 0000
0x01C6 67FF
0x01C6 6FFF
0x01C6 77FF
0x01C6 7FFF
0x01C7 FFFF
0x01C8 0FFF
0x01C8 1FFF
0x01C8 3FFF
0x01C8 47FF
0x01D0 0FFF
0x01D0 13FF
0x01D0 17FF
0x01D0 1BFF
0x01D0 1FFF
0x01DF FFFF
0x01FF FFFF
0x021F FFFF
0x023F FFFF
0x0FFF FFFF
2K
2K
ATA
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SPI
x
x
2K
GPIO
HPI
x
x
2K
HPI
x
x
96K
4K
Reserved
Reserved
x
x
EMAC Control Registers
EMAC Control Module Registers
EMAC Control Module RAM
MDIO Control Registers
Reserved
x
x
4K
x
x
Reserved
8K
x
x
2K
x
x
498K
1K
Reserved
x
x
McASP0 Registers
McASP0 Registers
McASP0 Data Port
McASP1 Registers
McASP1 Data Port
Reserved
x
x
1K
McASP0 Data Port
x
x
1K
McASP1 Registers
x
x
1K
McASP1 Data Port
x
x
1016K Reserved
2M
2M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2M
Reserved
220M
Reserved
2.7 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.7, Multiplexed Pin Configurations, of this document.
2.7.1 Pin Map (Bottom View)
Figure 2-3 through Figure 2-8 show the bottom view of the package pin assignments in six quadrants (A,
B, C, D, E, and F).
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1
2
3
4
5
6
7
8
GP[4]/
STC_CLKIN
VP_DOUT14/
TS1_PSTIN
VP_DOUT9/
TS1_ENAO
VP_DOUT1/
BTMODE1
VP_DOUT6/
DSPBOOT
VP_DOUT5/
PCIEN
VSS
VSS
AC
AB
AA
Y
AC
GP[3]/
AUDIO_CLK0
VP_DOUT15/
TS1_DIN
VP_DOUT0/
BTMODE0
VP_DOUT3/
BTMODE3
VSS
AHCLKR0
ACLKR0
AMUTE0
AHCLKX1
AXR1[0]
TOUT1U
AB
AA
Y
VP_DOUT7
GP[2]/
AUDIO_CLK1
VP_DOUT12/
TS1_WAITO
VP_DOUT4/
CS2BW
ACLKX0
AHCLKX0
ACLKX1
SPI_CLK
AMUTEIN0
AFSR0
TOUT1L
TOUT2
GP[0]
TINP0U
TINP1L
VP_DOUT2/
BTMODE2
AFSX0
AXR0[2]
AXR0[1]
TINP0L
TOUT0U
DVDD33
DVDD33
DVDD33
DVDD33
CVDD
AXR0[3]
W
V
TOUT0L
DVDD33
CVDD
W
V
RESET
AXR0[0]
GP[1]
VSS
VLYNQ_
SCRUN
VLYNQ_
CLOCK
SPI_CS1
VSS
VSS
VSS
VSS
U
SDA
SCL
U
VLYNQ_TXD1
MTCLK
VLYNQ_TXD2
VLYNQ_RXD2
GMTCLK
VLYNQ_TXD3
VLYNQ_RXD3
VLYNQ_RXD1
SPI_CS0
SPI_EN
CVDD
T
T
VLYNQ_TXD0
VLYNQ_RXD0
SPI_SOMI
SPI_SIMO
CVDD
R
R
CVDD
P
MTXD7
P
MTXD3
1
MTXD4
2
VSS
VSS
VSS
VSS
N
MTXD5
3
MTXD6
4
N
5
6
7
8
A
B
E
C
F
D
Figure 2-3. Pin Map [Section A]
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9
10
11
12
13
14
15
16
VP_DIN4/
TS0_DOUT4/
TS1_WAITO
VP_CLKIN3/
TS1_CLKO
VP_CLKO3/
TS0_CLKO
VP_DIN0/
TS0_DOUT0
VP_DIN8/
TS0_DIN0
UCTS0/
USD0
TS1_CLKIN
VP_CLKIN0
AC
AB
AA
Y
AC
AB
AA
Y
VP_DIN5/
TS0_DOUT5/
TS1_EN_WAITO
UDSR0/
TS0_PSTO/
GP[37]
VP_DOUT8/
TS1_WAITIN
VP_DOUT11/
TS1_DOUT
VP_DIN9/
TS0_DIN1
URXD0/
TS1_DIN
VP_DIN1/
TS0_DOUT1
V
SS
URTS0/
UIRTX0/
TS1_EN_WAITO
VP_DIN6/
TS0_DOUT6/
TS1_PSTIN
UDCD0/
TS0_WAITIN/
GP[38]
VP_DOUT10/
TS1_PSTO
DV
VP_DIN2/
TS0_DOUT2
VP_DIN10/
TS0_DIN2
DD33
VP_CLKO2
URIN0/
GP[8]/
TS1_WAITIN
UTXD0/
URCTX0/
TS1_PSTIN
VP_DIN7/
TS0_DOUT7/
TS1_DIN
UDTR0/
TS0_ENAO/
GP[36]
VP_DOUT13/
TS1_EN_WAITO
VP_DIN3/
TS0_DOUT3
VP_DIN11/
TS0_DIN3
VP_CLKIN2
DV
DV
DV
DV
DV
DV
DV
DV
W
V
W
V
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DD33
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
V
SS
V
SS
V
SS
CV
DD
CV
DD
CV
DD
U
U
CV
DD
CV
DD
CV
DD
V
SS
CV
DD
CV
DD
CV
DD
V
SS
T
T
CV
DD
CV
DD
CV
DD
V
SS
CV
DD
CV
DD
CV
DD
V
SS
R
R
CV
DD
CV
DD
CV
DD
V
SS
CV
DD
CV
DD
CV
DD
V
SS
P
P
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
N
N
9
10
11
12
13
14
15
16
A
B
C
F
D
E
Figure 2-4. Pin Map [Section B]
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17
18
19
20
21
22
23
URTS2/
UIRTX2/
TS0_PSTIN/
GP[41]
UCTS2/USD2/
CRG0_VCXI/
GP[42]/
VP_DIN15_
VP_VSYNC/
TS0_DIN7
VP_DIN12/
TS0_DIN4
TS0_CLKIN
V
V
AC
AC
AB
AA
Y
SS
SS
TS1_PSTO
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
URXD2/
CRG1_VCXI/
GP[39]/
VP_DIN13_
FIELD/
TS0_DIN5
VP_CLKIN1
V
SS
DDR_D[23]
DDR_D[21]
DDR_D[22]
V
AB
AA
Y
SS
CRG0_VCXI
UTXD2/URCTX2/
CRG1_PO/
GP[40]/
URTS1/
UIRTX1/
TS0_WAITO/
GP[25]
VP_DIN14_
VP_HSYNC/
TS0_DIN6
DV
DDR2
DDR_D[28]
DDR_D[29]
DDR_D[20]
DDR_DQM[2]
DDR_DQS[2]
DDR_D[19]
DDR_D[18]
DDR_A[10]
DDR_A[1]
CRG0_PO
URXD1/
TS0_DIN7/
GP[23]
UCTS1/USD1/
TS0_EN_WAITO/
GP[26]
V
SS
DDR_D[31]
DDR_D[30]
DDR_DQM[3]
DDR_DQS[3]
DDR_D[24]
DDR_D[25]
DDR_A[12]
PWM0/
CRG0_PO/
TS1_ENAO
PWM1/
TS1_DOUT
V
SS
DV
V
SS
W
V
W
V
DDR2
DV
V
SS
V
SS
DDR_DQS[3]
DDR_D[27]
DDR_DQS[2]
DDR_D[16]
DDR_D[17]
DDR_A[3]
DD33
V
SS
V
SS
DV
U
U
DDR2
V
SS
DV
DV
DDR_D[26]
T
T
DDR2
DDR2
DV
DV
DDR_DQGATE2
DDR_BA[2]
DDR_DQGATE3
R
R
DDR2
DDR2
V
SS
V
SS
DV
V
DDR_VREF
P
P
DDR2
SS
V
V
DDR_BA[0]
19
DDR_A[7]
20
DDR_A[5]
21
DDR_A[9]
22
DDR_A[14]
23
N
N
SS
SS
17
18
A
D
B
E
C
F
Figure 2-5. Pin Map [Section C]
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A
D
B
E
C
F
1
2
3
4
5
6
7
8
V
DV
V
V
V
V
M
L
MTXD1
MTXD2
M
SS
DD33
SS
SS
SS
SS
SS
SS
SS
SS
MCRS
MRXD6
MRXD2
MRXER
V
V
V
V
V
SS
V
SS
V
SS
MTXD0
MRCLK
MRXD4
MTXEN
MRXD7
MRXD3
MRXD1
MRXD0
MCOL
MRXD5
MRXDV
MDIO
L
DV
DV
CV
CV
CV
CV
K
J
K
J
DD33
DD33
DD33
DD33
DD
DD
DD
DD
DV
DV
CV
DD
DD
CV
H
G
F
RFTCLK
MDCLK
H
G
F
E
D
C
B
A
PCI_AD0/
HD0/
EM_D0
PCI_AD2/
HD2/
EM_D2
PCI_AD4/
HD4/
EM_D4
V
SS
V
SS
DV
DD33
PCI_CBE0/
ATA_CS0/
GP[33]/
PCI_AD1/
HD1/
EM_D1
PCI_AD3/
HD3/
EM_D3
PCI_AD6/
HD6/
EM_D6
PCI_AD9/
HD9/
EM_D9
V
DV
DD33
SS
EM_A[18]
PCI_AD18/
DD2/
HD18/
PCI_AD5/
HD5/
EM_D5
PCI_AD7/
HD7/
EM_D7
PCI_AD11/
HD11/
EM_D11
PCI_AD13/
HD13/
EM_D13
PCI_AD15/
HD15/
EM_D15
PCI_IDSEL/
HDDIR/
EM_R/W
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
E
D
C
B
A
EM_A[2]
PCI_AD20/
DD4/
HD20/
PCI_AD24/
DD8/
HD24/
PCI_AD8/
HD8/
EM_D8
PCI_AD10/
HD10/
EM_D10
PCI_AD12/
HD12/
EM_D12
PCI_PAR/
HAS/
EM_DQM0
PCI_STOP/
HCNTL0/
EM_WE
PCI_FRAME/
HINT/
EM_BA[0]
EM_A[4]
EM_A[8]
PCI_AD21/
DD5/
HD21/
PCI_AD16/
DD0/
HD16/
PCI_AD22/
DD6/
HD22/
PCI_AD26/
DD10/
HD26/
PCI_CBE1/
ATA_CS1/
GP[32]/
PCI_AD14/
HD14/
EM_D14
PCI_PERR/
HCS/
EM_DQM1
PCI_CBE2/
HDS2/
EM_CS2
EM_A[5]
EM_A[0]
EM_A[6]
EM_A[10]
EM_A[19]
PCI_AD17/
DD1/
HD17/
PCI_AD23/
DD7/
HD23/
PCI_AD25/
DD9/
HD25/
PCI_AD29/
DD13/
HD29/
PCI_SERR/
HDS1/
EM_OE
PCI_DEVSEL/
HCNTL1/
EM_BA[1]
V
SS
DV
DD33
EM_A[1]
EM_A[7]
EM_A[9]
EM_A[13]
PCI_AD19/
DD3/
HD19/
PCI_AD27/
DD11/
HD27/
PCI_AD31/
DD15/
HD31/
PCI_IRDY/
HRDY/
EM_A[17]/(CLE)
PCI_CBE3/
HR/W/
EM_CS3
RSV1
1
RSV2
2
V
SS
EM_A[3]
EM_A[11]
EM_A[15]
3
4
5
6
7
8
Figure 2-6. Pin Map [Section D]
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A
D
B
E
C
F
9
10
11
12
13
14
15
16
V
V
V
V
V
V
V
V
V
M
L
M
L
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
SS
V
V
V
SS
SS
SS
SS
SS
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
CV
K
J
K
J
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
DD
DD
DD
DD
DD
CV
V
SS
V
SS
V
SS
V
SS
CV
CV
CV
DD
H
G
F
H
G
F
DD
DD
CV
CV
CV
CV
CV
CV
CV
DD
RSV7
DD
DD
DD
DD
DD
DD
DV
DV
DV
DV
DV
DV
DV
DV
DD33
DD33
DD33
DD33
DD33
DD33
TDI
DD33
DD33
PCI_RSV3/
DIOR/
GP[19]/
EM_WAIT5/
(RDY5/BSY5)
PCI_RSV1/
DA0/
GP[17]/
DEV_DV
DEV_CV
DEV_DV
AUX_CV
DD
GP[6]
E
D
C
B
A
E
D
C
B
A
TRST
TMS
SS
DD
EM_A[20]
PCI_RSV5/
IORDY/
GP[21]/
EM_WAIT3/
(RDY3/BSY3)
PCI_AD28/
DD12/
HD28/
PCI_GNT/
DMACK/
GP[12]/
AUX_DV
TDO
RSV5
DD18
DD18
EM_A[12]
EM_CS4
PCI_AD30/
DD14/
HD30/
PCI_RST/
DA2/
GP[13]/
EM_A[22]
PCI_INTA/
EM_WAIT2/
(RDY2/BSY2)
PLL1V
DEV_V
AUX_DV
RTCK
TCK
CLKOUT0
EMU1
SS
SS
SS
EM_A[14]
PCI_REQ/
DMARQ/
GP[11]/
PCI_RSV2/
INTRQ/
GP[18]/
DEV_MXI/
DEV_CLKIN
GP[5]
PLL1V
DD18
PLL2V
DD18
EM_CS5
EM_RSV0
PCI_RSV4/
DIOW/
GP[20]/
EM_WAIT4/
(RDY4/BSY4)
PCI_RSV0/
DA1/
GP[16]/
PCI_CLK/
GP[10]
GP[7]
12
V
SS
DEV_MXO
15
PLL2V
SS
EMU0
13
EM_A[21]
9
10
11
14
16
Figure 2-7. Pin Map [Section E]
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A
D
B
E
C
F
17
18
19
20
21
22
23
V
V
DDR_ZN
DDR_CKE
DDR_BA[1]
DDR_A[6]
DDR_CLK
DDR_CLK
DDR_A[11]
DDR_A[8]
M
M
L
SS
SS
SS
SS
SS
SS
SS
V
SS
V
V
V
V
V
DDR_ZP
DDR_RAS
DDR_A[2]
DDR_WE
DDR_ODT0
DDR_CS
DDR_CAS
L
K
J
DV
DDR2
DV
DDR2
DV
DDR2
DV
DDR2
DV
V
SS
K
DDR2
DDR_DQGATE0
DDR_DQGATE1
DDR_A[13]
DDR_D[6]
DDR_A[4]
DDR_D[15]
DDR_D[13]
DDR_DQM[1]
J
V
SS
DDR_D[7]
DDR_A[0]
H
G
F
H
DV
DDR_D[4]
DDR_D[14]
DDR_D[12]
DDR_D[11]
DDR_DQS[1]
DDR_D[8]
G
DDR2
RSV6
USB_V
V
SS
DDR_DQM[0]
DDR_DQS[0]
DDR_D[1]
DDR_D[5]
F
E
D
C
B
A
DDA3P3
USB_
USB_V
V
SS
DV
V
SS
E
D
C
B
A
DD1P8
DDR2
V
DDA1P2LDO
POR
USB_R1
V
SS
DDR_DQS[0]
DDR_D[0]
DDR_DQS[1]
DDR_D[10]
DDR_D[9]
AUX_V
USB_V
V
SS
DDR_D[2]
SS
SSREF
USB_
DRVVBUS/
GP[22]
AUX_MXI/
AUX_CLKIN
V
SS
DV
DDR_D[3]
V
SS
DDR2
AUX_MXO
17
V
USB_DP
19
USB_DN
20
V
SS
RSV3
22
RSV4
23
SS
18
21
Figure 2-8. Pin Map [Section F]
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2.8 Terminal Functions
The terminal functions tables (Table 2-6 through Table 2-33) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and see the Device
Configurations section of this data manual.
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Table 2-6. BOOT Terminal Functions
OTHER(2)
SIGNAL
NAME
TYPE(1)
DESCRIPTION
(3)
NO.
BOOT
ARM Boot Mode configuration bits. These pins are multiplexed between ARM boot mode and the Video Port Interface (VPIF). At reset, the
boot mode inputs BTMODE[3:0] are sampled to determine the ARM boot configuration. See below the boot modes set by these inputs. For
more details on the types of boot modes, see the Section 3.4.1, Boot Modes. After reset, these pins are Video port data outputs 3 through 0
(VP_DOUT[3:0]).
BTMODE[3:0]
0000
ARM Boot Mode
Emulation Boot (PCIEN = 0)
0001
Reserved
HPI Boot (16-Bit width) (if PCIEN = 0)
or
PCI Boot without auto-initialization (if PCIEN = 1)
VP_DOUT0/
BTMODE0
IPD
DVDD33
0010
AB5
AC4
I/O/Z
I/O/Z
HPI Boot (32-Bit width) (if PCIEN = 0)
or
PCI Boot with auto-initialization (if PCIEN = 1)
0011
0100
EMIFA Direct Boot (ROM/NOR) (PCIEN = 0) [error if PCIEN =
1; defaults to UART0]
VP_DOUT1/
BTMODE1
IPD
DVDD33
0101
0110
Reserved
I2C Boot
0111
NAND Flash Boot (PCIEN = 0) [error if PCIEN = 1]
1000
UART0 Boot
Reserved
Reserved
Reserved
Reserved
SPI Boot
1001
VP_DOUT2/
BTMODE2
IPD
DVDD33
Y8
I/O/Z
I/O/Z
1010
1011
1100 - 1101
1110
VP_DOUT3/
BTMODE3
IPD
DVDD33
AB6
1111
Reserved
DEVICE CONTROL
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus width
for the CS2 (boot) chip select region.
VP_DOUT4/
CS2BW
IPD
DVDD33
AA7
I/O/Z
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
After reset, this pin is video port data output 4 (VP_DOUT4).
PCI Enable. This pin is multiplexed between PCI Control and the VPIF. At reset, the
input state is sampled to enable/disable the PCI interface pin multiplexing. Note:
When PCI boot mode is not used, for proper device operation out of reset PCIEN
must be "0".
VP_DOUT5/
IPD
DVDD33
AC6
I/O/Z
PCIEN
0 = PCI pin function is disabled; EMIFA or HPI pin function enabled
1 = PCI pin function is enabled
After reset, this pin is video port data output 5 (VP_DOUT5).-
DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
VP_DOUT6/
DSPBOOT
IPD
DVDD33
The DSP is booted by the ARM when DSPBOOT = 0.
The DSP boots from EMIFA when DSPBOOT = 1 (and ARM HPI or PCI boot mode
is not selected).
AC5
I/O/Z
After reset, this pin is video port data output 6 (VP_DOUT6).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-7. Oscillator/PLL Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
OSCILLATOR, PLL
Crystal input DEV_MXI for DEV oscillator (system oscillator, between 27 MHz and
DEV_DVDD18 35 MHz, typically 33 MHz or 33.3 MHz). If the internal oscillator is bypassed, this pin
is the 1.8-V external oscillator clock input.
DEV_MXI/
DEV_CLKIN
B15
I
Crystal output for DEV oscillator. If the internal oscillator is bypassed, DEV_MXO
should be left as a No Connect.
DEV_MXO
DEV_DVDD18
DEV_DVSS
DEV_CVDD
A15
D15
E14
E15
O
S
DEV_DVDD18
1.8-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_DVDD18 should still be connected to the 1.8-V power supply.
(3)
I/O ground for DEV oscillator. If the internal oscillator is bypassed, DEV_DVSS
(3)
GND
S
should be connected to ground VSS
.
1.3-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_CVDD should be connected to the 1.3-V power supply (CVDD).
(3)
(3)
Ground for DEV oscillator. Connect to crystal load capacitors. Do not connect to
board ground (VSS). If the internal oscillator is bypassed, DEV_VSS should still be
DEV_VSS
C15
B17
A17
D16
C16
E16
GND
connected to ground VSS
.
Crystal input for Auxiliary (AUX) oscillator (24/48 MHz for USB, and UART2/1/0 and
McASP1/0). If the internal oscillator is bypassed, this pin is the 1.8-V external
oscillator clock input. When the peripheral is not used, AUX_MXI should be left as a
No Connect.
AUX_MXI/
AUX_CLKIN
I
O
AUX_DVDD18
Crystal output for AUX oscillator. If the internal oscillator is bypassed, AUX_MXO
AUX_DVDD18 should be left as a No Connect. When the peripheral is not used, AUX_MXO should
AUX_MXO
AUX_DVDD18
AUX_DVSS
AUX_CVDD
be left as a No Connect.
1.8-V power supply for AUX oscillator. If the internal oscillator is bypassed,
AUX_DVDD18 should still be connected to the 1.8-V power supply. When the
peripheral is not used, AUX_DVDD18 should be connected to the 1.8-V power
supply.
(3)
S
I/O ground for AUX oscillator. If the internal oscillator is bypassed, AUX_DVSS
should be connected to ground (VSS). When the peripheral is not used, AUX_DVSS
should be connected to ground (VSS).
(3)
GND
S
1.3-V power supply for AUX oscillator. If the internal oscillator is bypassed,
AUX_CVDD should be connected to the 1.3-V power supply (CVDD). When the
peripheral is not used, AUX_CVDD should be connected to the 1.3-V power supply
(3)
(CVDD).
Ground for AUX oscillator. Connect to crystal load capacitors. Do not connect to
board ground (VSS). If the internal oscillator is bypassed, AUX_VSS should still be
connected to ground (VSS). When the peripheral is not used, AUX_VSS should be
(3)
AUX_VSS
C17
GND
connected to ground (VSS).
PLL1VDD18
PLL2VDD18
PLL1VSS
B14
B16
C14
A16
(3)
S
1.8-V power supply for PLLs.
(3)
GND
Ground for PLLs.
PLL2VSS
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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Table 2-8. Clock Generator Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
CLOCK GENERATOR
CLKOUT0
C13
AB3
O/Z
DVDD33
Configurable output clock.
GP[3]/
AUDIO_CLK0
IPD
DVDD33
This pin is multiplexed between GPIO and the Audio Clock Selector. For the audio
clock selector, this pin is the configurable AUDIO_CLK0 output.
I/O/Z
GP[2]/
AUDIO_CLK1
IPD
DVDD33
This pin is multiplexed between GPIO and the Audio Clock Selector. For the audio
clock selector, this pin is the configurable AUDIO_CLK1 output.
AA4
AC3
I/O/Z
I/O/Z
This pin is multiplexed between GPIO and the TSIF Clock Selector. For TSIF, this
pin is the STC_CLKIN which can be used as an external clock source for the TSIF
counters or as TSIF output clock.
GP[4]/
STC_CLKIN
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 2-9. RESET and JTAG Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
RESET
Device reset.
IPU
DVDD33
RESET
POR
W6
I
IPU
DVDD33
D17
I
Power-on reset.
JTAG
IPU
DVDD33
JTAG test-port mode select input.
For proper device operation, do not oppose the IPU on this pin.
TMS
TDO
D12
D13
E13
B12
C12
E12
B13
A13
I
–
O/Z
JTAG test-port data output.
DVDD33
IPU
DVDD33
TDI
I
JTAG test-port data input.
IPU
DVDD33
TCK
I
JTAG test-port clock input.
JTAG test-port return clock output.
–
O/Z
RTCK
TRST
EMU1
EMU0
DVDD33
IPD
DVDD33
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG compatibility statement portion of this data manual.
I
IPU
I/O/Z
Emulation pin 1
Emulation pin 0
DVDD33
IPU
I/O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
EMIFA BOOT CONFIGURATION
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus
width for the CS2 (boot) chip select region.
VP_DOUT4/
CS2BW
IPD
I/O/Z
AA7
DVDD33
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
After reset, this pin is video port data output 4 (VP_DOUT4).
DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
VP_DOUT6/
DSPBOOT
IPD
I/O/Z
AC5
The DSP is booted by the ARM when DSPBOOT = 0.
The DSP boots from EMIFA when DSPBOOT=1.
DVDD33
After reset, this pin is video port data output 6 (VP_DOUT6).
EMIFA FUNCTIONAL PINS: ASYNC
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
PCI_CBE2/
HDS2/
EM_CS2
IPU
DVDD33
C4
A5
I/O/Z
I/O/Z
I/O/Z
PCI_CBE3/
HR/W
EM_CS3
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
memories (i.e., NOR Flash).
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is Chip Select 4 output EM_CS4 (O/Z). Asynchronous
memories (i.e., NOR Flash).
PCI_GNT/
DACK/
GP[12]/ EM_CS4
IPU
DVDD33
D10
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_REQ/
DMARQ/
GP[11]/ EM_CS5
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is Chip Select 5 output EM_CS5 (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
DVDD33
B9
E8
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_IDSEL/
HDDIR/
EM_R/W
IPU
DVDD33
This pin is multiplexed between PCI, ATA, and EMIFA.
In EMIFA mode, this pin is the read/write output EM_R/W (O/Z).
PCI_SERR/
HDS1/
EM_OE
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
B2
PCI_STOP/
HCNTL0/
EM_WE
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
D5
PCI_PERR/
HCS/
EM_DQM1
IPU
DVDD33
C3
These pins are multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, these pins are EM_DQM[1:0] and act as byte enables (O/Z).
PCI_PAR/
HAS/
EM_DQM0
IPU
DVDD33
D4
PCI_INTA/
EM_WAIT2/
(RDY2/BSY2)
This pin is multiplexed between PCI and EMIFA.
In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
IPU
DVDD33
C11
D11
A11
PCI_RSV5/IORDY/
GP[21]/EM_WAIT3/
(RDY3/BSY3)
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
IPU
DVDD33
PCI_RSV4/DIOW/
GP[20]/EM_WAIT4/
(RDY4/BSY4)
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
IPU
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
36
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Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
PCI_RSV3/DIOR/
GP[19]/EM_WAIT5/
(RDY5/BSY5)
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
IPU
I/O/Z
E10
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 0 output EM_BA[0] (O/Z).
When connected to a 16-bit asynchronous memory, this pin has the same
function as EMIF address pin 22 (EM_A[22]).
When connected to an 8-bit asynchronous memory, this pin is the lowest order bit
of the byte address.
PCI_FRAME/
HINT/
EM_BA[0]
IPU
I/O/Z
D6
B3
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this is the Bank Address 1 output EM_BA[1] (O/Z).
When connected to a 16 bit asynchronous memory this pin is the lowest order bit
of the 16-bit word address.
When connected to an 8-bit asynchronous memory, this pin is the second bit of
the address.
PCI_DEVSEL/
HCNTL1/
EM_BA[1]
IPU
I/O/Z
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is reserved.
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_RSV2/INTRQ/
GP[18]/EM_RSV0
IPD
I/O/Z
B10
C10
A9
E9
C2
F4
DVDD33
PCI_RST/
DA2/
GP[13]/EM_A[22]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 22 output EM_A[22] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 21 output EM_A[21] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_RSV0/DA1/
GP[16]/EM_A[21]
IPD
I/O/Z
DVDD33
This pin is multiplexed between PCI ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 20 output EM_A[20] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_RSV1/DA0/
GP[17]/EM_A[20]
IPD
I/O/Z
DVDD33
PCI_CBE1/
ATA_CS1/
GP[32]/EM_A[19]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 19 output EM_A[19] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
I/O/Z
DVDD33
PCI_CBE0/
ATA_CS0/
GP[33]/EM_A[18]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is address bit 18 output EM_A[18] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
I/O/Z
DVDD33
PCI_IRDY/
HRDY/
EM_A[17]/(CLE)
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
IPU
I/O/Z
A3
E6
A8
C9
B8
D9
A6
C8
B6
DVDD33
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
IPU
I/O/Z
DVDD33
PCI_AD31/
DD15/
HD31/EM_A[15]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 15 output EM_A[15] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD30/
DD14/
HD30/EM_A[14]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 14 output EM_A[14] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD29/
DD13/
HD29/EM_A[13]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 13 output EM_A[13] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD28/
DD12/
HD28/EM_A[12]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 12 output EM_A[12] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD27/
DD11/
HD27/EM_A[11]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 11 output EM_A[11] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD26/
DD10/
HD26/EM_A[10]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 10 output EM_A[10] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD25/
DD9/
HD25/EM_A[9]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 9 output EM_A[9] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
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Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
PCI_AD24/
DD8/
HD24/EM_A[8]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 8 output EM_A[8] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
D8
DVDD33
PCI_AD23/
DD7/
HD23/EM_A[7]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 7 output EM_A[7] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
B5
C7
C5
D7
A4
E7
B4
DVDD33
PCI_AD22/
DD6/
HD22/EM_A[6]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 6 output EM_A[6] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD21/
DD5/
HD21/EM_A[5]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 5 output EM_A[5] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD20/
DD4/
HD20/EM_A[4]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 4 output EM_A[4] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD19/
DD3/
HD19/EM_A[3]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 3 output EM_A[3] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD18/
DD2/
HD18/EM_A[2]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 2 output EM_A[2] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
PCI_AD17/
DD1/
HD17/EM_A[1]
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 1 output EM_A[1] (O/Z).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPD
I/O/Z
DVDD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 0 output EM_A[0] (O/Z), which is the least
significant bit on a 32-bit word address.
When connected to a 16-bit asynchronous memory, this pin is the second bit of
the address.
PCI_AD16/
DD0/
HD16/EM_A[0]
IPD
I/O/Z
C6
DVDD33
For an 8-bit asynchronous memory, this pin is the third bit of the address.
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Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
PCI_AD15/
HD15/EM_D15
IPD
I/O/Z
E5
DVDD33
PCI_AD14/
HD14 /EM_D14
IPD
I/O/Z
C1
E4
D3
E3
D2
F5
D1
E2
F3
E1
G5
F2
G4
F1
G3
DVDD33
PCI_AD13/
HD13/EM_D13
IPD
I/O/Z
DVDD33
PCI_AD12/
HD12/EM_D12
IPD
I/O/Z
DVDD33
PCI_AD11/
HD11/EM_D11
IPD
I/O/Z
DVDD33
PCI_AD10/
HD10/EM_D10
IPD
I/O/Z
DVDD33
PCI_AD9/
HD9/EM_D9
IPD
I/O/Z
DVDD33
These pins are multiplexed between PCI, HPI, and EMIFA.
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
pins are used.
PCI_AD8/
HD8/EM_D8
IPD
I/O/Z
DVDD33
PCI_AD7/
HD7/EM_D7
IPD
I/O/Z
DVDD33
PCI_AD6/
HD6/EM_D6
IPD
I/O/Z
DVDD33
PCI_AD5/
HD5/EM_D5
IPD
I/O/Z
DVDD33
PCI_AD4/
HD4/EM_D4
IPD
I/O/Z
DVDD33
PCI_AD3/
HD3/EM_D3
IPD
I/O/Z
DVDD33
PCI_AD2/
HD2/EM_D2
IPD
I/O/Z
DVDD33
PCI_AD1/
HD1/EM_D1
IPD
I/O/Z
DVDD33
PCI_AD0/
HD0/EM_D0
IPD
I/O/Z
DVDD33
EMIFA FUNCTIONAL PINS: NAND
PCI_IRDY/
HRDY/
EM_A[17]/(CLE)
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
IPU
DVDD33
A3
E6
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
IPU
DVDD33
PCI_INTA/
EM_WAIT2/
(RDY2/BSY2)
This pin is multiplexed between PCI and EMIFA.
In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
IPU
DVDD33
C11
D11
A11
E10
B2
IORDY/
GP[21]/EM_WAIT3/
(RDY3/BSY3)
This pin is multiplexed between ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
IPU
DVDD33
DIOW/
GP[20]/EM_WAIT4/
(RDY4/BSY4)
This pin is multiplexed between ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
IPU
DVDD33
DIOR/
GP[19]/EM_WAIT5/
(RDY5/BSY5)
This pin is multiplexed between ATA, GPIO, and EMIFA.
For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
IPU
DVDD33
PCI_SERR/
HDS1/
EM_OE
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
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Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
PCI_STOP/
HCNTL0/
EM_WE
IPU
I/O/Z
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
D5
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
PCI_CBE2/
HDS2/
EM_CS2
IPU
I/O/Z
C4
A5
DVDD33
PCI_CBE3/
HR/W
EM_CS3
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
memories (i.e., NOR Flash).
IPU
I/O/Z
DVDD33
PCI_AD15/
HD15/EM_D15
IPD
I/O/Z
E5
C1
E4
D3
E3
D2
F5
D1
E2
F3
E1
G5
F2
G4
F1
G3
DVDD33
PCI_AD14/
HD14 /EM_D14
IPD
I/O/Z
DVDD33
PCI_AD13/
HD13/EM_D13
IPD
I/O/Z
DVDD33
PCI_AD12/
HD12/EM_D12
IPD
I/O/Z
DVDD33
PCI_AD11/
HD11/EM_D11
IPD
I/O/Z
DVDD33
PCI_AD10/
HD10/EM_D10
IPD
I/O/Z
DVDD33
PCI_AD9/
HD9/EM_D9
IPD
I/O/Z
DVDD33
These pins are multiplexed between PCI, HPI, and EMIFA.
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
pins are used.
PCI_AD8/
HD8/EM_D8
IPD
I/O/Z
DVDD33
PCI_AD7/
HD7/EM_D7
IPD
I/O/Z
DVDD33
PCI_AD6/
HD6/EM_D6
IPD
I/O/Z
DVDD33
PCI_AD5/
HD5/EM_D5
IPD
I/O/Z
DVDD33
PCI_AD4/
HD4/EM_D4
IPD
I/O/Z
DVDD33
PCI_AD3/
HD3/EM_D3
IPD
I/O/Z
DVDD33
PCI_AD2/
HD2/EM_D2
IPD
I/O/Z
DVDD33
PCI_AD1/
HD1/EM_D1
IPD
I/O/Z
DVDD33
PCI_AD0/
HD0/EM_D0
IPD
I/O/Z
DVDD33
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Table 2-11. DDR2 Memory Controller Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
DDR2 Memory Controller
DDR2 Clock
DDR_CLK
DDR_CLK
M23
L23
M20
J20
L20
K19
L21
V20
Y23
F22
F20
U20
V22
D22
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
I/O/Z
I/O/Z
I/O/Z
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DDR2 Differential clock
DDR2 Clock Enable
DDR_CKE
DDR_CS
DDR2 Active low chip select
DDR2 Active low Write enable
DDR2 Row Access Signal output
DDR_WE
DDR_RAS
DDR_CAS
DDR2 Column Access Signal output
DDR_DQM[3]
DDR_DQM[2]
DDR_DQM[1]
DDR_DQM[0]
DDR_DQS[3]
DDR_DQS[2]
DDR_DQS[1]
DDR2 Data mask outputs
DDR_DQM[3]: For upper byte data bus DDR_D[31:24]
DDR_DQM[2]: For DDR_D[23:16]
DDR_DQM[1]: For DDR_D[15:8]
DDR_DQM[0]: For lower byte DDR_D[7:0]
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
synchronize the data transfers.
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0]: For bottom byte DDR_D[7:0]
DDR_DQS[0]
D21
I/O/Z
DVDDR2
DDR_DQS[3]
DDR_DQS[2]
DDR_DQS[1]
V21
W23
D23
I/O/Z
I/O/Z
I/O/Z
DVDDR2
DVDDR2
DVDDR2
Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They
are outputs to the DDR2 memory when writing and inputs when reading. They are
used to synchronize the data transfers.
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0]: For bottom byte DDR_D[7:0]
DDR_DQS[0]
E20
I/O/Z
O/Z
DVDDR2
DVDDR2
DDR_ODT0
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DDR_A[14]
DDR_A[13]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
K20
P19
M21
N19
N23
H21
P20
K23
T23
N22
J23
DDR2 on-die termination control
Bank address outputs (BA[2:0]).
O/Z
DVDDR2
N20
M22
N21
J22
O/Z
DVDDR2
DDR2 address bus
R22
L22
R23
H23
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
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Table 2-11. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
Y20
W20
Y21
AA21
U21
T21
R20
T20
AB22
Y22
AA22
AA23
V23
U23
T22
U22
H22
G23
G22
F23
E23
C22
B22
C23
H20
G21
F21
G20
B21
C20
D20
C21
J19
DDR_D[31]
DDR_D[30]
DDR_D[29]
DDR_D[28]
DDR_D[27]
DDR_D[26]
DDR_D[25]
DDR_D[24]
DDR_D[23]
DDR_D[22]
DDR_D[21]
DDR_D[20]
DDR_D[19]
DDR_D[18]
DDR_D[17]
DDR_D[16]
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
I/O/Z
DVDDR2
DDR2 data bus can be configured as 32 bits wide or 16 bits wide.
DDR_D[8]
DDR_D[7]
DDR_D[6]
DDR_D[5]
DDR_D[4]
DDR_D[3]
DDR_D[2]
DDR_D[1]
DDR_D[0]
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
DDR_VREF
O/Z
DVDDR2
DVDDR2
DVDDR2
DDR2 strobe gate signal for lower-half data bus
DDR2 strobe gate signal return for lower-half data bus
DDR2 strobe gate signal for upper-half data bus
DDR2 strobe gate signal return for upper-half data bus
Reference voltage input for the SSTL_18 IO buffers.
J21
I
O/Z
I
R19
R21
P23
DVDDR2
(4)
S
Impedance control for DDR2 outputs. This must be connected via a 50-Ω (±5%
tolerance) resistor to VSS
(4)
(4)
DDR_ZP
DDR_ZN
L19
O
O
.
Impedance control for DDR2 outputs. This must be connected via a 50-Ω (±5%
M19
tolerance) resistor to DVDDR2
.
(4) For more information, see the Recommended Operating Conditions table
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Table 2-12. Peripheral Component Interconnect (PCI) Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
PCI
Notes: When PCI boot mode is not used, for proper device operation out of reset PCIEN must be "0".
The PCI pin functions are enabled when PCIEN = 1 (PCI mode). This can be done via an external PU on the PCIEN pin (AC6) or by setting
the PCIEN bit (bit 2) in the PINMUX0 register to a "1" after device reset. For more details on the PCIEN pin, see Table 2-6, Boot Terminal
Functions.
In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have external
pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see Section 3.8.1,
Pullup/Pulldown Resistors.
Also in PCI mode (PCIEN = 1), the internal pulldowns (IPDs) are disabled on the GP[5:7] pins. It is recommended to have external pullup
resistors on the GP[5] pin when PCIEN = 1 and on GP[6:7] pins when PCIEN = 1 and VADJEN = 0.
[IPU]
DVDD33
This pin is multiplexed between PCI and GPIO.
In PCI mode, this pin is the PCI clock input PCI_CLK (I).
PCI_CLK/GP[10]
A10
C10
I/O/Z
I/O/Z
PCI_RST /DA2/
GP[13]/EM_A[22]
[IPD]
DVDD33
This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
In PCI mode, this pin is PCI reset PCI_RST (I).
This pin is multiplexed between PCI, ATA, and EMIFA.
In PCI mode, this pin is the PCI initialization device select, PCI_IDSEL
(I).
PCI_IDSEL/
HDDIR/EM_R/W
[IPU]
DVDD33
E8
I/O/Z
PCI_DEVSEL /
HCNTL1/EM_BA[1]
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI device select, PCI_DEVSEL (I/O/Z).
B3
D6
A3
E6
D5
B2
C3
D4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_FRAME /
HINT/EM_BA[0]
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI cycle frame, PCI_FRAME (I/O/Z).
PCI_IRDY /HRDY/
EM_A[17]/(CLE)
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI initiator ready, PCI_IRDY (I/O/Z).
PCI_ TRDY /HHWIL/
EM_A[16]/(ALE)
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI target ready, PCI_ TRDY (I/O/Z).
PCI_STOP /
HCNTL0/EM_WE
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI stop, PCI_STOP (I/O/Z).
PCI_SERR /
HDS1/EM_OE
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI system error, PCI_SERR (I/O/Z).
PCI_PERR /
HCS/EM_DQM1
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI parity error, PCI_PERR (I/O/Z).
PCI_PAR/
HAS/EM_DQM0
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI parity, PCI_PAR (I/O/Z).
PCI_INTA /
EM_WAIT2/
(RDY2/BSY2)
[IPU]
DVDD33
This pin is multiplexed between the PCI and EMIFA.
In PCI mode, this pin is the PCI interrupt A, PCI_INTA (O/Z).
C11
B9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_REQ /
DMARQ/
GP[11]/EM_CS5
[IPU]
DVDD33
This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
In PCI mode, this pin is the PCI bus request, PCI_REQ (O/Z).
PCI_GNT /
DMACK/
GP[12]/EM_CS4
[IPU]
DVDD33
This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
In PCI mode, this pin is PCI bus grant, PCI_GNT (I).
D10
A5
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI command/byte enable 3, PCI_CBE3
(I/O/Z).
PCI_CBE3 /
HR/W/EM_CS3
[IPU]
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In PCI mode, this pin is the PCI command/byte enable 2, PCI_CBE2
(I/O/Z).
PCI_CBE2 /
HDS2/EM_CS2
[IPU]
DVDD33
C4
PCI_CBE1 /
ATA_CS1/
GP[32]/EM_A[19]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In PCI mode, this pin is the PCI command/byte enable 1 PCI_CBE1
(I/O/Z).
[IPU]
DVDD33
C2
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-12. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
PCI_CBE0 /
ATA_CS0/
GP[33]/EM_A[18]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
In PCI mode, this pin is the PCI command/byte enable 0 PCI_CBE0
(I/O/Z).
[IPU]
DVDD33
F4
I/O/Z
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Table 2-12. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
PCI_AD31/DD15/
HD31/EM_A[15]
[IPD]
DVDD33
A8
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_AD30/DD14/
HD30/EM_A[14]
[IPD]
DVDD33
C9
B8
D9
A6
C8
B6
D8
B5
C7
C5
D7
A4
E7
B4
C6
E5
C1
E4
D3
E3
D2
F5
D1
PCI_AD29/DD13/
HD29/EM_A[13]
[IPD]
DVDD33
PCI_AD28/DD12/
HD28/EM_A[12]
[IPD]
DVDD33
PCI_AD27/DD11/
HD27/EM_A[11]
[IPD]
DVDD33
PCI_AD26/DD10/
HD26/EM_A[10]
[IPD]
DVDD33
PCI_AD25/DD9/
HD25/EM_A[9]
[IPD]
DVDD33
PCI_AD24/DD8/
HD24/EM_A[8]
[IPD]
DVDD33
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
In PCI mode, these pins are the PCI address/data bus, PCI_AD[31:16]
(I/O/Z).
PCI_AD23/DD7/
HD23/EM_A[7]
[IPD]
DVDD33
PCI_AD22/DD6/
HD22/EM_A[6]
[IPD]
DVDD33
PCI_AD21/DD5/
HD21/EM_A[5]
[IPD]
DVDD33
PCI_AD20/DD4/
HD20/EM_A[4]
[IPD]
DVDD33
PCI_AD19/DD3/
HD19/EM_A[3]
[IPD]
DVDD33
PCI_AD18/DD2/
HD18/EM_A[2]
[IPU]
DVDD33
PCI_AD17/DD1/
HD17/EM_A[1]
[IPD]
DVDD33
PCI_AD16/DD0/
HD16/EM_A[0]
[IPD]
DVDD33
PCI_AD15/
HD15/EM_D15
[IPD]
DVDD33
PCI_AD14/
HD14/EM_D14
[IPD]
DVDD33
PCI_AD13/
HD13/EM_D13
[IPD]
DVDD33
PCI_AD12/
HD12/EM_D12
[IPD]
DVDD33
These pins are multiplexed between PCI, HPI, and EMIFA.
For PCI, these pins are PCI data/address bus, PCI_AD [15:0] (I/O/Z).
PCI_AD11/
HD11/EM_D11
[IPD]
DVDD33
PCI_AD10/
HD10/EM_D10
[IPD]
DVDD33
PCI_AD9/
HD9/EM_D9
[IPU]
DVDD33
PCI_AD8/
HD8/EM_D8
[IPD]
DVDD33
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Table 2-12. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
PCI_AD7/
HD7/EM_D7
[IPD]
DVDD33
E2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PCI_AD6/
HD6/EM_D6
[IPD]
DVDD33
F3
E1
G5
F2
PCI_AD5/
HD5/EM_D5
[IPD]
DVDD33
PCI_AD4/
HD4/EM_D4
[IPD]
DVDD33
These pins are multiplexed between PCI, HPI, and EMIFA.
For PCI, these pins are PCI data/address bus [15:0] (I/O/Z)
PCI_AD3/
HD3/EM_D3
[IPD]
DVDD33
PCI_AD2/
HD2/EM_D2
[IPD]
DVDD33
G4
F1
PCI_AD1/
HD1/EM_D1
[IPD]
DVDD33
PCI_AD0/
HD0/EM_D0
[IPD]
DVDD33
G3
A9
E9
B10
PCI_RSV0/DA1/
GP[16]/EM_A[21]
[IPD]
DVDD33
PCI reserved (I)(1)
PCI reserved (O/Z)(1)
PCI reserved (I)(1)
PCI_RSV1/DA0/
GP[17]/EM_A[20]
[IPD]
DVDD33
PCI_RSV2/INTRQ/
GP[18]/EM_RSV 0
[IPD]
DVDD33
PCI_RSV3/DIOR/
GP[19]/
[IPU]
DVDD33
E10
A11
D11
I/O/Z
I/O/Z
I/O/Z
PCI reserved (O/Z)(1)
PCI reserved (I/O/Z)(1)
PCI reserved (I/O/Z)(1)
EM_WAIT5
PCI_RSV4/DIOW/
GP[20]/
[IPU]
DVDD33
EM_WAIT4
PCI_RSV5/IORDY/
GP[21]/
[IPU]
DVDD33
EM_WAIT3
(1) In PCI mode (PCIEN = 1), it is recommended to have an external pullup resistor on this pin.
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Table 2-13. EMAC [G]MII and MDIO Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
EMAC [G]MII
IPD
DVDD33
RFTCLK
GMTCLK
MTCLK
H1
P2
R1
I
Gigabit (GMII) reference transmit clock (125 MHz)
GMII source asynchronous transmit clock
[G]MII transmit clock input
-
O/Z
DVDD33
IPD
DVDD33
I
MTXD7
MTXD6
MTXD5
MTXD4
MTXD3
MTXD2
MTXD1
MTXD0
P1
N4
N3
N2
N1
M4
M1
L1
-
[G]MII transmit data [7:0]. For 1000 GMII operation, MTXD[7:0] are used. For 10/100
MII operation, only MTXD[3:0] are used.
O/Z
DVDD33
-
MTXEN
MCOL
L2
L4
L3
K1
O/Z
[G]MII transmit data enable output
[G]MII collision detect (sense) input
[G]MII carrier sense input
DVDD33
IPD
DVDD33
I
IPD
DVDD33
MCRS
MRCLK
I
IPU
DVDD33
I
[G]MII receive clock
MRXD7
MRXD6
MRXD5
MRXD4
MRXD3
MRXD2
MRXD1
MRXD0
K2
K3
K4
J1
IPU
DVDD33
[G]MII receive data [7:0]. For 1000 GMII operation, MRXD[7:0] are used. For 10/100
MII operation, only MRXD[3:0] are used.
I
J2
J3
H2
G2
IPU
DVDD33
MRXDV
MRXER
J4
I
[G]MII receive data valid input
IPU
DVDD33
H3
I
[G]MII receive data error input
MDIO
IPU
O/Z
MDCLK
MDIO
G1
H4
Management data serial clock output
DVDD33
IPU
I/O/Z
Management Data IO
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-14. VLYNQ Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
VLYNQ
IPU
DVDD33
VLYNQ_CLOCK
VLYNQ_SCRUN
U1
U2
I/O/Z
I/O/Z
VLYNQ serial clock
IPU
DVDD33
VLYNQ serial clock run request
VLYNQ_TXD3
VLYNQ_TXD2
VLYNQ_TXD1
VLYNQ_TXD0
VLYNQ_RXD3
VLYNQ_RXD2
VLYNQ_RXD1
VLYNQ_RXD0
T3
T2
T1
R4
R3
R2
P3
P4
–
O/Z
VLYNQ transmit bus [3:0]
DVDD33
IPD
DVDD33
I
VLYNQ receive bus [3:0]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-15. HPI Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
Host-Port Interface (HPI)
HPI is enabled by the PINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependent for 16-/32-bit modes). For more detailed information on
the HPI pin muxing, see Section 3.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_PERR/
HCS /
EM_DQM1
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI active-low chip select input, HCS (I).
C3
D5
B3
I/O/Z
I/O/Z
I/O/Z
PCI_STOP/
HCNTL0/
EM_WE
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI control input 0, HCNTL0 (I)
PCI_DEVSEL/
HCNTL1/
EM_BA[1]
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI control input 1, HCNTL1 (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
PCI_PAR/ HAS /
IPU
DVDD33
In HPI mode, this pin is the HPI address strobe, HAS (I).
NOTE: The VCE6467T HPI does not support the HAS feature. For proper HPI
operation if the pin is routed out, it must be pulled up via an external resistor.
D4
I/O/Z
EM_DQM0
PCI_SERR/
HDS1 /EM_OE
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI data strobe input 1, HDS1 (I).
B2
C4
A5
I/O/Z
I/O/Z
I/O/Z
PCI_CBE2/
HDS2 /EM_CS2
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI data strobe input 2, HDS2 (I).
PCI_CBE3/
HR/W /EM_CS3
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI host read/write select input, HR/W (I).
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI half-word identification input control, HHWIL (I).
E6
A8
C9
B8
D9
A6
C8
B6
D8
I/O/Z
PCI_AD31/
DD15/
HD31/EM_A[15]
PCI_AD30/
DD14/
HD30/EM_A[14]
PCI_AD29/
DD13/
HD29/EM_A[13]
PCI_AD28/
DD12/
HD28/EM_A[12]
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
In HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
IPD
DVDD33
I/O/Z
PCI_AD27/
DD11/
HD27/EM_A[11]
PCI_AD26/
DD10/
HD26/ EM_A[10]
PCI_AD25/
DD9/
HD25/EM_A[9]
PCI_AD24/
DD8/
HD24/EM_A[8]
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-15. HPI Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
PCI_AD23/
DD7/
B5
HD23/EM_A[7]
PCI_AD22/
DD6/
HD22/EM_A[6]
C7
C5
D7
A4
E7
B4
C6
PCI_AD21/
DD5/
HD21/EM_A[5]
PCI_AD20/
DD4/
HD20/EM_A[4]
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
In HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
IPD
DVDD33
I/O/Z
PCI_AD19/
DD3/
HD19/EM_A[3]
PCI_AD18/
DD2/
HD18/EM_A[2]
PCI_AD17/
DD1/
HD17/EM_A[1]
PCI_AD16/
DD0/
HD16/EM_A[0]
PCI_AD15/
HD15/EM_D15
E5
C1
E4
D3
E3
D2
F5
D1
E2
F3
E1
G5
F2
G4
F1
G3
PCI_AD14/
HD14/EM_D14
PCI_AD13/
HD13/EM_D13
PCI_AD12/
HD12/EM_D12
These pins are multiplexed between PCI, HPI, and EMIFA.
In HPI-16 mode, these pins are the HPI data bus, HD[15:0] (I/O/Z).
In HPI-32 mode, these pins are the HPI lower data bus, HD[15:0] (I/O/Z).
IPD
DVDD33
I/O/Z
PCI_AD11/
HD11/EM_D11
PCI_AD10/
HD10/EM_D10
PCI_AD9/
HD9/EM_D9
PCI_AD8/
HD8/EM_D8
PCI_AD7/
HD7/EM_D7
PCI_AD6/
HD6/EM_D6
PCI_AD5/
HD5/EM_D5
PCI_AD4/
HD4/EM_D4
These pins are multiplexed between PCI, HPI, and EMIFA.
In HPI-16 mode, these pins are the HPI data bus, HD[15:0] (I/O/Z).
In HPI-32 mode, these pins are the HPI lower data bus, HD[15:0] (I/O/Z).
IPD
DVDD33
I/O/Z
PCI_AD3/
HD3/EM_D3
PCI_AD2/
HD2/EM_D2
PCI_AD1/
HD1/EM_D1
PCI_AD0/
HD0/EM_D0
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Table 2-15. HPI Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
PCI_IRDY/
HRDY /
EM_A[17]/(CLE)
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI host ready output from DSP to host, HRDY (O/Z).
A3
I/O/Z
I/O/Z
PCI_FRAME/
HINT /EM_BA[0]
IPU
DVDD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In HPI mode, this pin is the HPI host interrupt output, HINT (O/Z).
D6
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Table 2-16. USB Terminal Functions
OTHER(2) (3)
SIGNAL
TYPE(1)
DESCRIPTION
(4)
NAME
NO.
USB 2.0
USB bidirectional Data Differential signal pair [positive/negative].
When the USB peripheral is not used, the USB_DP signal should be pulled up
(high) and the USB_DN signal should be pulled down (low) via a 10-kΩ resistor.
USB_DP
USB_DN
A19
A20
A I/O
A I/O
USB current reference output. When the USB peripheral is used, this pin must be
connected via a 10-kΩ ±1% resistor to USB_VSSREF
When the USB peripheral is not used, this pin must be connected via a 10-kΩ
resistor to USB_VSSREF
.
(4)
USB_R1
D18
B18
C18
A I/O
I/O/Z
GND
.
This pin is multiplexed between USB and GPIO.
USB_DRVVBUS/
IPD
DVDD33
When this pin is used as USB_DRVVBUS (PINMUX0.VBUSDIS = 0), and the USB
Controller is operating as a Host (USBCTL.USBID = 0 and Session is in progress),
this signal is used by the USB Controler to enable the external VBUS charge pump.
GP[22]
Ground for reference current. This pin must be connected via a 10-kΩ ±1% resistor
to USB_R1.
When the USB peripheral is not used, the USB_VSSREF signal should be connected
(4)
USB_VSSREF
to VSS
.
Analog 3.3 V power supply for USB PHY.
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
(4)
(4)
USB_VDDA3P3
USB_VDD1P8
F18
E18
S
S
connected to DVDD33
.
1.8-V I/O power supply for USB PHY.
When the USB peripheral is not used, the USB_VDD1P8 signal should be connected
to 1.8-V power supply.
Core power supply LDO output for USB PHY. This pin must be connected via a
1-μF capacitor to VSS
When the USB peripheral is not used, the USB_VDDA1P2LDO signal should still be
connected via a 1-μF capacitor to VSS
.
(4)
USB_VDDA1P2LDO
E17
S
.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
(4) For more information, see the Recommended Operating Conditions table
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Table 2-17. Video-Port Interface (VPIF) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
VIDEO-PORT INTERFACE (VPIF) – CAPTURE
IPD
DVDD33
VP_CLKIN0
VP_CLKIN1
AC13
AB18
I
I
VPIF capture channel 0 input clock (I).
VPIF capture channel 1 input clock (I).
IPD
DVDD33
This pin is multiplexed between the VPIF and TSIF0.
When used for the VPIF, this pin is capture data bit 15 or the vertical sync
input, VP_DIN15_VSYNC (I).
VP_DIN15_VP_VSYNC/
IPD
DVDD33
AC18
AA17
AB17
I
I
I
TS0_DIN7
This pin is multiplexed between the VPIF and TSIF0.
When used for the VPIF, this pin is capture data bit 14 or the horizontal sync
input, VP_DIN14_HSYNC (I).
VP_DIN14_VP_HSYNC/
IPD
DVDD33
TS0_DIN6
This pin is multiplexed between the VPIF and TSIF0.
When used for the VPIF, this pin is capture data bit 13 or the field indicator
input, VP_DIN13_FIELD (I).
VP_DIN13_FIELD/
IPD
DVDD33
TS0_DIN5
VP_DIN12/
TS0_DIN4
AC17
Y16
VP_DIN11/
TS0_DIN3
VP_DIN10/
TS0_DIN2
IPD
DVDD33
These pins are multiplexed between the VPIF and TSIF0.
When used for the VPIF, these pins are capture data bits, VP_DIN[12:8] (I).
AA16
AB16
AC16
I
VP_DIN9/
TS0_DIN1
VP_DIN8/
TS0_DIN0
VP_DIN7/
TS0_DOUT7/
TS1_DIN
Y14
VP_DIN6/
TS0_DOUT6/
TS1_PSTIN
AA14
AB14
AC14
IPD
DVDD33
These pins are multiplexed between the VPIF, TSIF0, and TSIF1.
When used for the VPIF, these pins are capture data bits, VP_DIN[7:4] (I).
I/O/Z
VP_DIN5/
TS0_DOUT5/
TS1_EN_WAITO
VP_DIN4/
TS0_DOUT4/
TS1_WAITO
VP_DIN3/
TS0_DOUT3
Y15
VP_DIN2/
TS0_DOUT2
AA15
AB15
AC15
IPD
DVDD33
These pins are multiplexed between the VPIF and TSIF0.
When used for the VPIF, these pins are capture data bits, VP_DIN[3:0] (I).
I/O/Z
VP_DIN1/
TS0_DOUT1
VP_DIN0/
TS0_DOUT0
VIDEO-PORT INTERFACE (VPIF) – DISPLAY
IPD
DVDD33
VP_CLKIN2
Y10
AC9
AA9
I
VPIF display channel 2 source input clock (I).
This pin is multiplexed between the VPIF and TSIF1.
When used for VPIF, this pin is display channel 3 source clock, VP_CLKIN3
(I).
VP_CLKIN3/
TS1_CLKO
IPD
DVDD33
I/O/Z
O/Z
-
VP_CLKO2
VPIF display channel 2 output clock (O/Z).
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-17. Video-Port Interface (VPIF) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
This pin is multiplexed between the VPIF and TSIF0.
When used for VPIF, this pin is the display channel 3 output clock,
VP_CLKO3 (O/Z).
VP_CLKO3/
TS0_CLKO
-
AC10
O/Z
DVDD33
VP_DOUT15/
TS1_DIN
AB8
AC7
Y9
I/O/Z
I/O/Z
I/O/Z
VP_DOUT14/
TS1_PSTIN
VP_DOUT13/
TS1_EN_WAITO
VP_DOUT12/
TS1_WAITO
AA8
AB10
AA10
AC8
AB9
I/O/Z
IPD
These pins are multiplexed between the VPIF and TSIF1.
When used for the VPIF, these pins are display data bits, VP_DOUT[15:8]
(O/Z).
DVDD33
VP_DOUT11/
TS1_DOUT
O/Z
VP_DOUT10/
TS1_PSTO
O/Z
O/Z
O/Z
VP_DOUT9/
TS1_ENAO
VP_DOUT8/
TS1_WAITIN
This pin is video display data bit 7, VP_DOUT[7] (O/Z).
IPD
O/Z
VP_DOUT7
AB7
Note: For proper device operation, do not oppose the IPD resistor on this
pin at reset (i.e., this pin should be low at the rising edge of RESET or POR).
DVDD33
VP_DOUT6/
DSPBOOT
AC5
AC6
AA7
AB6
Y8
VP_DOUT5/
PCIEN
VP_DOUT4/
CS2BW
These pins are multiplexed between the VPIF and boot configuration.
After reset, these pins are used by the VPIF as display data bits,
VP_DOUT[6:0] (O/Z).
VP_DOUT3/
BTMODE3
IPD
I/O/Z
DVDD33
VP_DOUT2/
BTMODE2
VP_DOUT1/
BTMODE1
AC4
AB5
VP_DOUT0/
BTMODE0
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Table 2-18. Transport Stream Interface 0 (TSIF0) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
AC19
Y17
TSIF0 PARALLEL INPUT (PINMUX0.PTSIMUX = 10)
IPD
DVDD33
TS0_CLKIN
I
TSIF0 receive clock input (I).
This pin is multiplexed between UART1, TSIF0, and GPIO.
When TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in synchronous
mode, this pin is the data enable indicator (I) or in asynchronous mode, this
pin is the wait output (O/Z), TS0_EN_WAITO.
UCTS1/USD1/
TS0_EN_WAITO/
GP[26]
IPU
DVDD33
I/O/Z
This pin is multiplexed between UART1, TSIF0, and GPIO.
When TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in asynchronous
mode, this pin is the wait output, TS0_WAITO (O/Z).
URTS1/UIRTX1/
TS0_WAITO/GP[25]
IPU
DVDD33
AA18
AC20
I/O/Z
I/O/Z
This TSIF pin function is not used in synchronous mode.
This pin is multiplexed between UART2, TSIF0, and GPIO.
When TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), this pin is the
packet start input indicator, TS0_PSTIN (I).
URTS2/UIRTX2/
TS0_PSTIN/GP[41]
IPU
DVDD33
VP_DIN15_VP_VSYNC/
AC18
AA17
AB17
AC17
Y16
TS0_DIN7
VP_DIN14_VP_HSYNC/
TS0_DIN6
VP_DIN13_FIELD/
TS0_DIN5
VP_DIN12/
TS0_DIN4
These pins are multiplexed between the VPIF and TSIF0.
When TSIF0 parallel input mux mode is enabled (PINMUX0.PTSIMUX = 10),
these pins are input data bits TS0_DIN[7:0] (I).
IPD
DVDD33
I/O/Z
VP_DIN11/
TS0_DIN3
VP_DIN10/
TS0_DIN2
AA16
AB16
AC16
VP_DIN9/
TS0_DIN1
VP_DIN8/
TS0_DIN0
TSIF0 SERIAL INPUT (PINMUX0.PTSIMUX = 11)
IPD
TS0_CLKIN
AC19
Y17
I
TSIF0 receive clock input (I).
DVDD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
UCTS1/USD1/
TS0_EN_WAITO/
GP[26]
IPU
DVDD33
When TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in synchronous
mode, this pin is the data enable indicator (I) or in asynchronous mode, this
pin is the wait output (O/Z), TS0_EN_WAITO.
I/O/Z
This pin is multiplexed between UART2, TSIF0, and GPIO.
When TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in
synchronous/asynchronous modes, this pin is the packet start input indicator,
TS0_PSTIN (I).
URTS2/UIRTX2/
TS0_PSTIN/GP[41]
IPU
DVDD33
AC20
Y18
I/O/Z
I/O/Z
This pin is multiplexed between UART1, TSIF0, and GPIO.
When TSIF0 serial input mux mode is enabled (PINMUX0.PTSIMUX = 11), in
synchronous/asynchronous modes, this pin is the serial input data bit (I),
TS0_DIN7(I).
URXD1/
TS0_DIN7/GP[23]
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-18. Transport Stream Interface 0 (TSIF0) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
AC10
Y12
TSIF0 PARALLEL OUTPUT (PINMUX0.PTSIMUX = 10)
This pin is multiplexed between the VPIF and TSIF0.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
transmit clock output, TS0_CLKO (O/Z).
VP_CLKO3/
TS0_CLKO
-
O/Z
DVDD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
data enable indicator, TS0_ENAO (O/Z) in either synchronous/asynchronous
modes.
UDTR0/
TS0_ENAO/GP[36]
IPU
DVDD33
I/O/Z
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
packet start output indicator, TS0_PSTO (O/Z) in either
synchronous/asynchronous modes.
UDSR0/
TS0_PSTO/
GP[37]
IPU
DVDD33
AB11
AA11
I/O/Z
I/O/Z
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), in asynchronous
mode, this pin is the wait input, TS0_WAITIN (I).
UDCD0/
TS0_WAITIN/
GP[38]
IPU
DVDD33
This TSIF pin function is not used in synchronous mode.
VP_DIN7/
TS0_DOUT7/
TS1_DIN
Y14
VP_DIN6/
TS0_DOUT6/
TS1_PSTIN
These pins are multiplexed between the VPIF, TSIF0, and TSIF1.
When parallel TSIF0 output is enabled (PINMUX0.PTSOMUX = 10), and
TSIF1 VPIF_DIN muxing is not enabled (TSSI_MUX ≠ 11), these pins are
the output data bits TS0_DOUT[7:4] (O/Z) in either
AA14
AB14
AC14
IPD
DVDD33
I/O/Z
VP_DIN5/
TS0_DOUT5/
TS1_EN_WAITO
synchronous/asynchronous modes.
VP_DIN4/
TS0_DOUT4/
TS1_WAITO
VP_DIN3/
TS0_DOUT3
Y15
VP_DIN2/
TS0_DOUT2
These pins are multiplexed between the VPIF and TSIF0.
When parallel TSIF0 output is enabled (PINMUX0.PTSOMUX = 10), these
pins are the output data bits TS0_DOUT[3:0] (O/Z) in either
synchronous/asynchronous modes.
AA15
AB15
AC15
IPD
DVDD33
I/O/Z
VP_DIN1/
TS0_DOUT1
VP_DIN0/
TS0_DOUT0
TSIF0 SERIAL OUTPUT (PINMUX0.PTSIMUX = 11)
This pin is multiplexed between the VPIF and TSIF0.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
transmit clock output, TS0_CLKO (O/Z).
VP_CLKO3/
TS0_CLKO
-
AC10
Y12
O/Z
DVDD33
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
data enable indicator, TS0_ENAO (O/Z) in either synchronous/asynchronous
modes.
UDTR0/
TS0_ENAO/GP[36]
IPU
DVDD33
I/O/Z
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the
packet start output indicator, TS0_PSTO (O/Z) in either
synchronous/asynchronous modes.
UDSR0/
TS0_PSTO/GP[37]
IPU
DVDD33
AB11
AA11
AB19
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between UART0, TSIF0, and GPIO.
When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), in asynchronous
mode, this pin is the wait input, TS0_WAITIN (I).
UDCD0/
TS0_WAITIN/GP[38]
IPU
DVDD33
This TSIF pin function is not used in synchronous mode.
This pin is multiplexed between UART1, TSIF0, and GPIO.
When serial TSIF0 output is enabled (PINMUX0.PTSOMUX = 11), in
synchronous/asynchronous modes, this pin is the serial output data bit,
TS0_DOUT[7] (O/Z).
UTXD1/URCTX1/
TS0_DOUT7/GP[24]
IPD
DVDD33
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Table 2-19. Transport Stream Interface 1 (TSIF1) Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
TSIF1 INPUT – UART0 MUXING (PINMUX0.TSSIMUX = 01)
IPD
DVDD33
TS1_CLKIN
AC11
AB13
I
I
TSIF1 receive clock input (I).
This pin is multiplexed between UART0 and TSIF1.
When TSIF1 input on UART0 muxing is enabled (PINMUX0.TSSIMUX = 01), this
pin is the serial data input, TS1_DIN (I).
URXD0/
TS1_DIN
IPD
DVDD33
This pin is multiplexed between UART0 and TSIF1.
URTS0/UIRTX0/
TS1_EN_WAITO
IPU
DVDD33
When TSIF1 input on UART0 muxing is enabled (PINMUX0.TSSIMUX = 01), in
synchronous mode, this pin is the data enable indicator (I) or in asynchronous
mode, this pin is the wait output, TS1_EN_WAITO (O/Z).
AA13
Y13
I/O/Z
I/O/Z
This pin is multiplexed between UART0 and TSIF1.
When TSIF1 input on UART0 muxing is enabled (PINUMX0.TSSIMUX = 01), this
pin is the packet start indicator, TS1_PSTIN (I).
UTXD0/URCTX0/
TS1_PSTIN
IPD
DVDD33
TSIF1 INPUT – VPIF DOUT MUXING (PINMUX0.TSSIMUX = 10)
IPD
TS1_CLKIN
AC11
AB8
I
TSIF1 receive clock input (I).
DVDD33
This pin is multiplexed between VPIF and TSIF1.
When TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10),
this pin is the serial data input, TS1_DIN (I).
VP_DOUT15/
TS1_DIN
IPD
DVDD33
I/O/Z
This pin is multiplexed between VPIF and TSIF1.
VP_DOUT13/
TS1_EN_WAITO
IPD
DVDD33
When TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10), in
synchronous mode, this pin is the data enable indicator (I) or in asynchronous
mode, this pin is the wait output, TS1_EN_WAITO (O/Z).
Y9
I/O/Z
I/O/Z
This pin is multiplexed between VPIF and TSIF1.
VP_DOUT14/
TS1_PSTIN
IPD
DVDD33
When TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10), in
synchronous/asynchronous modes, this pin is the packet start indicator,
TS1_PSTIN (I).
AC7
TSIF1 INPUT – VPIF DIN MUXING (PINMUX0.TSSIMUX = 11)
IPD
TS1_CLKIN
AC11
Y14
I
TSIF1 receive clock input (I).
DVDD33
VP_DIN7/
TS0_DOUT7/
TS1_DIN
This pin is multiplexed between VPIF, TSIF0, and TSIF1.
When TSIF1 input on VPIF DIN muxing is enabled (PINMUX0.TSSIMUX = 11), in
synchronous/asynchronous modes, this pin is the serial data input, TS1_DIN (I).
IPD
DVDD33
I/O/Z
This pin is multiplexed between VPIF, TSIF0, and TSIF1.
VP_DIN5/
TS0_DOUT5/
TS1_EN_WAITO
IPD
DVDD33
When TSIF1 input on VPIF DIN muxing is enabled (PINMUX0.TSSIMUX = 11), in
synchronous mode, this pin is the data enable indicator (I) or in asynchronous
mode, this pin is the wait output, TS1_EN_WAITO (O/Z).
AB14
AA14
I/O/Z
I/O/Z
This pin is multiplexed between VPIF, TSIF0, and TSIF1.
When TSIF1 input on VPIF DIN muxing is enabled (PINMUX0.TSSIMUX = 11), in
synchronous/asynchronous modes, this pin is the packet start indicator,
TS1_PSTIN (I).
VP_DIN6/
TS0_DOUT6/
TS1_PSTIN
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-19. Transport Stream Interface 1 (TSIF1) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
AC9
AB10
AC8
AA10
AB9
TSIF1 OUTPUT – VPIF DOUT MUXING (PINMUX0.TSSOMUX = 10)
This pin is multiplexed between the VPIF and TSIF1.
VP_CLKIN3/
TS1_CLKO
IPD
DVDD33
When TSIF1 output is enabled (PINMUX0.TSSOMUX = 1x), in
synchronous/asynchronous modes, this pin is the transmit clock output,
TS1_CLKO (O/Z).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between the VPIF and TSIF1.
VP_DOUT11/
TS1_DOUT
IPD
DVDD33
When TSIF1 output on VPIF DOUT muxing is enabled (PINMUX0.TSSOMUX = 10),
in synchronous/asynchronous modes, this pin is the serial data output,
TS1_DOUT (O/Z).
This pin is multiplexed between the VPIF and TSIF1.
When TSIF1 output on VPIF DOUT muxing is enabled (PINMUX0.TSSOMUX = 10),
in synchronous/asynchronous modes, this pin is the data enable indicator,
TS1_ENAO (O/Z).
VP_DOUT9/
TS1_ENAO
IPD
DVDD33
This pin is multiplexed between the VPIF and TSIF1.
VP_DOUT10/
TS1_PSTO
IPD
DVDD33
When TSIF1 output on VPIF DOUT muxing is enabled (PINMUX0.TSSOMUX = 10),
in synchronous/asynchronous modes, this pin is the packet start indicator output,
TS1_PSTO (O/Z).
This pin is multiplexed between the VPIF and TSIF1.
VP_DOUT8/
TS1_WAITIN
IPD
DVDD33
When TSIF1 output on VPIF DOUT muxing is enabled (PINMUX0.TSSOMUX = 10),
in asynchronous mode, this pin is the wait indicator input, TS1_WAITIN (I).
This TSIF pin function is not used in synchronous mode.
TSIF1 OUTPUT – UART/PWM MUXING (PINMUX0.TSSOMUX = 11)
This pin is multiplexed between the VPIF and TSIF1.
VP_CLKIN3/
TS1_CLKO
IPD
DVDD33
When TSIF1 output is enabled (PINMUX0.TSSOMUX = 1x), in
synchronous/asynchronous modes, this pin is the transmit clock output,
TS1_CLKO (O/Z).
AC9
W18
W17
AC21
Y11
I/O/Z
I/O/Z
O/Z
This pin is multiplexed between PWM1 and TSIF1.
When TSIF1 output on UART/PWM is enabled (PINMUX0.TSSOMUX = 11), in
synchronous/asynchronous modes, this pin is the serial data output,
TS1_DOUT (O/Z).
PWM1/
TS1_DOUT
-
DVDD33
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
When TSIF1 output on UART/PWM is enabled (PINMUX0.TSSOMUX = 11), in
synchronous/asynchronous modes, this pin is the data enable indicator output,
TS1_ENAO (O/Z)
PWM0/
CRG0_PO/
TS1_ENAO
-
DVDD33
UCTS2/USD2/
CRG0_VCX1/
GP[42]/
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When TSIF1 output on UART/PWM is enabled (PINMUX0.TSSOMUX = 11), in
synchronous/asynchronous modes, this pin is the packet start indicator output,
TS1_PSTO (O/Z).
IPU
DVDD33
I/O/Z
I/O/Z
TS1_PSTO
This pin is multiplexed between UART0, GPIO, and TSIF1.
URIN0/GP[8]/
TS1_WAITIN
IPD
DVDD33
When TSIF1 output on UART/PWM is enabled (PINMUX0.TSSOMUX = 11), in
asynchronous mode, this pin is the wait indicator input, TS1_WAITIN (I).
This TSIF pin function is not used in synchronous mode.
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Table 2-20. I2C Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
I2C
-
I2C clock output SCL. For proper device operation, this pin must be pulled up via
external resistor.
SCL
SDA
U5
U4
I/O/Z
I/O/Z
DVDD33
-
I2C bidirectional data signal SDA. For proper device operation, this pin must be
pulled up via external resistor.
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
Table 2-21. SPI Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
SPI
IPD
I/O/Z
SPI_CLK
SPI_EN
V1
T5
T4
U3
R5
P5
SPI clock
DVDD33
IPD
I/O/Z
SPI device enable
DVDD33
IPD
I/O/Z
SPI_CS0
SPI_CS1
SPI_SOMI
SPI_SIMO
SPI chip select 0
DVDD33
IPD
I/O/Z
SPI chip select 1
DVDD33
IPD
I/O/Z
SPI slave out, master in data pin
SPI slave in, master out data pin
DVDD33
IPD
I/O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-22. Multichannel Audio Serial Port (McASP) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
McASP0
IPD
I/O/Z
ACLKR0
AHCLKR0
AFSR0
AA2
AB2
Y3
McASP0 receive bit clock
DVDD33
IPD
I/O/Z
McASP0 receive high-frequency master clock
McASP0 receive frame sync
DVDD33
IPD
I/O/Z
DVDD33
IPD
I/O/Z
ACLKX0
AHCLKX0
AFSX0
AA1
Y1
McASP0 transmit bit clock
DVDD33
IPD
I/O/Z
McASP0 transmit high-frequency master clock
McASP0 transmit frame sync
DVDD33
IPD
I/O/Z
Y4
DVDD33
AXR0[3]
AXR0[2]
AXR0[1]
AXR0[0]
W3
W4
V4
IPD
I/O/Z
McASP0 transmit/receive data pins [3:0]
McASP0 mute output
DVDD33
V3
IPD
I/O/Z
AMUTE0
Y2
DVDD33
IPD
DVDD33
AMUTEIN0
AA3
I
McASP0 mute input
McASP1
IPD
I/O/Z
ACLKX1
AHCLKX1
AXR1[0]
W1
W2
V2
McASP1 transmit bit clock
DVDD33
IPD
I/O/Z
McASP1 transmit high-frequency master clock
McASP1 transmit data pin [0]
DVDD33
IPD
I/O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-23. Clock Recovery Generator (CRGEN) Terminal Functions
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
CRGEN1 ONLY MODE (PINMUX0.CRGMUX = 001)
URXD2/
CRG1_VCXI/
GP[39]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1 input
clock from external VCXO, CRG1_VCXI (I).
IPD
DVDD33
AB20
AA19
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1
pulse width modulation output, CRG1_PO (O/Z).
IPD
DVDD33
CRG0_PO
CRGEN0 ONLY (UART2/PWM0 MUX) MODE (PINMUX0.CRGMUX = 100)
UCTS2/ USD2/
CRG0_VCXI/
GP[42]/
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
IPU
DVDD33
AC21
W17
I/O/Z
O/Z
TS1_PSTO
PWM0/
CRG0_PO/
TS1_ENAO
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
–
DVDD33
CRGEN0 AND CRGEN1 MODE (PINMUX0.CRGMUX = 101)
URXD2/
CRG1_VCXI/
GP[39]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1 input
clock from external VCXO, CRG1_VCXI (I).
IPD
DVDD33
AB20
AA19
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1
pulse width modulation output, CRG1_PO (O/Z).
IPD
DVDD33
CRG0_PO
UCTS2/ USD2/
CRG0_VCXI/
GP[42]/
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
IPU
DVDD33
AC21
W17
I/O/Z
O/Z
TS1_PSTO
PWM0/
CRG0_PO/
TS1_ENAO
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
When CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
this pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
–
DVDD33
CRGEN0 ONLY (UART2 MUX) MODE (PINMUX0.CRGMUX = 110)
URXD2/
CRG1_VCXI/
GP[39]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
IPD
DVDD33
AB20
AA19
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
IPD
DVDD33
CRG0_PO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-24. UART0 Terminal Functions
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
Actual UART0 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 3.7.3, Pin Multiplexing.
UART0 WITH MODEM CONTROL (PINMUX1.UART0CTL = 00)
This pin is multiplexed between UART0 and TSIF1.
URXD0/
TS1_DIN
IPD
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
AB13
Y13
I
This pin is multiplexed between UART0 and TSIF1.
UTXD0/
URCTX0/
TS1_PSTIN
IPD
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 transmit data, UTXD0 (O/Z).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between UART0 and TSIF1.
URTS0 /
UIRTX0/
TS1_EN_WAITO
IPU
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is the UART0 request-to-send signal, URTS0 (O/Z).
AA13
AC12
Y12
This pin is multiplexed between UART0 and TSIF1.
IPU
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is the UART0 clear-to-send signal, UCTS0 (I).
UCTS0 / USD0
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDTR0 /
TS0_ENAO/
GP[36]
IPU
DVDD33
When UART0 UART with modem functional muxing is selected
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-terminal-ready, UDTR0 (O/Z).
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDSR0 /
TS0_PSTO/
GP[37]
IPU
DVDD33
When UART0 UART with modem functional muxing is selected
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-set-ready, UDSR0 (I).
AB11
AA11
This pin is multiplexed between UART0, TSIF0, and GPIO.
UDCD0 /
TS0_WAITIN/
GP[38]
IPU
DVDD33
When UART0 UART with modem functional muxing is selected
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-carrier-detect, UDCD0 (I).
This pin is multiplexed between UART0, GPIO, and TSIF1.
When UART0 UART with modem functional muxing is selected
(PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is the UART0 ring indicator,
URIN0 (I).
URIN0 /GP[8]/
TS1_WAITIN
IPD
DVDD33
Y11
I/O/Z
UART0 WITHOUT MODEM CONTROL (PINMUX1.UART0CTL = 01)
This pin is multiplexed between UART0 and TSIF1.
URXD0/
TS1_DIN
IPD
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
AB13
Y13
I
This pin is multiplexed between UART0 and TSIF1.
UTXD0/
URCTX0/
TS1_PSTIN
IPD
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 transmit data, UTXD0 (O/Z).
I/O/Z
This pin is multiplexed between UART0 and TSIF1.
URTS0 /
UIRTX0/
TS1_EN_WAITO
IPU
DVDD33
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 request-to-send signal, URTS0 (O/Z).
AA13
AC12
I/O/Z
I/O/Z
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 clear-to-send signal, UCTS0 (I).
UCTS0 /
USD0
IPU
DVDD33
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-24. UART0 Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
AB13
Y13
UART0 IrDA/CIR FUNCTION (PINMUX1.UART0CTL = 1x)
This pin is multiplexed between UART0 and TSIF1.
When TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01),
this pin is UART0 IrDA/CIR receive data, URXD0 (I).
URXD0/
TS1_DIN
IPD
DVDD33
I
This pin is multiplexed between UART0 and TSIF1.
UTXD0/
URCTX0/
TS1_PSTIN
IPD
DVDD33
When UART0 IrDA/CIR functional muxing is selected (PINMUX1.UART0CTL = 1x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 CIR transmit data, URCTX0 (O/Z).
I/O/Z
This pin is multiplexed between UART0 and TSIF1.
URTS0/
UIRTX0/
TS1_EN_WAITO
IPU
DVDD33
When UART0 IrDA/CIR functional muxing is selected (PINMUX1.UART0CTL = 1x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 IrDA transmit data, UIRTX0 (O/Z).
AA13
AC12
I/O/Z
I/O/Z
When UART0 IrDA/CIR functional muxing is selected (PINMUX1.UART0CTL = 1x)
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 IrDA transceiver control, USD0 (O/Z).
UCTS0/
USD0
IPU
DVDD33
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Table 2-25. UART1 Terminal Functions
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
UART1 WITH FLOW CONTROL (PINMUX1.UART1CTL = 00)
Actual UART1 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 3.7.3, Pin Multiplexing.
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
URXD1/
TS0_DIN7/
GP[23]
IPD
DVDD33
Y18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
and TSIF0 serial output is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 transmit data, UTXD1 (O/Z).
IPD
DVDD33
AB19
AA18
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART with flow control muxing is selected (PINMUX1.UART1CTL =
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX ≠ 0x), this pin is UART1
request-to-send, URTS1 (O/Z).
URTS1 /UIRTX1/
TS0_WAITO/
GP[25]
IPU
DVDD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART with flow control muxing is selected (PINMUX1.UART1CTL =
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX ≠ 0x), this pin is UART1
clear-to-send, UCTS1 (I).
UCTS1 /USD1
TS0_EN_WAITO/ Y17
GP[26]
IPU
DVDD33
UART1 WITHOUT FLOW CONTROL (PINMUX1.UART1CTL = 01)
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
URXD1/
TS0_DIN7/
GP[23]
IPD
DVDD33
Y18
I/O/Z
I/O/Z
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
and TSIF0 serial output is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 transmit data, UTXD1 (O/Z).
IPD
DVDD33
AB19
UART1 IrDA/CIR FUNCTION (PINMUX1.UART1CTL = 10)
This pin is multiplexed between UART1, TSIF0, and GPIO.
URXD1/
TS0_DIN7/
GP[23]
IPD
DVDD33
When UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
Y18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between UART1, TSIF0, and GPIO.
UTXD1/URCTX1/
TS0_DOUT7/
GP[24]
IPD
DVDD33
When UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
and TSIF0 serial output is not enabled (PINMUX0.PTSOMUX ≠ 11), this pin is
UART1 CIR transmit data, URCTX1 (O/Z).
AB19
AA18
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART1 IrDA
transmit data, UIRTX1 (O/Z).
URTS1/UIRTX1/
TS0_WAITO/
GP[25]
IPU
DVDD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART1 IrDA
tranceiver control, USD1 (O/Z).
UCTS1/USD1/
TS0_EN_WAITO/ Y17
GP[26]
IPU
DVDD33
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-26. UART2 Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NO.
UART2 WITH FLOW CONTROL (PINMUX1.UART2CTL = 00)
Actual UART2 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 3.7.3, Pin Multiplexing.
URXD2/
CRG1_VCXI/
GP[39]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 receive data, URXD2 (I).
IPD
DVDD33
AB20
AA19
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/
URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 transmit data, UTXD2 (O/Z).
IPD
DVDD33
CRG0_PO
This pin is multiplexed between UART2, TSIF0, and GPIO.
When UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2
request-to-send, URTS2 (O/Z).
URTS2 /UIRTX2/
TS0_PSTIN/
GP[41]
IPU
DVDD33
AC20
AC21
I/O/Z
I/O/Z
UCTS2 /USD2/
CRG0_VCXI/
GP[42]/
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =
00) and TSIF1 output is not enabled (PINMUX0.PTSOMUX = 0x), this pin is
UART2 clear-to-send, UCTS2 (I).
IPU
DVDD33
TS1_PSTO
UART2 WITHOUT FLOW CONTROL (PINMUX1.UART2CTL = 01)
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
URXD2/
CRG1_VCXI/
GP[39]/
IPD
DVDD33
When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 receive data, URXD2 (I).
AB20
AA19
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/
URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 transmit data, UTXD2 (O/Z).
IPD
DVDD33
CRG0_PO
UART2 IrDA/CIR FUNCTION (PINMUX1.UART2CTL = 10)
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
URXD2/
CRG1_VCXI/
GP[39]/
IPD
DVDD33
When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 receive data, URXD2 (I).
AB20
AA19
AC20
AC21
I/O/Z
I/O/Z
I/O/Z
I/O/Z
CRG0_VCXI
UTXD2/URCTX2/
CRG1_PO/
GP[40]/
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is the
UART2 CIR transmit data, URCTX2 (O/Z).
IPD
DVDD33
CRG0_PO
This pin is multiplexed between UART2, TSIF0, and GPIO.
When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2 IrDA
transmit data, UIRTX2 (O/Z).
URTS2/UIRTX2/
TS0_PSTIN/
GP[41]
IPU
DVDD33
UCTS2/USD2/
CRG0_VCXI/
GP[42]/
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
and CRGEN0 on TSIF0 output is not enabled (PINMUX0.TSSOMUX = 0x), this
pin is UART2 IrDA tranceiver control, USD2 (O/Z).
IPU
DVDD33
TS1_PSTO
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-27. PWM Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)
DESCRIPTION
NAME
NO.
PWM0
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
PWM0/
CRG0_PO/
TS1_ENAO
–
When not overridden by CRGEN or TSIF1 output muxing (PINMUX0.CRGMUX ≠
10x and PINMUX0.TSSOMUX ≠ 11), this pin is the pulse width modulation 0 output,
PWM0 (O/Z).
W17
O/Z
DVDD33
PWM1
This pin is multiplexed between PWM1 and TSIF1.
When not overridden by TSIF1 output muxing (PINMUX0.TSSOMUX ≠ 11), this pin
is the pulse width modulation 1 output, PWM1 (O/Z).
PWM1/
TS1_DOUT
–
W18
O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
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Table 2-28. Timer 0, Timer 1, and Timer 2 Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
Timer 0
IPD
I/O/Z
Timer0 lower input. This pin is the Timer0 input for 64-mode operation. For 32-bit
timer operation, this pin is the input for the Timer0 lower 32-bit counter.
TINP0L
TINP0U
TOUT0L
TOUT0U
Y7
AA6
W8
W7
DVDD33
IPD
I/O/Z
Timer0 upper input. For 32-bit timer operation, this pin is the input for the Timer0
upper 32-bit counter. Not used for Timer0 64-mode operation.
DVDD33
IPD
I/O/Z
Timer0 lower output. This pin is the Timer0 output for 64-mode operation. For 32-bit
timer operation, this pin is the output for the Timer0 lower 32-bit counter.
DVDD33
IPD
I/O/Z
Timer0 upper output. For 32-bit timer operation, this pin is the output for the Timer0
upper 32-bit counter. Not used for Timer0 64-mode operation.
DVDD33
Timer 1
IPD
I/O/Z
Timer1 lower input. This pin is the Timer1 input for 64-mode operation. For 32-bit
timer operation, this pin is the input for the Timer1 lower 32-bit counter.
TINP1L
TOUT1L
TOUT1U
Y6
DVDD33
IPD
I/O/Z
Timer1 lower output. This pin is the Timer1 output for 64-mode operation. For 32-bit
timer operation, this pin is the output for the Timer1 lower 32-bit counter.
AA5
AB4
DVDD33
IPD
I/O/Z
Timer1 upper output. For 32-bit timer operation, this pin is the output for the Timer1
upper 32-bit counter. Not used for Timer1 64-mode operation.
DVDD33
WATCHDOG TIMER (Timer 2)
IPD
I/O/Z
TOUT2
Y5
Watchdog timer output.
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-29. ATA Terminal Functions
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
ATA
ATA is enabled by the PINMUX0.ATAEN =1 (and PCIEN = 0). For more detailed information on the ATA pin muxing, see Section 3.7.3.1,
PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_CBE0/
ATA_CS0 /
GP[33]/EM_A[18]
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA chip select 0 output, ATA_CS0 (O/Z).
F4
C2
I/O/Z
I/O/Z
PCI_CBE1/
ATA_CS1 /
GP[32]/EM_A[19]
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA chip select 1 output, ATA_CS1 (O/Z).
PCI_RSV4/ DIOW /
GP[20]/EM_WAIT4
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is the ATA write strobe output, DIOW (O/Z).
A11
E10
D11
I/O/Z
I/O/Z
I/O/Z
PCI_RSV3/ DIOR /
GP[19]/EM_WAIT5
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is the ATA read strobe output, DIOR (O/Z).
PCI_RSV5/IORDY/
GP[21]/EM_WAIT3
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA I/O ready, IORDY (I).
PCI_RST/
DA2/
GP[13]/EM_A[22]
IPD
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA address bit 2, DA2 (O/Z).
C10
I/O/Z
PCI_RSV0/DA1/
GP[16]/EM_A[21]
IPD
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA address bit 1, DA1 (O/Z).
A9
E9
I/O/Z
I/O/Z
I/O/Z
PCI_RSV1/DA0/
GP[17]/EM_A[20]
IPD
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is ATA address bit 0, DA0 (O/Z).
PCI_RSV2/INTRQ/
GP[18]/EM_RSV0
IPD
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is the ATA interrupt request input, INTRQ (I).
B10
PCI_REQ/
DMARQ/
GP[11]/EM_CS5
IPU
DVDD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is the ATA DMA request input, DMARQ (I).
B9
D10
E8
I/O/Z
I/O/Z
I/O/Z
PCI_GNT/
DMACK /
GP[12]/EM_CS4
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When ATA is enabled, this pin is the ATA DMA acknowledge output, DMACK
(O/Z).
IPU
DVDD33
PCI_IDSEL/
HDDIR/
EM_R/W
This pin is multiplexed between PCI, ATA, and EMIFA.
When ATA is enabled, this pin is the data direction indicator for external buffer
control, HDDIR (O/Z).
IPU
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-29. ATA Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
PCI_AD31/
DD15/
A8
HD31/ EM_A[15]
PCI_AD30/
DD14/
HD30/EM_A[14]
C9
B8
D9
A6
C8
B6
D8
B5
C7
C5
D7
A4
E7
B4
C6
PCI_AD29/
DD13/
HD29/EM_A[13]
PCI_AD28/
DD12/
HD28/EM_A[12]
PCI_AD27/
DD11/
HD27/EM_A[11]
PCI_AD26/
DD10/
HD26/EM_A[10]
PCI_AD25/
DD9/
HD25/EM_A[9]
PCI_AD24/
DD8/
HD24/EM_A[8]
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
When ATA is enabled, these pins are the ATA 16-bit bidirectional data bus,
DD[15:0] (I/O/Z).
IPD
I/O/Z
DVDD33
PCI_AD23/
DD7/
HD23/EM_A[7]
PCI_AD22/
DD6/
HD22/EM_A[6]
PCI_AD21/
DD5/
HD21/EM_A[5]
PCI_AD20/
DD4/
HD20/EM_A[4]
PCI_AD19/
DD3/
HD19/EM_A[3]
PCI_AD18/
DD2/
HD18/EM_A[2]
PCI_AD17/
DD1/
HD17/EM_A[1]
PCI_AD16/
DD0/
HD16/EM_A[0]
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Table 2-30. General Purpose Input/Output (GPIO) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2) (3)
DESCRIPTION
NO.
GPIO
The VCE6467T device does not support GP[47:43], GP[35:34], GP[31:27], GP[15:14], and GP[9] signals (not pinned out).
GP[7:0] pins have dedicated ARM926 and DSP interrupts.
When PCI is used, GP[19:16] pins are reserved.
IPD
DVDD33
GP[0]
GP[1]
W5
V5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
GP[0] (I/O/Z). This pin is general-purpose input/output 0.
IPD
DVDD33
GP[1] (I/O/Z). This pin is general-purpose input/output 1.
GP[2]/
AUDIO_CLK1
IPD
DVDD33
This pin is multiplexed between GPIO and the audio clock selector.
When audio clock 1 is disabled (PINMUX0.AUDCK1 = 0), this pin is GP[2] (I/O/Z).
AA4
AB3
GP[3]/
AUDIO_CLK0
IPD
DVDD33
This pin is multiplexed between GPIO and the audio clock selector.
When audio clock 0 is disabled (PINMUX0.AUDCK0 = 0), this pin is GP[3] (I/O/Z).
This pin is multiplexed between GPIO and the TSIF clock selector.
When the STC source clock input is disabled (PINMUX0.STCCK = 0), this pin is
GP[4] (I/O/Z).
GP[4]/
STC_CLKIN
IPD
DVDD33
AC3
I/O/Z
IPD
DVDD33
GP[5]
GP[6]
GP[7]
B11
E11
A12
I/O/Z
I/O/Z
I/O/Z
This pin is GP[5] (I/O/Z).
This pin is GP[6] (I/O/Z).
This pin is GP[7] (I/O/Z).
IPD
DVDD33
IPD
DVDD33
This pin is multiplexed between UART0, GPIO, and TSIF1.
URIN0/GP[8]/
TS1_WAITIN
IPD
DVDD33
When UART0 UART with modem functional muxing is not selected
(PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is GP[8] (I/O/Z).
Y11
I/O/Z
GP[9]
n/a
–
–
GP[9] is not pinned out on this device.
IPU
DVDD33
This pin is multiplexed between PCI and GPIO.
When PCI is disabled (PINMUX0.PCIEN = 0), this pin is GP[10] (I/O/Z).
PCI_CLK/GP[10]
A10
I/O/Z
PCI_REQ/
DMARQ/
GP[11]/EM_CS5
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), this pin is GP[11] (I/O/Z).
IPU
DVDD33
B9
I/O/Z
I/O/Z
PCI_GNT/
DMACK/
GP[12]/EM_CS4
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), this pin is GP[12] (I/O/Z).
IPU
DVDD33
D10
PCI_RST/
DA2/
GP[13]/EM_A[22]
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), this pin is GP[13] (I/O/Z).
IPD
DVDD33
C10
n/a
A9
I/O/Z
–
GP[14:15]
–
GP[14:15] are not pinned out on this device.
PCI_RSV0/DA1/
GP[16]/
IPD
DVDD33
I/O/Z
EM_A[21]
PCI_RSV1/DA0/
GP[17]/EM_A[20]
IPD
DVDD33
E9
I/O/Z
I/O/Z
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[16:19] (I/0/Z). When PCI mode is enabled
(PINMUX0.PCIEN = 1), these pins are reserved.
PCI_RSV2/
INTRQ/
GP[18]/
IPD
DVDD33
B10
EM_RSV0
PCI_RSV3/DIOR/
GP[19]/
IPU
DVDD33
E10
I/O/Z
EM_WAIT5
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-30. General Purpose Input/Output (GPIO) Terminal Functions (continued)
SIGNAL
TYPE(1) OTHER(2) (3)
DESCRIPTION
NAME
NO.
PCI_RSV4/
DIOW/
GP[20]/
IPU
I/O/Z
A11
DVDD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[20:21] (I/0/Z).
EM_WAIT4
PCI_RSV5/
IORDY/
GP[21]/
IPU
I/O/Z
D11
DVDD33
EM_WAIT3
USB_DRVVBUS/
IPD
I/O/Z
This pin is multiplexed between USB and GPIO.
When not used for USB (PINMUX0.VBUSDIS = 1), this pin is GP[22] (I/O/Z).
B18
Y18
GP[22]
DVDD33
URXD1/
TS0_DIN7/
GP[23]
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[23] (I/O/Z).
IPD
I/O/Z
DVDD33
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
This pin is multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1. UART1CTL = 11) and TSIF0
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[24] (I/O/Z).
IPD
I/O/Z
AB19
AA18
DVDD33
URTS1/
UIRTX1/
TS0_WAITO/
GP[25]
IPD
I/O/Z
DVDD33
These pins are multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
input is not enabled (PINMUX0.PTSIMUX = 0x), these pins are GP[25:26] (I/O/Z).
UCTS1/USD1/
TS0_EN_WAITO/ Y17
IPU
I/O/Z
DVDD33
GP[26]
GP[27:31]
n/a
C2
–
–
GP[27:31] are not pinned out on this device.
PCI_CBE1/
ATA_CS1/
GP[32]/
IPU
DVDD33
I/O/Z
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[32:33] (I/O/Z).
EM_A[19]
PCI_CBE0/
ATA_CS0/
GP[33]/
IPU
DVDD33
F4
I/O/Z
EM_A[18]
GP[34:35]
n/a
–
–
GP[34:35] are not pinned out on this device.
UDTR0/
TS0_ENAO/
GP[36]
IPU
DVDD33
Y12
I/O/Z
These pins are multiplexed between UART0, TSIF0, and GPIO.
When UART0 UART with modem functional muxing is not selected
(PINMUX1.UART0CTL ≠ 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), these pins are GP[36:38] (I/O/Z).
UDSR0/
TS0_PSTO/
GP[37]
IPU
DVDD33
AB11
AA11
I/O/Z
I/O/Z
UDCD0/
TS0_WAITIN/
GP[38]
IPU
DVDD33
URXD2/
CRG1_VCXI/
GP[39]/
IPD
DVDD33
AB20
AA19
AC20
I/O/Z
I/O/Z
I/O/Z
These pins are multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART GPIO muxing is selected (PINMUX1.UART2CTL = 11) and
CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), these pins are
GP[39:40] (I/O/Z).
CRG0_VCXI
UTXD2/URCTX2/
CRG1_PO/
GP[40]/
IPD
DVDD33
CRG0_PO
This pin is multiplexed between UART2, TSIF0, and GPIO.
When UART2 UART without flow control or GPIO muxing is selected
(PINMUX1.UART2CTL = x1) and TSIF0 input is not enabled
(PINMUX0.PTSIMUX = 0x), this pin is GP[41] (I/O/Z).
URTS2/UIRTX2/
TS0_PSTIN/
GP[41]
IPU
DVDD33
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When UART2 UART without flow control or GPIO muxing is selected
(PINMUX1.UART2CTL = x1) and CRGEN0 on UART2/PWM muxing is not enabled
(PINMUX0.CRGMUX ≠ 10x) and TSIF1 output is not enabled
(PINMUX0.TSSOMUX = 0x), this pin is GP[42] (I/O/Z).
UCTS2/USD2/
CRG0_VCXI/
GP[42]/
IPU
DVDD33
AC21
I/O/Z
TS1_PSTO
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Table 2-30. General Purpose Input/Output (GPIO) Terminal Functions (continued)
SIGNAL
NAME
GP[43:47]
TYPE(1) OTHER(2) (3)
DESCRIPTION
GP[43:47] are not pinned out on this device.
NO.
n/a
–
–
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Table 2-31. Reserved Terminal Functions
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
RESERVED
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
A1
A2
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. (Leave unconnected, do not connect to power or ground.)
Reserved. (Leave unconnected, do not connect to power or ground.)
.
.
.
A22
A23
D14
F17
G16
Reserved. For proper device operation, this pin must be tied directly to CVDD
.
.
Reserved. For proper device operation, this pin must be tied directly to CVDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-32. Supply Terminal Functions
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
SUPPLY VOLTAGE PINS
B7
F8
F9
F10
F11
F12
F13
F14
F15
F16
G7
H6
J6
K6
K7
3.3-V I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDD33
M3
S
R7
T7
U7
V7
V8
V17
W9
W10
W11
W12
W13
W14
W15
W16
AA12
B20
E21
G17
G19
H17
J17
K17
K21
P21
R17
1.8-V DDR2 I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDDR2
S
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-32. Supply Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER
DESCRIPTION
NO.
R18
T18
T19
U19
W21
AA20
G8
1.8-V DDR2 I/O supply voltage
DVDDR2
S
(see the Power-Supply Decoupling section of this data manual)
G9
G10
G11
G12
G13
G14
G15
H7
H8
H9
H14
H15
H16
J7
J8
J9
J10
J11
J13
J14
J15
J16
K8
1.3-V core supply voltage (-1G devices)
(see the Power-Supply Decoupling section of this data manual)
CVDD
S
K9
K10
K11
K13
K14
K15
K16
P7
P8
P9
P10
P11
P13
P14
P15
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Table 2-32. Supply Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
R8
R9
R10
R11
R13
R14
R15
T8
T9
T10
T11
T13
T14
T15
U8
1.3-V core supply voltage (-1G devices)
(see the Power-Supply Decoupling section of this data manual)
CVDD
S
U9
U10
U14
U15
U16
V9
V10
V11
V12
V13
V14
V15
V16
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Table 2-33. Ground Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER
DESCRIPTION
NO.
GROUND PINS
A7
A14
A18
A21
B1
B19
B23
C19
D19
E19
E22
F6
F7
F19
G6
G18
H5
H10
H11
H12
H13
H18
H19
J5
VSS
GND
Ground pins
J12
J18
K5
K12
K18
K22
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-33. Ground Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER
DESCRIPTION
NAME
NO.
L18
M2
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
P6
VSS
GND
Ground pins
P12
P16
P17
P18
P22
R6
R12
R16
T6
T12
T16
T17
U6
U11
U12
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Table 2-33. Ground Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER
DESCRIPTION
NO.
U13
U17
U18
V6
V18
V19
W19
W22
Y19
VSS
GND
Ground Pins
AB1
AB12
AB21
AB23
AC1
AC2
AC22
AC23
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2.9 Device Support
2.9.1 Development Support
TI offers an extensive line of development tools for the TMS320DM646x DMSoC platform (which also
encompasses the VCE6467T/AVCE6467T devices), including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320DM646x SoC-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SoC application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the TMS320DM646x DMSoC platform, visit the
Texas Instruments web site on the Worldwide Web at www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
2.9.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g.,VCE6467TZUTL1). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz or gigahertz (for example, "L1" is the
default [1-GHz DSP, 500-MHz ARM9, 108-MHz VPIF, 400-MHz DDR2]).
Figure 2-9 provides a legend for reading the complete device name for any VCE6467T DMSoC platform
member.
(
)
L1
VCE6467T ( ) ZUT
DEVICE SPEED RANGE
L1 = 1-GHz DSP, 500-MHz ARM9,108-MHz VPIF, 400-MHz DDR2
TEMPERATURE RANGE
Blank = 0° C to 85° C, Commercial Temperature
DEVICE
D
= -40° C to 85° C, Industrial Temperature
C64x+™ DSP:
VCE6467T
AVCE6467T (Advanced)
PACKAGE TYPE (A)
ZUT = 529-pin plastic BGA, with Pb-Free soldered balls [Green]
SILICON REVISION
TMS
Blank = Revision 3.0
A. BGA = Ball Grid Array
B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com)
Figure 2-9. Device Nomenclature(B)
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2.10 Documentation Support
2.10.1 Related Documentation From Texas Instruments
The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC) platform
(which includes the VCE6467T/AVCE6467T devices). Copies of these documents are available on the
Internet at www.ti.com. Tip: Enter the literature number in the search box provided.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUEP8 TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9 TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM
subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the
DSP subsystem and a majority of the peripherals and external memories.
SPRUEQ0 TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM646x Digital Media
System-on-Chip (DMSoC).
SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRAAV0 Understanding TI's PCB Routing Rule-Based DDR Timing Specification Application
Report This application report describes the way the DDR high-speed timing requirements
are now going to be communicated to system designers. The system designer uses this
information to evaluate whether timing specifications are met and can be expected to
operate reliably.
2.11 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
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3 Device Configurations
3.1 System Module Registers
The system module includes status and control registers for configuration of the device.Brief descriptions
of the various registers are shown in Table 3-1. System Module registers required for device
configurations are discussed in the following sections.
Table 3-1. System Module Register Memory Map
HEX ADDRESS RANGE
0x01C4 0000
REGISTER ACRONYM
PINMUX0
DESCRIPTION
Pin Multiplexing Control 0 (see Section 3.7.2.1, PINMUX0 Register).
Pin Multiplexing Control 1 (see Section 3.7.2.2, PINMUX1 Register).
0x01C4 0004
0x01C4 0008
PINMUX1
DSPBOOTADDR
DSP Boot Address. Decoded by bootloader software for host boots.
(See Section 3.4.2.1, DSPBOOTADDR Register.)
0x01C4 000C
SUSPSRC
BOOTSTAT
BOOTCFG
–
Emulator Suspend Source (see Section 3.7.3.12, Emulation Control).
Boot Status (see Section 3.4.2.2, BOOTSTAT Register).
Device Boot Configuration (see Section 3.4.2.3, BOOTCFG Register).
Reserved
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C - 0x01C4 0020
0x01C4 0024
–
Reserved
ARMBOOT
JTAGID
ARM926 Boot Control (see Section 3.4.2.4, ARMBOOT Register).
0x01C4 0028
Device ID Number [see Section 6.29.1, JTAG ID (JTAGID) Register
Description(s)].
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
–
Reserved
HPICTL
USBCTL
VIDCLKCTL
MSTPRI0
HPI Control (see Section 3.6.2.1, HPICTL Register).
USB Control (see Section 3.6.2.2, USBCTL Register).
Video Clock Control (see Section 3.3.2.1, Video Clock Control).
Bus Master Priority Control 0 (see Section 3.6.1, Switch Central
Resource (SCR) Bus Priorities).
0x01C4 0040
0x01C4 0044
0x01C4 0048
MSTPRI1
Bus Master Priority Control 1 (see Section 3.6.1, Switch Central
Resource (SCR) Bus Priorities).
MSTPRI2
Bus Master Priority Control 2 (see Section 3.6.1, Switch Central
Resource (SCR) Bus Priorities).
VDD3P3V_PWDN
VDD 3.3-V I/O Powerdown Control (see Section 3.2, Power
Considerations).
0x01C4 004C
0x01C4 0050
0x01C4 0054
–
Reserved
TSIFCTL
PWMCTL
TSIF Control Register (see Section 3.3.2.2, TSIF Control).
PWM Control (see Section 3.6.2.3, PWM (Trigger Source) Control
Register).
0x01C4 0058
0x01C4 005C
0x01C4 0060
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
EDMATCCFG
CLKCTL
EDMA TC Configuration (see Section 3.6.2.4, EDMATCCFG
Register).
Oscillator and Output Clock Control (see Section 3.3.3, Clock and
Oscillator Control).
DSPINT
ARM to DSP Interrupt Status (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
DSPINTSET
DSPINTCLR
VSCLKDIS
ARMINT
ARM to DSP Interrupt Set (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
ARM to DSP Interrupt Clear (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
Video and TSIF Clock Disable (see Section 3.3.2.3, Video and TSIF
Clock Disable).
DSP to ARM Interrupt Status (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
ARMINTSET
DSP to ARM Interrupt Set (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
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Table 3-1. System Module Register Memory Map (continued)
HEX ADDRESS RANGE
0x01C4 0078
REGISTER ACRONYM
DESCRIPTION
ARMINTCLR
DSP to ARM Interrupt Clear (see Section 3.7.3.11, ARM/DSP
Communications Interrupts).
0x01C4 007C
ARMWAIT
–
ARM Memory Wait State Control (see Section 3.4.2.5, ARMWAIT
Register).
0x01C4 0080 - 0x01C4 03FF
Reserved
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3.2 Power Considerations
The VCE6467T provides several means of managing power consumption.
As described in the Section 6.3.4, VCE6467T Power and Clock Domains, the VCE6467T has one single
power domain—the “Always On” power domain. Within this power domain, the VCE6467T utilizes local
clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the
PSC, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM646x DMSoC ARM
Subsystem Reference Guide (literature number SPRUEP9).
Some of the VCE6467T peripherals support additional power saving features. For more details on power
saving features supported, see the peripheral-specific reference guides [listed/linked in the
TMS320DM646x DMSoC Peripherals Overview Reference Guide (literature number SPRUEQ0).
Most VCE6467T 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN
register in the System Module (see Figure 3-1 ) is used to selectively power down unused 3.3-V I/O pins.
Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user
must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers.
For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section 3.7.3,
Pin Multiplexing Details.
Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep
Controller (PSC) determines the clock/power state of the peripheral.
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
USBV
CLKOUT
RSV
SPI
VLYNQ
RESERVED
GMII
MII
MCASP1 MCASP0 PCIHPI1 PCIHPI0
R-000
R/W-1 R/W-0
R-0
R/W-1 R/W-1
R-00
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO
WDTIM
TIM23
TIM01
PWM1
PWM0
UR2FC
UR2DAT
UR1FC
UR1DAT UR0MDM UR0DF
VPIF3
VPIF2
VPIF1
VPIF0
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-1. VDD3P3V_PWDN Register [0x01C4 0048]
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Table 3-2. VDD3P3V_PWDN Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:29
RESERVED
Reserved. Read returns "0".
USB_DRVVBUS Powerdown Control.
0 = I/O cells powered up.
1 = I/O cells powered down.
28
USBV
This bit controls the USB_DRVVBUS/GP[22] pin.
CLKOUT0 Powerdown Control.
This bit controls the CLKOUT0 pin.
27
26
CLKOUT
RSV
Reserved. Read returns "0".
SPI Powerdown Control.
25
SPI
This bit controls the six SPI interface pins: SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_SOMI, and
SPI_SIMO.
VLYNQ Powerdown Control.
24
23:22
21
VLYNQ
RESERVED
GMII
This bit controls the ten VLYNQ interface pins: VLYNQ_CLOCK, VLYNQ_SCRUN,
VLYNQ_TXD[3:0], and VLYNQ_RXD[3:0].
Reserved. Read returns "0".
GMII Powerdown Control.
This bit controls the ten pins used by GMII (Gigabit) only: RFTCLK, GMTCLK, MTXD[7:4], and
MRXD[7:4].
MII Powerdown Control.
20
19
18
MII
This bit controls the 17 pins used by (G)MII (10/100/1000) and MDIO interfaces: MTCLK,
MTXD[3:0], MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, and MDIO.
McASP1 Powerdown Control.
This bit controls the three McASP1 pins: ACLKX1, AHCLKX1, and AXR1[0].
MCASP1
MCASP0
McASP0 Powerdown Control.
This bit controls the 12 McASP0 pins: ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0,
AXR0[3:0], AMUTE0, and AMUTEIN0.
PCI/HPI/EMIFA/ATA Powerdown Control.
This bit controls the 28 pins used by the ATA or PCI`, HPI, or EMIFA. These pins include:
PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],
DIOW/GP[20]/EM_WAIT4/(RDY4/BSY4), IORDY/GP[21]/EM_WAIT3/(RDY3/BSY3),
DIOR/GP[19]/EM_WAIT5/(RDY5/BSY5), DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20],
INTRQ/GP[18]/RSV , PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0]
Defaults to powered up for NOR boot.
17
PCIHPI1
PCI/HPI/EMIFA Powerdown Control.
This bit controls the 28 pins used by PCI, HPI, or EMIFA but not shared with ATA. These pins
include: PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17]/(CLE), PCI_TRDY/HHWIL/EM_A[16]/(ALE),
PCI_STOP/HCNTL0/EM_WE, PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1,
PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2/(RDY2/BSY2), PCI_CBE3/HR/W/EM_CS3,
PCI_CBE2/HDS2/EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0]
16
PCIHPI0
Defaults to powered up for NOR boot.
GPIO Powerdown Control.
This bit controls the eight GP[7:0] pins. Defaults to powered up.
15
14
13
12
11
10
GPIO
WDTIM
TIM23
TIM01
PWM1
PWM0
WD Timer Powerdown Control.
This bit controls the WD Timer pin TOUT2.
Timer1 Powerdown Control.
This bit controls the three Timer1 pins TINP1L, TOUT1L, and TOUT1U.
Timer0 Powerdown Control.
This bit controls the four Timer0 pins TINP0L, TINP0U, TOUT0L, and TOUT0U.
PWM1 Powerdown Control.
This bit controls the PWM1/TS1_DOUT pin.
PWM0 Powerdown Control.
This bit controls the PWM0/CRG0_PO/TS1_ENAO pin.
UART2 Flow Control Powerdown Control.
9
UR2FC
This bit controls the URTS2/UIRTX2/TS0_PSTIN/GP[41] and
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO pins.
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Table 3-2. VDD3P3V_PWDN Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
UART2 Data Powerdown Control.
8
UR2DAT
This bit controls the URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI and
UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO pins.
UART1 Flow Control Powerdown Control.
7
6
5
UR1FC
UR1DAT
UR0MDM
This bit controls the URTS1/UIRTX1/TS0_WAITO/GP[25] and
UCTS1/USD1/TS0_EN_WAITO/GP[26] pins.
UART1 Data Powerdown Control.
This bit controls the URXD1/TS0_DIN7/GP[23] and UTXD1/URCTX1/TS0_DOUT7/GP[24] pins.
UART0 Modem Control Powerdown Control.
This bit controls the UDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37],
UDCD0/TS0_WAITIN/GP[38], and URIN0/GP[8]/TS1_WAITIN pins.
UART0 Data and Flow Control Powerdown Control.
4
3
UR0DF
VPIF3
This bit controls the URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN,
URTS0/UIRTX0/TS1_EN_WAITO, and UCTS0/USD0 pins.
VPIF MSB Output Powerdown Control.
This bit controls the VP_DOUT[15:8]/TS1_xx, VP_CLKIN3/TS1_CLKO, and VP_CLKO3/TS0_CLKO
pins.
VPIF LSB Output Powerdown Control.
2
1
0
VPIF2
VPIF1
VPIF0
This bit controls the VP_DOUT[7:0], VP_CLKIN2, and VP_CLKO2 pins. (VP_DOUT[7:0] are boot
configuration inputs.)
VPIF MSB Input Powerdown Control.
This bit controls the VP_DIN[15:8]/TS0_DIN[7:0] and VP_CLKIN1 pins.
VPIF LSB Input Powerdown Control.
This bit controls the VP_DIN[3:0]/TS0_DOUT[3:0], VP_DIN[7:4]/TS0_DOUT[7:4]/TS1_xx, and
VP_CLKIN0 pins.
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3.3 Clock Considerations
Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC). In addition, the System Module Video Clock Control (VIDCLKCTL),
TSIF Control (TSIFCTL), and Clock and Oscillator Control (CLKCTL) registers configure the clock sources
to the VPIF, TSIF, CRGEN peripherals, and the Auxiliary Oscillator.
The selected Video, TSIF, and CRGEN module input clocks are disabled using the System Module Video
Source Clock Disable (VSCLKDIS) register. Note: To ensure glitch-free operation, the clock should be
disabled before changing the clock source frequency or muxing via the VIDCLKCTL and TSIFCTL.
3.3.1 Clock Configurations after Device Reset
After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the
desired peripheral clock state (clock gating or not).
For additional power savings, some of the VCE6467T peripherals support clock gating within the
peripheral boundary. For more details on clock gating and power saving features supported by a specific
peripheral, see the peripheral-specific reference/user's guides [listed/linked in the TMS320DM646x
DMSoC Peripherals Overview Reference Guide (literature number SPRUEQ0)].
3.3.1.1 Device Clock Frequency
The VCE6467T defaults to PLL bypass mode. If the ROM bootloader is selected (BTMODE[3:0] ≠ 0100),
the bootloader code programs PLLC1 and PLLC2.
Section 3.4.1, Boot Modes discusses the different boot modes in more detail.
The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:
•
PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see
Section 6.5.1, PLL1 and PLL2.
3.3.1.2 Module Clock State
The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).
Table 3-3 shows the default state of each module after a device-level global reset. The VCE6467T device
has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on
the definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep
Controller (PSC) and the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
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Table 3-3. VCE6467T Default Module States
DEFAULT MODULE STATE
[PSC Register MDSTATn.STATE]
LPSC #
MODULE NAME
0
ARM
Enable
DSP C64x+
If DSPBOOT = 0 then, Enable and Module Local Reset is asserted
(MDSTATn.LRST = 0).
1
If DSPBOOT = 1 then, Enable and Module Local Reset is asserted
(MDSTATn.LRST = 1).
2
3
HDVICP0
HDVICP1
EDMACC
EDMATC0
EDMATC1
EDMATC2
EDMATC3
USB2.0
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
4
5
6
7
8
9
10
11
12
13
14
15
16 – 17
18
19
20
ATA
VLYNQ
HPI
PCI
EMAC/MDIO
VDCE
Video Port(1)
TSIF0
TSIF1
DDR2 Memory Contoller
If BTMODE[3:0] ≠ 0100 and DSPBOOT = 0 then, SwRstDisable
If BTMODE[3:0] = 0100 or DSPBOOT = 1 then, Enable
21
EMIFA
22
23
McASP0
McASP1
CRGEN0
CRGEN1
UART0
UART1
UART2
PWM0
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
Reserved
24
25
26
27
28
29
30
PWM1
31
I2C
32
SPI
33
GPIO
34
TIMER0
TIMER1
Reserved
ARM INTC
35
36 – 44
45
Enable
(1) The Video Port Module has a total of five clock inputs that can be controlled by the LPSC. One LPSC can support only a maximum of
four clocks; therefore, two LPSCs are assigned to the Video Port. Both Video Port LPSCs should be controlled together and should be
set to the same state.
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3.3.2 Clock Control
This section describes the following registers: the VPIF (Video)/TSIF clock control and clock disable
registers and the Clock and Oscillator control register.
3.3.2.1 Video Clock Control Register
The Video Clock Control (VIDCLKCTL) register allows the user to select/control the clock muxing for the
video channels' (i.e., channels 1, 2, and 3) output clock source.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
12
11
10
8
7
5
4
3
0
RSV
VCH3CLK
RSV
VCH2CLK
RESERVED
VCH1CLK
RESERVED
R-0
R/W-111
R-0
R/W-110
R-000
R/W-1
R-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-2. VIDCLKCTL Register [0x01C4 0038]
Table 3-4. VIDCLKCTL Register Bit Descriptions
BIT
NAME
DESCRIPTION
Reserved. Read returns "0".
31:15
RESERVED
Video Channel 3 Clock Source.
This field selects the clock source for the Channel 3 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
010 = SYSCLK8 (PLLC1)
14:12
11
VCH3CLK
RSV
011 = AUXCLK (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = STC_CLKIN (external pin)
110 = VP_CLKIN2 (external pin)
111 = VP_CLKIN3 (external pin)
Reserved. Read returns "0".
Video Channel 2 Clock Source.
This field selects the clock source for the Channel 2 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
010 = SYSCLK8 (PLLC1)
10:8
VCH2CLK
011 = AUXCLK (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = STC_CLKIN (external pin)
110 = VP_CLKIN2 (external pin)
111 = Reserved
7:5
4
RESERVED
VCH1CLK
Reserved. Read returns "0".
Video Channel 1 Clock Source.
This bit selects the clock source for the Channel 1 input clock.
0 = VP_CLKIN0 (external pin)
1 = VP_CLKIN1 (external pin)
3:0
RESERVED
Reserved. Read returns "0".
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3.3.2.2 TSIF Control
The TSIF Control (TSIFCTL) registers allows the user to select/control the clock muxing for the counter
and serial output of TSIF1 andthe counter and parallel/serial output for TSIF0.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
TSIF1_CNTCLK
R/W-000
12
11
8
7
6
4
3
2
0
RSV
R-0
TSSO_CLK
R/W-0000
RSV
R-0
TSIF0_CNTCLK
R/W-000
RSV
R-0
TSPO_CLK
R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-3. TSIFCTL Register [0x01C4 0050]
Table 3-5. TSIFCTL Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:15
RESERVED
Reserved. Read returns "0".
TSIF1 Counter Clock Source.
This field selects the clock source for the TSIF1 module's counter.
000 = CRG1_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
011 = CRG0_VCXI (external pin)
100 = VP_CLKIN2 (external pin)
101 = VP_CLKIN3 (external pin)
110 = Reserved
14:12
TSIF1_CNTCLK
111 = Reserved
TSIF1 Serial Output Clock Source.
This field selects the clock source for the TSIF1 output source clock.
0000 = CRG1_VCXI (external pin)
0001 = STC_CLKIN (external pin)
0010 = SYSCLK6 (PLLC1)
0011 = SYSCLKBP (PLLC1)
0100 = VP_CLKIN0 (external pin)
0101 = TS1_CLKIN (external pin)
0110 = VP_CLKIN2 (external pin)
0111 = Reserved
11:8
TSSO_CLK
1000 = CRG0_VCXI
1001 = Reserved
1xx1 = Reserved
7
RSV
TSIF0_CNTCLK
RSV
Reserved. Read returns "0".
TSIF0 Counter Clock Source.
This field selects the clock source for the TSIF0 module's counter.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
011 = CRG1_VCXI (external pin)
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = Reserved
6:4
111 = Reserved
3
Reserved. Read returns "0".
TSIF0 Parallel/Serial Output Clock Source.
This field selects the clock source for the TSIF0 output source clock.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = SYSCLK5 (PLLC1)
011 = SYSCLKBP (PLLC1)
2:0
TSPO_CLK
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = TS0_CLKIN (external pin)
111 = CRG1_VCXI (external pin)
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3.3.2.3 Video and TSIF Clock Disable
The Video Source Clock Disable (VSCLKDIS) register allows the user to disable the selected Video
(VPIF), TSIF, and CRGEN module input clocks.
Note: To ensure glitch-free operation, the clock should be disabled before changing the clock source
frequency or muxing via the VIDCLKCTL and TSIFCTL.
31
15
16
RESERVED
R-0000 0000 0000 0000
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
VID3
VID2
VID1
VID0
TSIFCNT1 TSIFCNT0 TSIFTX1 TSIFTX0 TSIFRX1 TSIFRX0
CRG1
CRG0
R-0000
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-4. VSCLKDIS Register [0x01C4 006C]
Table 3-6. VSCLKDIS Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:12
RESERVED
Reserved. Read returns "0".
VPIF Channel 3 Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
11
10
9
VID3
VID2
VPIF Channel 2 Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
VPIF Channel 1 Clock Disable.
0 = Clock enabled.
VID1
1 = Clock disabled.
VPIF Channel 0 Clock Disable.
0 = Clock enabled.
8
VID0
1 = Clock disabled.
TSIF1 Counter Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
7
TSIFCNT1
TSIFCNT0
TSIFTX1
TSIFTX0
TSIFRX1
TSIFRX0
CRG1
TSIF0 Counter Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
6
TSIF1 Transmit Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
5
TSIF0 Transmit Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
4
TSIF1 Receive Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
3
TSIF0 Receive Clock Disable.
0 = Clock enabled.
1 = Clock disabled.
2
CRGEN1 Clock Disable.
0 = Clock enabled.
1
1 = Clock disabled.
CRGEN0 Clock Disable.
0 = Clock enabled.
0
CRG0
1 = Clock disabled.
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3.3.3 Clock and Oscillator Control
The Clock and Oscillator Control (CLKCTL) register allows the user to disable the OSC pwrdwn and pwr
disable
31
15
26
25
24
23
20
19
16
RESERVED
OSCPWRDN OSCDIS
RESERVED
CLKOUT
R-0000 00
R/W-0
R/W-1
8
R-0000
R/W-1000
12
11
7
4
3
0
RESERVED
AUD_CLK1
RESERVED
AUD_CLK0
R-0000
R/W-0000
R-0000
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-5. CLKCTL Register [0x01C4 005C]
Table 3-7. CLKCTL Register Bit Descriptions
BIT
31:26
25
NAME
DESCRIPTION
RESERVED
OSCPWRDN
Reserved. Read returns "0".
Auxiliary Oscillator Powerdown.
This bit controls the internal bias resistor conection.
0 = Internal bias resistor connected (normal operation)
1 = Internal bias resistor disconnected (external bias resistor required or clock input used)
24
OSCDIS
Auxiliary Oscillator Disable.
This bit disables the oscillator.
0 = Oscillator enabled (normal operation).
1 = Oscillator disabled (clock input used or no Auxiliary clock required).
23:20
19:16
RESERVED
CLKOUT
Reserved. Read returns "0".
CLKOUT0 Source(1)
This field selects the clock source for the CLKOUT0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = Reserved
0011 = SYSCLK3
0100 = SYSCLK4
0101 = SYSCLK5
0110 = SYSCLK6
0111 = Reserved
1000 = SYSCLK8
1001 = SYSCLK9
1010 = AUX_MXI
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
15:12
RESERVED
Reserved. Read returns "0".
(1) The maximum frequency allowed for the CLKOUT0 pin is 148.5 MHz. Do not configure the CLKOUT bits to any SYSCLKx that is greater
than 148.5 MHz. For more details on the CLKOUT0 timings, see Table 6-14, Switching Characteristics Over Recommended Operating
Conditions for CLKOUT0.
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Table 3-7. CLKCTL Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
11:8
AUD_CLK1
AUDIO_CLK1 Source.
This field selects the clock source for the AUDIO_CLK1 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
7:4
3:0
RESERVED
AUD_CLK0
Reserved. Read returns "0".
AUDIO_CLK0 Source.
This field selects the clock source for the AUDIO_CLK0 output.
0000 = Disabled
0001 = PLL1 AUXCLK
0010 = CRG0_VCXI
0011 = CRG1_VCXI
0100 = VP_CLKIN0
0101 = VP_CLKIN1
0110 = VP_CLKIN2
0111 = VP_CLKIN3
1000 = AUX_MXI
1001 = STC_CLKIN
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
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3.4 Boot Sequence
The boot sequence is a process by which the device's memory is loaded with program and data sections,
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see Section 6.7, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more
information on the bootmode selections, see Section 3.4.1, Boot Modes.
The device is booted through multiple means—primary bootloaders within internal ROM or EMIFA, and
secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and
register configurations required for booting the device, are described in the following subsections.
3.4.1 Boot Modes
The VCE6467T boot modes are determined by these device boot and configuration pins. For information
on how these pins are sampled at device reset, see Section 6.7.1.2, Latching Boot and Configuration
Pins.
•
•
•
•
BTMODE[3:0]
PCIEN
CS2BW
DSPBOOT
The TMS320DM646x DMSoC ARM can boot either from asynchronous EMIF/NOR Flash or from ARM
ROM, as determined by the device boot and configuration pins at reset (BTMODE[3:0] and PCIEN). The
PCIEN pin configuration is used to select the default configuration of the EMIFA/PCI/HPI pins at reset.
This allows the DM646xT DMSoC to be PCI-compliant at reset. When PCIEN = 1, the PCI module
controls the multiplexed pins with the appropriate pullup/pulldown configuration. For all other bootmodes
(non-PCI bootmodes), the PCIEN must be cleared to "0".
For a more detailed description of the ROM boot modes supported by the DM646xT DMSoC, see Using
the TMS320DM646x Bootloader Application Report (literature number SPRAAS0).
3.4.2 Boot Mode Registers
The DSPBOOTADDR, BOOTCMPLT, BOOTCMD, and BOOTCFG registers are used to control boot and
device configurations.
3.4.2.1 DSPBOOTADDR Register
The DSPBOOTADDR register contains the upper 22 bits of the DSP reset vector.
31
10
9
0
BOOTADDR[21:0]
RESERVED
R/W-0100 0010 0010 0000 0000 00
R-00 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-6. DSPBOOTADDR Register
Table 3-8. DSPBOOTADDR Register Bit Descriptions
BIT
31:10
9:0
NAME
DESCRIPTION
BOOTADDR[21:0]
RESERVED
Upper 22 bits of the C64x+ DSP boot address.
Reserved
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3.4.2.2 BOOTSTAT Register
The Boot Status (BOOTSTAT) register indicates the status of the device boot process (e.g., boot error,
boot complete, or watchdog timer reset).
31
30
20
19
16
WDRST
R/W-0
RESERVED
BOOTERR
R-0000
R-000 0000 0000
15
1
0
RESERVED
R-0000 0000 0000 000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
BC
R/W-0
Figure 3-7. BOOTSTAT Register
Table 3-9. BOOTSTAT Register Bit Descriptions
BIT
NAME
DESCRIPTION
Watchdog Timer Reset.
0 = Device reset was not a result of a watchdog timer timeout.
1 = Device reset was a result of a watchdog timer timeout.
31
WDRST
This is a "sticky" bit that can be used to debug WD timeout conditions. The bit is set when a WD
timeout occurs (TOUT2). This bit is reset (to "0") by a POR reset only; otherwise it retains its value.
It is not cleared by a Warm Reset or Soft Reset.
The bit may be cleared by writing a "1".
30:20
19:16
15:1
RESERVED
BOOTERR
RESERVED
Reserved. Read returns "0".
Boot Error.
0000 = No boot error [default].
Others = Bootloader detected boot error.
The exact meaning of the various error codes will be determined by the bootloader software.
Reserved. Read returns "0".
Boot Complete.
0 = Host has not completed the boot sequence [default].
1 = Host has completed the boot sequence.
This bit may be optionally set by a host boot device (such as PCI or HPI) to indicate that it has
finished loading code. The ARM926 can poll this bit to determine whether to continue the boot
process.
0
BC
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3.4.2.3 BOOTCFG Register
The Boot Configuration (BOOTCFG) register is a read-only register that indicates the value of the device
bootmode and configuration pins latched at the end of reset. During a hard reset (POR or RESET pin
active [low]), the values of the CFG pins (i.e., BTMODE[3:0], CS2BW, PCIEN, DSPBOOT) are propagated
through the BOOTCFG register to the Boot Controller. When RESET or POR is de-asserted, the value of
the pins is latched. The BOOTCFG value does not change as a result of a soft reset, instead the value
latched at the end of the previous global reset is retained.
31
15
18
17
DSP_BT
16
PCIEN
RESERVED
R-0000 0000 0000 00
R-L
R-L
0
9
8
7
4
3
RESERVED
CS2_BW
RESERVED
BOOTMODE
R-0000000
R-L
R-0000
R-LLLL
LEGEND: R = Read only; L = Latched pin value; -n = value after reset
Figure 3-8. BOOTCFG Register
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Table 3-10. BOOTCFG Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:18
RESERVED
Reserved. Read returns "0".
DSP Boot. Latched from DSPBOOT input at the rising edge of RESET or POR.
0 = ARM boots C64x+.
1 = C64x+ self-boots.
17
DSP_BT
This bit will cause the DSP to be released from reset automatically. The C64x+ will boot from
EMIFA (default DSPBOOTADDR address 0x4220 0000). If BOOTMODE = 0010 or 0011,
or PCIEN = 1, then the C64x+ self-boot will fail since EMIFA will be disabled.
PCI Enable. Latched from PCIEN input at the rising edge of RESET or POR.
0 = PCI disabled.
16
PCIEN
1 = PCI enabled.
PCIEN = 1 disables the internal pullup and pulldown resistors on the PCI pins and configures the
pin muxing for PCI.
15:9
RESERVED
Reserved. Read returns "0".
EMIFA EM_CS2 Default Bus Width. Latched from CS2BW input at the rising edge of RESET or
POR.
0 = Default to 8-bit operation.
1 = Default to 16-bit operation.
8
CS2_BW
This bit determines the default bus width of the EMIFA EM_CS2 memory space. This ensures that
boot from EMIFA (ARM or DSP) will correctly read the attached memory.
7:4
RESERVED
Reserved. Read returns "0".
Boot Mode Configuration Bits. Bit values latched from BTMODE[3:0] at the rising edge of RESET or
POR.
0000 = Emulation boot.
0001 = Reserved.
0010 = HPI-16 (if PCIEN = 0).
PCI without autoinitialization (if PCIEN = 1).
0011 = HPI-32 (if PCIEN = 0).
PCI with autoinitialization (if PCIEN = 1).
0100 = EMIFA direct boot (ROM/NOR) (if PCIEN = 0; error if PCIEN = 1 defaults to UART0).
0101 = Reserved.
3:0
BOOTMODE
0110 = I2C boot.
0111 = NAND Flash boot (if PCIEN = 0; error if PCIEN = 1 defaults to UART0).
1000 = UART0 boot.
1001 = Reserved.
1010 = Reserved.
1011 = Reserved.
1100 = Reserved.
1101 = Reserved.
1110 = SPI boot.
1111 = Reserved.
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3.4.2.4 ARMBOOT Register
The ARM Boot Configuration (ARMBOOT) register is used to control the ARM926 boot. The ARMBOOT
value does not change as a result of a soft reset, instead the last value written is retained.
When ROM boot is selected (BTMODE[3:0] ≠ 0100), a jump to the internal TCM ROM (0x0000 8000) is
forced into the first fetched instruction word. The embedded ROM boot loader (RBL) code can then
perform certain configuration steps, read the BOOTCFG register to determine the desired boot method,
and branch to an appropriate secondary loader utility.
If EMIFA boot is selected (BTMODE[3:0] = 0100), a jump to the highest branch address (0x0200 0000) is
forced into the first fetched instruction word. This must be modified to address 0x4200 0000 in order to
map to the EMIFA. The ARM will then continue executing from external memory using the default EMIFA
timings until modified by software. Note: that either NOR Flash or ROM must be connected to the first
EMIFA chip select space (EM_CS2). The EMIFA does not support direct execution from NAND Flash.
31
5
4
3
1
0
RESERVED
ADDRMOD
R/W-C
RESERVED
R-000
TRAMBOOT
R/W-0
R-0000 0000 0000 0000 0000 0000 000
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Figure 3-9. ARMBOOT Register
Table 3-11. ARMBOOT Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:5
RESERVED
Reserved. Read returns "0".
IAHB Address Modification.
0 = No address modification.
1 = Address bit 30 is tied high to modify IAHB fetch address to point to EMIFA.
The default value for this bit is determined by the BOOTMODE configuration bits (BTMODE[3:0]). If
BTMODE[3:0] = 0100 [EMIFA direct boot (ROM/NOR)] , then ADDRMOD defaults to "1" so that
instruction fetches from the ARM will point to EMIFA CS2 memory space. For all other
BTMODE[3:0] values, ADDRMOD defaults to "0" because ARM will boot from its TCM (ROM or
RAM).
4
ADDRMOD
The ADDRMOD value is ignored when TRAMBOOT is set (1) [address modification is disabled].
After branching into the EMIFA CS2 space, software should clear this bit as part of the reset routine
so that subsequent IAHB access addresses are not modified.
3:1
0
RESERVED
TRAMBOOT
Reserved. Read returns "0".
ARM TCM RAM Boot.
0 = Use BTMODE[3:0] selected boot mode
1 = Boot from ITCM RAM
This is a "sticky" bit that can be used to force the ARM926 to boot from ITCM RAM. On POR reset,
this bit will be initialized to "0" because TCM RAM is not initialized; otherwise, the bit retains the
value. After initializing ITCM RAM, software can set this bit so that subsequent Warm Reset
(RESET) or Soft Reset will boot from the ITCM.
3.4.2.5 ARMWAIT Register
The ARM Wait State Control (ARMWAIT) register is used to control ARM926 accesses to its TCM RAM.
At normal ARM operating frequency, a wait state must be inserted when accessing TCM RAM. When the
device is operated at low speeds, performance may be increased by removing the wait state. Note: TCM
ROM will always operate with a wait state enabled.
31
1
0
RESERVED
RAMWAIT
R/W-1
R-0000 0000 0000 0000 0000 0000 0000 000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-10. ARMWAIT Register
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Table 3-12. ARMWAIT Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:1
RESERVED
Reserved. Read returns "0".
ARM TCM RAM Wait State Configuration.
0 = TCM RAM wait state disabled.
1 = TCM RAM wait state enabled.
0
RAMWAIT
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3.5 Configurations At Reset
Some device configurations are determined at reset. The following subsections give more details.
3.5.1 Device and Peripheral Configurations at Device Reset
Table 2-6, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device
reset for configuring basic device settings for proper device operation. Table 3-13, summarizes the device
boot and configuration pins, and the device functions that they affect.
Table 3-13. Default Functions Affected by Device Boot and Configuration Pins
DEVICE BOOT AND
CONFIGURATION PINS
BOOT SELECTED
Boot Mode
PIN MUX CONTROL
GLOBAL SETTING
PERIPHERAL SETTING
BOOTMODE[3:0]
PINMUX0/PINMUX1
Registers:
I/O Pin Power:
Based on
PSC/Peripherals:
Based on
Based on
BOOTMODE[3:0], the
BOOTMODE[3:0], the
BOOTMODE[3:0], the
bootloader code programs bootloader code programs
bootloader code programs VDD3P3V_PWDN register the PSC to put
PINMUX0 and PINMUX1 to power up the I/O pins boot-related peripheral(s)
registers to select the
appropriate pin functions
required for boot.
required for boot.
in the Enable State, and
programs the peripheral(s)
for boot operation.
CS2BW
EMIFA Direct Boot Mode PINMUX0.HPIEN = 0
PINMUX0.PCIEN = 0
–
The default width of the
first EMIFA chip select
space (CS2) is
PINMUIX0.ATAEN = 0
determined by the
CS2BW value. If CS2BW
= 0, the space defaults to
8-bits wide. If CS2BW = 1,
it defaults to 16-bits wide.
This allows the ARM to
make full use of the width
of the attached memory
device when booting from
EMIFA.
PCIEN(1)
Host Boot:
PINMUX0.PCIEN:
–
PSC/Peripheral
PCIEN selects the type of sets this field to control
(Applicable to Host Boot
only):
Based on the Host Boot
type (PCI or HPI), the
bootloader code programs
the PSC to put the
Host Boot
the PCI pin muxing in .
(1) (2)
(HPI Boot or PCI Boot)
corresponding peripheral
in the Enable State, and
programs the peripheral
for boot operation.
(1) Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults.
(2) In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal
pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are
disabled to be compliant to the PCI Local Bus Specification Revision 2.3.
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Table 3-13. Default Functions Affected by Device Boot and Configuration Pins (continued)
DEVICE BOOT AND
CONFIGURATION PINS
BOOT SELECTED
PIN MUX CONTROL
GLOBAL SETTING
PERIPHERAL SETTING
DSPBOOT
Bit = 0, DSP is booted by
the ARM
Bit =1, DSP boots self
from EMIFA
–
–
Note: that either NOR
Flash or ROM must be
connected to the first
EMIFA chip select space
(CS2).
The EMIFA does not
support direct execution
from NAND Flash. Code
within the EMIFA memory
should execute a branch
to the actual EMIFA
address and then disable
the Instruction Address
Modification logic (by
clearing the ADDRMOD
bit in the ARMBOOT
register of the System
Module).
For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. For discussion situations where external pullup/pulldown resistors are required, see
Section 3.8.1, Pullup/Pulldown Resistors.
Note: All VCE6467T device configuration inputs (BOOTMODE[3:0], CS2BW, PCIEN, and DSPBOOT) are
multiplexed with other functional pins. These pins function as device boot and configuration pins only
during device reset. The user must take care of any potential data contention in the system. To help avoid
system data contention, the VCE6467T puts these configuration pins into a high-impedance state (Hi-Z)
when device reset (RESET or POR) is asserted, and continues to hold them in a high-impedance state
until the internal global reset is removed; at which point, the default peripheral (VPIF) will now control
these pins.
All of the device boot and configuration pin settings are captured in the corresponding bit fields in the
BOOTCFG register (see Section 3.4.2.3).
The following subsections provide more details on the device configurations determined at device reset:
CS2BW, PCIEN, and DSPBOOT.
3.5.2 EMIFA CS2 Bus Width (CS2BW)
The default width of the first EMIFA chip select space (CS2) is determined by the CS2BW value. If
CS2BW = 0, the space defaults to 8-bits wide. If CS2BW = 1, it defaults to 16-bits wide. This allows the
ARM to make full use of the width of the attached memory device when booting from EMIFA.
Note: CS2BW only selects the default bus width. The EMIFA bus width may be changed at any time via
software by accessing the appropriate EMIFA control register.
The default width affects only the first chip select space (CS2). All other chip select spaces default to
8-bits wide and must be modified using the appropriate EMIFA control register if 16-bit operation is
desired.
3.5.3 PCI Enable (PCIEN)
The PCIEN configuration pin determines if the PCI peripheral is used on this device. If PCIEN = 1
indicating the PCI is used, then the PCI multiplexed pins default to PCI functions, and the pins’
corresponding internal pullup/pulldown resistors are disabled. If PCIEN = 0 indicating the PCI is not used,
then the PCI muxed pins default to non-PCI functions (e.g., EMIFA or HPI pin functions), and the pins’
corresponding internal pullup/pulldown resistors are enabled.
The PCIEN setting is captured and stored in the BOOTCFG.PCIEN bit field, and also in the
PINMUX0.PCIEN bit field.
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3.5.4 DSPBOOT
The DSPBOOT input determines DSP operation at reset. For most applications, the ARM is the master
device and controls the reset and boot of the DSP. Under this scenario (DSPBOOT = 0), the DSP will
remain disabled (held in reset) after reset. The ARM is responsible for releasing DSP from reset. Before
releasing DSP from reset, the ARM must transfer a valid DSP boot image to program memory accessible
by the DSP (DSP memory, EMIFA or DDR2), and configure the DSP boot address in DSPBOOTADDR
register (in SYSTEM module) from which the DSP will begin execution.
When DSPBOOT = 1, the DSP will boot itself. Under this scenario, DSP will be released from reset
without ARM intervention. The DSP boot address is set to an EMIFA address 0x4220 0000h. DSP will
begin execution with instruction (L1P) cache enabled.
Note: The DSPBOOT operation is overridden when ARM HPI or PCI boot is selected (BTMODE[3:0] =
001x). This is because ARM HPI/PCI boot selection will force the HPIEN or PCIEN bit in PINMUX0 to ‘1’.
This enables UHPI/PCI functions on the EMIFA control and data pins and prevents the DSP from using
EMIFA. DSPBOOT is treated as "0" internally when BTMODE[3:0] = 001x, regardless of the value at the
configuration pin (The actual pin value should still be latched in the BOOTCFG register of the System
Module).
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3.6 Configurations After Reset
The following sections provide details on configuring the device after reset.
Multiplexed pin are configured both at and after reset. Section 3.5.1, Device and Peripheral Configurations
at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed pins control
after reset, see Section 3.7, Multiplexed Pin Configurations.
3.6.1 Switch Central Resource (SCR) Bus Priorities
Prioritization within the Switched Central Resource (SCR) is programmable for each master. The register
bit fields and default priority levels for VCE6467T bus masters are shown in Table 3-14, VCE6467T
Default Bus Master Priorities. The priority levels should be tuned to obtain the best system performance
for a particular application. Lower values indicate higher priority. For most masters, their priority values are
programmed at the system level by configuring the MSTPRI0, MSTPRI1, and MSTPRI2 registers. Details
on the MSTPRI0/1/2 registers are shown in Figure 3-11, Figure 3-12, and Figure 3-13.
Table 3-14. VCE6467T Default Bus Master Priorities
Priority Bit Field
VP0P
Bus Master
VPIF Capture
VPIF Display
TSIF0
Default Priority Level
1 (MSTPRI2 Register)
1 (MSTPRI2 Register)
1 (MSTPRI2 Register)
1 (MSTPRI2 Register)
2 (MSTPRI2 Register)
2 (MSTPRI2 Register)
2 (MSTPRI2 Register)
2 (MSTPRI2 Register)
3 (MSTPRI0 Register)
3 (MSTPRI0 Register)
4 (MSTPRI0 Register)
4 (MSTPRI0 Register)
4 (MSTPRI0 Register)
4 (MSTPRI0 Register)
4 (MSTPRI1 Register)
5 (MSTPRI1 Register)
5 (MSTPRI1 Register)
5 (MSTPRI1 Register)
5 (MSTPRI1 Register)
6 (MSTPRI1 Register)
6 (MSTPRI1 Register)
VP1P
TSIF0P
TSIF1P
TSIF1
EDMATC0P
EDMATC1P
EDMATC2P
EDMATC3P
HDVICP0P
HDVICP1P
ARMINSTP
ARMDATAP
DSPDMAP
DSPCFGP
VDCEP
EDMATC0
EDMATC1
EDMATC2
EDMATC3
HDVICP0 (CFG)(1)
HDVICP1 (CFG)(1)
ARM926 (INST)
ARM926 (DATA)
C64x+ DSP (DMA)
C64x+ DSP (CFG)(1)
VDCE
EMACP
EMAC
USBP
USB2.0
ATAP
ATA
VLYNQP
PCIP
VLYNQ
PCI
HPIP
HPI
(1) The C64x+ DSP (CFG), HDVICP0 (CFG), and HDVICP1 (CFG) priority values are not actually used by the DMSoC infrastructure –
which gives equal weight round-robin priority to accesses from these three masters. Therefore, the priority settings for these three
masters in the MSTPRI0 register have no effect.
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31
23
22
6
20
4
19
RSV
18
2
16
0
HDVICP1P(1)
HDVICP0P(1)
RESERVED
R-0000 0000 0
R/W-011
R-0
R/W-011
15
RSV
14
12
11
RSV
8
7
RSV
3
RSV
DSPDMAP
DSPCFGP(1)
ARMDATAP
ARMINSTP
R-0
R/W-100
R-0
R/W-100
R-0
R/W-100
R-0
R/W-100
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-11. MSTPRI0 Register [0x01C4 003C]
(1) The DSPCFGP, HDVICP0P, and HDVICP1P priority values are not actually used by the infrastructure, which gives equal weight
round-robin priority to accesses from this master; therefore, the settings have no effect.
Table 3-15. MSTPRI0 Register Bit Descriptions
BIT
31:23
22:20
19
NAME
DESCRIPTION
RESERVED
Reserved. Read returns "0".
HDVICP1P(1) HDVICP1 master port priority in System Infrastructure. Read returns "011". Writes have no effect.
RSV Reserved. Read returns "0".
HDVICP0P(1) HDVICP0 master port priority in System Infrastructure. Read returns "011". Writes have no effect.
18:16
15
RSV
Reserved. Read returns "0".
14:12
DSPDMAP
DSPDMA master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1
100 = Priority 4 [Default]
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
11
10:8
7
RSV
DSPCFGP(1)
RSV
Reserved. Read returns "0".
DSPCFG master port priority in System Infrastructure. Read returns "100". Writes have no effect.
Reserved. Read returns "0".
6:4
ARMDATAP
ARM DATA master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1
100 = Priority 4 [Default]
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
3
RSV
Reserved. Read returns "0".
2:0
ARMINSTP
ARM INST master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1
100 = Priority 4 [Default]
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
(1) The priorities for these masters are fixed at their default values. Writing alternate values to these fields has no effect..
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31
30
14
28
12
27
26
10
24
8
23
22
20
19
18
2
16
RSV
R-0
VDCEP
RSV
R-0
PCIP
RSV
R-0
HPIP
RSV
R-0
VLYNQP
R/W-100
R/W-110
R/W-110
R/W-101
15
11
7
3
0
RSV
R-0
ATAP
RSV
R-0
USBP
RESERVED
R-0000 0
EMACP
R/W-101
R/W-101
R/W-101
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-12. MSTPRI1 Register [0x01C4 0040]
Table 3-16. MSTPRI1 Register Bit Descriptions
BIT
31
NAME
RSV
DESCRIPTION
Reserved. Read returns "0".
30:28
VDCEP
VDCE master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1
100 = Priority 4 [Default]
101 = Priority 5
010 = Priority 2
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
27
RSV
Reserved. Read returns "0".
PCI master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1
26:24
PCIP
100 = Priority 4
101 = Priority 5
010 = Priority 2
110 = Priority 6 [Default]
111 = Priority 7 (Lowest)
011 = Priority 3
23
22:20
19
RSV
HPIP
Reserved. Read returns "0".
HPI master port priority in System Infrastructure. Same priority 0–7 selection as above.
"110" = Priority 6 [default].
RSV
Reserved. Read returns "0".
VLYNQ master port priority in System Infrastructure. Same priority 0–7 selection as above.
"110" = Priority 6 [default].
18:16
15
VLYNQP
RSV
Reserved. Read returns "0".
ATA master port priority in System Infrastructure. Same priority 0–7 selection as above.
"101" = Priority 5 [default].
14:12
11
ATAP
RSV
Reserved. Read returns "0".
USB master port priority in System Infrastructure. Same priority 0–7 selection as above.
"101" = Priority 5 [default].
10:8
7:3
USBP
RESERVED
EMACP
Reserved. Read returns "0".
EMAC master port priority in System Infrastructure. Same priority 0–7 selection as above.
"101" = Priority 5 [default].
2:0
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31
30
14
28
12
27
26
10
24
8
23
22
6
20
4
19
18
2
16
0
RSV
R-0
TSIF1P
RSV
R-0
TSIF0P
RSV
R-0
VP1P
RSV
R-0
VP0P
R/W-001
R/W-001
R/W-001
R/W-001
15
11
7
3
RSV
R-0
EDMATC3P
R/W-010
RSV
R-0
EDMATC2P
R/W-010
RSV
R-0
EDMATC1P
R/W-010
RSV
R-0
EDMATC0P
R/W-010
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-13. MSTPRI2 Register
Table 3-17. MSTPRI2 Register Bit Descriptions
BIT
31
NAME
RSV
DESCRIPTION
Reserved. Read returns "0".
30:28
TSIF1P
TSIF1 master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1 [Default]
010 = Priority 2
100 = Priority 4
101 = Priority 5
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
27
RSV
Reserved. Read returns "0".
TSIF0 master port priority in System Infrastructure.
000 = Priority 0 (Highest)
001 = Priority 1 [Default]
010 = Priority 2
26:24
TSIF0P
100 = Priority 4
101 = Priority 5
110 = Priority 6
011 = Priority 3
111 = Priority 7 (Lowest)
23
22:20
19
RSV
VP1P
Reserved. Read returns "0".
VPIF display master port priority in System Infrastructure. Same priority 0–7 selection as above.
"001" = Priority 1 [default].
RSV
Reserved. Read returns "0".
VPIF capture master port priority in System Infrastructure. Same priority 0–7 selection as above.
"001" = Priority 1 [default].
18:16
15
VP0P
RSV
Reserved. Read returns "0".
EDMATC3 master port priority in System Infrastructure. Same priority 0–7 selection as above.
"010" = Priority 2 [default].
14:12
11
EDMATC3P
RSV
Reserved. Read returns "0".
EDMATC2 master port priority in System Infrastructure. Same priority 0–7 selection as above.
"010" = Priority 2 [default].
10:8
7
EDMATC2P
RSV
Reserved. Read returns "0".
EDMATC1 master port priority in System Infrastructure. Same priority 0–7 selection as above.
"010" = Priority 2 [default].
6:4
EDMATC1P
RSV
3
Reserved. Read returns "0".
EDMATC0 master port priority in System Infrastructure. Same priority 0–7 selection as above.
"010" = Priority 2 [default].
2:0
EDMATC0P
3.6.2 Peripheral Selection After Device Reset
After device reset, most peripheral configurations are done within the peripheral’s registers. This
section discusses some additional peripheral controls in the System Module. For information on
multiplexed pin controls that determine what peripheral pins are brought out to the pins, see
Section 3.7, Multiplexed Pin Configurations.
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3.6.2.1 HPICTL Register
The HPI control register (HPICTL) [0x01C4 0030] controls write access to HPI control and address
registers and determines the host time-out value. HPICTL is not reset by a soft reset so that the HPI width
will remain correctly configured. Figure 3-14 and Table 3-18 describe in detail the HPICTL register.
31
18
17
16
RESERVED
RESERVED
R-0000 0000 0000 00
R/W-00
15
14
10
9
8
7
0
WIDTH
RESERVED
CTLMODE
ADDMODE
TIMOUT
R/W-0
R-000 00
R/W-0
R/W-0
R/W-1000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-14. HPICTL Register [0x01C4 0030]
Table 3-18. HPICTL Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:18
17:16
RESERVED
RESERVED
Reserved. Read-only, writes have no effect.
Reserved. For proper device operation, the user should only write "0" to these bits (default).
HPI Data Width.
0 = Half-width (16-bit) data bus
15
WIDTH
1 = Full-width (32-bit) data bus
This bit value must be determined before releasing the UHPI from reset to ensure correct UHPI
operation.
14:10
9
RESERVED
CTLMODE
Reserved. Read-only, writes have no effect.
HPIC Register Write Access.
0 = Host
1 = DMSoC (if ADDMODE = 1)
HPIA Register Write Access.
0 = Host
1 = DMSoC
8
ADDMODE
TIMOUT
Host Burst Write Timeout Value.
When the HPI time-out counter reaches the value programmed here, the HPI write FIFO content is
flushed. For more details on the time-out counter and its use in write bursting, see the
TMS320DM646x DMSoC Host Port Interface (HPI) User's Guide (literature number SPRUES1).
7:0
3.6.2.2 USBCTL Register
The USB interface control register (USBCTL) [0x01C4 0034] is described in Figure 3-15 and Table 3-19.
31
19
18
17
16
RESERVED
DATAPOL VBUSVAL USBID
R-0000 0000 0000 0
R/W-1 R/W-0 R/W-0
15
9
8
7
5
4
3
1
0
PHY
CLKGD
PHY
PLLON
PHY
PDWN
RESERVED
RESERVED
RESERVED
R-0000 000
R-0
R-000
R/W-0
R-000
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-15. USBCTL Register [0x01C4 0034]
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Table 3-19. USBCTL Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:19
RESERVED
Reserved. Read returns "0".
USB Data Polarity.
18
17
DATAPOL
VBUSVAL
0 = Inverted data.
1 = Normal data polarity [default].
VBUS Sense Control.
0 = Disabled [default].
1 = Session starts.
USB Mode.
16
15:9
8
USBID
0 = Host [default].
1 = Peripheral.
RESERVED
PHYCLKGD
RESERVED
PHYPLLON
RESERVED
PHYPDWN
Reserved. Read returns "0".
USB PHY Power and Clock Good.
0 = PHY power is not ramped or PLL is not locked [default].
1 = PHY power is good and PLL is locked.
7:5
4
Reserved. Read returns "0".
USB PHY PLL Suspend Override.
0 = Normal PLL operation [default].
1 = Override PLL suspend state.
3:1
0
Reserved. Read returns "0".
USB PHY Power-Down Control.
0 = PHY powered on.
1 = PHY power off [default].
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3.6.2.3 PWMCTL (Trigger Source) Control Register
The PWM control register (PWMCTL) [0x01C4 0054] chip-level connections of both PWM0 and PWM1.
Figure 3-16 and Table 3-20 describe in detail the PWMCTL register.
31
15
16
RESERVED
R-0000 0000 0000 0000
8
7
4
3
0
RESERVED
PWM11TRG
PWM0TRG
R/W-1111
R-0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W-1111
Figure 3-16. PWMCTL Register [0x01C4 0054]
Table 3-20. PWMCTL Register Bit Descriptions
BIT
31:8
7:4
NAME
DESCRIPTION
RESERVED Reserved. Read-only, writes have no effect.
PWM1TRG PWM1 Trigger Source
0000 = GP[0]
0001 = GP[1]
0010 = GP[2]
0011 = GP[3]
0100 = GP[4]
0101 = GP[5]
0110 = GP[6]
0111 = GP[7]
1000 = VPIF Vertical Interrupt 0
1001 = VPIF Vertical Interrupt 1
1010 = VPIF Vertical Interrupt 2
1011 = VPIF Vertical Interrupt 3
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
PWM0 Trigger Source
same selection as above.
3:0
PWM0TRG
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3.6.2.4 EDMATCCFG Register
The EDMA Transfer Controller Default Burst Size Configuration Register (EDMATCCFG) [0x01C4 0058]
configures the default burst size (DBS) for EDMA TC0, EDMA TC1, EDMA TC2, and EDMA TC3.
Figure 3-17 and Table 3-21 describe in detail the EDMATCCFG register. For more information on the
correct usage of DBS, see the TMS320DM646x DMSoC Enhanced Direct Memory Access (EDMA)
Controller User's Guide (literature number SPRUEQ5).
31
15
16
RESERVED
R-0000 0000 0000 0000
8
7
6
5
4
3
2
1
0
RESERVED
R-0000 0000
TC3DBS
R/W-01
TC2DBS
R/W-01
TC1DBS
R/W-01
TC0DBS
R/W-01
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-17. EDMA Transfer Controller Default Burst Size Configuration Register (EDMATCCFG)
[0x01C4 0058]
Table 3-21. EDMATCCFG Register Bit Descriptions
BIT
NAME
DESCRIPTION
Reserved. Read-only, writes have no effect.
31:8
RESERVED
EDMA TC3 Default Burst Size.
00 = 16 byte
01 = 32 byte [default]
10 = 64 byte
11 = reserved
7:6
5:4
3:2
1:0
TC3DBS
TC2DBS
TC1DBS
TC0DBS
TC3 FIFO size is 256 bytes, regardless of Default Burst Size setting.
EDMA TC2 Default Burst Size.
00 = 16 byte
01 = 32 byte [default]
10 = 64 byte
11 = reserved
TC2 FIFO size is 256 bytes, regardless of Default Burst Size setting.
EDMA TC1 Default Burst Size.
00 = 16 byte
01 = 32 byte [default]
10 = 64 byte
11 = reserved
TC1 FIFO size is 256 bytes, regardless of Default Burst Size setting.
EDMA TC0 Default Burst Size.
00 = 16 byte
01 = 32 byte [default]
10 = 64 byte
11 = reserved
TC0 FIFO size is 256 bytes, regardless of Default Burst Size setting.
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3.7 Multiplexed Pin Configurations
VCE6467T makes extensive use of pin multiplexing to accommodate a large number of peripheral function
in the smallest possible package, providing the ultimate flexibility for end applications.
The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsiblie for controlling
all pin multiplexing functions on the VCE6467T. The default setting of some of the PINMUX0 and
PINMUX1 bit fields are configured by configuration pins latched at reset (see Section 3.5.1, Device and
Peripheral Configurations at Device Reset). After reset, software may program the PINMUX0 and
PINMUX1 registers to switch pin functionalities.
The following peripherals have multiplexed pins: VPIF, TSIF0, TSIF1, CRGEN0, CRGEN1, EMIFA, PCI,
HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin,
and GPIO.
3.7.1 Pin Muxing Selection At Reset
This section summarizes pin mux selection at reset.
The configuration pins CS2BW and PCIEN, latched at device reset, determine the default pin muxing. For
more details on the default pin muxing at reset, see Section 3.5, Configurations At Reset.
3.7.2 Pin Muxing Selection After Reset
The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions.
Some pin functions require a combination of PINMUX0/PINMUX1 bit fields. For more details on the
combination of the PINMUX bit fields that control each muxed pin, see Section 3.7.3, Pin Multiplexing
Details.
This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed
discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details.
3.7.2.1 PINMUX0 Register Description
The Pin Multiplexing 0 Register controls the pin function in the EMIFA/ATA/HPI/PCI, TSIF0, TSIF1,
CRGEN, Block. The PINMUX0 register format is shown in Figure 3-18 and the bit field descriptions are
given in Table 3-22. Some muxed pins are controlled by more than one PINMUX bit field. For the
combination of the PINMUX bit fields that control each muxed pin, see Section 3.7.3, Pin Multiplexing
Details. For more information on the block pin muxing and pin-by-pin muxing control, see specific block
muxing section (for example, for CRGEN Pin Mux Control, see Section 3.7.3.7, CRGEN Signal Muxing).
31
30
29
28
27
26
24
23
22
21
20
19
18
17
16
VBUSDIS STCCK
AUDCK1 AUDCK0
RSV
CRGMUX
TSSOMUX
TSSIMUX
TSPOMUX
TSPIMUX
R/W-0 R/W-0 R/W-0 R/W-0
15
R-0
R/W-000
R/W-00
R/W-00
R/W-00
R/W-00
6
5
4
3
2
1
0
RESERVED
RSV
RESERVED
PCIEN
HPIEN
ATAEN
R-0000 0000 00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W-0
R-0
R/W-L R/W-0 R/W-0
Figure 3-18. PINMUX0 Register [0x01C4 0000]
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Table 3-22. PINMUX0 Register Bit Descriptions
BIT
NAME
DESCRIPTION
This bit disables USB_DRVVBUS output.
0 = USB_DRVVBUS function selected.
1 = GP[22] function selected.
31
VBUSDIS
This bit enables STC Source Clock input.
0 = GP[4] function selected.
1 = STC_CLKIN function selected.
30
29
STCCK
This bit enables AUDIO_CLK1 output.
0 = GP[2] function selected.
AUDCK1
1 = AUDIO_CLK1 function selected.
This bit enables AUDIO_CLK0 output.
0 = GP[3] function selected.
1 = AUDIO_CLK0 function selected.
28
27
AUDCK0
RSV
Reserved. Read returns "0".
CRGEN Pin Mux Control (see Section 3.7.3.7, CRGEN Signal Muxing).
000 = No CRGEN signals enabled.
001 = CRGEN1 selection enabled (muxed with UART2 data).
010 = Reserved (no CRGEN signals enabled).
26:24
CRGMUX
011 = Reserved (no CRGEN signals enabled).
100 = CRGEN0 selection enabled (muxed with UCTS2 and PWM0).
101 = CRGEN0 and CRGEN1 selection enabled.
110 = CRGEN0 selection enabled (muxed with UART2 data).
111 = Reserved (no CRGEN signals enabled).
TSIF1 Serial Output Pin Mux Control (see (1), TSSO Signal Muxing).
0x = No TS1 output signals enabled.
10 = TS1 output selection enabled (muxed on VP_DOUT pins).
11 = TS1 output selection enabled (muxed on URIN0, UCTS2, PWM0, and PWM1 pins).
23:22
21:20
TSSOMUX
TSSIMUX
TSIF1 Serial Input Pin Mux Control (see Section 3.7.3.5, TSIF1 Input Signal Muxing).
00 = No TS1 input signals enabled.
01 = TS1 input selection enabled (muxed on UART0 pins).
10 = TS1 input selection enabled (muxed on VP_DOUT pins).
11 = TS1 input selection enabled (muxed on VP_DIN pins).
TSIF0 Parallel/Serial Output Pin Mux Control (see Section 3.7.3.4, TSIF0 Output Signal Muxing).
0x = No TS0 output signals enabled.
10 = TS0 parallel output muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial output muxing enabled (muxed TS0_DOUT7 with UTXD1).
19:18
17:16
TSPOMUX
TSPIMUX
TSIF0 Parallel/Serial Input Pin Mux Control (see Section 3.7.3.3, TSIF0 Input Signal Muxing).
0x = No TS0 signals enabled.
10 = TS0 parallel input muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial input muxing enabled (muxed TS0_DIN7 with URXD1).
15:6
5
RESERVED
RESERVED
RESERVED
PCIEN
Reserved. Read returns "0".
Reserved. Read returns "0". Note: For proper device operation, when writing to this bit, only a "0"
should be written.
4:3
2
Reserved. Read returns "0".
PCI Function Enable (see Section 3.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
Default value is determined by PCIEN boot configuration pin.
1
0
HPIEN
ATAEN
HPI Function Enable (see Section 3.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
ATA Function Enable (see Section 3.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1, Pullup/Pulldown Resistors.
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3.7.2.2 PINMUX1 Register Description
The Pin Multiplexing 1 Register controls the pin function in the UART0, UART1, and UART2 Blocks. The
PINMUX1 register format is shown in Figure 3-19 and the bit field descriptions are given in Table 3-23.
Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX
bit fields that control each muxed pin, see Section 3.7.3, Pin Multiplexing Details. For the pin-by-pin
muxing control of the UART0, UART1, and UART2 Blocks, see Section 3.7.3.8, UART0 Pin Muxing;
Section 3.7.3.9, UART1 Pin Muxing; and Section 3.7.3.10, UART2 Pin Muxing.
31
15
16
RESERVED
R-0000 0000 0000 0000
6
5
4
3
2
1
0
RESERVED
UART2CTL
R/W-00
UART1CTL
R/W-00
UART0CTL
R/W-00
R-0000 0000 00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-19. PINMUX1 Register
Table 3-23. PINMUX1 Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:6
RESERVED
Reserved. Read returns "0".
UART2 Pin Configuration (see Section 3.7.3.10, UART2 Pin Muxing).
00 = UART function with flow control.
01 = UART function without flow control.
10 = IrDA/CIR function.
5:4
UART2CTL
11 = GPIO function.
(Individual pin functions may be overridden by TSPIMUX, CRGEN0, and CRGEN1 values.)
UART1 Pin Configuration (see Section 3.7.3.9, UART1 Pin Muxing).
00 = UART function with flow control.
01 = UART function without flow control.
10 = IrDA/CIR function.
11 = GPIO function.
3:2
1:0
UART1CTL
UART0CTL
(Individual pin functions may be overridden by TSPIMUX and TSPOMUX values.)
UART0 Pin Configuration (see Section 3.7.3.8, UART0 Pin Muxing).
00 = UART function with modem control.
01 = UART function without modem control.
1x = IrDA/CIR function.
(Individual pin functions may be overridden by TSPOMUX value.)
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3.7.3 Pin Multiplexing Details
This section discusses how to program each Pin Mux Register to select the desired peripheral functions
and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin.
For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2, Pin Muxing Selection After Reset.
3.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
The PCI, HPI, EMIFA, and ATA signal muxing is determined by the value of the PCIEN, HPIEN, and
ATAEN bit fields in the PINMUX0 register. For more details on the actual pin functions, see Table 3-24
and Table 3-25.
Table 3-24. PCIEN, HPIEN, and ATAEN Encoding
PCIEN
HPIEN
ATAEN
PIN FUNCTIONS
EMIFA
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
EMIFA (NAND) and ATA
HPI (32-bit)
HPI (16-bit) and ATA
PCI(1)
(1) In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and
it is recommended to have external pullup resistors on the PCI_RSV[5:0] pins. See Table 3-25 for the
actual PCI pin functions and any associated footnotes.
Table 3-25. PCI, HPI, EMIFA, and ATA Pin Muxing
PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES)
1xx(1)
PCI_CLK
010
GP[10]
–
011
GP[10]
HDDIR
HCNTL1
HINT
000
001
GP[10]
GP[10]
PCI_IDSEL
PCI_DEVSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_STOP
PCI_SERR
PCI_PERR
PCI_PAR
EM_R/W
EM_BA[1]
EM_BA[0]
EM_A[17]
EM_A[16]
EM_WE
HDDIR
HCNTL1
HINT
EM_BA[1]
EM_BA[0]
EM_A[17]/(CLE)
EM_A[16]/(ALE)
EM_WE
HRDY
HHWIL
HCNTL0
HDS1
HCS
HRDY
HHWIL
HCNTL0
HDS1
HCS
EM_OE
EM_OE
EM_DQM1
EM_DQM0
EM_WAIT2
EM_CS5
EM_CS4
EM_CS3
EM_CS2
EM_A[19]
EM_A[18]
EM_A[15]
EM_A[14]
EM_A[13]
EM_A[12]
EM_A[11]
EM_DQM1
EM_DQM0
EM_WAIT2/(RDY2/BSY2)
DMARQ
HAS
HAS
PCI_INTA
PCI_REQ
PCI_GNT
–
–
GP[11]
GP[12]
HR/W
HDS2
GP[32]
GP[33]
HD31
HD30
HD29
HD28
HD27
DMARQ
DACK
HR/W
HDS2
ATA_CS1
ATA_CS0
DD15
DACK
PCI_CBE3
PCI_CBE2
PCI_CBE1
PCI_CBE0
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
EM_CS3
EM_CS2
ATA_CS1
ATA_CS0
DD15
DD14
DD14
DD13
DD13
DD12
DD12
DD11
DD11
(1) In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have
external pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see
Section 3.8.1, Pullup/Pulldown Resistors.
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Table 3-25. PCI, HPI, EMIFA, and ATA Pin Muxing (continued)
PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES)
1xx(1)
010
HD26
HD25
HD24
HD23
HD22
HD21
HD20
HD19
HD18
HD17
HD16
HD15
HD14
HD13
HD12
HD11
HD10
HD9
011
DD10
DD9
000
EM_A[10]
EM_A[9]
001
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
DD10
DD9
DD8
EM_A[8]
DD8
DD7
EM_A[7]
DD7
DD6
EM_A[6]
DD6
DD5
EM_A[5]
DD5
DD4
EM_A[4]
DD4
DD3
EM_A[3]
DD3
DD2
EM_A[2]
DD2
DD1
EM_A[1]
DD1
DD0
EM_A[0]
DD0
HD15
HD14
HD13
HD12
HD11
HD10
HD9
EM_D15
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
DA2
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
PCI_AD8
HD8
HD8
EM_D8
PCI_AD7
HD7
HD7
EM_D7
PCI_AD6
HD6
HD6
EM_D6
PCI_AD5
HD5
HD5
EM_D5
PCI_AD4
HD4
HD4
EM_D4
PCI_AD3
HD3
HD3
EM_D3
PCI_AD2
HD2
HD2
EM_D2
PCI_AD1
HD1
HD1
EM_D1
PCI_AD0
HD0
HD0
EM_D0
PCI_RST
GP[13]
GP[16]
GP[17]
GP[18]
GP[19]
GP[20]
GP[21]
DA2
EM_A[22]
EM_A[21]
EM_A[20]
EM_RSV0
EM_WAIT5/(RDY5/BSY5)
EM_WAIT4/(RDY4/BSY4)
EM_WAIT3/(RDY3/BSY3)
PCI_RSV0(2)
PCI_RSV1(2)
PCI_RSV2(2)
PCI_RSV3(2)
PCI_RSV4(2)
PCI_RSV5(2)
DA1
DA1
DA0
DA0
INTRQ
DIOR
DIOW
IORDY
INTRQ
DIOR
DIOW
IORDY
(2) In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have
external pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see
Section 3.8.1, Pullup/Pulldown Resistors.
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3.7.3.2 PWM Signal Muxing
The two PWM outputs will be configured as PWM pin functions by default. The PWM functions may be
overridden by the settings of various PINMUX0 bit fields as shown in Table 3-26 and Table 3-27.
Table 3-26. PWM0 Pin Muxing
PIN FUNCTION
CRGMUX ≠ 10x
TSSOMUX ≠ 11
CRGMUX = 10x
TSSOMUX ≠ 11
TSSOMUX = 11
PWM0
CRG0_PO
TS1_ENAO
Table 3-27. PWM1 Pin Muxing
PIN FUNCTION
TSSOMUX ≠ 11
PWM1
TSSOMUX = 11
TS1_DOUT
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3.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
The TSIF 0 (TS0) input signals have muxing options for both parallel or serial operation as configured by
the TPSIMUX bits as shown in Table 3-28.
Table 3-28. TSIF0 Input Pin Muxing
TSPIMUX = 0x
(NO TSIF0 SIGNALS ENABLED)
TSPIMUX = 10
(PARALLEL)
TSPIMUX = 11
(SERIAL)
TS0_CLKIN
VP_DIN15_VSYNC
VP_DIN14_HSYNC
VP_DIN13_FIELD
VP_DIN12
TS0_CLKIN
TS0_DIN7
TS0_DIN6
TS0_DIN5
TS0_DIN4
TS0_DIN3
TS0_DIN2
TS0_DIN1
TS0_DIN0
URXD1(1)
UTXD1(1)
TS0_CLKIN
VP_DIN15_VSYNC
VP_DIN14_HSYNC
VP_DIN13_FIELD
VP_DIN12
VP_DIN11
VP_DIN11
VP_DIN10
VP_DIN10
VP_DIN9
VP_DIN9
VP_DIN8
URXD1(1)
UTXD1(1)
VP_DIN8
TS0_DIN7
(see Table 3-22—TSPOMUX bit
field)
(also see Table 3-35)
(1)
URTS1
TS0_WAITO
TS0_EN_WAITO
TS0_PSTIN
TS0_WAITO
TS0_EN_WAITO
TS0_PSTIN
(1)
UCTS1
(2)
URTS2
(1) Function is determined by UART1CTL bit field value in the PINMUX0 register.
(2) Function is determined by UART2CTL bit field value in the PINMUX0 register.
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3.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
The TSIF 0 (TS0) output signals have muxing options for both parallel or serial operation as configured by
the TPSOMUX bits as shown in Table 3-29.
Table 3-29. TSIF0 Output Pin Muxing
TSPOMUX = 0x
TSPOMUX = 10
(PARALLEL)
TSPOMUX = 11
(SERIAL)
UART0CTL = 00
VP_CLKO3
VP_DIN7(1)
VP_DIN6(1)
VP_DIN5(1)
VP_DIN4(1)
VP_DIN3(1)
VP_DIN2(1)
VP_DIN1(1)
VP_DIN0(1)
UDTR0
UART0CTL ≠ 00
VP_CLKO3
VP_DIN7(1)
VP_DIN6(1)
VP_DIN5(1)
VP_DIN4(1)
VP_DIN3(1)
VP_DIN2(1)
VP_DIN1(1)
VP_DIN0(1)
GP[36]
TS0_CLKO
TS0_DOUT7(1)
TS0_DOUT6(1)
TS0_DOUT5(1)
TS0_DOUT4(1)
TS0_DOUT3(1)
TS0_DOUT2(1)
TS0_DOUT1(1)
TS0_DOUT0(1)
TS0_ENAO
TS0_CLKO
VP_DIN7(1)
VP_DIN6(1)
VP_DIN5(1)
VP_DIN4(1)
VP_DIN3(1)
VP_DIN2(1)
VP_DIN1(1)
VP_DIN0(1)
TS0_ENAO
TS0_PSTO
TS0_WAITIN
GP[8]
UDSR0
GP[37]
TS0_PSTO
UDCD0
GP[38]
TS0_WAITIN
GP[8]
URIN0
GP[8]
URXD1(2)
URXD1(2)
URXD1(2)
(see Table 3-22—TSPIMUX bit
field)
(also see Table 3-35)
UTXD1(2)
UTXD1(2)
UTXD1(2)
TS0_DOUT7
(1) Function will be overridden by TSIF1 signals if TSSIMUX = 11 (PINMUX0 register).
(2) Function is determined by UART1CTL bit field value in the PINMUX1 register.
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3.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
The TSIF 1 (TS1) input signals have three muxing options as configured by the TSSIMUX bits as shown
in Table 3-30. When TSSIMUX = 11, the TSSI data and control pins are muxed onto the VP_DIN[7:4]
regardless of the value of TSPOMUX.
Table 3-30. TSIF1 Serial Input Pin Muxing
TSSIMUX = 00
TS1_CLKIN
TSSIMUX = 01
TS1_CLKIN
TSSIMUX = 10
TS1_CLKIN
TSSIMUX = 11
TS1_CLKIN
TS1_DIN
VP_DIN7/TS0_DOUT7(1)
VP_DIN6/TS0_DOUT6(1)
VP_DIN5/TS0_DOUT5(1)
VP_DIN4/TS0_DOUT4(1)
VP_DIN3/TS0_DOUT3(1)
VP_DIN2/TS0_DOUT2(1)
VP_DIN1/TS0_DOUT1(1)
VP_DIN0/TS0_DOUT0(1)
VP_DOUT15
VP_DIN7/TS0_DOUT7(1)
VP_DIN6/TS0_DOUT6(1)
VP_DIN5/TS0_DOUT5(1)
VP_DIN4/TS0_DOUT4(1)
VP_DIN3/TS0_DOUT3(1)
VP_DIN2/TS0_DOUT2(1)
VP_DIN1/TS0_DOUT1(1)
VP_DIN0/TS0_DOUT0(1)
VP_DOUT15
VP_DIN7/TS0_DOUT7(1)
VP_DIN6/TS0_DOUT6(1)
VP_DIN5/TS0_DOUT5(1)
VP_DIN4/TS0_DOUT4(1)
VP_DIN3/TS0_DOUT3(1)
VP_DIN2/TS0_DOUT2(1)
VP_DIN1/TS0_DOUT1(1)
VP_DIN0/TS0_DOUT0(1)
TS1_DIN
TS1_PSTIN
TS1_EN_WAITO
TS1_WAITO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VP_DOUT15
VP_DOUT14
VP_DOUT13
VP_DOUT12
URXD0(2)
UTXD0(2)
VP_DOUT14
VP_DOUT14
TS1_PSTIN
VP_DOUT13
VP_DOUT13
TS1_EN_WAITO
VP_DOUT12
URXD0(2)
UTXD0(2)
VP_DOUT12
TS1_WAITO
URXD0(2)
UTXD0(2)
TS1_DIN
TS1_PSTIN
(2)
(2)
(2)
URTS0
TS1_EN_WAITO
USD0
URTS0
URTS0
(2)
(2)
(2)
UCTS0
UCTS0
UCTS0
(1) Function will be determined by TSPOMUX bit field value in the PINMUX0 register.
(2) Function is determined by UART0CTL bit field value in the PINMUX1 register
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3.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
The TSIF 1 (TS1) output signals are muxed with either the VP_DOUT signals or UART0, UART2, and
PWM signals as selected by TSSOMUX (PINMUX0 register). The TS1 output pin muxing is shown in
Table 3-31.
Table 3-31. TSIF1 Serial Output Pin Muxing
PIN FUNCTION
TSSOMUX = 0x
VP_CLKIN3
TSSOMUX = 10
TS1_CLKO
TSSOMUX = 11
TS1_CLKO
VP_DOUT11
VP_DOUT10
VP_DOUT9
VP_DOUT8
TS1_WAITIN
TS1_PSTO
TS1_ENAO
TS1_DOUT
VP_DOUT11
TS1_DOUT
VP_DOUT10
TS1_PSTO
VP_DOUT9
TS1_ENAO
VP_DOUT8
TS1_WAITIN
URIN0/GP[8](1)
UCTS2/GP[42]/CRG0_VCXI(2)
PWM0/CRG0_PO(3)
PWM1
URIN0/GP[8](1)
UCTS2/GP[42]/CRG0_VCXI(2)
PWM0/CRG0_PO(3)
PWM1
(1) Function will be determined by UART0CTL bit field value in the PINMUX1 register.
(2) Function will be determined by UART2CTL and CRGMUX bit field values in the PINMUX1 and PINMUX0 registers, respectively.
(3) Function will be determined by CRGMUX bit field value in the PINMUX0 register.
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3.7.3.7 CRGEN Signal Muxing
The two CRGEN modules share pins with UART2 and PWM0. The CRGEN function is selected using the
CRGMUX bit field in the PINMUX0 register (see Table 3-32).
Table 3-32. CRG Pin Muxing
PIN FUNCTION
CRGMUX = 001
CRGMUX = 100
CRG0_PO(1)
CRG0_VCXI(3)
URXD2(2)
CRGMUX = 101
CRG0_PO(1)
CRG0_VCXI(3)
CRG1_VCXI
CRG1_PO
CRGMUX = 110
CRGMUX = other
PWM0(1)
PWM0(1)
PWM0(1)
(2) (3)
(2) (3)
(2) (3)
UCTS2
UCTS2
UCTS2
CRG1_VCXI
CRG1_PO
CRG0_VCXI
CRG0_PO
URXD2(2)
UTXD2(2)
UTXD2(2)
(1) Function will be overridden by TS1_ENAO pin if TSSOMUX = 11 (PINMUX0 register).
(2) Function is determined by UART2CTL bit field value in the PINMUX1 register.
(3) Function will be overridden by TS1_PSTO if TSSOMUX = 11 (PINMUX0 register).
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3.7.3.8 UART0 Pin Muxing
The UART0 module can operate as either a UART or IrDA/CIR interface. The UART0 pin muxing is
controlled by the UART0CTL bit field in the PINMUX1 register and the TSPOMUX, TSSIMUX, and
TSSOMUX bit fields in the PINMUX0 register. Muxing options are shown in Table 3-33 and Table 3-34.
When UART operation is selected, UART0CTL must be set to either ‘00’ for UART with modem signals or
‘01’ for UART without modem signals. When IrDA/CIR operation is selected, UART0CTL must be set to
‘1x’ to use the IrDA/CIR signals and the modem signal become GPIOs. A TSPOMUX setting of ‘1x’
overrides the modem control mux settings. UART0 can still be used as a UART without modem control or
in IrDA/CIR mode based on the UART0CTL bit field value. A TSSIMUX setting of ‘01’ overrides the UART
data and flow control settings and prevents UART0 from being used. The UART0 modem control pins may
be used as either TSIF 0 output or GPIO pins based on the TSPOMUX and UART0CTL settings. A
TSSOMUX setting of ‘11’ overrides the RIN function with the TS1_WAITIN function.
Table 3-33. UART0 Pin Muxing—Part 1
PIN FUNCTIONS
UTXD0/
URCTX0/
TS1_PSTIN
URTS0 /
UIRTX0/
TS1_EN_WAITO
TSSIMUX[1]
TSSIMUX[0]
UART0CTL[1] UART0CTL[0]
URXD0/
TS1_DIN
UCTS0 /
USD0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
URXD0
URXD0
URXD0
URXD0
TS1_DIN
TS1_DIN
TS1_DIN
TS1_DIN
URXD0
URXD0
URXD0
URXD0
UTXD0
UTXD0
URTS0
URTS0
UCTS0
UCTS0
USD0
USD0
–
URCTX0
URCTX0
TS1_PSTIN
TS1_PSTIN
TS1_PSTIN
TS1_PSTIN
UTXD0
UIRTX0
UIRTX0
TS1_EN_WAITO
TS1_EN_WAITO
TS1_EN_WAITO
TS1_EN_WAITO
URTS0
–
–
–
UCTS0
UCTS0
USD0
USD0
UTXD0
URTS0
URCTX0
URCTX0
UIRTX0
UIRTX0
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Table 3-34. UART0 Pin Muxing—Part 2
PIN FUNCTIONS
UDTR0 /
TS0_ENAO/
GP[36]
UDSR0 /
TS0_PSTO/
GP[37]
UDCD0 /
TS0_WAITIN/
GP[38]
URIN0/
GP[8]/
TS1_WAITIN
TSSOMUX[1]
TSSOMUX[0]
TSPOMUX[1]
TSPOMUX[0]
UART0CTL[1]
UART0CTL[0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UDTR0
GP[36]
UDSR0
GP[37]
UDCD0
GP[38]
URIN0
GP[8]
GP[36]
GP[37]
GP[38]
GP[8]
GP[36]
GP[37]
GP[38]
GP[8]
TS0_ENAO
TS0_ENAO
TS0_ENAO
TS0_ENAO
UDTR0
TS0_PSTO
TS0_PSTO
TS0_PSTO
TS0_PSTO
UDSR0
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
UDCD0
GP[8]
GP[8]
GP[8]
GP[8]
URIN0
GP[36]
GP[37]
GP[38]
GP[8]
GP[36]
GP[37]
GP[38]
GP[8]
GP[36]
GP[37]
GP[38]
GP[8]
TS0_ENAO
TS0_ENAO
TS0_ENAO
TS0_ENAO
UDTR0
TS0_PSTO
TS0_PSTO
TS0_PSTO
TS0_PSTO
UDSR0
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
UDCD0
GP[8]
GP[8]
GP[8]
GP[8]
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
TS1_WAITIN
GP[36]
GP[37]
GP[38]
GP[36]
GP[37]
GP[38]
GP[36]
GP[37]
GP[38]
TS0_ENAO
TS0_ENAO
TS0_ENAO
TS0_ENAO
TS0_PSTO
TS0_PSTO
TS0_PSTO
TS0_PSTO
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
TS0_WAITIN
124
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3.7.3.9 UART1 Pin Muxing
The UART1 module can operate as either a UART or IrDA/CIR interface. The UART1 pin muxing options
are shown in Table 3-35. When UART operation is selected, UART1CTL must be set to either ‘00’ for
UART with flow control or ‘01’ for UART without flow control signals. When IrDA/CIR operation is selected,
UART1CTL must be set to ‘10’ to use the IrDA/CIR signals. If UART1 is unused, then setting UART1CTL
= 11 muxes GPIO function onto all the pins. The UART1 pin functions may be overridden based on the
settings of TSPIMUX and TSPOMUX
Table 3-35. UART1 Pin Muxing
PIN FUNCTIONS
UTXD1/
URCTX1/
TS0_DOUT7/
GP[24]
URTS1 /
UIRTX1/
UCTS1 /
USD1/
URXD1/
TS0_DIN7/
GP[23]
TSPIMUX[1]
TSPIMUX[0]
TSPOMUX[1]
TSPOMUX[0]
UART1CTL[1]
UART1CTL[0]
TS0_WAITO/ TS0_EN_WAITO/
GP[25]
GP[26]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
x
x
x
x
0
0
0
0
1
1
1
1
x
x
x
0
0
0
1
1
1
x
x
x
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
URXD1
URXD1
URXD1
GP[23]
UTXD1
UTXD1
URTS1
UCTS1
GP[25]
GP[26]
URCTX1
GP[24]
UIRTX1
USD1
GP[25]
GP[26]
URXD1
URXD1
URXD1
GP[23]
UTXD1
URTS1
UCTS1
UTXD1
GP[25]
GP[26]
URCTX1
GP[24]
UIRTX1
USD1
GP[25]
GP[26]
URXD1
URXD1
URXD1
GP[23]
TS0_DOUT7
TS0_DOUT7
TS0_DOUT7
TS0_DOUT7
UTXD1
URTS1
UCTS1
GP[25]
GP[26]
UIRTX1
USD1
GP[25]
GP[26]
URXD1
URXD1
GP[23]
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
TS0_EN_WAITO
URCTX1
GP[24]
URXD1
URXD1
GP[23]
UTXD1
URCTX1
GP[24]
URXD1
URXD1
GP[23]
TS0_DOUT7
TS0_DOUT7
TS0_DOUT7
UTXD1
TS0_DIN7
TS0_DIN7
TS0_DIN7
TS0_DIN7
TS0_DIN7
TS0_DIN7
TS0_DIN7
URCTX1
GP[24]
UTXD1
URCTX1
GP[24]
TS0_DOUT7
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3.7.3.10 UART2 Pin Muxing
The UART2 module can operate as either a UART or IrDA/CIR interface. The UART2 pin muxing options
are shown in Table 3-36 through Table 3-38. When UART operation is selected, UART2CTL must be set
to either ‘00’ for UART with flow control or ‘01’ for UART without flow control signals. When IrDA/CIR
operation is selected, UART2CTL must be set to ‘10’ to use the IrDA/CIR signals. If UART2 is unused,
then setting UART2CTL = 11 muxes GPIO function onto all the pins. The UART2 pin functions may be
overridden based on the settings of TSPIMUX, CRGMUX, and TSSOMUX.
Table 3-36. UART2 Data Pin Muxing
PIN FUNCTIONS
UTXD2/
URCTX2/
CRG1_PO/
GP[40]/
CRG0_PO
URXD2/
CRG1_VCXI/
GP[39]/
CRGMUX[2]
CRGMUX[1]
CRGMUX[0]
UART2CTL[1]
UART2CTL[0]
CRG0_VCXI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
URXD2
URXD2
UTXD2
UTXD2
URXD2
URCTX2
GP[40]
GP[39]
CRG1_VCXI
CRG1_VCXI
CRG1_VCXI
CRG1_VCXI
URXD2
CRG1_PO
CRG1_PO
CRG1_PO
CRG1_PO
UTXD2
URXD2
UTXD2
URXD2
URCTX2
GP[40]
GP[39]
URXD2
UTXD2
URXD2
UTXD2
URXD2
URCTX2
GP[40]
GP[39]
URXD2
UTXD2
URXD2
UTXD2
URXD2
URCTX2
GP[40]
GP[39]
CRG1_VCXI
CRG1_VCXI
CRG1_VCXI
CRG1_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
URXD2
CRG1_PO
CRG1_PO
CRG1_PO
CRG1_PO
CRG0_PO
CRG0_PO
CRG0_PO
CRG0_PO
UTXD2
URXD2
UTXD2
URXD2
URCTX2
GP[40]
GP[39]
126
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Table 3-37. UART2 Ready-to-Send ( URTS2 ) Pin Muxing
PIN FUNCTION
URTS2 /
UIRTX2/
TSPIMUX[1]
TSPIMUX[0]
UART2CTL[1]
UART2CTL[0]
TS0_PSTIN/
GP[41]
0
0
0
0
1
x
x
x
x
x
0
0
1
1
x
0
1
0
1
x
URTS2
GP[41]
UIRTX2
GP[41]
TS0_PSTIN
Table 3-38. UART2 Clear-to-Send ( UCTS2 ) Pin Muxing
PIN
FUNCTION
PIN
FUNCTION
TSSOMUX ≠ 11
TSSOMUX = 11
UCTS2 /
USD2/
UCTS2 /
USD2/
CRGMUX[2] CRGMUX[1] CRGMUX[0] UART2CTL[1] UART2CTL[0] CRG0_VCXI/ CRGMUX[2] CRGMUX[1] CRGMUX[0] UART2CTL[1] UART2CTL[0] CRG0_VCXI/
GP[42]/
GP[42]/
TS1_PSTO
TS1_PSTO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UCTS2
GP[42]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
TS1_PSTO
USD2
GP[42]
UCTS2
GP[42]
USD2
GP[42]
UCTS2
GP[42]
USD2
GP[42]
UCTS2
GP[42]
USD2
GP[42]
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
CRG0_VCXI
UCTS2
GP[42]
USD2
GP[42]
UCTS2
GP[42]
USD2
GP[42]
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3.7.3.11 ARM/DSP Communications Interrupts
The system module includes registers for generating interrupts between the ARM and DSP.
The DSPINT register shows the status of the ARM-to-DSP interrupts. The DSPINT register format is
shown in Figure 3-20. Table 3-39 describes the register bit fields. The ARM may generate an interrupt to
the DSP by setting one of the four INTDSP[3:0] bits or by setting the INTNMI bit in the DSPINTSET
pseudo-register (see Figure 3-21). The interrupt set bit then self-clears and the corresponding
INTDSP[3:0] or INTNMI bit in the DSPINT status register (see Figure 3-20) is automatically set to indicate
that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by writing ‘1’ to
the corresponding bit in the DSPINTCLR register (see Figure 3-22). The ARM may poll the status bit to
determine when the DSP has completed the interrupt service.
The DSP may generate an interrupt to the ARM in the same manner using the ARMINTSET and
ARMINTCLR registers shown/described in Figure 3-24, Table 3-43, and Figure 3-25, Table 3-44,
respectively. The DSP can then view the status of the DSP-to-ARM interrupts via the ARMINT register
shown/described in Figure 3-23 and Table 3-42.
31
15
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
R-0000 0000 0000 0000
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
INTNMI
Reserved
INTDSP3 INTDSP2 INTDSP1 INTDSP0
R-0000 000
R-0
R-0000
R-0
R-0
R-0
R-0
LEGEND: R = Read only, n = Value at reset
Figure 3-20. DSPINT Status Register [0x01C4 0060]
Table 3-39. DSPINT Status Register Bit Descriptions(1)
BIT
31:9
8
NAME
DESCRIPTION
Reserved. A read returns 0.
DSP NMI Status
Reserved
INTNMI
7:4
3
Reserved
INTDSP3
INTDSP2
INTDSP1
INTDSP0
Reserved. A read returns 0.
ARM-to-DSP Int3 Status
2
ARM-to-DSP Int2 Status
1
ARM-to-DSP Int1 Status
0
ARM-to-DSP Int0 Status
(1) Read only, writes have no effect.
128
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31
30
14
29
13
28
27
11
26
10
25
24
Reserved
23
22
21
5
20
4
19
18
17
16
R-0000 0000 0000 0000
15
12
9
8
7
6
3
2
1
0
Reserved
INTNMI
Reserved
INTDSP3 INTDSP2 INTDSP1 INTDSP0
R-0000 000
R/W-0
R-0000
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 3-21. DSPINTSET Register [0x01C4 0064]
Table 3-40. DSPINTSET Register Bit Descriptions
BIT
31:9
8
NAME
DESCRIPTION
Reserved. A read returns 0.
DSP NMI Set(1)
Reserved
INTNMI
7:4
3
Reserved
INTDSP3
INTDSP2
INTDSP1
INTDSP0
Reserved. A read returns 0.
ARM-to-DSP Int3 Set(1)
ARM-to-DSP Int2 Set(1)
ARM-to-DSP Int1 Set(1)
ARM-to-DSP Int0 Set(1)
2
1
0
(1) Writing a '1' generates the interrupt and sets the corresponding bit in the DSPINT status register. The register bit automatically clears to
a value of '0'. Writing a '0' has no effect. This register always reads as '0'.
31
15
30
14
29
13
28
27
11
26
10
25
24
Reserved
23
22
21
20
4
19
18
17
16
R-0000 0000 0000 0000
12
9
8
7
6
5
3
2
1
0
Reserved
INTNMI
Reserved
INTDSP3 INTDSP2 INTDSP1 INTDSP0
R-0000 000
R/W-0
R-0000
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 3-22. DSPINTCLR Register [0x01C4 0068]
Table 3-41. DSPINTCLR Register Bit Descriptions
BIT
31:9
8
NAME
DESCRIPTION
Reserved. A read returns 0.
DSP NMI Clear(1)
Reserved
INTNMI
7:4
3
Reserved
INTDSP3
INTDSP2
INTDSP1
INTDSP0
Reserved. A read returns 0.
ARM-to-DSP Int3 Clear(1)
ARM-to-DSP Int2 Clear(1)
ARM-to-DSP Int1 Clear(1)
ARM-to-DSP Int0 Clear(1)
2
1
0
(1) Writing a '1' clears the corresponding bit in the DSPINT status register. The register bit automatically clears to a value of '0'. Writing a '0'
has no effect. This register always reads as '0'.
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31
15
30
14
29
13
28
12
27
11
26
10
25
24
Reserved
23
22
21
5
20
4
19
3
18
2
17
1
16
R-0000 0000 0000 0000
9
8
7
6
0
Reserved
INTARM0
R-0000 0000 0000 000
R-0
LEGEND: R = Read only, n = Value at reset
Figure 3-23. ARMINT Status Register [0x01C4 0070]
Table 3-42. ARMINT Status Register Bit Descriptions(1)
BIT
31:1
0
NAME
DESCRIPTION
Reserved. A read returns 0.
Reserved
INTARM0
DSP-to-ARM Int0 Status
(1) Read only, writes have no effect.
31
15
30
14
29
13
28
12
27
11
26
10
25
24
Reserved
23
22
21
5
20
4
19
3
18
2
17
1
16
R-0000 0000 0000 0000
9
8
7
6
0
Reserved
INTARM0
R-0000 0000 0000 000
R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 3-24. ARMINTSET Register [0x01C4 0074]
Table 3-43. ARMINTSET Register Bit Descriptions
BIT
31:1
0
NAME
DESCRIPTION
Reserved. A read returns 0.
DSP-to-ARM Int0 Set(1)
Reserved
INTARM0
(1) Writing a '1' generates the interrupt and sets the corresponding bit in the ARMINT status register. The register bit automatically clears to
a value of '0'. Writing a '0' has no effect. This register always reads as '0'.
130
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31
30
14
29
13
28
12
27
11
26
10
25
24
Reserved
23
22
21
5
20
4
19
3
18
2
17
1
16
R-0000 0000 0000 0000
15
9
8
7
6
0
Reserved
INTARM0
R-0000 0000 0000 000
R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 3-25. ARMINTCLR Register [0x01C4 0078]
Table 3-44. ARMINTCLR Register Bit Descriptions
BIT
31:1
0
NAME
DESCRIPTION
Reserved. A read returns 0.
DSP-to-ARM Int0 Clear(1)
Reserved
INTARM0
(1) Writing a '1' clears the corresponding bit in the ARMINT status register. The register bit automatically clears to a value of '0'. Writing a '0'
has no effect. This register always reads as '0'.
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3.7.3.12 Emulation Control
The flexibility of the DM646xT DMSoC architecture allows either the ARM or DSP to control the various
peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software
convention, during an emulation halt it is necessary for the device to know which peripherals are
associated with the halting processor so that only those modules receive the suspend signal. This allows
peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC
register indicates the emulation suspend source for those peripherals which support emulation suspend.
The SUSPSRC register format is shown in Figure 3-26. Brief details on the peripherals which correspond
to the register bits are listed in Table 3-45. When the associated SUSPSRC bit is ‘0’, the peripheral’s
emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP
emulator.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CRGEN1 CRGEN0
SRC SRC
TIMR2
SRC
TIMR1
SRC
TIMR0
SRC
GPIO
SRC
PWM1
SRC
PWM0
SRC
SPI
SRC
UART2
SRC
UART1
SRC
UART0
SRC
I2C
SRC
MCASP1 MCASP0
SRC SRC
RSV
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R-0
9
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15
13
12
11
10
8
7
6
5
4
3
0
HPI
SRC
EMAC
SRC
USB
SRC
VDCE
SRC
TSIF1
SRC
TSIF0
SRC
VPIF
SRC
RESERVED
RSV
RSV
RESERVED
R-000
R/W-0
R-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R-0
R/W-0
R-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-26. SUSPSRC Register
Table 3-45. SUSPSRC Register Bit Descriptions
BIT
NAME
DESCRIPTION
Clock Recovery Generator 1 Emulation Suspend Source.
0 = ARM emulation suspend.
31
CRGEN1SRC
1 = DSP emulation suspend.
Clock Recovery Generator 0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
30
29
28
27
CRGEN0SRC
TIMR2SRC
TIMR1SRC
TIMR0SRC
Timer2 (WD Timer) Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
Timer1 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
Timer0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
GPIO Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
26
25
24
GPIOSRC
RSV
Reserved. Read returns "0".
PWM1 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
PWM1SRC
PWM0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
23
22
21
PWM0SRC
SPISRC
SPI Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
UART2 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
UART2SRC
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Table 3-45. SUSPSRC Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
UART1 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
20
UART1SRC
UART0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
19
18
17
UART0SRC
I2CSRC
I2C Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
McASP1 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
MCASP1SRC
McASP0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
16
15:13
12
MCASP0SRC
RESERVED
HPISRC
Reserved. Read returns "0".
HPI Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
11
RSV
Reserved. Read returns "0".
Ethernet MAC Emulation Suspend Source.
0 = ARM emulation suspend.
10
EMACSRC
1 = DSP emulation suspend.
USB Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
9
8
7
USBSRC
VDCESRC
TSIF1SRC
VDCE Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
TSIF1 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
TSIF0 Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
6
5
TSIF0SRC
RSV
Reserved. Read returns "0".
Video Port Emulation Suspend Source.
0 = ARM emulation suspend.
1 = DSP emulation suspend.
4
VPIFSRC
RESERVED
3:0
Reserved. Read returns "0".
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3.8 Debugging Considerations
3.8.1 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the TMS320DM646x DMSoC device always be at a
valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The TMS320DM646x
DMSoC features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the
need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired
value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins (listed in Table 2-6, Boot Terminal Functions), if they are both routed
out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be
implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the
desired configuration value, providing external connectivity can help ensure that valid logic levels are
latched on these device boot and configuration pins. In addition, applying external pullup/pulldown
resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in
switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have
IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users
should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for
the VCE6467T DMSoC, see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply
Voltage and Operating Temperature.
134
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For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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4 System Interconnect
On the VCE6467T device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers,
and the system peripherals are interconnected through a switch fabric architecture. The switch fabric is
composed of multiple switched central resources (SCRs) and multiple bridges.
For more detailed information on the DMSoC System Interconnect Architecture, including the
device-specific SCRs, bridges, and the system connection matrix, see the TMS320DM6467 SoC
Architecture and Throughput Overview Application Report (literature number SPRAAW4).
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless
Otherwise Noted)(1)
(2)
Supply voltage ranges:
Core (CVDD, DEV_CVDD, AUX_CVDD
)
–0.5 V to 1.5 V
-0.3 V to 3.8 V
-0.3 V to 2.6 V
(2)
I/O, 3.3V (DVDD33, USB_VDDA3P3
)
I/O, 1.8V (DVDDR2, PLL1VDD18, PLL2VDD18, DEV_DVDD18, AUX_DVDD18
,
(2)
USB_VDD1P8
)
Input and Output voltage ranges:
–0.3 V to 3.8 V
–0.3 V to DVDD33 + 0.3 V
–0.5 V to 4.2 V
V I/O, 3.3-V pins (except PCI-capable pins)
V I/O, 3.3-V pins PCI-capable pins
V I/O, 1.8 V
–0.5 V to DVDD33 + 0.5 V
–0.3 V to 2.6 V
–0.3 V to DVDD18 + 0.3 V
0°C to 85°C
Operating case temperature
ranges, Tc:
(default) [-1G]
(D version) Industrial Temperature [-1G]
(default)
ESD-HBM (Human Body Model)(3)
ESD-CDM (Charged-Device Model)(4)
-40°C to 85°C
Storage temperature range, Tstg
–55°C to 150°C
± 2000 V
Electrostatic Discharge (ESD)
Performance:
± 500 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) Based on JEDEC JESD22-A114E (Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)).
(4) Based on JEDEC JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds
of Microelectronic Components).
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5.2 Recommended Operating Conditions
MIN
1.235
3.14
NOM
1.3
MAX
UNIT
Supply voltage, Core (CVDD, DEV_CVDD
,
CVDD
DVDD
(-1G)
1.365
3.46
1.89
V
V
V
(1)
AUX_CVDD
Supply voltage, I/O, 3.3V (DVDD33, USB_VDDA3P3
Supply voltage, I/O, 1.8V (DVDDR2, PLL1VDD18, PLL2VDD18
)
)
3.3
,
1.71
1.8
(2)
DEV_DVDD18, AUX_DVDD18, USB_VDD1P8
)
(3)
Supply ground (VSS, PLL1VSS, PLL2VSS, DEV_VSS
,
VSS
0
0
0.5DVDDR2
VSS
0
V
V
V
AUX_VSS (3), USB_VSSREF
DDR2 reference voltage(4)
)
DDR_VREF
DDR_ZP
0.49DVDDR2
0.51DVDDR2
DDR2 impedance control, connected via 50-Ω (±5%
tolerance) resistor to VSS
DDR2 impedance control, connected via 50-Ω (±5%
tolerance) resistor to DVDDR2
DDR_ZN
DVDDR2
V
V
High-level input voltage, 3.3 V (except JTAG[TCK],
PCI-capable, and I2C pins)
2
High-level input voltage, JTAG [TCK]
High-level input voltage, PCI
2.5
0.5DVDD33
0.7DVDD33
0.65DVDD18
V
V
V
V
VIH
High-level input voltage, I2C
High-level input voltage, non-DDR I/O, 1.8 V
Low-level input voltage, 3.3 V (except PCI-capable and I2C
pins)
0.8
V
Low-level input voltage, PCI
0.3DVDD33
V
V
VIL
Low-level input voltage, I2C
0
0.3DVDD33
Low-level input voltage, non-DDR I/O, 1.8 V
0.35DVDD18
V
Default
Operating case temperature
0
-40
20
85
85
1
°C
°C
GHz
Tc
D Version
FSYSCLK1
DSP Operating Frequency (SYSCLK1)
-1G
(1) Future variants of TI SoC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V, 1.3 V, 1.365 V with ± 3% tolerances) by implementing simple board changes such as reference resistor
values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future
versions of TI SoC devices.
(2) Oscillator 1.8 V power supply (DEV_DVDD18) can be connected to the same 1.8 V power supply as DVDDR2
.
(3) Oscillator ground (DEV_VSS and AUX_VSS) must be kept separate from other grounds and connected directly to the crystal load
capacitor ground.
(4) DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2
.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
2.8
TYP
MAX UNIT
Low/full speed: USB_DN and USB_DP
High speed: USB_DN and USB_DP
USB_VDDA3P3
V
360
440
mV
High-level output voltage (3.3V I/O except
PCI-capable and I2C pins)
VOH
DVDD33 = MIN, IOH = MAX
2.4
V
V
High-level output voltage (3.3V I/O
PCI-capable pins)
(2)
IOH = –0.5 mA, DVDD33 = 3.3 V
0.9DVDD33
Low/full speed: USB_DN and USB_DP
High speed: USB_DN and USB_DP
0.0
0.3
10
V
–10
mV
Low-level output voltage (3.3V I/O except
PCI-capable and I2C pins)
DVDD33 = MIN, IOL = MAX
0.4
V
V
VOL
Low-level output voltage (3.3V I/O
PCI-capable pins)
(2)
IOL = 1.5 mA, DVDD33 = 3.3 V
0.1DVDD33
Low-level output voltage (3.3V I/O I2C pins) IO = 3 mA
USB_VDDA1P2LDO output voltage
0
0.4
V
V
VLDO
1.14
1.2
1.26
VI = VSS to DVDD33 without opposing
internal resistor
±20
250
μA
μA
Input current [DC] (except I2C and
PCI-capable pins)
VI = VSS to DVDD33 with opposing
50
100
(4)
internal pullup resistor
VI = VSS to DVDD33 with opposing
internal pulldown resistor
–250
–100
–50
±20
±50
μA
μA
μA
(4)
(3)
II
Input current [DC] (I2C)
VI = VSS to DVDD33
0 < VI < DVDD33 = 3.3 V without
opposing internal resistor
0 < VI < DVDD33 = 3.3 V with opposing
internal pullup resistor
Input current (PCI-capable pins) [DC](5)
50
250
–50
μA
μA
(4)
0 < VI < DVDD33 = 3.3 V with opposing
–250
(4)
internal pulldown resistor
GMTCLK, MTXD[7:0], MTXEN
DDR2; VOH = DVDDR2 – 0.4 V
–8
–8
mA
mA
IOH
High-level output current [DC]
PCI-capable pins
(PCI pin function only)
–0.5(2)
mA
All other peripherals
–4
8
mA
mA
mA
GMTCLK, MTXD[7:0], MTXEN
DDR2; VOL = 0.4 V
8
IOL
Low-level output current [DC]
I/O Off-state output current
PCI-capable pins
(PCI pin function only)
1.5(2)
4
mA
mA
μA
All other peripherals
VO = DVDD33 or VSS; internal pull
disabled
±20
(6)
IOZ
VO = DVDD33 or VSS; internal pull
enabled
±100
μA
CVDD = 1.3 V, DSP clock = 1 GHz
ARM Clock = 500 MHz, DDR Clock =
400 MHz
Core (CVDD, DEV_CVDD, AUX_CVDD
)
ICDD
1792.22
mA
supply current(7)
DVDD = 3.3 V, DSP clock = 1 GHz
ARM Clock = 500 MHz, DDR Clock =
400 MHz
3.3V I/O (DVDD33, USB_VDDA3P3) supply
current(7)
IDDD
25.66
mA
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) These rated numbers are from the PCI Local Bus Specification Revision 2.3. The DC specifications and AC specifications are defined in
Table 4-3 (DC Specifications for 3.3V Signaling) and Table 4-4 (AC Specifications for 3.3V Signaling), respectively.
(3) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(5) PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
(6) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(7) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other
housekeeping activities); DDR2 Memory Controller at 50% utilization, 50% writes, 32 bits, 50% bit switching at room temperature (25
°C). The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and
I/O activity, as well as information relevant to board power supply design, see the TMS320DM6467T Power Consumption Summary
Application Report (literature number SPRAB64).
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature
(Unless Otherwise Noted) (continued)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.8V I/O (DVDDR2, PLL1VPRW18
,
DVDD = 1.8 V, DSP clock = 1 GHz
ARM Clock = 500 MHz, DDR Clock =
400 MHz
IDDD
PLL2VPRW18, DEV_DVDD18, AUX_DVDD18
,
214.02
mA
USB_VDD1P8) supply current(7)
CI
Input capacitance
Output capacitance
4
4
pF
pF
Co
140
Device Operating Conditions
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1 1.8-V and 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3-V I/O,
Vref = 1.5 V. For 1.8-V I/O, Vref = 0.9 V.
Vref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
6.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
6.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
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adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing
characteristics. Section 6.10.2, DDR2 Interface, provides a PCB routing rules solution that describes the
routing rules to ensure the DDR2 memory controller interface timings are met.
6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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6.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/processorpower.
6.3.1 Power-Supply Sequencing
The VCE6467T includes one core supply (CVDD), and two I/O supplies—DVDD33 and DVDDR2. To ensure
proper device operation, a specific power-up sequence must be followed. Some TI power-supply devices
include features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable
features. For more information on TI power supplies and their features, visit www.ti.com/processorpower.
Here is a summary of the power sequencing requirements:
•
The power ramp order must be CVDD before DVDDR2, and DVDDR2 before DVDD33—meaning during
power up, the voltage at the DVDDR2 rail should never exceed the voltage at the CVDD rail. Similarly,
the voltage at the DVDDD33 rail should never exceed the voltage at the DVDDR2 rail.
•
From the time that power ramp begins, all power supplies (CVDD, DVDDR2, DVDD33) must be stable
within 200 ms. The term "stable" means reaching the recommended operating condition (see
Section 5.2, Recommended Operating Conditions table).
6.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the VCE6467T device, the PC board should include separate power planes for core,
I/O, and ground; all bypassed with high-quality low-ESL/ESR capacitors.
6.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the VCE6467T. These caps need to be close to the VCE6467T power pins, no more
than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better but
need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the
effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while
maintaining the largest available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 μF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the
TMS320DM646x DMSoC Application Report (literature number SPRAAM1A).
6.3.4 VCE6467T Power and Clock Domains
The VCE6467T includes one single power domain — the "Always On" power domain. The "Always On"
power domain is always on when the chip is on. The "Always On" domain is powered by the CVDD pins of
the VCE6467T. All VCE6467T modules lie within the "Always On" power domain. Table 6-1 provides a
listing of the VCE6467T clock domains.
Two primary reference clocks are required for the VCE6467T device. These can either be crystal inputs or
driven by external oscillators. A 33-MHz or 33.3-MHz crystal is recommended for the system PLLs, which
generate the internal clocks for the ARM926, DSP, HDVICPs, peripherals, and the EDMA3. A 24- or
48-MHz crystal is also required if the USB (24-MHz only) or UART (either 24- or 48-MHz) peripherals are
to be used. In addition, the 24- or 48-MHz input clock can be used to source the McASPs' clocks. For
further description of the VCE6467T clock domains, see and Figure 6-4.
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The VCE6467T architecture is divided into the power and clock domains shown in Table 6-1. Table 6-2
further discusses the clock domains and their ratios. Figure 6-4 shows the Clock Domain Block Diagram.
Table 6-1. VCE6467T Power and Clock Domains
POWER DOMAIN
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
Always On
CLOCK DOMAIN
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK2
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK3
SYSCLK4
SYSCLK3
SYSCLK1
SYSCLK2
PERIPHERAL/MODULE
UART0
UART1
UART2
I2C
Timer0
Timer1
Timer2
PWM0
PWM1
DDR2
VPIF
TSIF0
TSIF1
VDCE
HDVICP0
HDVICP1
EDMA3
PCI
SCR
GPSC
LPSCs
PLLC1
PLLC2
Ice Pick
EMIFA
USB
HPI
VLYNQ
EMAC/MDIO
SPI
McASP0
McASP1
CRGEN0
CRGEN1
ATA
GPIO
C64x+ CPU
ARM926
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Table 6-2. VCE6467T Clock Domains
CLOCK
DOMAIN
DOMAIN CLOCK
SOURCE
FIXED RATIO vs.
SYSCLK1 FREQ
CLOCK MODES FREQUENCY (MHz)
SUBSYSTEM
BYPASS MODE
PLL MODE (-1G)(1)
[default RATIO]
DSP Subsystem
PLLDIV1
PLLDIV2
PLLC1 SYSCLK1
PLLC1 SYSCLK2
1:1
1:2
33.30 MHz
999 MHz
ARM926 Subsystem,
EDMA3, HDVICP, PCI,
VDCE, VPIF, TSIFs, DDR2
Mem Ctlr
16.65 MHz
499.50 MHz
Peripherals (GPIO, Timers,
I2C, PWMs, HPI, EMAC,
EMIFA, VLYNQ, SPI, ARM
INTC, USB2.0, UARTs,
McASPs, CRGENs,
1:4
PLLDIV3
PLLC1 SYSCLK3
8.33 MHz
249.75 MHz
SYSTEM)
ATA
1:6 [default]
1:7(2)
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV8
PLLC1 SYSCLK4
PLLC1 SYSCLK5
PLLC1 SYSCLK6
PLLC1 SYSCLK8
5.55 MHz
4.16 MHz
4.16 MHz
4.16 MHz
142.71 MHz
99.90 MHz
99.90 MHz
99.90 MHz(4)
(3)
TSIF0
1:8 [default]
1:10(2)
TSIF1(3)
VPIF(3)
1:8 [default]
1:10(2)
1:8 [default]
1:10(2)
VLYNQ
1:6 [default]
1:10(2)
PLLDIV9
PLLDIV1
PLLC1 SYSCLK9
PLLC2 SYSCLK1
5.55 MHz
99.90 MHz
DDR2 PHY
1:1
33.30 MHz
799.20 MHz
(1) These table values assume a DEV_MXI/DEV_CLKIN of 33.3 MHz and a PLL1 multiplier equal to 30. Any input crystal with a frequency
between 20 MHz and 35 MHz can be used.
(2) To achieve these quoted frequencines, the PLLC1 SYSCLKx (for SYSCLK4, SYSCLK5, SYSCLK6, SYSCLK8, SYSCLK9) default
divider values must be changed based on the input crystal frequency. For the steps to change the PLLC1 SYSCLKx divider values, see
theTMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
(3) These domain clock sources, along with VP_CLKIN[3:0], STC_CLKIN, CRG0_VCXI, and CRG1_VCXI clock signals, go through the
clock select logic to determine the clock source enabled as the input to the VPIF and TSIF peripherals.
(4) Use an external clock source for the 54-/74.25-/108-MHz VPIF clock.
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GPIO
Timer 0
Timer 1
Timer 2 (WD)
I2C
PCI
VDCE
TINP0L
TINP0U
TINP1L
HDVICP0
PLL Controller 1
HDVICP1
DEV_MXI/
DEV_CLKIN
(33.3 MHz)
PLLM
EDMA3
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK9
SYSCLK5
SYSCLK6
SYSCLK8
SYSCLKBP
AUXCLK
PLLDIV1 (/1 Fixed)
PLLDIV2 (/2 Fixed)
PLLDIV3 (/4 Fixed)
PLLDIV4 (/6 Prog)
PLLDIV9 (/6 Prog)
PLLDIV5 (/8 Prog)
PLLDIV6 (/8 Prog)
PLLDIV8 (/8 Prog)
BPDIV (/1 Prog)
DSP Subsystem
Crossbar/SCR
ARM Subsystem
PWM (x2)
HPI
EMAC/MDIO
EMIFA
ATA
VLYNQ
SPI
TSIF0
TSIF1
ARM INTC
USB 2.0
60 MHz
AUX_MXI/
AUX_CLKIN
(24/48 MHz)
USB PHY
Video Port
I/F
UART0
UART1
VP_CLKIN0
VP_CLKIN1
VP_CLKIN2
VP_CLKIN3
STC_CLKIN
Clock Select
Logic
UART2
McASP0
McASP1
CLKOUT0
AUDIO_CLK0
AUDIO_CLK1
CRG0_VCXI
CRG1_VCXI
CRGEN0
CRGEN1
PLL Controller 2
PLLM
DDR2 Mem Cltr
PLL2_SYSCLK1
PLLDIV1 (/1 Prog)
Figure 6-4. PLL1 and PLL2 Clock Domain Block Diagram
For further detail on PLL1 and PLL2, see the structure block diagrams shown in Figure 6-5 and
Figure 6-6, respectively.
PLLDIV1 (/1 Fixed)
PLLDIV2 (/2 Fixed)
PLLDIV3 (/4 Fixed)
PLLDIV4 (/6 Prog)
PLLDIV5 (/8 Prog)
PLLDIV6 (/8 Prog)
PLLDIV8 (/8 Prog)
PLLDIV9 (/6 Prog)
BPDIV (/1 Prog)
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK8
SYSCLK9
SYSCLKBP
AUXCLK
CLKMODE
PLLOUT
PLLEN
1
0
CLKIN
OSCIN
1
0
PLL
PLLM
Figure 6-5. PLL1 Structure Block Diagram
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PLLOUT
PLLEN
CLKIN/OSCIN(A)
1
0
PLL
PLL2_SYSCLK1
(DDR2_PHY)
PLLDIV1 (/1 Prog)
PLLM
(A) As selected by the PLL2 PLLCTL register
Figure 6-6. PLL2 Structure Block Diagram
6.3.5 Power and Sleep Controller (PSC)
The Power and Sleep Controller (PSC) controls device power by gating off clocks to individual
peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The
GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. The GPSC controls all of the VCE6467T's LPSCs. The ARM Subsystem does not have an LPSC
module. ARM sleep mode is accomplished through the wait for interrupt instruction. The LPSCs for
VCE6467T are shown in Table 6-3. The PSC Register memory map is given in Table 6-4. For more
details on the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature
number SPRUEP9).
Table 6-3. VCE6467T LPSC Assignments
LPSC
PERIPHERAL/MODULE
LPSC
PERIPHERAL/MODULE
LPSC
PERIPHERAL/MODULE
NUMBER
NUMBER
NUMBER
0
1
Reserved
C64x+ CPU
HDVICP0
HDVICP1
EDMA CC
EDMA TC0
EDMA TC1
EDMA TC2
EDMA TC3
USB2.0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Video Port
Video Port
TSIF0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
SPI
GPIO
2
TIMER0
TIMER1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM INTC
3
TSIF1
4
DDR2 Memory Controller
EMIFA
5
6
McASP0
McASP1
CRGEN0
CRGEN1
UART0
7
8
9
10
11
12
13
14
15
ATA
VLYNQ
UART1
HPI
UART2
PCI
PWM0
EMAC/MDIO
VDCE
PWM1
I2C
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Table 6-4. PSC Registers
REGISTER
ACRONYM
HEX ADDRESS RANGE
DESCRIPTION
0x01C4 1000
PID
–
Peripheral Revision and Class Information Register
Reserved
0x01C4 1004 - 0x01C4 1017
0x01C4 1018
INTEVAL
–
Interrupt Evaluation Register
0x01C4 101C - 0x01C4 1039
0x01C4 1040
Reserved
MERRPR0
MERRPR1
–
Module Error Pending 0 (mod 0- 31) Register
Module Error Pending 1 (mod 32- 63) Register
Reserved
0x01C4 1044
0x01C4 1048 - 0x01C4 1049
0x01C4 1050
MERRCR0
MERRCR1
Module Error Clear 0 (mod 0 - 31) Register
Module Error Clear 1 (mod 32 - 63) Register
Reserved
0x01C4 1054
0x01C4 1058 - 0x01C4 111F
0x01C4 1120
PTCMD
–
Power Domain Transition Command Register
Reserved
0x01C4 1124 - 0x01C4 1127
0x01C4 1128
PTSTAT
Power Domain Transition Status Register
Reserved
0x01C4 112C - 0x01C4 11FF
0x01C4 1200
–
PDSTAT0
–
Power Domain Status 0 Register (Always On)
Reserved
0x01C4 1204 - 0x01C4 12FF
0x01C4 1300
PDCTL0
Power Domain Control 0 Register (Always On)
Reserved
0x01C4 1304 - 0x01C4 17FF
0x01C4 1800 - 0x01C4 1803
0x01C4 1804
–
–
Reserved
MDSTAT1
MDSTAT2
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
MDSTAT14
MDSTAT15
MDSTAT16
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
MDSTAT28
Module Status 1 Register (C64x+ CPU)
Module Status 2 Register (HDVICP0)
Module Status 3 Register (HDVICP1)
Module Status 4 Register (EDMA CC)
Module Status 5 Register (EDMA TC0)
Module Status 6 Register (EDMA TC1)
Module Status 7 Register (EDMA TC2)
Module Status 8 Register (EDMA TC3)
Module Status 9 Register (USB)
Module Status 10 Register (ATA)
Module Status 11 Register (VLYNQ)
Module Status 12 Register (HPI)
Module Status 13 Register (PCI)
Module Status 14 Register (EMAC)
Module Status 15 Register (VDCE)
Module Status 16 Register (Vdieo Port)
Module Status 17 Register (Video Port)
Module Status 18 Register (TSIF0)
Module Status 19 Register (TSIF1)
Module Status 20 Register (DDR2 Mem Ctlr)
Module Status 21 Register (EMIFA)
Module Status 22 Register (McASP0)
Module Status 23 Register (McASP1)
Module Status 24 Register (CRGEN0)
Module Status 25 Register (CRGEN1)
Module Status 26 Register (UART0)
Module Status 27 Register (UART1)
Module Status 28 Register (UART2)
0x01C4 1808
0x01C4 180C
0x01C4 1810
0x01C4 1814
0x01C4 1818
0x01C4 181C
0x01C4 1820
0x01C4 1824
0x01C4 1828
0x01C4 182C
0x01C4 1830
0x01C4 1834
0x01C4 1838
0x01C4 183C
0x01C4 1840
0x01C4 1844
0x01C4 1848
0x01C4 184C
0x01C4 1850
0x01C4 1854
0x01C4 1858
0x01C4 185C
0x01C4 1860
0x01C4 1864
0x01C4 1868
0x01C4 186C
0x01C4 1870
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Table 6-4. PSC Registers (continued)
REGISTER
HEX ADDRESS RANGE
DESCRIPTION
ACRONYM
MDSTAT29
MDSTAT30
MDSTAT31
MDSTAT32
MDSTAT33
MDSTAT34
MDSTAT35
–
0x01C4 1874
Module Status 29 Register (PWM0)
0x01C4 1878
Module Status 30 Register (PWM1)
Module Status 31 Register (I2C)
Module Status 32 Register (SPI)
Module Status 33 Register (GPIO)
Module Status 34 Register (TIMER0)
Module Status 35 Register (TIMER1)
Reserved
0x01C4 187C
0x01C4 1880
0x01C4 1884
0x01C4 1888
0x01C4 188C
0x01C4 1890 - 0x01C4 18B3
0x01C4 18B4
MDSTAT45
–
Module Status 45 Register (ARM INTC)
Reserved
0x01C4 18B8 - 0x01C4 19FF
0x01C4 1A00 - 0x01C4 1A03
0x01C4 1A04
–
Reserved
MDCTL1
MDCTL2
MDCTL3
MDCTL4
MDCTL5
MDCTL6
MDCTL7
MDCTL8
MDCTL9
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
MDCTL16
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
MDCTL29
MDCTL30
MDCTL31
MDCTL32
MDCTL33
MDCTL34
MDCTL35
–
Module Control 1 Register (C64x+ CPU)
Module Control 2 Register (HDVICP0)
Module Control 3 Register (HDVICP1)
Module Control 4 Register (EDMA CC)
Module Control 5 Register (EDMA TC0)
Module Control 6 Register (EDMA TC1)
Module Control 7 Register (EDMA TC2)
Module Control 8 Register (EDMA TC3)
Module Control 9 Register (USB)
Module Control 10 Register (ATA)
Module Control 11 Register (VLYNQ)
Module Control 12 Register (HPI)
Module Control 13 Register (PCI)
Module Control 14 Register (EMAC)
Module Control 15 Register (VDCE)
Module Control 16 Register (Video Port)
Module Control 17 Register (Video Port)
Module Control 18 Register (TSIF0)
Module Control 19 Register (TSIF1)
Module Control 20 Register (DDR2 Mem Ctlr)
Module Control 21 Register (EMIFA)
Module Control 22 Register (McASP0)
Module Control 23 Register (McASP1)
Module Control 24 Register (CRGEN0)
Module Control 25 Register (CRGEN1)
Module Control 26 Register (UART0)
Module Control 27 Register (UART1)
Module Control 28 Register (UART2)
Module Control 29 Register (PWM0)
Module Control 30 Register (PWM1)
Module Control 31 Register (I2C)
Module Control 32 Register (SPI)
Module Control 33 Register (GPIO)
Module Control 34 Register (TIMER0)
Module Control 35 Register (TIMER1)
Reserved
0x01C4 1A08
0x01C4 1A0C
0x01C4 1A10
0x01C4 1A14
0x01C4 1A18
0x01C4 1A1C
0x01C4 1A20
0x01C4 1A24
0x01C4 1A28
0x01C4 1A2C
0x01C4 1A30
0x01C4 1A34
0x01C4 1A38
0x01C4 1A3C
0x01C4 1A40
0x01C4 1A44
0x01C4 1A48
0x01C4 1A4C
0x01C4 1A50
0x01C4 1A54
0x01C4 1A58
0x01C4 1A5C
0x01C4 1A60
0x01C4 1A64
0x01C4 1A68
0x01C4 1A6C
0x01C4 1A70
0x01C4 1A74
0x01C4 1A78
0x01C4 1A7C
0x01C4 1A80
0x01C4 1A84
0x01C4 1A88
0x01C4 1A8C
0x01C4 1A90 - 0x01C4 1AB3
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Table 6-4. PSC Registers (continued)
REGISTER
HEX ADDRESS RANGE
DESCRIPTION
ACRONYM
MDCTL45
–
0x01C4 1AB4
Module Control 45 Register (ARM INTC)
Reserved
0x01C4 1AB8 - 0x01C4 1FFF
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6.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
The VCE6467T device includes two options to provide an external clock input for both the system and
auxiliary oscillators:
•
Use an on-chip oscillator with external crystal (fundamental parallel resonant mode only, no overtone
support).
•
Use an external 1.8-V LVCMOS-compatible clock input.
Any input crystal frequency between 27 MHz and 35 MHz can be used for the System Oscillator
(DEV_MXI/DEV_CLKIN).
The optimal external clock input frequency for the crystals are 33 MHz or 33.3 MHz for the system
oscillator (DEV_MXI/DEV_CLKIN) and 24 MHz for the auxiliary oscillator. Section 6.4.1.1 provides more
details on Option 1, using an on-chip oscillator with external crystal for the 33.3-MHz system oscillator.
Section 6.4.1.2 provides more details on Option 1, using an on-chip oscillator with external crystal for the
24-MHz auxiliary oscillator. Section 6.4.2.1 provides details on Option 2, using an external 1.8-V
LVCMOS-compatible clock input for the 33.3-MHz system oscillator. Section 6.4.2 provides details on
Option 2, using an external 1.8-V LVCMOS-compatible clock input for the 24-MHz auxiliary oscillator.
6.4.1 Clock Input Option 1—Crystal
6.4.1.1 33.3-MHz for System Oscillator Clock Input Option 1—Crystal
In this option, a crystal is used as the external clock input to the VCE6467T system oscillator.
The 33.3-MHz oscillator provides the reference clock for all VCE6467T subsystems and peripherals. The
on-chip oscillator requires an external 33.3-MHz crystal connected across the DEV_MXI and DEV_MXO
pins, along with two load capacitors, as shown in Figure 6-7. The external crystal load capacitors must be
connected only to the 33.3-MHz oscillator ground pin (DEV_VSS). Do not connect to board ground (VSS).
The DEV_DVDD18 pin can be connected to the same 1.8 V power supply as DVDDR2
.
DEV_MXI/
DEV_CLKIN
DEV_MXO DEV_VSS
DEV_DVDD18 DEV_DVSS DEV_CVDD
Crystal
33.3 MHz
C1
C2
1.8 V
1.3 V
Figure 6-7. 33.3-MHz System Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (for typical values,
see Table 6-5). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (DEV_MXI and DEV_MXO) and to the DEV_VSS pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
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Table 6-5. Input Requirements for Crystal on the 27 – 35-MHz System Oscillator
PARAMETER
MIN
NOM
MAX
4
UNIT
ms
Start-Up Time (from power up until oscillating at stable frequency)
Oscillation Frequency
27
33 or 33.3
35
MHz
Ω
27 – 31-MHz
32 – 35-MHz
50
ESR
40
Ω
Parallel Load Capacitance (C1 and C2) [Max]
Frequency Tolerance
Aging
12 – 20
pF
± 50
± 5
ppm
ppm
ppm
n/a
Thermal Stability
± 50
Oscillation Mode
Fundamental
Drive Level (Max)
0.8
5
mW
pF
Shunt Capacitance (Max)
6.4.1.2 24-MHz Auxiliary Oscillator Clock Input Option 1—Crystal
In this option, a crystal is used as the external clock input to the VCE6467T auxiliary oscillator.
The 24-MHz oscillator provides the reference clock for USB and UART peripherals and the internal clock
source for the McASP peripherals. The on-chip oscillator requires an external 24-MHz crystal connected
across the AUX_MXI and AUX_MXO pins, along with two load capacitors, as shown in Figure 6-8. The
external crystal load capacitors must be connected only to the 24-MHz oscillator ground pin (AUX_VSS).
Do not connect to board ground (VSS). The AUX_DVDD18 pin can be connected to the same 1.8 V power
supply as DVDDR2
.
AUX_MXI/
AUX_CLKIN
AUX_MXO AUX_VSS
AUX_DVDD18 AUX_DVSS AUX_CVDD
Crystal
24 MHz
C1
C2
1.8 V
1.3 V
Figure 6-8. 24-MHz Auxiliary Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (for typical values,
see Table 6-6). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (AUX_MXI and AUX_MXO) and to the AUX_VSS pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
Table 6-6. Input Requirements for Crystal on the 24-MHz Auxiliary Oscillator
PARAMETER
MIN
NOM
MAX
UNIT
Start-Up Time (from power up until oscillating at stable
frequency of 24 MHz)
4
ms
Oscillation Frequency
ESR
24
MHz
60
Ω
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Table 6-6. Input Requirements for Crystal on the 24-MHz Auxiliary Oscillator (continued)
PARAMETER
MIN
NOM
MAX
±50
UNIT
ppm
pF
(1)
Frequency Stability
Parallel Load Capacitance (C1 and C2) [Max]
Frequency Tolerance
Aging
12 – 20
± 50
± 5
ppm
ppm
ppm
n/a
Thermal Stability
± 50
Oscillation Mode
Fundamental
Drive Level (Max)
0.8
5
mW
pF
Shunt Capacitance (Max)
(1) If the USB is used, a 24-MHz, 50-ppm crystal is recommended.
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6.4.2 Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input
6.4.2.1 33.3-MHz System Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input
In this option, a 1.8-V LVCMOS-Compatible Clock Input is used as the external clock input to the system
oscillator. The external connections are shown in Figure 6-9. The DEV_MXI/DEV_CLKIN pin is connected
to the 1.8-V LVCMOS-Compatible clock source. The DEV_MXO pin is left unconnected. The DEV_VSS pin
is connected to board ground (VSS). The DEV_DVDD18 pin can be connected to the same 1.8-V power
supply as DVDDR2
.
DEV_MXI/
DEV_CLKIN
DEV_MXO
NC
DEV_VSS DEV_DVDD18 DEV_DVSS DEV_CVDD
1.8 V
1.3 V
Figure 6-9. 1.8-V LVCMOS-Compatible Clock Input
The clock source must meet the DEV_MXI/DEV_CLKIN timing requirements in Section 6.5.5, Clock PLL
Electrical Data/Timing (Input and Output Clocks).
6.4.2.2 24-MHz Auxiliary Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input
In this option, a 1.8-V LVCMOS-Compatible Clock Input is used as the external clock input to the auxiliary
oscillator. The external connections are shown in Figure 6-10. The AUX_MXI/AUX_CLKIN pin is
connected to the 1.8-V LVCMOS-Compatible clock source. The AUX_MXO pin is left unconnected. The
AUX_VSS pin is connected to board ground (VSS). The AUX_DVDD18 pin can be connected to the same
1.8-V power supply as DVDDR2
.
AUX_MXI/
AUX_CLKIN
AUX_MXO
NC
AUX_VSS AUX_DVDD18 AUX_DVSS AUX_CVDD
1.8 V
1.3 V
Figure 6-10. 1.8-V LVCMOS-Compatible Clock Input
The clock source must meet the AUX_MXI/AUX_CLKIN timing requirements in Section 6.5.5, Clock PLL
Electrical Data/Timing (Input and Output Clocks).
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6.5 Clock PLLs
There are two independently controlled PLLs on VCE6467T. PLL1 generates the frequencies required for
the ARM, DSP, HDVICP0/1, EDMA, and peripherals. PLL2 generates the frequencies required for the
DDR2 interface. Any input crystal frequency between 27 MHz and 35 MHz can be used for the System
Oscillator (DEV_MXI/DEV_CLKIN). The recommended reference clock for both PLLs is the 33-MHz or
33.3-MHz crystal input. The VCE6467T has a third PLL that is embedded within the USB2.0 PHY and the
24-MHz oscillator is its reference clock source. This particular PLL is only usable for USB operation, and is
discussed further in the TMS320DM646x DMSoC Universal Serial Bus (USB) Controller User's Guide
(literature number SPRUER7).
6.5.1 PLL1 and PLL2
Both PLL1 and PLL2 power are supplied externally via the 1.8-V PLL power-supply pins (PLL1VDD18 and
PLL2VDD18). An external EMI filter circuit must be added to PLL1VDD18 and PLL2VDD18, as shown in
Figure 6-11. The 1.8-V supply of the EMI filters must be from the same 1.8-V power plane supplying the
device’s 1.8-V I/O power-supply pins (DVDDR2). TI recommends EMI filter manufacturer Murata, part
number NFM18CC222R1C3.
All PLL external components (C1, C2, C3, C4, and the EMI Filters) must be placed as close to the device
as possible. For the best performance, TI recommends that all the PLL external components be on a
single side of the board without jumpers, switches, or components other than the ones shown in
Figure 6-11. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external
components (C1, C2, C3, C4, and the EMI Filters).
DM646x
+1.8 V
EMI Filter
PLL1VDD18
PLL1
C4
C3
0.1μF
0.01μF
+1.8 V
EMI Filter
PLL2VDD18
PLL2
C2
C1
0.1μF
0.01μF
Figure 6-11. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 6.5.5, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for DEV_MXI/DEV_CLKIN, PLLOUT, AUX_MXI/AUX_CLKIN, and the device clocks
(SYSCLKs). The PLL Controllers must be configured not to exceed any of these constraints documented
in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios
might not be supported). For these constraints (ranges), see Table 6-7 through .
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Table 6-7. PLL1 and PLL2 Multiplier Ranges
-1G
PLL MULTIPLIER (PLLM)
MIN
x14
x14
MAX
x32
PLL1 Multiplier
PLL2 Multiplier
x32
Table 6-8. PLLC1 Clock Frequency Ranges
-1G
CLOCK SIGNAL NAME
UNIT
MIN
20
MAX
35
DEV_MXI/DEV_CLKIN
PLLOUT
MHz
MHz
MHz
400
1000
1000
SYSCLK1 (PLLDIV1 Domain)
Table 6-9. PLLC2 Clock Frequency Ranges
-1G
CLOCK SIGNAL NAME
UNIT
MIN
20
MAX
35
DEV_MXI/DEV_CLKIN(1)
PLLOUT
MHz
MHz
MHz
400
800
800
PLL2_SYSCLK1 (to DDR2 PHY)
(1) DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers
(PLLC1 and PLLC2).
Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after the PLL is powered up (after the PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see Table 6-10.
The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 1)
before bringing the PLL out of reset (writing PLLRST = 0). For the PLL reset time value, see Table 6-10.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 0
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the
PLL lock time value, see Table 6-10.
Table 6-10. PLL1 and PLL2 Stabilization, Lock, and Reset Times
PLL STABILIZATION/
LOCK/RESET TIME
MIN
NOM
MAX
UNIT
PLL Stabilization Time
150
μs
ns
ns
PLL Lock Time
PLL Reset Time
2000C(1)
128C(1)
(1) C = CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN or AUX_MXI/AUX_CLKIN
frequency is 27 MHz, use C = 37.037 ns.
For details on the PLL initialization software sequence, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number SPRUEP9).
For more information on the clock domains and their clock ratio restrictions, see Section 6.3.4, VCE6467T
Power and Clock Domains.
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6.5.2 PLL Controller Register Description(s)
A summary of the PLL controller registers is shown in Table 6-11. For more details, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
Table 6-11. PLL and Reset Controller Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
PLL1 Controller Registers
Peripheral ID Register
Reset Type Register
0x01C4 0800
0x01C4 08E4
0x01C4 0900
0x01C4 0910
0x01C4 0918
0x01C4 091C
0x01C4 0920
0x01C4 0928
0x01C4 092C
0x01C4 0938
0x01C4 093C
PID
RSTYPE
PLLCTL
PLLM
PLL Controller 1 PLL Control Register
PLL Controller 1 PLL Multiplier Control Register
PLL Controller 1 Divider 1 Register (SYSCLK1)
PLL Controller 1 Divider 2 Register (SYSCLK2)
PLL Controller 1 Divider 3 Register (SYSCLK3)
Reserved
PLLDIV1
PLLDIV2
PLLDIV3
–
BPDIV
PLL Controller 1 Bypass Control-Divider Register (SYSCLKBP)
PLL Controller 1 Command Register
PLLCMD
PLLSTAT
PLL Controller 1 Status Register (Shows PLLC1 PLLCTL Status)
PLL Controller 1 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
0x01C4 0940
0x01C4 0944
ALNCTL
PLL Controller 1 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has been modified)
DCHANGE
0x01C4 0948
0x01C4 094C
0x01C4 0950
0x01C4 0960
0x01C4 0964
0x01C4 0968
0x01C4 096C
0x01C4 0970
0x01C4 0974
CKEN
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
–
PLL Controller 1 Clock Enable Control Register
PLL Controller 1 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 1 SYSCLK Status Register (Indicates SYSCLK on/off Status)
PLL Controller 1 Divider 4 Register (SYSCLK4)
PLL Controller 1 Divider 5 Register (SYSCLK5)
PLL Controller 1 Divider 6 Register (SYSCLK6)
Reserved
PLLDIV8
PLLDIV9
PLL Controller 1 Divider 8 Register (SYSCLK8)
PLL Controller 1 Divider 9 Register (SYSCLK9)
PLL2 Controller Registers
0x01C4 0C00
0x01C4 0D00
0x01C4 0D10
0x01C4 0D18
0x01C4 0D28
0x01C4 0D38
0x01C4 0D3C
PID
PLLCTL
PLLM
Peripheral ID Register
PLL Controller 2 PLL Control Register
PLL Controller 2 PLL Multiplier Control Register
PLL Controller 2 Divider 1 Register (PLL2_SYSCLK1 DDR2 PHY)
Reserved
PLLDIV1
–
PLLCMD
PLLSTAT
PLL Controller 2 Command Register
PLL Controller 2 Status Register (Shows PLLC2 PLLCTL Status)
PLL Controller 2 Clock Align Control Register
(Indicates Which SYSCLKs Need to be Aligned for Proper Device Operation)
0x01C4 0D40
0x01C4 0D44
ALNCTL
PLL Controller 2 PLLDIV Divider Ratio Change Status Register
(Indicates if SYSCLK Divide Ratio has been modified)
DCHANGE
0x01C4 0D48
CKEN
CKSTAT
SYSTAT
–
PLL Controller 2 Clock Enable Control Register
PLL Controller 2 Clock Status Register (For All Clocks Except SYSCLKx)
PLL Controller 2 SYSCLK Status Register (Indicates SYSCLK on/off Status)
Reserved
0x01C4 0D4C
0x01C4 0D50
0x01C4 0D54 - 0x01C4 0FFF
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6.5.3 Clock PLL Considerations With External Clock Sources
If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power
both the VCE6467T device and the external clock oscillator circuit. The minimum CLKIN rise and fall times
should also be observed. For the input clock timing requirements, see Section 6.5.5, Clock PLL Electrical
Data/Timing (Input and Output Clocks).
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock
source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 6.5.5, Clock
PLL Electrical Data/Timing (Input and Output Clocks).)
6.5.4 Output Clocks (CLKOUT0, AUDIO_CLK1, AUDIO_CLK0) - Clock Select Logic
The VCE6467T includes a selectable general-purpose clock output (CLKOUT0) [see Figure 6-12] and two
selectable audio output clocks (AUDIO_CLK0 and AUDIO_CLK1) for synchronizing external audio devices
with the on-chip system or video clocks [see Figure 6-13 and Figure 6-14]. The source for these output
clocks is controlled by the CLKCTL register (0x01C4 005C). For more detailed information on the CLKCTL
register, see Section 3.3.3, Clock and Oscillator Control.
CLKCTL.CLKOUT
AUX_MXI
1010
AUX_MXI/AUX_CLKIN
DEV_MXI/DEV_CLKIN
SYSCLK9
PLLDIV9 (/6 Prog)
PLLDIV8 (/8 Prog)
PLLDIV6 (/8 Prog)
PLLDIV5 (/8 Prog)
PLLDIV4 (/6 Prog)
PLLDIV3 (/4 Fixed)
1001
1000
0110
0101
0100
0011
0001
0000
SYSCLK8
SYSCLK6
SYSCLK5
SYSCLK4
CLKOUT0
SYSCLK3
AUXCLK
PLL Controller 1
Figure 6-12. CLKOUT0 Source Selection
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CLKCTL.AUD_CLK0
STC_CLKIN
1001
GP[4]/STC_CLKIN
AUX_MXI/AUX_CLKIN
VP_CLKIN3/TS1_CLKO
VP_CLKIN2
AUX_MXI
1000
0111
0110
0101
0100
0011
VP0_CLKIN3
VP0_CLKIN2
VP0_CLKIN1
VP0_CLKIN0
CRG1_VCXI
PINMUX0.AUDCK0
VP_CLKIN1
VP_CLKIN0
AUDIO_CLK0
GP[3]
1
0
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
CRG0_VCXI
AUXCLK
11x
10x
0010
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
PLL
Controller 1
0001
0000
DEV_MXI/DEV_CLKIN
Figure 6-13. AUDIO_CLK0 Source Selection
CLKCTL.AUD_CLK1
STC_CLKIN
1001
1000
0111
0110
0101
0100
0011
GP[4]/STC_CLKIN
AUX_MXI/AUX_CLKIN
VP_CLKIN3/TS1_CLKO
VP_CLKIN2
AUX_MXI
VP0_CLKIN3
VP0_CLKIN2
VP0_CLKIN1
VP0_CLKIN0
CRG1_VCXI
PINMUX0.AUDCK1
VP_CLKIN1
VP_CLKIN0
AUDIO_CLK1
GP[2]
1
0
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
CRG0_VCXI
AUXCLK
11x
10x
0010
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
PLL
Controller 1
0001
0000
DEV_MXI/DEV_CLKIN
Figure 6-14. AUDIO_CLK1 Source Selection
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6.5.5 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 6-12. Timing Requirements for DEV_MXI/DEV_CLKIN(1) (2) (3) (4) (see Figure 6-15)
-1G
NO.
UNIT
MIN
28.57
0.45C
0.45C
NOM
MAX
50
1
2
3
4
5
tc(DMXI)
tw(DMXIH)
tw(DMXIL)
tt(DMXI)
Cycle time, DEV_MXI/DEV_CLKIN
30.03
ns
ns
ns
ns
ns
Pulse duration, DEV_MXI/DEV_CLKIN high
Pulse duration, DEV_MXI/DEV_CLKIN low
Transition time, DEV_MXI/DEV_CLKIN
Period jitter, DEV_MXI/DEV_CLKIN
0.55C
0.55C
7
tJ(DMXI)
0.02C
(1) The DEV_MXI/DEV_CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the
specific range for CPU operating frequency. For example, for a -1G speed device with a 33.3-MHz DEV_CLKIN frequency, the PLL
multiply factor should be ≤ 30.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) For more details on the PLL multiplier factors, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (Literature Number
SPRUEP9).
(4) C = DEV_CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN frequency is 33.3 MHz, use C = 30.03 ns.
5
1
4
1
2
DEV_MXI/
DEV_CLKIN
3
4
Figure 6-15. DEV_MXI/DEV_CLKIN Timing
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Table 6-13. Timing Requirements for AUX_MXI/AUX_CLKIN (1) (2) (3) (see Figure 6-16)
-1G
NO.
UNIT
MIN
NOM
MAX
(4)
1
2
3
4
5
6
tc(AMXI)
Cycle time, AUX_MXI/AUX_CLKIN
41.6 or 20.83
ns
tw(AMXIH)
tw(AMXIL)
tt(AMXI)
tJ(AMXI)
Sf
Pulse duration, AUX_MXI/AUX_CLKIN high
Pulse duration, AUX_MXI/AUX_CLKIN low
Transition time, AUX_MXI/AUX_CLKIN
Period jitter, AUX_MXI/AUX_CLKIN
0.45C
0.45C
0.55C ns
0.55C ns
7
ns
0.02C ns
± 50 ppm
Frequency stability, AUX_MXI/AUX_CLKIN(4)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) For more details on the PLL, see the TMS320DM646x DMSoC Universal Serial Bus (USB) Controller User's Guide (Literature Number
SPRUER7).
(3) C = DEV_CLKIN cycle time in ns. For example, when AUX_MXI/AUX_CLKIN frequency is 24 MHz, use C = 41.6 ns and when
AUX_MXI/AUX_CLKIN frequency is 48 MHz, use C = 20.83 ns.
(4) If the USB is used, a 24-MHz, 50-ppm crystal is recommended.
5
1
4
1
2
AUX_MXI/
AUX_CLKIN
3
4
Figure 6-16. AUX_MXI/AUX_CLKIN Timing
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Table 6-14. Switching Characteristics Over Recommended Operating Conditions for CLKOUT0(1) (2)
(see Figure 6-17)
-1G
NO.
PARAMETER
UNIT
MIN
6.734
0.4P
MAX
296.296
0.6P
1
2
3
4
tc(CLKOUT0)
tw(CLKOUT0H)
tw(CLKOUT0L)
tt(CLKOUT0)
Cycle time, CLKOUT0
ns
ns
ns
ns
Pulse duration, CLKOUT0 high
Pulse duration, CLKOUT0 low
Transition time, CLKOUT0
0.4P
0.6P
0.05P
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/CLKOUT0 clock frequency in nanoseconds (ns). For example, when CLKOUT0 frequency is 33.3 MHz, use P = 30.03 ns.
2
4
1
CLKOUT0
(Divide-by-1)
3
4
Figure 6-17. CLKOUT0 Timing
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6.6 Enhanced Direct Memory Access (EDMA3) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the VCE6467T device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
•
•
Transfer to/from on-chip memories
–
–
–
ARM926 TCM
DSP L1D memory
DSP L2 memory
Transfer to/from external storage
–
–
–
–
DDR2 SDRAM
NAND flash
Asynchronous EMIF (EMIFA)
ATA
•
Transfer to/from peripherals/hosts
–
–
–
–
–
–
–
–
VLYNQ
HPI
McASP0/1
SPI
I2C
PWM0/1
UART0/1/2
PCI
The EDMA supports two addressing modes: constant addressing and increment addressing. On the
VCE6467T, constant addressing mode is not supported by any peripheral or internal memory. For more
information on these two addressing modes, see the TMS320DM646x DMSoC Enhanced Direct Memory
Access (EDMA) Controller User’s Guide (literature number SPRUEQ5).
The VCE6467T device supports a programmable default burst size feature. The default burst size of each
EDMA3 Transfer Controller (TC) is configured via the EDMA Transfer Controller Default Burst Size
Configuration register (EDMATCCFG). For more detailed information on the EDMATCCFG register, see
Section 3.6.2, Peripheral Selection After Device Reset.
6.6.1 EDMA3 Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 6-15 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the VCE6467T device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the TMS320DM646x DMSoC Enhanced
Direct Memory Access (EDMA) Controller User’s Guide (literature number SPRUEQ5)
Table 6-15. VCE6467T EDMA Channel Synchronization Events(1)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0-3
–
Reserved
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with
the transfer completion or alternate transfer completion events. For more detailed information on
EDMA event-transfer chaining, see the TMS320DM646x DMSoC Enhanced Direct Memory Access
(EDMA) Controller User's Guide (literature number SPRUEQ5).
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Table 6-15. VCE6467T EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
4
5
AXEVTE0
AXEVTO0
AXEVT0
AREVTE0
AREVTO0
AREVT0
AXEVTE1
AXEVTO1
AXEVT1
–
McASP0 Transmit Event Even
McASP0 Transmit Event Odd
McASP0 Transmit Event
McASP0 Receive Event Even
McASP0 Receive Event Odd
McASP0 Receive Event
McASP1 Transmit Event Even
McASP1 Transmit Event Odd
McASP1 Transmit Event
Reserved
6
7
8
9
10
11
12
13-15
16
17
18
19
20
21
22
23
24-27
28
29
30-31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54-56
57
58
SPIXEVT
SPIREVT
URXEVT0
UTXEVT0
URXEVT1
UTXEVT1
URXEVT2
UTXEVT2
–
SPI Transmit Event
SPI Receive Event
UART 0 Receive Event
UART 0 Transmit Event
UART 1 Receive Event
UART 1 Transmit Event
UART 2 Receive Event
UART 2 Transmit Event
Reserved
ICREVT
ICXEVT
–
I2C Receive Event
I2C Transmit Event
Reserved [Unused]
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPBNKINT0
GPBNKINT1
GPBNKINT2
GPIO 0 Interrupt Event
GPIO 1 Interrupt Event
GPIO 2 Interrupt Event
GPIO 3 Interrupt Event
GPIO 4 Interrupt Event
GPIO 5 Interrupt Event
GPIO 6 Interrupt Event
GPIO 7 Interrupt Event
GPIO Bank 0 Interrupt Event
GPIO Bank 1 Interrupt Event
GPIO Bank 2 Interrupt Event
CP_ECDCMP1 HDVICP1 ECDCMP Interrupt Event
CP_MC1
CP_BS1
CP_CALC1
CP_LPF1
TEVTL0
TEVTH0
TEVTL1
TEVTH1
PWM0
HDVICP1 MC Interrupt Event
HDVICP1 BS Interrupt Event
HDVICP1 CALC Interrupt Event
HDVICP1 LPF Interrupt Event
Timer 0 Event Low Interrupt
Timer 0 Event High Interrupt
Timer 1 Event Low Interrupt
Timer 1 Event High Interrupt
PWM 0 Interrupt Event
PWM1
PWM 1 Interrupt Event
–
Reserved
CP_ME0
CP_IPE0
HDVICP0 ME Interrupt Event
HDVICP0 IPE Interrupt Event
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Table 6-15. VCE6467T EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
59
60
61
62
63
CP_ECDCMP0 HDVICP0 ECDCMP Interrupt Event
CP_MC0
CP_BS0
HDVICP0 MC Interrupt Event
HDVICP0 BS Interrupt Event
HDVICP0 CALC Interrupt Event
HDVICP0 LPF Interrupt Event
CP_CALC0
CP_LPF0
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6.6.2 EDMA Peripheral Register Description(s)
Table 6-16 lists the EDMA registers, their corresponding acronyms, and VCE6467T device memory
locations.
Table 6-16. VCE6467T EDMA Registers
HEX ADDRESS RANGE
ACRONYM
Channel Controller Registers
REGISTER NAME
0x01C0 0000
0x01C0 0004
PID
CCCFG
–
Peripheral Identification Register
EDMA3CC Configuration Register
Reserved
0x01C0 0008 - 0x01C0 00FF
Global Registers
0x01C0 0100
0x01C0 0104
0x01C0 0108
0x01C0 010C
0x01C0 0110
0x01C0 0114
0x01C0 0118
0x01C0 011C
0x01C0 0120
0x01C0 0124
0x01C0 0128
0x01C0 012C
0x01C0 0130
0x01C0 0134
0x01C0 0138
0x01C0 013C
0x01C0 0140
0x01C0 0144
0x01C0 0148
0x01C0 014C
0x01C0 0150
0x01C0 0154
0x01C0 0158
0x01C0 015C
0x01C0 0160
0x01C0 0164
0x01C0 0168
0x01C0 016C
0x01C0 0170
0x01C0 0174
0x01C0 0178
0x01C0 017C
0x01C0 0180
0x01C0 0184
0x01C0 0188
0x01C0 018C
0x01C0 0190
0x01C0 0194
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP12
DCHMAP13
DCHMAP14
DCHMAP15
DCHMAP16
DCHMAP17
DCHMAP18
DCHMAP19
DCHMAP20
DCHMAP21
DCHMAP22
DCHMAP23
DCHMAP24
DCHMAP25
DCHMAP26
DCHMAP27
DCHMAP28
DCHMAP29
DCHMAP30
DCHMAP31
DCHMAP32
DCHMAP33
DCHMAP34
DCHMAP35
DCHMAP36
DCHMAP37
DMA Channel 0 Mapping to PaRAM Register
DMA Channel 1 Mapping to PaRAM Register
DMA Channel 2 Mapping to PaRAM Register
DMA Channel 3 Mapping to PaRAM Register
DMA Channel 4 Mapping to PaRAM Register
DMA Channel 5 Mapping to PaRAM Register
DMA Channel 6 Mapping to PaRAM Register
DMA Channel 7 Mapping to PaRAM Register
DMA Channel 8 Mapping to PaRAM Register
DMA Channel 9 Mapping to PaRAM Register
DMA Channel 10 Mapping to PaRAM Register
DMA Channel 11 Mapping to PaRAM Register
DMA Channel 12 Mapping to PaRAM Register
DMA Channel 13 Mapping to PaRAM Register
DMA Channel 14 Mapping to PaRAM Register
DMA Channel 15 Mapping to PaRAM Register
DMA Channel 16 Mapping to PaRAM Register
DMA Channel 17 Mapping to PaRAM Register
DMA Channel 18 Mapping to PaRAM Register
DMA Channel 19 Mapping to PaRAM Register
DMA Channel 20 Mapping to PaRAM Register
DMA Channel 21 Mapping to PaRAM Register
DMA Channel 22 Mapping to PaRAM Register
DMA Channel 23 Mapping to PaRAM Register
DMA Channel 24 Mapping to PaRAM Register
DMA Channel 25 Mapping to PaRAM Register
DMA Channel 26 Mapping to PaRAM Register
DMA Channel 27 Mapping to PaRAM Register
DMA Channel 28 Mapping to PaRAM Register
DMA Channel 29 Mapping to PaRAM Register
DMA Channel 30 Mapping to PaRAM Register
DMA Channel 31 Mapping to PaRAM Register
DMA Channel 32 Mapping to PaRAM Register
DMA Channel 33 Mapping to PaRAM Register
DMA Channel 34 Mapping to PaRAM Register
DMA Channel 35 Mapping to PaRAM Register
DMA Channel 36 Mapping to PaRAM Register
DMA Channel 37 Mapping to PaRAM Register
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DCHMAP38
DCHMAP39
DCHMAP40
DCHMAP41
DCHMAP42
DCHMAP43
DCHMAP44
DCHMAP45
DCHMAP46
DCHMAP47
DCHMAP48
DCHMAP49
DCHMAP50
DCHMAP51
DCHMAP52
DCHMAP53
DCHMAP54
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DCHMAP59
DCHMAP60
DCHMAP61
DCHMAP62
DCHMAP63
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
–
REGISTER NAME
DMA Channel 38 Mapping to PaRAM Register
0x01C0 0198
0x01C0 019C
0x01C0 01A0
0x01C0 01A4
0x01C0 01A8
0x01C0 01AC
0x01C0 01B0
0x01C0 01B4
0x01C0 01B8
0x01C0 01BC
0x01C0 01C0
0x01C0 01C4
0x01C0 01C8
0x01C0 01CC
0x01C0 01D0
0x01C0 01D4
0x01C0 01D8
0x01C0 01DC
0x01C0 01E0
0x01C0 01E4
0x01C0 01E8
0x01C0 01EC
0x01C0 01F0
0x01C0 01F4
0x01C0 01F8
0x01C0 01FC
0x01C0 0200
DMA Channel 39 Mapping to PaRAM Register
DMA Channel 40 Mapping to PaRAM Register
DMA Channel 41 Mapping to PaRAM Register
DMA Channel 42 Mapping to PaRAM Register
DMA Channel 43 Mapping to PaRAM Register
DMA Channel 44 Mapping to PaRAM Register
DMA Channel 45 Mapping to PaRAM Register
DMA Channel 46 Mapping to PaRAM Register
DMA Channel 47 Mapping to PaRAM Register
DMA Channel 48 Mapping to PaRAM Register
DMA Channel 49 Mapping to PaRAM Register
DMA Channel 50 Mapping to PaRAM Register
DMA Channel 51 Mapping to PaRAM Register
DMA Channel 52 Mapping to PaRAM Register
DMA Channel 53 Mapping to PaRAM Register
DMA Channel 54 Mapping to PaRAM Register
DMA Channel 55 Mapping to PaRAM Register
DMA Channel 56 Mapping to PaRAM Register
DMA Channel 57 Mapping to PaRAM Register
DMA Channel 58 Mapping to PaRAM Register
DMA Channel 59 Mapping to PaRAM Register
DMA Channel 60 Mapping to PaRAM Register
DMA Channel 61 Mapping to PaRAM Register
DMA Channel 62 Mapping to PaRAM Register
DMA Channel 63 Mapping to PaRAM Register
QDMA Channel 0 Mapping to PaRAM Register
QDMA Channel 1 Mapping to PaRAM Register
QDMA Channel 2 Mapping to PaRAM Register
QDMA Channel 3 Mapping to PaRAM Register
QDMA Channel 4 Mapping to PaRAM Register
QDMA Channel 5 Mapping to PaRAM Register
QDMA Channel 6 Mapping to PaRAM Register
QDMA Channel 7 Mapping to PaRAM Register
Reserved
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0220 - 0x01C0 023F
0x01C0 0240
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
DMAQNUM4
DMAQNUM5
DMAQNUM6
DMAQNUM7
QDMAQNUM
–
DMA Queue Number Register 0 (Channels 00 to 07)
DMA Queue Number Register 1 (Channels 08 to 15)
DMA Queue Number Register 2 (Channels 16 to 23)
DMA Queue Number Register 3 (Channels 24 to 31)
DMA Queue Number Register 4 (Channels 32 to 39)
DMA Queue Number Register 5 (Channels 40 to 47)
DMA Queue Number Register 6 (Channels 48 to 55)
DMA Queue Number Register 7 (Channels 56 to 63)
CC QDMA Queue Number
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0250
0x01C0 0254
0x01C0 0258
0x01C0 025C
0x01C0 0260
0x01C0 0264 - 0x01C0 0283
0x01C0 0284
Reserved
QUEPRI
Queue Priority Register
0x01C0 0288 - 0x01C0 02FF
–
Reserved
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C0 0300
ACRONYM
EMR
REGISTER NAME
Event Missed Register
0x01C0 0304
EMRH
EMCR
EMCRH
QEMR
QEMCR
CCERR
CCERRCLR
EEVAL
–
Event Missed Register High
0x01C0 0308
Event Missed Clear Register
0x01C0 030C
0x01C0 0310
Event Missed Clear Register High
QDMA Event Missed Register
0x01C0 0314
QDMA Event Missed Clear Register
EDMA3CC Error Register
0x01C0 0318
0x01C0 031C
0x01C0 0320
EDMA3CC Error Clear Register
Error Evaluate Register
0x01C0 0324 - 0x01C0 033F
0x01C0 0340
Reserved
DRAE0
DRAEH0
DRAE1
DRAEH1
–
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register High for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register High for Region 1
Reserved
0x01C0 0344
0x01C0 0348
0x01C0 034C
0x01C0 0350- 0x01C0 035F
0x01C0 0360
DRAE4
DRAEH4
DRAE5
DRAEH5
DRAE6
DRAEH6
DRAE7
DRAEH7
QRAE0
QRAE1
–
DMA Region Access Enable Register for Region 4
DMA Region Access Enable Register High for Region 4
DMA Region Access Enable Register for Region 5
DMA Region Access Enable Register High for Region 5
DMA Region Access Enable Register for Region 6
DMA Region Access Enable Register High for Region 6
DMA Region Access Enable Register for Region 7
DMA Region Access Enable Register High for Region 7
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
Reserved
0x01C0 0364
0x01C0 0368
0x01C0 036C
0x01C0 0370
0x01C0 0374
0x01C0 0378
0x01C0 037C
0x01C0 0380
0x01C0 0384
0x01C0 0388 - 0x01C0 038F
0x01C0 0390
QRAE4
QRAE5
QRAE6
QRAE7
–
QDMA Region Access Enable Register for Region 4
QDMA Region Access Enable Register for Region 5
QDMA Region Access Enable Register for Region 6
QDMA Region Access Enable Register for Region 7
Reserved
0x01C0 0394
0x01C0 0398
0x01C0 039C
0x01C0 03A0 - 0x01C0 03FF
0x01C0 0400
Q0E0
Event Q0 Entry 0 Register
0x01C0 0404
Q0E1
Event Q0 Entry 1 Register
0x01C0 0408
Q0E2
Event Q0 Entry 2 Register
0x01C0 040C
0x01C0 0410
Q0E3
Event Q0 Entry 3 Register
Q0E4
Event Q0 Entry 4 Register
0x01C0 0414
Q0E5
Event Q0 Entry 5 Register
0x01C0 0418
Q0E6
Event Q0 Entry 6 Register
0x01C0 041C
0x01C0 0420
Q0E7
Event Q0 Entry 7 Register
Q0E8
Event Q0 Entry 8 Register
0x01C0 0424
Q0E9
Event Q0 Entry 9 Register
0x01C0 0428
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Event Q0 Entry 10 Register
0x01C0 042C
0x01C0 0430
Event Q0 Entry 11 Register
Event Q0 Entry 12 Register
0x01C0 0434
Event Q0 Entry 13 Register
0x01C0 0438
Event Q0 Entry 14 Register
0x01C0 043C
Event Q0 Entry 15 Register
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
Q1E0
Q1E1
Q1E2
Q1E3
Q1E4
Q1E5
Q1E6
Q1E7
Q1E8
Q1E9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Q2E1
Q2E2
Q2E3
Q2E4
Q2E5
Q2E6
Q2E7
Q2E8
Q2E9
Q2E10
Q2E11
Q2E12
Q2E13
Q2E14
Q2E15
Q3E0
Q3E1
Q3E2
Q3E3
Q3E4
Q3E5
Q3E6
Q3E7
Q3E8
Q3E9
Q3E10
Q3E11
Q3E12
Q3E13
Q3E14
REGISTER NAME
0x01C0 0440
0x01C0 0444
0x01C0 0448
0x01C0 044C
0x01C0 0450
0x01C0 0454
0x01C0 0458
0x01C0 045C
0x01C0 0460
0x01C0 0464
0x01C0 0468
0x01C0 046C
0x01C0 0470
0x01C0 0474
0x01C0 0478
0x01C0 047C
0x01C0 0480
0x01C0 0484
0x01C0 0488
0x01C0 048C
0x01C0 0490
0x01C0 0494
0x01C0 0498
0x01C0 049C
0x01C0 04A0
0x01C0 04A4
0x01C0 04A8
0x01C0 04AC
0x01C0 04B0
0x01C0 04B4
0x01C0 04B8
0x01C0 04BC
0x01C0 04C0
0x01C0 04C4
0x01C0 04C8
0x01C0 04CC
0x01C0 04D0
0x01C0 04D4
0x01C0 04D8
0x01C0 04DC
0x01C0 04E0
0x01C0 04E4
0x01C0 04E8
0x01C0 04EC
0x01C0 04F0
0x01C0 04F4
0x01C0 04F8
Event Q1 Entry 0 Register
Event Q1 Entry 1 Register
Event Q1 Entry 2 Register
Event Q1 Entry 3 Register
Event Q1 Entry 4 Register
Event Q1 Entry 5 Register
Event Q1 Entry 6 Register
Event Q1 Entry 7 Register
Event Q1 Entry 8 Register
Event Q1 Entry 9 Register
Event Q1 Entry 10 Register
Event Q1 Entry 11 Register
Event Q1 Entry 12 Register
Event Q1 Entry 13 Register
Event Q1 Entry 14 Register
Event Q1 Entry 15 Register
Event Q2 Entry 0 Register
Event Q2 Entry 1 Register
Event Q2 Entry 2 Register
Event Q2 Entry 3 Register
Event Q2 Entry 4 Register
Event Q2 Entry 5 Register
Event Q2 Entry 6 Register
Event Q2 Entry 7 Register
Event Q2 Entry 8 Register
Event Q2 Entry 9 Register
Event Q2 Entry 10 Register
Event Q2 Entry 11 Register
Event Q2 Entry 12 Register
Event Q2 Entry 13 Register
Event Q2 Entry 14 Register
Event Q2 Entry 15 Register
Event Q3 Entry 0 Register
Event Q3 Entry 1 Register
Event Q3 Entry 2 Register
Event Q3 Entry 3 Register
Event Q3 Entry 4 Register
Event Q3 Entry 5 Register
Event Q3 Entry 6 Register
Event Q3 Entry 7 Register
Event Q3 Entry 8 Register
Event Q3 Entry 9 Register
Event Q3 Entry 10 Register
Event Q3 Entry 11 Register
Event Q3 Entry 12 Register
Event Q3 Entry 13 Register
Event Q3 Entry 14 Register
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C0 04FC
ACRONYM
Q3E15
–
REGISTER NAME
Event Q3 Entry 15 Register
Reserved
0x01C0 0500 - 0x01C0 05FF
0x01C0 0600
QSTAT0
QSTAT1
QSTAT2
QSTAT3
–
Queue 0 Status Register
Queue 1 Status Register
Queue 2 Status Register
Queue 3 Status Register
Reserved
0x01C0 0604
0x01C0 0608
0x01C0 060C
0x01C0 0610 - 0x01C0 061F
0x01C0 0620
QWMTHRA
–
Queue Watermark Threshold A Register for Q[3:0]
Reserved
0x01C0 0624 - 0x01C0 063F
0x01C0 0640
CCSTAT
–
EDMA3CC Status Register
Reserved
0x01C0 0644 - 0x01C0 0FFF
Global Channel Registers
0x01C0 1000
0x01C0 1004
0x01C0 1008
0x01C0 100C
0x01C0 1010
0x01C0 1014
0x01C0 1018
0x01C0 101C
0x01C0 1020
0x01C0 1024
0x01C0 1028
0x01C0 102C
0x01C0 1030
0x01C0 1034
0x01C0 1038
0x01C0 103C
0x01C0 1040
0x01C0 1044
0x01C0 1048 - 0x01C0 104F
0x01C0 1050
0x01C0 1054
0x01C0 1058
0x01C0 105C
0x01C0 1060
0x01C0 1064
0x01C0 1068
0x01C0 106C
0x01C0 1070
0x01C0 1074
0x01C0 1078
0x01C0 107C - 0x01C0 107F
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
–
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QEESR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
QSER
QSECR
–
REGISTER NAME
0x01C0 1090
0x01C0 1094
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 1098 - 0x01C0 1FFF
Shadow Region 0 Channel Registers
0x01C0 2000
0x01C0 2004
ER
ERH
Event Register
Event Register High
0x01C0 2008
ECR
Event Clear Register
0x01C0 200C
0x01C0 2010
ECRH
ESR
Event Clear Register High
Event Set Register
0x01C0 2014
ESRH
CER
Event Set Register High
0x01C0 2018
Chained Event Register
0x01C0 201C
0x01C0 2020
CERH
EER
Chained Event Register High
Event Enable Register
0x01C0 2024
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
0x01C0 2028
0x01C0 202C
0x01C0 2030
0x01C0 2034
0x01C0 2038
0x01C0 203C
0x01C0 2040
SERH
SECR
SECRH
–
0x01C0 2044
0x01C0 2048 - 0x01C0 204F
0x01C0 2050
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01C0 2054
IERH
IECR
IECRH
IESR
IESRH
IPR
0x01C0 2058
0x01C0 205C
0x01C0 2060
0x01C0 2064
0x01C0 2068
0x01C0 206C
0x01C0 2070
IPRH
ICR
0x01C0 2074
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01C0 2078
0x01C0 207C - 0x01C0 207F
0x01C0 2080
QER
QDMA Event Register
0x01C0 2084
QEER
QEECR
QEESR
QSER
QSECR
–
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
0x01C0 2098 - 0x01C0 21FF
Shadow Region 1 Channel Registers
0x01C0 2200
0x01C0 2204
0x01C0 2208
0x01C0 220C
ER
ERH
ECR
ECRH
Event Register
Event Register High
Event Clear Register
Event Clear Register High
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C0 2210
ACRONYM
ESR
REGISTER NAME
Event Set Register
0x01C0 2214
ESRH
CER
Event Set Register High
0x01C0 2218
Chained Event Register
0x01C0 221C
CERH
EER
Chained Event Register High
Event Enable Register
0x01C0 2220
0x01C0 2224
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
0x01C0 2228
0x01C0 222C
0x01C0 2230
0x01C0 2234
0x01C0 2238
0x01C0 223C
SERH
SECR
SECRH
–
0x01C0 2240
0x01C0 2244
0x01C0 2248 - 0x01C0 224F
0x01C0 2250
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01C0 2254
IERH
IECR
IECRH
IESR
IESRH
IPR
0x01C0 2258
0x01C0 225C
0x01C0 2260
0x01C0 2264
0x01C0 2268
0x01C0 226C
IPRH
ICR
0x01C0 2270
0x01C0 2274
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01C0 2278
0x01C0 227C - 0x01C0 227F
0x01C0 2280
QER
QDMA Event Register
0x01C0 2284
QEER
QEECR
QEESR
QSER
QSECR
–
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 2298 - 0x01C0 23FF
0x01C0 2400 - 0x01C0 25FF
0x01C0 2600 - 0x01C0 27FF
–
Reserved
–
Reserved
Shadow Region 4 Channel Registers
0x01C0 2800
0x01C0 2804
0x01C0 2808
0x01C0 280C
0x01C0 2810
0x01C0 2814
0x01C0 2818
0x01C0 281C
0x01C0 2820
0x01C0 2824
ER
Event Register
ERH
Event Register High
ECR
Event Clear Register
Event Clear Register High
Event Set Register
ECRH
ESR
ESRH
CER
Event Set Register High
Chained Event Register
Chained Event Register High
Event Enable Register
Event Enable Register High
CERH
EER
EERH
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SPRS690–MARCH 2011
Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
EECR
EECRH
EESR
EESRH
SER
REGISTER NAME
0x01C0 2828
0x01C0 282C
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
0x01C0 2830
0x01C0 2834
0x01C0 2838
0x01C0 283C
SERH
SECR
SECRH
–
0x01C0 2840
0x01C0 2844
0x01C0 2848 - 0x01C0 284F
0x01C0 2850
IER
Interrupt Enable Register
0x01C0 2854
IERH
IECR
IECRH
IESR
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01C0 2858
0x01C0 285C
0x01C0 2860
0x01C0 2864
IESRH
IPR
0x01C0 2868
0x01C0 286C
IPRH
ICR
0x01C0 2870
0x01C0 2874
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01C0 2878
0x01C0 287C - 0x01C0 287F
0x01C0 2880
QER
QDMA Event Register
0x01C0 2884
QEER
QEECR
QEESR
QSER
QSECR
–
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2888
0x01C0 288C
0x01C0 2890
0x01C0 2894
0x01C0 2898 - 0x01C0 29FF
Shadow Region 5 Channel Registers
0x01C0 2A00
0x01C0 2A04
0x01C0 2A08
0x01C0 2A0C
0x01C0 2A10
0x01C0 2A14
0x01C0 2A18
0x01C0 2A1C
0x01C0 2A20
0x01C0 2A24
0x01C0 2A28
0x01C0 2A2C
0x01C0 2A30
0x01C0 2A34
0x01C0 2A38
0x01C0 2A3C
0x01C0 2A40
0x01C0 2A44
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
SERH
SECR
SECRH
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C0 2A48 - 0x01C0 2A4F
0x01C0 2A50
ACRONYM
–
REGISTER NAME
Reserved
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x01C0 2A54
IERH
IECR
IECRH
IESR
IESRH
IPR
0x01C0 2A58
0x01C0 2A5C
0x01C0 2A60
0x01C0 2A64
0x01C0 2A68
0x01C0 2A6C
IPRH
ICR
0x01C0 2A70
0x01C0 2A74
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01C0 2A78
0x01C0 2A7C - 0x01C0 2A7F
0x01C0 2A80
QER
QDMA Event Register
0x01C0 2A84
QEER
QEECR
QEESR
QSER
QSECR
–
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2A88
0x01C0 2A8C
0x01C0 2A90
0x01C0 2A94
0x01C0 2A98 - 0x01C0 2BFF
Shadow Region 6 Channel Registers
0x01C0 2C00
0x01C0 2C04
0x01C0 2C08
0x01C0 2C0C
0x01C0 2C10
0x01C0 2C14
0x01C0 2C18
0x01C0 2C1C
0x01C0 2C20
0x01C0 2C24
0x01C0 2C28
0x01C0 2C2C
0x01C0 2C30
0x01C0 2C34
0x01C0 2C38
0x01C0 2C3C
0x01C0 2C40
0x01C0 2C44
0x01C0 2C48 - 0x01C0 2C4F
0x01C0 2C50
0x01C0 2C54
0x01C0 2C58
0x01C0 2C5C
0x01C0 2C60
0x01C0 2C64
0x01C0 2C68
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
–
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
IERH
IECR
IECRH
IESR
IESRH
IPR
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SPRS690–MARCH 2011
Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
IPRH
ICR
REGISTER NAME
0x01C0 2C6C
0x01C0 2C70
Interrupt Pending Register High
Interrupt Clear Register
0x01C0 2C74
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x01C0 2C78
0x01C0 2C7C - 0x01C0 2C7F
0x01C0 2C80
QER
QDMA Event Register
0x01C0 2C84
QEER
QEECR
QEESR
QSER
QSECR
–
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2C88
0x01C0 2C8C
0x01C0 2C90
0x01C0 2C94
0x01C0 2C98 - 0x01C0 2DFF
Shadow Region 7 Channel Registers
0x01C0 2E00
0x01C0 2E04
0x01C0 2E08
0x01C0 2E0C
0x01C0 2E10
0x01C0 2E14
0x01C0 2E18
0x01C0 2E1C
0x01C0 2E20
0x01C0 2E24
0x01C0 2E28
0x01C0 2E2C
0x01C0 2E30
0x01C0 2E34
0x01C0 2E38
0x01C0 2E3C
0x01C0 2E40
0x01C0 2E44
0x01C0 2E48 - 0x01C0 2E4F
0x01C0 2E50
0x01C0 2E54
0x01C0 2E58
0x01C0 2E5C
0x01C0 2E60
0x01C0 2E64
0x01C0 2E68
0x01C0 2E6C
0x01C0 2E70
0x01C0 2E74
0x01C0 2E78
0x01C0 2E7C - 0x01C0 2E7F
0x01C0 2E80
0x01C0 2E84
0x01C0 2E88
ER
ERH
Event Register
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
–
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
–
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C0 2E8C
ACRONYM
REGISTER NAME
QEESR
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x01C0 2E90
QSER
0x01C0 2E94
QSECR
0x01C0 2E98 - 0x01C0 2FFF
0x01C0 3000 - 0x01C0 3FFF
0x01C0 4000 - 0x01C0 7FFF
0x01C0 8000 - 0x01C0 FFFF
–
–
–
–
Reserved
Parameter Set RAM (see Table 6-17)
Reserved
Transfer Controller 0 Registers
0x01C1 0000
0x01C1 0004
PID
TCCFG
–
Peripheral Identification Register
EDMA3 TC0 Configuration Register
Reserved
0x01C1 0008 - 0x01C1 00FF
0x01C1 0100
TCSTAT
–
EDMA3 TC0 Channel Status Register
Reserved
0x01C1 0104 - 0x01C1 0113
0x01C1 0114 - 0x01C1 011F
0x01C1 0120
–
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
–
EDMA3 TC0 Error Status Register
EDMA3 TC0 Error Enable Register
EDMA3 TC0 Error Clear Register
EDMA3 TC0 Error Details Register
EDMA3 TC0 Error Interrupt Command Register
Reserved
0x01C1 0124
0x01C1 0128
0x01C1 012C
0x01C1 0130
0x01C1 0134 - 0x01C1 013F
0x01C1 0140
RDRATE
–
EDMA3 TC0 Read Command Rate Register
Reserved
0x01C1 0144 - 0x01C1 01FF
0x01C1 0200 - 0x01C1 023F
0x01C1 0240
–
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
–
EDMA3 TC0 Source Active Options Register
EDMA3 TC0 Source Active Source Address Register
EDMA3 TC0 Source Active Count Register
EDMA3 TC0 Source Active Destination Address Register
EDMA3 TC0 Source Active B-Index Register
EDMA3 TC0 Source Active Memory Protection Proxy Register
EDMA3 TC0 Source Active Count Reload Register
0x01C1 0244
0x01C1 0248
0x01C1 024C
0x01C1 0250
0x01C1 0254
0x01C1 0258
0x01C1 025C
EDMA3 TC0 Source Active Source Address B-Reference Register
EDMA3 TC0 Source Active Destination Address B-Reference Register
Reserved
0x01C1 0260
0x01C1 0264 - 0x01C1 027F
0x01C1 0280
DFCNTRLD
DFSRCBREF
EDMA3 TC0 Destination FIFO Set Count Reload Register
EDMA3 TC0 Destination FIFO Set Source Address B-Reference Register
0x01C1 0284
EDMA3 TC0 Destination FIFO Set Destination Address B-Reference
Register
0x01C1 0288
DFDSTBREF
0x01C1 028C - 0x01C1 02FF
0x01C1 0300
–
Reserved
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
–
EDMA3 TC0 Destination FIFO Options Register 0
EDMA3 TC0 Destination FIFO Source Address Register 0
EDMA3 TC0 Destination FIFO Count Register 0
EDMA3 TC0 Destination FIFO Destination Address Register 0
EDMA3 TC0 Destination FIFO B-Index Register 0
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01C1 0304
0x01C1 0308
0x01C1 030C
0x01C1 0310
0x01C1 0314
0x01C1 0318 - 0x01C1 033F
0x01C1 0340
DFOPT1
DFSRC1
DFCNT1
EDMA3 TC0 Destination FIFO Options Register 1
EDMA3 TC0 Destination FIFO Source Address Register 1
EDMA3 TC0 Destination FIFO Count Register 1
0x01C1 0344
0x01C1 0348
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SPRS690–MARCH 2011
Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DFDST1
DFBIDX1
DFMPPRXY1
–
REGISTER NAME
EDMA3 TC0 Destination FIFO Destination Address Register 1
0x01C1 034C
0x01C1 0350
EDMA3 TC0 Destination FIFO B-Index Register 1
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01C1 0354
0x01C1 0358 - 0x01C1 037F
0x01C1 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
–
EDMA3 TC0 Destination FIFO Options Register 2
EDMA3 TC0 Destination FIFO Source Address Register 2
EDMA3 TC0 Destination FIFO Count Register 2
EDMA3 TC0 Destination FIFO Destination Address Register 2
EDMA3 TC0 Destination FIFO B-Index Register 2
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01C1 0384
0x01C1 0388
0x01C1 038C
0x01C1 0390
0x01C1 0394
0x01C1 0398 - 0x01C1 03BF
0x01C1 03C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
–
EDMA3 TC0 Destination FIFO Options Register 3
EDMA3 TC0 Destination FIFO Source Address Register 3
EDMA3 TC0 Destination FIFO Count Register 3
EDMA3 TC0 Destination FIFO Destination Address Register 3
EDMA3 TC0 Destination FIFO B-Index Register 3
EDMA3 TC0 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01C1 03C4
0x01C1 03C8
0x01C1 03CC
0x01C1 03D0
0x01C1 03D4
0x01C1 03D8 - 0x01C1 03FF
Transfer Controller 1 Registers
0x01C1 0400
0x01C1 0404
PID
TCCFG
–
Peripheral Identification Register
EDMA3 TC1 Configuration Register
Reserved
0x01C1 0408 - 0x01C1 04FF
0x01C1 0500
TCSTAT
–
EDMA3 TC1 Channel Status Register
Reserved
0x01C1 0504 - 0x01C1 0513
0x01C1 0514 - 0x01C1 051F
0x01C1 0520
–
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
–
EDMA3 TC1 Error Status Register
0x01C1 0524
EDMA3 TC1 Error Enable Register
EDMA3 TC1 Error Clear Register
0x01C1 0528
0x01C1 052C
EDMA3 TC1 Error Details Register
EDMA3 TC1 Error Interrupt Command Register
Reserved
0x01C1 0530
0x01C1 0534 - 0x01C1 053F
0x01C1 0540
RDRATE
–
EDMA3 TC1 Read Command Rate Register
Reserved
0x01C1 0544 - 0x01C1 05FF
0x01C1 0600 - 0x01C1 063F
0x01C1 0640
–
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
–
EDMA3 TC1 Source Active Options Register
EDMA3 TC1 Source Active Source Address Register
EDMA3 TC1 Source Active Count Register
EDMA3 TC1 Source Active Destination Address Register
EDMA3 TC1 Source Active B-Index Register
EDMA3 TC1 Source Active Memory Protection Proxy Register
EDMA3 TC1 Source Active Count Reload Register
EDMA3 TC1 Source Active Source Address B-Reference Register
EDMA3 TC1 Source Active Destination Address B-Reference Register
Reserved
0x01C1 0644
0x01C1 0648
0x01C1 064C
0x01C1 0650
0x01C1 0654
0x01C1 0658
0x01C1 065C
0x01C1 0660
0x01C1 0664 - 0x01C1 067F
0x01C1 0680
DFCNTRLD
DFSRCBREF
EDMA3 TC1 Destination FIFO Set Count Reload Register
EDMA3 TC1 Destination FIFO Set Source Address B-Reference Register
0x01C1 0684
EDMA3 TC1 Destination FIFO Set Destination Address B-Reference
Register
0x01C1 0688
DFDSTBREF
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C1 068C - 0x01C1 06FF
0x01C1 0700
ACRONYM
–
REGISTER NAME
Reserved
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
–
EDMA3 TC1 Destination FIFO Options Register 0
EDMA3 TC1 Destination FIFO Source Address Register 0
EDMA3 TC1 Destination FIFO Count Register 0
EDMA3 TC1 Destination FIFO Destination Address Register 0
EDMA3 TC1 Destination FIFO B-Index Register 0
0x01C1 0704
0x01C1 0708
0x01C1 070C
0x01C1 0710
0x01C1 0714
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01C1 0718 - 0x01C1 073F
0x01C1 0740
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
–
EDMA3 TC1 Destination FIFO Options Register 1
EDMA3 TC1 Destination FIFO Source Address Register 1
EDMA3 TC1 Destination FIFO Count Register 1
EDMA3 TC1 Destination FIFO Destination Address Register 1
EDMA3 TC1 Destination FIFO B-Index Register 1
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01C1 0744
0x01C1 0748
0x01C1 074C
0x01C1 0750
0x01C1 0754
0x01C1 0758 - 0x01C1 077F
0x01C1 0780
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
–
EDMA3 TC1 Destination FIFO Options Register 2
EDMA3 TC1 Destination FIFO Source Address Register 2
EDMA3 TC1 Destination FIFO Count Register 2
EDMA3 TC1 Destination FIFO Destination Address Register 2
EDMA3 TC1 Destination FIFO B-Index Register 2
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01C1 0784
0x01C1 0788
0x01C1 078C
0x01C1 0790
0x01C1 0794
0x01C1 0798 - 0x01C1 07BF
0x01C1 07C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
–
EDMA3 TC1 Destination FIFO Options Register 3
EDMA3 TC1 Destination FIFO Source Address Register 3
EDMA3 TC1 Destination FIFO Count Register 3
EDMA3 TC1 Destination FIFO Destination Address Register 3
EDMA3 TC1 Destination FIFO B-Index Register 3
EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01C1 07C4
0x01C1 07C8
0x01C1 07CC
0x01C1 07D0
0x01C1 07D4
0x01C1 07D8 - 0x01C1 07FF
Transfer Controller 2 Registers
0x01C1 0800
0x01C1 0804
PID
TCCFG
–
Peripheral Identification Register
EDMA3 TC2 Configuration Register
Reserved
0x01C1 0808 - 0x01C1 08FF
0x01C1 0900
TCSTAT
–
EDMA3 TC2 Channel Status Register
Reserved
0x01C1 0904 - 0x01C1 0913
0x01C1 0914 - 0x01C1 091F
0x01C1 0920
–
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
–
EDMA3 TC2 Error Status Register
EDMA3 TC2 Error Enable Register
EDMA3 TC2 Error Clear Register
EDMA3 TC2 Error Details Register
EDMA3 TC2 Error Interrupt Command Register
Reserved
0x01C1 0924
0x01C1 0928
0x01C1 092C
0x01C1 0930
0x01C1 0934 - 0x01C1 093F
0x01C1 0940
RDRATE
–
EDMA3 TC2 Read Command Rate Register
Reserved
0x01C1 0944 - 0x01C1 09FF
0x01C1 0A00 - 0x01C1 0A3F
0x01C1 0A40
–
Reserved
SAOPT
SASRC
EDMA3 TC2 Source Active Options Register
EDMA3 TC2 Source Active Source Address Register
0x01C1 0A44
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
SACNT
REGISTER NAME
EDMA3 TC2 Source Active Count Register
0x01C1 0A48
0x01C1 0A4C
SADST
EDMA3 TC2 Source Active Destination Address Register
EDMA3 TC2 Source Active B-Index Register
0x01C1 0A50
SABIDX
0x01C1 0A54
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
–
EDMA3 TC2 Source Active Memory Protection Proxy Register
EDMA3 TC2 Source Active Count Reload Register
EDMA3 TC2 Source Active Source Address B-Reference Register
EDMA3 TC2 Source Active Destination Address B-Reference Register
Reserved
0x01C1 0A58
0x01C1 0A5C
0x01C1 0A60
0x01C1 0A64 - 0x01C1 0A7F
0x01C1 0A80
DFCNTRLD
DFSRCBREF
EDMA3 TC2 Destination FIFO Set Count Reload Register
EDMA3 TC2 Destination FIFO Set Source Address B-Reference Register
0x01C1 0A84
EDMA3 TC2 Destination FIFO Set Destination Address B-Reference
Register
0x01C1 0A88
DFDSTBREF
0x01C1 0A8C - 0x01C1 0AFF
0x01C1 0B00
–
Reserved
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
–
EDMA3 TC2 Destination FIFO Options Register 0
EDMA3 TC2 Destination FIFO Source Address Register 0
EDMA3 TC2 Destination FIFO Count Register 0
EDMA3 TC2 Destination FIFO Destination Address Register 0
EDMA3 TC2 Destination FIFO B-Index Register 0
EDMA3 TC2 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01C1 0B04
0x01C1 0B08
0x01C1 0B0C
0x01C1 0B10
0x01C1 0B14
0x01C1 0B18 - 0x01C1 0B3F
0x01C1 0B40
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
–
EDMA3 TC2 Destination FIFO Options Register 1
EDMA3 TC2 Destination FIFO Source Address Register 1
EDMA3 TC2 Destination FIFO Count Register 1
EDMA3 TC2 Destination FIFO Destination Address Register 1
EDMA3 TC2 Destination FIFO B-Index Register 1
EDMA3 TC2 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01C1 0B44
0x01C1 0B48
0x01C1 0B4C
0x01C1 0B50
0x01C1 0B54
0x01C1 0B58 - 0x01C1 0B7F
0x01C1 0B80
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
–
EDMA3 TC2 Destination FIFO Options Register 2
EDMA3 TC2 Destination FIFO Source Address Register 2
EDMA3 TC2 Destination FIFO Count Register 2
EDMA3 TC2 Destination FIFO Destination Address Register 2
EDMA3 TC2 Destination FIFO B-Index Register 2
EDMA3 TC2 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01C1 0B84
0x01C1 0B88
0x01C1 0B8C
0x01C1 0B90
0x01C1 0B94
0x01C1 0B98 - 0x01C1 0BBF
0x01C1 0BC0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
–
EDMA3 TC2 Destination FIFO Options Register 3
EDMA3 TC2 Destination FIFO Source Address Register 3
EDMA3 TC2 Destination FIFO Count Register 3
EDMA3 TC2 Destination FIFO Destination Address Register 3
EDMA3 TC2 Destination FIFO B-Index Register 3
EDMA3 TC2 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01C1 0BC4
0x01C1 0BC8
0x01C1 0BCC
0x01C1 0BD0
0x01C1 0BD4
0x01C1 0BD8 - 0x01C1 0BFF
Transfer Controller 3 Registers
0x01C1 0C00
0x01C1 0C04
PID
TCCFG
–
Peripheral Identification Register
EDMA3 TC3 Configuration Register
Reserved
0x01C1 0C08 - 0x01C1 0CFF
0x01C1 0D00
TCSTAT
–
EDMA3 TC3 Channel Status Register
Reserved
0x01C1 0D04 - 0x01C1 0D1F
0x01C1 0D20
ERRSTAT
EDMA3 TC3 Error Status Register
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
0x01C1 0D24
ACRONYM
ERREN
REGISTER NAME
EDMA3 TC3 Error Enable Register
0x01C1 0D28
ERRCLR
ERRDET
ERRCMD
–
EDMA3 TC3 Error Clear Register
0x01C1 0D2C
EDMA3 TC3 Error Details Register
0x01C1 0D30
EDMA3 TC3 Error Interrupt Command Register
Reserved
0x01C1 0D34 - 0x01C1 0D3F
0x01C1 0D40
RDRATE
–
EDMA3 TC3 Read Command Rate Register
Reserved
0x01C1 0D44 - 0x01C1 0E3F
0x01C1 0E40
SAOPT
EDMA3 TC3 Source Active Options Register
EDMA3 TC3 Source Active Source Address Register
EDMA3 TC3 Source Active Count Register
EDMA3 TC3 Source Active Destination Address Register
EDMA3 TC3 Source Active B-Index Register
EDMA3 TC3 Source Active Memory Protection Proxy Register
EDMA3 TC3 Source Active Count Reload Register
0x01C1 0E44
SASRC
0x01C1 0E48
SACNT
0x01C1 0E4C
SADST
0x01C1 0E50
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
–
0x01C1 0E54
0x01C1 0E58
0x01C1 0E5C
EDMA3 TC3 Source Active Source Address B-Reference Register
EDMA3 TC3 Source Active Destination Address B-Reference Register
Reserved
0x01C1 0E60
0x01C1 0E64 - 0x01C1 0E7F
0x01C1 0E80
DFCNTRLD
DFSRCBREF
EDMA3 TC3 Destination FIFO Set Count Reload Register
EDMA3 TC3 Destination FIFO Set Source Address B-Reference Register
0x01C1 0E84
EDMA3 TC3 Destination FIFO Set Destination Address B-Reference
Register
0x01C1 0E88
DFDSTBREF
0x01C1 0E8C - 0x01C1 0EFF
0x01C1 0F00
–
Reserved
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
–
EDMA3 TC3 Destination FIFO Options Register 0
EDMA3 TC3 Destination FIFO Source Address Register 0
EDMA3 TC3 Destination FIFO Count Register 0
EDMA3 TC3 Destination FIFO Destination Address Register 0
EDMA3 TC3 Destination FIFO B-Index Register 0
EDMA3 TC3 Destination FIFO Memory Protection Proxy Register 0
Reserved
0x01C1 0F04
0x01C1 0F08
0x01C1 0F0C
0x01C1 0F10
0x01C1 0F14
0x01C1 0F18 - 0x01C1 0F3F
0x01C1 0F40
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
–
EDMA3 TC3 Destination FIFO Options Register 1
EDMA3 TC3 Destination FIFO Source Address Register 1
EDMA3 TC3 Destination FIFO Count Register 1
EDMA3 TC3 Destination FIFO Destination Address Register 1
EDMA3 TC3 Destination FIFO B-Index Register 1
EDMA3 TC3 Destination FIFO Memory Protection Proxy Register 1
Reserved
0x01C1 0F44
0x01C1 0F48
0x01C1 0F4C
0x01C1 0F50
0x01C1 0F54
0x01C1 0F58 - 0x01C1 0F7F
0x01C1 0F80
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
–
EDMA3 TC3 Destination FIFO Options Register 2
EDMA3 TC3 Destination FIFO Source Address Register 2
EDMA3 TC3 Destination FIFO Count Register 2
EDMA3 TC3 Destination FIFO Destination Address Register 2
EDMA3 TC3 Destination FIFO B-Index Register 2
EDMA3 TC3 Destination FIFO Memory Protection Proxy Register 2
Reserved
0x01C1 0F84
0x01C1 0F88
0x01C1 0F8C
0x01C1 0F90
0x01C1 0F94
0x01C1 0F98 - 0x01C1 0FBF
0x01C1 0FC0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
EDMA3 TC3 Destination FIFO Options Register 3
EDMA3 TC3 Destination FIFO Source Address Register 3
EDMA3 TC3 Destination FIFO Count Register 3
EDMA3 TC3 Destination FIFO Destination Address Register 3
EDMA3 TC3 Destination FIFO B-Index Register 3
0x01C1 0FC4
0x01C1 0FC8
0x01C1 0FCC
0x01C1 0FD0
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Table 6-16. VCE6467T EDMA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DFMPPRXY3
–
REGISTER NAME
0x01C1 0FD4
EDMA3 TC3 Destination FIFO Memory Protection Proxy Register 3
Reserved
0x01C1 0FD8 - 0x01C1 0FFF
Table 6-17 shows an abbreviation of the set of registers which make up the parameter set for each of 512
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-18 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
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Table 6-17. EDMA Parameter Set RAM
HEX ADDRESS RANGE
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01C0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 7FC0 - 0x01C0 7FDF
0x01C0 7FE0 - 0x01C0 7FFF
Parameters Set 510 (8 32-bit words)
Parameters Set 511 (8 32-bit words)
Table 6-18. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
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6.7 Reset
The reset controller detects the different type of resets supported on the VCE6467T device and manages
the distribution of those resets throughout the device.
The VCE6467T device has several types of device-level global resets—power-on reset, warm reset, max
reset, and system reset. Table 6-19 explains further the types of reset, the reset initiator, and the effects of
each reset on the chip. See Section 6.7.9, Reset Electrical Data/Timing, for more information on the
effects of each reset on the PLL controllers and their clocks.
Table 6-19. Device-Level Global Reset Types
TYPE
INITIATOR
EFFECT(S)
POR pin
Global chip reset (Cold reset). Activates the POR signal on chip,
which resets the entire chip including the emulation logic.
The power-on reset (POR) pin must be driven low during power
ramp of the device.
Power-on Reset
(POR)
Device boot and configuration pins are latched.
Resets everything except for the emulation logic. Emulator stays
alive during Warm Reset.
Device boot and configuration pins are latched.
Warm Reset
Max Reset
RESET pin
Same as a Warm Reset, except the VCE6467T device boot and
configuration pins are not re-latched.
Emulator, WD Timer (Timer 2)
Emulator
A system reset maintains memory contents and does not reset the
test and emulation circuitry. The device boot and configuration pins
are also not re-latched.
System Reset
MMR controls the C64x+ reset input. This is used for control of
C64x+ reset by the ARM. The C64x+ Slave DMA port is still alive
when in local reset.
C64x+ Local Reset
(DSP Reset)
Software (register bit)
In addition to device-level global resets, the PSC provides the capability to cause local resets to
peripherals and/or the C64x+ DSP.
6.7.1 Power-on Reset (POR Pin)
Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test
and emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes
through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power
supplies have reached their normal operating conditions. If an external oscillator is used on the
DEV_MXI/DEV_CLKIN pin, the source clock should also be running at the correct frequency prior to
de-asserting the POR pin. Note: A device power-up cycle is not required to initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset.
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
2. Wait for the input clock source to be stable while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted
(low) for a minimum of 12 DEV_MXI cycles.
Within the low period of the POR pin, the following happens:
–
The reset signals flow to the entire chip (including the test and emulation logic), resetting the
modules on chip.
–
The PLL Controller clocks start at the frequency of the DEV_MXI clock. The clocks are propagated
throughout the chip to reset the chip synchronously. By default, both PLL1 and PLL2 are in reset
and unlocked. The PLL Controllers default to PLL Bypass Mode.
4. The POR pin may now be deasserted (driven high).
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When the POR pin is deasserted (high), the configuration pin values are latched and the PLL
Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are
still in PLL Bypass Mode. Other device initialization also begins.
5. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
–
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
–
–
The PLL Controllers are operating in PLL Bypass Mode.
The ARM926 begins executing from the default address (either ARM boot ROM or EMIFA).
After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the
Using the TMS320DM646x Bootloader Application Report (literature number SPRAAS0).
6.7.1.1 Usage of POR versus RESET Pins
POR and RESET are independent resets.
If the device needs to go through a power-up cycle, POR (not RESET) must be used to fully reset the
device.
In functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation
for functional end-system is to use the POR pin for full device reset. If RESET pin is not needed, it can be
pulled inactive (high) via an external pullup resistor.
In a debug system, it is typically desirable to allow the reset of the device without crashing an emulation
session. In this case, the user can use the POR pin to achieve full device reset and use the RESET pin to
achieve a debug reset—which resets the entire device except test and emulation logic.
6.7.1.2 Latching Boot and Configuration Pins
Internal to the chip, the two device reset pins RESET and POR are logically AND’ed together only for the
purpose of latching device boot and configuration pins. The values on all device and boot configuration
pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from
low to high.
6.7.2 Warm Reset (RESET Pin)
A Warm Reset is activated by driving the RESET pin active-low. This resets everything in the device
except the test or emulation logic. An emulator session will stay alive during warm reset.
For more information on POR vs. RESET usage, see Section 6.7.1.1, Usage of POR versus RESET Pins
and Section 6.7.1.2, Latching Boot and Configuration Pins.
The following sequence must be followed during a Warm Reset:
1. Power supplies and input clock source should already be stable.
2. The RESET pin must be asserted (low) for a minimum of 12 DEV_MXI cycles.
Within the low period of the RESET pin, the following happens:
–
The reset signals flow to the entire chip resetting all the modules on chip, except the test and
emulation logic.
–
The PLL Controllers are reset thereby, switching back to PLL Bypass Mode and resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
3. The RESET pin may now be deasserted (driven high).
When the RESET pin is deasserted (high), the configuration pin values are latched and the PLL
Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are
still in PLL Bypass Mode. Other device initialization also begins.
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4. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
–
The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
–
–
The PLL Controllers are operating in PLL Bypass Mode.
The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the
Using the TMS320DM646x Bootloader Application Report (literature number SPRAAS0).
6.7.3 Maximum Reset
A Maximum (Max) Reset is initiated by the emulator or the watchdog timer (Timer 2). The effects are the
same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator
initiates a maximum reset via the ICEPICK module. This ICEPICK-initiated reset is non-maskable. When
the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway
condition.
To invoke the maximum reset via the ICEPICK module, the user can perform the following from the Code
Composer Studio™ IDE menu: Debug→Advanced Resets→System Reset
This is the Max Reset sequence:
1. Max Reset is initiated by the emulator or the watchdog timer.
During this time, the following happens:
–
The reset signals flow to the entire chip, resetting all the modules on chip except the test and
emulation logic.
–
The PLL Controllers are reset —thereby, switching back to PLL Bypass Mode and resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
–
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
–
–
The PLL Controllers are operating in PLL Bypass Mode.
The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a Max Reset, the previous values (as shown in the BOOTCFG register) are used to select the boot
mode. For more details on the boot sequence, see the Using the TMS320DM646x Bootloader Application
Report (literature number SPRAAS0).
6.7.4 System Reset
A System Reset is initiated by the emulator. The following memory contents are maintained:
•
L1/L2 RAM: The C64x+ L1/L2 RAM content is retained. The L1/L2 cache content is not retained
because tag information is reset.
•
DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the DDR2
SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode before
invoking the System Reset.
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Test, emulation, clock, and power control logic are unaffected. The emulator initiates a System Reset via
the C64x+ emulation logic. This reset can be masked by the emulator.
This is the System Reset sequence:
1. The System Reset is initiated by the emulator.
During this time, the following happens:
–
The reset signals flow to the entire chip resetting all the modules on chip, except the test and
emulation logic.
–
The PLL Controllers are not reset. Internal system clocks are unaffected. If PLL1/PLL2 were locked
before the System Reset, they remain locked.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
–
–
–
–
–
The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
The clock and reset of each peripheral (except the DDR2 Memory Controller) is determined by the
default settings of the Power and Sleep Controller (PSC).
The DDR2 Memory Controller registers retain their previous values. Only the DDR2 Memory
Controller state machines are reset by the System Reset.
The PLL Controllers are operating in the mode prior to System Reset. The System clocks are
unaffected.
The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a System Reset, the previous values (as shown in the BOOTCFG register) are used to select the
boot mode. For more details on the boot sequence, see the Using the TMS320DM646x Bootloader
Application Report (literature number SPRAAS0).
6.7.5 C64x+ Local Reset (DSP Local Reset)
With access to the PSC registers, the ARM can perform two types of DSP reset: DSP local reset and DSP
module reset. When DSP local reset is asserted, the DSP’s internal memories (L1P, L1D, and L2) are still
accessible. The local reset only resets the DSP CPU core, not the rest of the DSP subsystem, as the DSP
module reset would. Local reset is useful when the DSP module is in the enable state or in the disable
state. The DSP module reset takes precedence over local reset. The ARM uses local reset to reset the
DSP to initiate the DSP boot process. The intent of module reset is to completely reset the DSP (like hard
reset). For more detailed information on DSP local reset and DSP module reset, see the ARM-DSP
Integration Chapter in the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
For information on peripheral selection at the rising edge of POR or RESET, see Section 3, Device
Configurations of this data manual.
6.7.6 Peripheral Local Reset
The user can configure the local reset and clock state of a peripheral through programming the PSC.
Table 6-3, VCE6467T LPSC Assignments, identifies the LPSC numbers and the peripherals capable of
being locally reset by the PSC. For more detailed information on the programming of these peripherals by
the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
SPRUEP9).
6.7.7 Reset Priority
If any of the above reset sources occur simultaneously, the PLLC only processes the highest-priority reset
request. The reset request priorities, from high to low, are as follows:
•
Power-on Reset
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•
•
•
Maximum Reset
Warm Reset
System Reset
6.7.7.1 Reset Type Status (RSTYPE) Register
The Reset Type Status (RSTYPE) register (0x01C4 08E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers (see Table 6-11 for the PLL1
Controller Registers (Including Reset Controller)). For more details on the RSTYPE register and its bit
descriptions, see Figure 6-18 and Table 6-20.
31
15
16
RESERVED
R-0000 0000 0000 0000
4
3
2
1
0
RESERVED
SRST MRST WRST POR
R-0/1 R-0/1 R-0/1 R-0/1
R-0000 0000 0000
LEGEND: R = Read only; -n = value after reset
Figure 6-18. Reset Type Status (RSTYPE) Register [0x01C4 08E4]
Table 6-20. RSTYPE Register Bit Descriptions
BIT
NAME
DESCRIPTION
Reserved. Read returns "0". Writes have no effect.
30:4
RESERVED
System Reset.
3
2
1
0
SRST
0 = System Reset was not the last reset to occur.
1 = System Reset was the last reset to occur.
Max Reset.
MRST
WRST
POR
0 = Max Reset was not the last reset to occur.
1 = Max Reset was the last reset to occur.
Warm Reset.
0 = Warm Reset was not the last reset to occur.
1 = Warm Reset was the last reset to occur.
Power-on Reset.
0 = Power-on Reset was not the last reset to occur.
1 = Power-on Reset was the last reset to occur.
6.7.8 Pin Behaviors at Reset
During normal operations, pins are controlled by the respective peripheral selected in the PINMUX0 or
PINMUX1 register. During device level global reset, the pin behaves as follows:
Multiplexed Boot and Configuration Pins
These pins are forced 3-stated when the device is in reset. This is to ensure the proper boot and
configuration values can be latched on these multiplexed pins. This is particularly useful in the case where
the boot and configuration values are driven by an external control device. Once the device is out of reset,
these pins are controlled by their respective default peripheral.
•
Boot and Configuration Pins Group: VP_DOUT6/DSPBOOT, VP_DOUT5/PCIEN,
VP_DOUT4/CS2BW, VP_DOUT3/BTMODE3, VP_DOUT2/BTMODE2, VP_DOUT1/BTMODE1, and
VP_DOUT0/BTMODE0.
For information on whether external pullup/pulldown resistors should be used on the boot and
configuration pins, see Section 3.8.1, Pullup/Pulldown Resistors.
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Default Power Down Pins
As discussed in Section 3.2, Power Considerations, the VDD3P3V_PWDN register controls power to the
3.3-V pins. The VDD3P3V_PWDN register defaults to powering down some 3.3-V pins to save power. For
more details on the VDD3P3V_PWDN register and which 3.3-V pins default to power up or power down,
see Section 3.2, Power Considerations. The pins that default to power down, are both reset to power
down and high-impedance. They remain in that state until configured otherwise by VDD3P3_PWDN and
PINMUX0/PINMUX1 programming.
•
Default Power Down Pin Group: USB_DRVVBUS/GP[22], CLKOUT0, SPI_CLK, SPI_EN, SPI_CS0,
SPI_CS1, SPI_MISO, SPI_MOSI, VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_TXD[3:0],
VLYNQ_RXD[3:0], RFTCLK, GMTCLK, MTXD[7:4], MRXD[7:4], MTCLK, MTXD[3:0], MTXEN, MCOL,
MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, MDIO, ACLKX1, AHCLKX1, AXR1[0],
ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0], AMUTE0, AMUTEIN0,
PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17], PCI_TRDY/HHWIL/EM_A[16], PCI_STOP/HCNTL0/EM_WE,
PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1, PCI_PAR/HAS/EM_DQM0,
PCI_INTA/EM_WAIT2, PCI_CBE3/HR/W/EM_CS3, PCI_CBE2/HDS2/EM_CS2,
PCI_AD[15:0]/HD[15:0]/EM_D[15:0], PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],
DIOW/GP[20]/EM_WAIT4, IORDY/GP[21]/EM_WAIT3, DIOR/GP[19]/EM_WAIT5,
DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20], INTRQ/GP[18]/RSV ,
PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0], GP[7], GP[6], GP[5], GP[4]/STC_CLKIN,
GP[3]/AUDIO_CLK0, GP[2]/AUDIO_CLK1, GP[1], GP[0], TOUT2, TINP1L, TOUT1L, TOUT1U,
TINP0L, TINP0U, TOUT0L, TOUT0U, PWM1/TS1_DOUT, PWM0/CRG0_PO/TS1_ENAO,
URTS2/UIRTX2/TS0_PSTIN/GP[41], UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO,
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI, UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO,
URTS1/UIRTX1/TS0_WAITO/GP[25], UCTS1/USD1/TS0_EN_WAITO/GP[26],
URXD1/TS0_DIN7/GP[23], UTXD1/URCTX1/TS0_DOUT7/GP[24], UDTR0/TS0_ENAO/GP[36],
UDSR0/TS0_PSTO/GP[37], UDCD0/TS0_WAITIN/GP[38], URIN0/GP[8]/TS1_WAITIN,
URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN, URTS0/UIRTX0/TS1_EN_WAITO, UCTS0/USD0,
VP_DOUT15/TS1_DIN, VP_DOUT14/TS1_PSTIN, VP_DOUT13/TS1_EN_WAITO,
VP_DOUT12/TS1_WAITO, VP_DOUT11/TS1_DOUT, VP_DOUT10/TS1_PSTO,
VP_DOUT9/TS1_ENAO, VP_DOUT8/TS1_WAITIN, VP_CLKIN3/TS1_CLKO, VP_CLKO3/TS0_CLKO,
VP_DOUT7, VP_DOUT6/DSPBOOT, VP_DOUT5/PCIEN, VP_DOUT4/CS2BW,
VP_DOUT3/BTMODE3, VP_DOUT2/BTMODE2, VP_DOUT1/BTMODE1, VP_DOUT0/BTMODE0,
VP_CLKIN2, VP_CLKO2, VP_DIN15_VSYNC/TS0_DIN7, VP_DIN14_HSYNC/TS0_DIN6,
VP_DIN13_FIELD/TS0_DIN5, VP_DIN12/TS0_DIN4, VP_DIN11/TS0_DIN3, VP_DIN10/TS0_DIN2,
VP_DIN9/TS0_DIN1, VP_DIN8/TS0_DIN0, VP_CLKIN1, VP_DIN7/TS0_DOUT7/TS1_DIN,
VP_DIN6/TS0_DOUT6/TS1_PSTIN, VP_DIN5/TS0_DOUT5/TS1_EN_WAITO,
VP_DIN4/TS0_DOUT4/TS1_WAITO, VP_DIN3/TS0_DOUT3, VP_DIN2/TS0_DOUT2,
VP_DIN1/TS0_DOUT1, VP_DIN0/TS0_DOUT0, VP_CLKIN0.
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All Other Pins
During device reset, all other pins are controlled by the default peripheral. The default peripheral is
determined by the default settings of the PINMUX0 or PINMUX1 registers.
Some of the PINMUX0/PINMUX1 settings are determined by configuration pins latched at reset. To
determine the reset behavior of these pins, see Section 3.7, Multiplexed Pin Configurations and read the
rest of the this subsection to understand how that default peripheral controls the pin.
The reset behaviors for all these other pins during all boot modes, except PCI Boot, are categorized as
follows (also see Figure 6-19 and Figure 6-20 in Section 6.7.9, Reset Electrical Data/Timing):
•
•
DDR2 Z Group: DDR_DQS[3:0], DDR_DQS[3:0], DDR_D[31:0], DDR_DQGATE1, DDR_DQGATE3
DDR2 Low Group: DDR_CLK, DDR_CKE, DDR_ODT0, DDR_A[14:0], DDR_DQGATE0,
DDR_DQGATE2
•
•
•
•
DDR2 High Group: DDR_CLK, DDR_CS, DDR_WE, DDR_RAS, DDR_CAS
DDR2 Z/High Group: DDR_DQM[3:0]
DDR2 Low/High Group: DDR_BA[2:0]
Z Group: These pin are 3-stated by default, and these pins remain 3-stated throughout POR or
RESET assertion. When POR or RESET is deasserted, these pins remain 3-stated until configured
otherwise by their respective peripheral (after the peripheral is enabled by the PSC).
PCI_CLK/GP[10], PCI_INTA/EM_WAIT2, DIOW/GP[20]/EM_WAIT4, IORDY/GP[21]/EM_WAIT3,
PCI_AD[15:0]/HD[15:0]/EM_D[15:0], RFTCLK, GMTCLK, MTCLK, MTXD[7:0], MTXEN, MCOL, MCRS,
MRCLK, MRXD[7:0], MRXDV, MRXER, MDCLK, MDIO, URXD0/TS1_DIN,
UTXD0/URCTX0/TS1_PSTIN, URTS0/UIRTX0/TS1_EN_WAITO, UCTS0/USD0,
UDTR0/TS0_ENAO/GP[36], UDSR0/TS0_PSTO/GP[37], UDCD0/TS0_WAITIN/GP[38],
URIN0/GP[8]/TS1_WAITIN, URXD1/TS0_DIN7/GP[23], UTXD1/URCTX1/TS0_DOUT7/GP[24],
URTS1/UIRTX1/TS0_WAITO/GP[25], UCTS1/USD1/TS0_EN_WAITO/GP[26],
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI, UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO,
URTS2/UIRTX2/TS0_PSTIN/GP[41], UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO, ACLKR0,
AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0], AMUTE0, AMUTEIN0, ACLKX1,
AHCLKX1, AXR1[0], SCL, SDA, SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_MISO, SPI_MOSI,
PWM0/CRG0_PO/TS1_ENAO, PWM1/TS1_DOUT, VLYNQ_CLOCK, VLYNQ_SCRUN,
VLYNQ_TXD[3:0], VLYNQ_RXD[3:0], USB_DRVVBUS/GP[22], TINP0L, TINP0U, TOUT0L, TOUT0U,
TINP1L, TOUT1L, TOUT1U, TOUT2, TS0_CLKIN, TS1_CLKIN, VP_CLKIN0, VP_CLKIN1,
VP_DIN15_VSYNC/TS0_DIN7, VP_DIN14_HSYNC/TS0_DIN6, VP_DIN13_FIELD/TS0_DIN5,
VP_DIN12/TS0_DIN4, VP_DIN11/TS0_DIN3, VP_DIN10/TS0_DIN2, VP_DIN9/TS0_DIN1,
VP_DIN8/TS0_DIN0, VP_DIN7/TS0_DOUT7/TS1_DIN, VP_DIN6/TS0_DOUT6/TS1_PSTIN,
VP_DIN5/TS0_DOUT5/TS1_EN_WAITO, VP_DIN4/TS0_DOUT4/TS1_WAITO,
VP_DIN3/TS0_DOUT3, VP_DIN2/TS0_DOUT2, VP_DIN1/TS0_DOUT1, VP_DIN0/TS0_DOUT0,
VP_CLKIN2, VP_CLKIN3/TS1_CLKO, VP_CLKO2, VP_CLKO3/TS0_CLKO, VP_DOUT15/TS1_DIN,
VP_DOUT14/TS1_PSTIN, VP_DOUT13/TS1_EN_WAITO, VP_DOUT12/TS1_WAITO,
VP_DOUT11/TS1_DOUT, VP_DOUT10/TS1_PSTO, VP_DOUT9/TS1_ENAO,
VP_DOUT8/TS1_WAITIN, VP_DOUT7, GP[0], GP[1], GP[2]/AUDIO_CLK1, GP[3]/AUDIO_CLK0,
GP[4]/STC_CLKIN, GP[5], GP[6], GP[7], TIMS, TDO, TDI, TCK, TRST, EMU1, EMU0,
DEV_MXI/DEV_CLKIN, AUX_MXI/AUX_CLKIN
•
•
Low Group: These pins are low by default, and remain low until configured otherwise by their
respective peripheral (after the peripheral is enabled by the PSC).
PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W, PCI_IRDY/HRDY/EM_A[17],
PCI_TRDY/HHWIL/EM_A[16], PCI_CBE1/ATA_CS1/GP[32]/EM_A[19],
PCI_CBE0/ATA_CS0/GP[33]/EM_A[18], PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0], CLKOUT0,
RTCLK,
High Group: These pins are high by default, and remain high until configured otherwise by their
respective peripheral (after the peripheral is enabled by the PSC).
PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0], PCI_STOP/HCNTL0/EM_WE,
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PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1, PCI_PAR/HAS/EM_DQM0,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4, PCI_CBE3/HR/W/EM_CS3,
PCI_CBE2/HDS2/EM_CS2,
NOTE: For PCI boot mode, all PCI pins now behave according to Z Group.
For more information on the pin behaviors during device-level global reset, see Figure 6-19 and
Figure 6-20 in Section 6.7.9, Reset Electrical Data/Timing.
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6.7.9 Reset Electrical Data/Timing
Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)
resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.
Table 6-21. Timing Requirements for Reset (see Figure 6-19 and Figure 6-20)
-1G
NO.
UNIT
MIN
MAX
1
2
tw(RESET)
Pulse duration, POR low or RESET low
12C(1)
ns
ns
Setup time, boot and configuration pins valid before POR high or RESET
high(2)
tsu(CONFIG)
12C(1)
Hold time, boot and configuration pins valid after POR high or RESET
high(2)
3
th(CONFIG)
0
ns
(1) C = 1/DEV_MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET)
requirement.
(2) For the list of boot and configuration pins, see Table 2-6, Boot Terminal Functions.
Table 6-22. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 6-20)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
10C
4
tw(PAUSE)
Pulse duration, SYSCLKs paused (low)
10C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
5
td(RSTH-PAUSE)
td(RSTL-BOOTZ)
td(RSTL-DDRZZ)
td(RSTL-DDRLL)
td(RSTL-DDRHH)
td(RSTL-DDRZHZ)
td(RSTL-DDRLHL)
td(RSTL-ZZ)
Delay time, RESET high or POR high to SYSCLKs paused (low)
Delay time, RESET low to Boot Configuration Group high impedance
Delay time, RESET low to DDR2 Z Group high impedance
Delay time, RESET low to DDR2 Low Group low
Delay time, RESET low to DDR2 High Group high
Delay time, RESET low to DDR2 Z/High Group high impedance
Delay time, RESET low to DDR2 Low/High Group low
Delay time, RESET low to Z Group high impedance
Delay time, RESET low to Low Group low
1990C
20
0
0
0
0
0
0
0
0
0
6
7P + 20
3P + 20
20
7
8
13
14
17
18
19
9
7P + 20
20
20
td(RSTL-LOWL)
td(RSTL-HIGHH)
td(RSTL-BOOTV)
td(RSTH-DDRZV)
td(RSTH-DDRLV)
td(RSTH-DDRHV)
td(RSTH-DDRZHV)
td(RSTH-DDRLHV)
td(RSTH-ZV)
20
Delay time, RESET low to High Group high
20
(2)
Delay time, RESET high to Boot Configuration Group valid
Delay time, RESET high to DDR2 Z Group valid
Delay time, RESET high to DDR2 Low Group valid
Delay time, RESET high to DDR2 High Group valid
Delay time, RESET high to DDR2 Z/High Group valid high
Delay time, RESET high to DDR2 Low/High Group valid high
Delay time, RESET high to Z Group valid
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
10
11
12
15
16
20
21
22
td(RSTH-LOWV)
td(RSTH-HIGHV)
Delay time, RESET high to Low Group valid
Delay time, RESET high to High Group valid
(1) C = 1/DEV_CLKIN clock frequency in ns.
(2) Following RESET high or POR high, this signal group maintains the state the pins(s) achieved while RESET or POR was driven low until
the peripheral is enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low or POR low and
remains in the high-impedance state following RESET high or POR high until the DDR2 controller is enabled via the PSC.
Figure 6-19 shows the Power-Up Timing. Figure 6-20 shows the Warm Reset (RESET) Timing. Max Reset
Timing is identical to Warm Reset Timing, except the boot and configuration pins are not relatched and
the BOOTCFG register retains its previous value latched before the Max Reset was initiated.
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Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
DEV_MXI(A)
CLKOUT0
POR
1
RESET
SYSCLKREFCLK
(PLLC1)
23
4
SYSCLKx
9
3
2
Hi-Z
Hi-Z
Boot and
Configuration Pins
Config
10
DDR2 Z Group
11
12
DDR2 Low Group
DDR2 High Group
15
16
Hi-Z
Hi-Z
DDR2 Z/High Group
DDR2 Low/High Group
20
21
Z Group
Low Group
22
High Group
A. Power supplies and DEV_MXI must be stable before the start of tW(RESET).
.
B. Pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. For more details on what
pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see Section 6.7.8, Pin Behaviors at
Reset.
Figure 6-19. Power-Up Timing
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Power Supplies Stable
DEV_MXI
CLKOUT0
POR
1
RESET
SYSCLKREFCLK
(PLLC1)
PLL1 CLOCK
DIVx CLOCK
23
4
SYSCLKx
9
3
5
2
Hi-Z
Hi-Z
Boot and
Configuration Pins
Config
10
6
7
8
DDR2 Z Group
11
12
DDR2 Low Group
DDR2 High Group
15
13
14
17
Hi-Z
Hi-Z
DDR2 Z/High Group
16
20
21
DDR2 Low/High Group
Z Group
18
19
Low Group
22
High Group
A. Pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. For more details on what
pin group (e.g., Z Group, Z/Low Group, Z/High Group, etc.) each pin belongs to, see Section 6.7.8, Pin Behaviors at
Reset.
Figure 6-20. Warm Reset (RESET) Timing
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6.8 Interrupts
The VCE6467T device has a large number of interrupts to service the needs of its many peripherals and
subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device
interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt
controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical
applications, the ARM handles most of the peripheral interrupts and grants control to the C64x+ for
interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other
through interrupts.
6.8.1 ARM CPU Interrupts
The ARM926 CPU core supports 2 direct interrupts: FIQ and IRQ. The VCE6467T ARM interrupt
controller prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed
in Table 6-23, and interrupts the ARM CPU. Each interrupt is programmable for up to 8 levels of priority.
There are 6 levels for IRQ and 2 levels for FIQ. Interrupts at the same priority level are serviced in order
by the ARM Interrupt Number, with the lowest number having the highest priority. Table 6-24 shows the
ARM interrupt controller registers and memory locations. For more details on ARM interrupt control, see
the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
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Table 6-23. VCE6467T ARM Interrupts
ARM
ARM
INTERRUPT
NUMBER
ACRONYM
SOURCE
INTERRUPT
NUMBER
ACRONYM
TINTL0
SOURCE
0
1
2
3
4
5
6
VP_VERTINT0
VP_VERTINT1
VP_VERTINT2
VP_VERTINT3
VP_ERRINT
-
VPIF
VPIF
VPIF
VPIF
VPIF
32
33
34
35
36
37
38
Timer 0 lower – TINT12
Timer 0 upper – TINT34
Timer 1 lower – TINT12
Timer 1 upper – TINT34
PWM 0
TINTH0
TINTL1
TINTH1
PWMINT0
PWMINT1
VLQINT
I2CINT
Reserved
Reserved
PWM 1
-
VLYNQ
WDINT
WD Timer (TIMER 2) –
TINT12
I2C
7
39
8
CRGENINT0
CRGENINT1
TSINT0
CRGEN 0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
UARTINT0
UARTINT1
UARTINT2
SPINT0
SPINT1
DSP2ARM0
-
UART 0
9
CRGEN 1
UART 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TSIF 0
UART 2
TSINT1
TSIF 1
SPI
VDCEINT
USBINT
VDCE
SPI
USB
DSP Controller to ARM
USBDMAINT
PCIINT
USB DMA
Reserved
PCI
PSCINT
GPIO0
Power and Sleep Controller
CCINT0
EDMA CC Region 0
EDMA CC Error
EDMA TC 0 Error
EDMA TC 1 Error
EDMA TC 2 Error
EDMA TC 3 Error
ATA
GPIO
CCERRINT
TCERRINT0
TCERRINT1
TCERRINT2
TCERRINT3
IDEINT
GPIO1
GPIO
GPIO2
GPIO
GPIO3
GPIO
GPIO4
GPIO
GPIO5
GPIO
GPIO6
GPIO
HPIINT
HPI
GPIO7
GPIO
MAC_RXTH
MAC_RX
MAC_TX
MAC_MISC
AXINT0
EMAC RX Threshold
EMAC Receive
EMAC Transmit
EMAC Miscellaneous
McASP0 Transmit
McASP0 Receive
McASP1 Transmit
Reserved
GPIOBNK0
GPIOBNK1
GPIOBNK2
DDRINT
EMIFAINT
COMMTX
COMMRX
EMUINT
GPIO Bank 0
GPIO Bank 1
GPIO Bank 2
DDR2 Memory Controller
EMIFA
ARINT0
ARMSS
ARMSS
E2ICE
AXINT1
-
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Table 6-24. ARM Interrupt Controller Registers
HEX ADDRESS RANGE
0x01C4 8000
ACRONYM
FIQ0
REGISTER NAME
FIQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to FIQ)]
FIQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to FIQ)]
IRQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to IRQ)]
IRQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to IRQ)]
Entry Address [28:0] for Valid FIQ Interrupt
Entry Address [28:0] for Valid IRQ Interrupt
Interrupt Enable Register 0
0x01C4 8004
FIQ1
0x01C4 8008
IRQ0
0x01C4 800C
IRQ1
0x01C4 8010
FIQENTRY
IRQENTRY
EINT0
0x01C4 8014
0x01C4 8018
0x01C4 801C
EINT1
Interrupt Enable Register 1
0x01C4 8020
INCTL
Interrupt Operation Control Register
Interrupt Entry Table Base Address Register
Reserved
0x01C4 8024
EABASE
-
0x01C4 8028 - 0x01C4 802F
0x01C4 8030
INTPRI0
INTPRI1
INTPRI2
INTPRI3
INTPRI4
INTPRI5
INTPRI6
INTPRI7
-
Interrupt 0-7 Priority Select
0x01C4 8034
Interrupt 8-15 Priority Select
0x01C4 8038
Interrupt 16-23 Priority Select
0x01C4 803C
Interrupt 24-31 Priority Select
0x01C4 8040
Interrupt 32-39 Priority Select
0x01C4 8044
Interrupt 40-47 Priority Select
0x01C4 8048
Interrupt 48-55 Priority Select
0x01C4 804C
Interrupt 56-63 Priority Select
0x01C4 8050 - 0x01C4 83FF
Reserved
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6.8.2 DSP Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user-programmable and is listed in Table 6-25. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-26
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see the TMS320DM646x DMSoC DSP Subsystem Reference Guide (literature number
SPRUEP8).
Table 6-25. VCE6467T DSP Interrupts
DSP
DSP
INTERRUPT
NUMBER
ACRONYM
SOURCE
C64x+ Int Ctl 0
INTERRUPT
NUMBER
ACRONYM
GPIO0
SOURCE
0
EVT0
EVT1
EVT2
EVT3
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
GPIO
1
C64x+ Int Ctl 1
C64x+ Int Ctl 2
C64x+ Int Ctl 3
Timer 0 lower – TINT12
Timer 0 upper – TINT34
Timer 1 lower – TINT12
Timer 1 upper – TINT34
Reserved
GPIO1
GPIO
2
GPIO2
GPIO
3
GPIO3
GPIO
4
TINTL0
GPIO4
GPIO
5
TINTH0
GPIO5
GPIO
6
TINTL1
GPIO6
GPIO
7
TINTH1
GPIO7
GPIO
8
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
9
EMU_DTDMA
C64x+ EMC
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–
Reserved
–
EMU_RTDXRX
C64x+ RTDX
C64x+ RTDX
C64x+ EMC 0
C64x+ EMC 1
Reserved
–
EMU_RTDXTX
–
IDMAINT0
–
IDMAINT1
–
–
–
ARM2DSP0
ARM to DSP Controller 0
ARM to DSP Controller 1
ARM to DSP Controller 2
ARM to DSP Controller 3
Reserved
–
ARM2DSP1
–
ARM2DSP2
–
ARM2DSP3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCINT1
EDMA CC Region 1
EDMA CC Error
EDMA TC0 Error
EDMA TC1 Error
EDMA TC2 Error
EDMA TC3 Error
ATA
Reserved
CCERRINT
Reserved
TCERRINT0
Reserved
TCERRINT1
Reserved
TCERRINT2
Reserved
TCERRINT3
Reserved
IDEINT
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
–
Reserved
Reserved
INTERR
C64x+ Interrupt Controller
Dropped CPU Interrupt Event
32
33
96
97
–
Reserved
EMC_IDMAERR
C64x+ EMC Invalid IDMA
Parameters
34
35
36
–
–
–
Reserved
Reserved
Reserved
98
99
–
–
–
Reserved
Reserved
Reserved
100
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Table 6-25. VCE6467T DSP Interrupts (continued)
DSP
DSP
INTERRUPT
NUMBER
ACRONYM
SOURCE
INTERRUPT
NUMBER
ACRONYM
SOURCE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PMC_ED
–
C64x+ PMC
Reserved
–
Reserved
UMCED1
UMCED2
PDCINT
C64x+ UMC 1
C64x+ UMC 2
C64x+ PDC
C64x+ SYS
C64x+ PMC
C64x+ PMC
C64x+ DMC
C64x+ DMC
C64x+ UMC
C64x+ UMC
C64x+ EMC
C64x+ EMC
AXINT0
McASP 0 Transmit
McASP 0 Receive
McASP 1 Transmit
Reserved
ARINT0
SYSCMPA
PMCCMPA
PMCDMPA
DMCCMPA
DMCDMPA
UMCCMPA
UMCDMPA
EMCCMPA
EMCBUSERR
AXINT1
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 6-26. C64x+ Interrupt Controller Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
0x0180 0000
EVTFLAG0 Event flag register 0
EVTFLAG1 Event flag register 1
EVTFLAG2 Event flag register 2
EVTFLAG3 Event flag register 3
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
0x0180 0180
0x0180 0184
0x0180 0188
EVTSET0
EVTSET1
EVTSET2
EVTSET3
EVTCLR0
EVTCLR1
EVTCLR2
EVTCLR3
Event set register 0
Event set register 1
Event set register 2
Event set register 3
Event clear register 0
Event clear register 1
Event clear register 2
Event clear register 3
EVTMASK0 Event mask register 0
EVTMASK1 Event mask register 1
EVTMASK2 Event mask register 2
EVTMASK3 Event mask register 3
MEVTFLAG0 Masked event flag register 0
MEVTFLAG1 Masked event flag register 1
MEVTFLAG2 Masked event flag register 2
MEVTFLAG3 Masked event flag register 3
EXPMASK0 Exception mask register 0
EXPMASK1 Exception mask register 1
EXPMASK2 Exception mask register 2
EXPMASK3 Exception mask register 3
MEXPFLAG0 Masked exception flag register 0
MEXPFLAG1 Masked exception flag register 1
MEXPFLAG2 Masked exception flag register 2
MEXPFLAG3 Masked exception flag register 3
INTMUX1
INTMUX2
INTMUX3
INTXSTAT
INTXCLR
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Interrupt exception status
Interrupt exception clear
INTDMASK Dropped interrupt mask register
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6.9 External Memory Interface (EMIF)
VCE6467T supports several memory and external device interfaces, including:
•
•
•
Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc.
NAND Flash
ATA (see Section 6.20, ATA Controller)
6.9.1 Asynchronous EMIF (EMIFA)
The VCE6467T Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width
up to 24 bits, and 4 chip selects, along with memory control signals. These signals are multiplexed
between these peripherals:
•
•
•
•
•
EMIFA and NAND interfaces
ATA interface
Host-Port Interface (HPI)
PCI
GPIO
6.9.2 NAND (NAND, SmartMedia/SSFDC, xD)
The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are
provided and each are individually configurable to provide either EMIFA or NAND support. The NAND
features supported are as follows.
•
•
•
•
•
NAND flash on up to 4 asynchronous chip selects
8- or 16-bit data bus width
Programmable cycle timings
Performs ECC calculation
NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
•
ARM ROM supports booting of the VCE6467T ARM926 processor from NAND flash located at CS2
The memory map for EMIFA and NAND registers is shown in Table 6-27. For more details on the EMIFA
and NAND interfaces, the TMS320DM646x DMSoC Asynchronous External Memory Interface (EMIF)
User's Guide (literature number SPRUEQ7).
6.9.3 EMIFA Peripheral Register Description(s)
Table 6-27 shows the EMIFA/NAND registers.
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Table 6-27. EMIFA/NAND Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Revision Code and Status Register
0x2000 8000
RCSR
AWCCR
–
0x2000 8004
Asynchronous Wait Cycle Configuration Register
Reserved
0x2000 8008 - 0x2000 800F
0x2000 8010
A1CR
Asynchronous 1 Configuration Register (CS2 Space)
Asynchronous 2 Configuration Register (CS3 Space)
Asynchronous 3 Configuration Register (CS4 Space)
Asynchronous 4 Configuration Register (CS5 Space)
Reserved
0x2000 8014
A2CR
0x2000 8018
A3CR
0x2000 801C
A4CR
0x2000 8020 - 0x2000 803F
0x2000 8040
–
EIRR
EMIF Interrupt Raw Register
0x2000 8044
EIMR
EMIF Interrupt Mask Register
0x2000 8048
EIMSR
EIMCR
–
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
Reserved
0x2000 804C
0x2000 8050 - 0x2000 805F
0x2000 8060
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
–
NAND Flash Control Register
0x2000 8064
NAND Flash Status Register
0x2000 8070
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
Reserved
0x2000 8074
0x2000 8078
0x2000 807C
0x2000 8080 - 0x2000 8FFF
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6.9.4 EMIFA Electrical Data/Timing
Table 6-28. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)
(see Figure 6-21 and Figure 6-22)
-1G
NO.
UNIT
MIN
MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
14 tsu (EMWAIT-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
Setup time, EM_WAITx asserted before EM_OE high(2)
WRITES
5
0
ns
ns
ns
4E + 3
28 t su(EMWAIT-EMWEH) Setup time, EM_WAITx asserted before EM_WE high(2)
4E + 3
ns
(1) E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 1 GHz, use E = 4 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 6-23 and Figure 6-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-29. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1) (2) (see Figure 6-21 and Figure 6-22)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
READS and WRITES
READS
1
3
td(TURNAROUND)
Turn around time
(TA + 1) * E - 3
(TA + 1) * E + 3 ns
(RS + RST + RH + (RS + RST + RH + TA +
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
ns
TA + 4) * E - 3
4) * E + 3
tc(EMRCYCLE)
(RS + RST + RH +
TA + 4) * E - 3
4184 * E + 3 ns
Output setup time, EM_CS[5:2] low to EM_OE low
(SS = 0)
(RS + 1) * E - 3
(RS + 1) * E + 3 ns
4
5
tsu(EMCSL-EMOEL)
Output setup time, EM_CS[5:2] low to EM_OE low
(SS = 1)
3
(RH + 1) * E - 3
3
ns
(RH + 1) * E + 3 ns
ns
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 0)
th(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 1)
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[22:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[22:0] invalid
EM_OE active low width (EW = 0)
(RS + 1) * E - 3
(RH + 1) * E - 3
(RS + 1) * E - 3
(RH + 1) * E - 3
(RST + 1) * E - 3
(RST + 1) * E - 3
(RS + 1) * E + 3 ns
(RH + 1) * E + 3 ns
(RS + 1) * E + 3 ns
(RH + 1) * E + 3 ns
(RST + 1) * E + 3 ns
(RST + 4097) * E + 3 ns
4E + 3 ns
10 tw(EMOEL)
EM_OE active low width (EW = 1)
11 td(EMWAITH-EMOEH) Delay time from EM_WAITx deasserted to EM_OE high
WRITES
(WS + WST + WH (WS + WST + WH + TA
EMIF write cycle time (EW = 0)
15 tc(EMWCYCLE)
ns
+ TA + 4) * E - 3
+ 4) * E + 3
(WS + WST + WH
+ TA + 4) * E - 3
EMIF write cycle time (EW = 1)
4184 * E + 3 ns
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 0)
(WS + 1) * E - 3
(WS + 1) * E + 3 ns
16 tsu(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to EM_WE low
3
(WH + 1) * E - 3
3
ns
(WH + 1) * E + 3 ns
ns
(SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 0)
17 th(EMWEH-EMCSH)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 1)
18 tsu(EMRNW-EMWEL) Output setup time, EM_R/W valid to EM_WE low
(WS + 1) * E - 3
(WH + 1) * E - 3
(WS + 1) * E - 3
(WH + 1) * E - 3
(WS + 1) * E - 3
(WH + 1) * E - 3
(WST + 1) * E - 3
(WST + 1) * E - 3
(WS + 1) * E + 3 ns
(WH + 1) * E + 3 ns
(WS + 1) * E + 3 ns
(WH + 1) * E + 3 ns
(WS + 1) * E + 3 ns
(WH + 1) * E + 3 ns
(WST + 1) * E + 3 ns
(WST + 4097) * E + 3 ns
4E + 3 ns
19 th(EMWEH-EMRNW)
20 tsu(EMBAV-EMWEL)
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
Output hold time, EM_WE high to EM_R/W invalid
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[22:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[22:0] invalid
EM_WE active low width (EW = 0)
24 tw(EMWEL)
EM_WE active low width (EW = 1)
25 td(EMWAITH-EMWEH) Delay time from EM_WAITx deasserted to EM_WE high
26 tsu(EMDV-EMWEL) Output setup time, EM_D[15:0] valid to EM_WE low
(WS + 1) * E - 3
(WS + 1) * E + 3 ns
(1) RS = Read setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold, TA = Turn Around,
EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous n Configuration and the
Asynchronous Wait Cycle Configuration registers and support the following range of values: TA[0–3], RS[0–15], RST[0–63], RH[0–7],
WS[0–15], WST[0–63], WH[0–7], EW[0–1], and MEWC[0–255]. For more information, see the TMS320DM646x DMSoC Asynchronous
External Memory Interface (EMIF) User's Guide (literature number SPRUEQ7).
(2) E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 1 GHz, use E = 4 ns.
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Table 6-29. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module (see Figure 6-21 and Figure 6-22) (continued)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
27 th(EMWEH-EMDIV)
Output hold time, EM_WE high to EM_D[15:0] invalid
(WH + 1) * E - 3
(WH + 1) * E + 3 ns
3
1
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[22:0]
4
8
5
9
7
6
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 6-21. Asynchronous Memory Read Timing for EMIF
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15
1
EM_CS[5:2]
EM_R/W
EM_BA[1:0]
EM_A[22:0]
16
18
20
22
17
19
21
23
24
EM_WE
27
26
EM_D[15:0]
EM_OE
Figure 6-22. Asynchronous Memory Write Timing for EMIF
SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CS[5:2]
EM_DQM[1:0]
EM_BA[1:0]
EM_A[22:0]
EM_D[15:0]
14
11
EM_OE
2
2
Asserted
Deasserted
EM_WAIT[5:2]
Figure 6-23. EM_WAITx Read Timing Requirements
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SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CS[5:2]
EM_DQM[1:0]
EM_BA[1:0]
EM_A[22:0]
EM_D[15:0]
28
25
EM_WE
2
2
Asserted
Deasserted
EM_WAIT[5:2]
Figure 6-24. EM_WAITx Write Timing Requirements
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6.10 DDR2 Memory Controller
The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM devices and can interface to either 16-bit or 32-bit DDR2 SDRAM
devices. For details on the DDR2 Memory Controller, see the TMS320DM646x DMSoC DDR2 Memory
Controller User's Guide (literature number SPRUEQ4).
A memory map of the DDR2 Memory Controller registers is shown in Table 6-30.
Table 6-30. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
0x01C4 004C
ACRONYM
REGISTER NAME
–
Reserved
0x01C4 2038
–
–
Reserved
0x2000 0000 - 0x2000 0003
0x2000 0004
Reserved
SDRSTAT
SDBCR
SDRCR
SDTIMR
SDTIMR2
–
SDRAM Status Register
0x2000 0008
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
Reserved
0x2000 000C
0x2000 0010
0x2000 0014
0x2000 0018 - 0x2000 001F
0x2000 0020
PBBPR
–
Peripheral Bus Burst Priority Register
Reserved
0x2000 0024 - 0x2000 00BF
0x2000 00C0
IRR
Interrupt Raw Register
Interrupt Masked Register
Interrupt Mask Set Register
Interrupt Mask Clear Register
Reserved
0x2000 00C4
IMR
0x2000 00C8
IMSR
IMCR
–
0x2000 00CC
0x2000 00D0 - 0x2000 00E3
0x2000 00E4
DDRPHYCR
–
DDR2 PHY Control Register
Reserved
0x2000 00E8 - 0x2000 00EF
0x2000 00F0
VTPIOCR
–
DDR2 VTP IO Control Register
Reserved
0x2000 00F4 - 0x2000 7FFF
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6.10.1 DDR2 Memory Controller Electrical Data/Timing
TI only supports board designs that follow the guidelines outlined in this document.
Table 6-31. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller(1) (2) (see Figure 6-25)
-1G
NO.
PARAMETER
UNIT
MIN
2.5
MAX
8
1
2
tc(DDR_CLK)
f(DDR_CLK)
Cycle time, DDR_CLK
Frequency, DDR_CLK
ns
125
400
MHz
(1) DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.
1
DDR_CLK
Figure 6-25. DDR2 Memory Controller Clock Timing
6.10.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see Understanding TI’s PCB Routing Rule-Based DDR2 Timing Specification Application
Report (SPRAAV0).
6.10.2.1 DDR2 Interface Schematic
Figure 6-26 shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system
schematic is identical except that the high word DDR2 device is deleted, see Figure 6-27. The pin
numbers for the VCE6467T can be obtained from the Section 2.7, Pin Assignments of this document.
6.10.2.2 Compatible JEDEC DDR2 Devices
Table 6-32 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 6-32. Compatible JEDEC DDR2 Devices
No.
1
Parameter
Min
Max
Unit
JEDEC DDR2 Device Speed Grade(1)
JEDEC DDR2 Device Bit Width
JEDEC DDR2 Device Count(2)
JEDEC DDR2 Device Ball Count(3)
DDR2-800
2
x16
1
x16
2
Bits
Devices
Balls
3
4
84
92
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) 1 DDR2 device is used for 16 bit DDR2 memory system. 2 DDR2 devices are used for 32 bit DDR2 memory system.
(3) 92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrrically the 92 and 84 ball DDR2
devices are the same.
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6.10.2.3 PCB Stackup
The minimum stackup required for routing the VCE6467T is a six layer stack as shown in Table 6-33.
Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size
of the PCB footprint.
Table 6-33. VCE6467T Minimum PCB Stack Up
Layer
Type
Signal
Plane
Plane
Signal
Plane
Signal
Description
Top Routing Mostly Horizontal
Ground
1
2
3
4
5
6
Power
Internal Routing
Ground
Bottom Routing Mostly Vertical
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Complete stack up specifications are provided in Table 6-34.
DM646x
DDR_D0
DDR2
DQ0
T
T
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
T
T
T
T
DDR_DQS0
DDR_D8
LDQS
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DQ15
UDM
T
T
UDQS
T
T
DDR_DQS1
UDQS
ODT
T
T
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
DDR_ODT0
DDR2
ODT
NC
DDR_D16
DQ0
T
T
DDR_D23
DDR_DQM2
DDR_DQS2
DQ7
LDM
LDQS
T
T
T
T
DDR_DQS2
DDR_D24
LDQS
DQ8
DDR_D31
DDR_DQM3
DDR_DQS3
DDR_DQS3
DQ15
UDM
T
T
UDQS
UDQS
T
T
DDR_BA0
T
BA0
BA0
DDR_BA2
DDR_A0
T
T
BA2
A0
BA2
A0
DDR_A14
DDR_CS
T
T
T
T
T
T
A14
CS
A14
CS
CAS
RAS
Vio 1.8(A)
DDR_CAS
DDR_RAS
CAS
RAS
DDR_WE
DDR_CKE
DDR_CLK
WE
CKE
CK
WE
CKE
CK
0.1 µF
0.1 µF
1 K Ω 1%
T
T
CK
CK
DDR_CLK
DDR_VREF
VREF VREF
VREF VREF
VREF
0.1 µF(B)
0.1 µF(B)
0.1 µF(B)
1 K Ω 1%
DVDDR2
50 Ω ( 5%)
DDR_ZN
DDR_ZP
50 Ω ( 5%)
T
Terminator, if desired. See terminator comments.
Vio1.8 is the power supply for the DDR2 memories and DM646x DDR2 interface.
A
B
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 6-26. VCE6467T 32-Bit DDR2 High Level Schematic
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DM646x
DDR_D0
DDR2
DQ0
T
T
DDR_D7
DQ7
LDM
LDQS
DDR_DQM0
DDR_DQS0
T
T
T
T
DDR_DQS0
DDR_D8
LDQS
DQ8
DDR_D15
DDR_DQM1
DDR_DQS1
DDR_DQS1
DQ15
UDM
T
T
UDQS
UDQS
T
T
T
T
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
DDR_ODT0
NC
DDR_D16
NC
ODT
Vio 1.8(A)
DDR_D23
NC
NC
DDR_DQM2
1 KΩ
1 KΩ
DDR_DQS2
DDR_DQS2
NC
DDR_D24
Vio 1.8(A)
DDR_D31
DDR_DQM3
DDR_DQS3
DDR_DQS3
NC
NC
1 KΩ
1 KΩ
DDR_BA0
T
BA0
DDR_BA2
DDR_A0
T
T
BA2
A0
DDR_A14
DDR_CS
T
T
T
T
T
T
A14
CS
CAS
Vio 1.8(A)
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CLK
RAS
WE
CKE
CK
0.1 µF
1 K Ω 1%
T
T
CK
DDR_CLK
DDR_VREF
VREF
VREF
VREF
0.1 µF(B)
0.1 µF(B)
DVDDR2
0.1 µF
1 K Ω 1%
50 Ω ( 5%)
DDR_ZN
DDR_ZP
50 Ω ( 5%)
T
Terminator, if desired. See terminator comments.
Vio1.8 is the power supply for the DDR2 memories and DM646x DDR2 interface.
A
B
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 6-27. VCE6467T 16-Bit DDR2 High Level Schematic
Table 6-34. PCB Stack Up Specifications
No. Parameter
Min
Typ
Max Unit
1
PCB Routing/Plane Layers
6
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Max Unit
0
Table 6-34. PCB Stack Up Specifications (continued)
No. Parameter
Min
3
Typ
2
3
Signal Routing Layers
Full ground layers under DDR2 routing Region
Number of ground plane cuts allowed within DDR routing region
Number of ground reference planes required for each DDR2 routing layer
Number of layers between DDR2 routing layer and reference ground plane
PCB Routing Feature Size
2
4
5
1
6
0
7
4
4
Mils
Mils
Mils
Mils
8
PCB Trace Width w
8
PCB BGA escape via pad size
18
8
9
PCB BGA escape via hole size
10
11
12
13
DSP Device BGA pad size(1)
DDR2 Device BGA pad size(2)
Single Ended Impedance, Zo
Impedance Control(3)
50
75
Ω
Ω
Z-5
Z
Z+5
(1) See the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DSP device BGA pad size.
(2) See the DDR2 device manufacturer documenation for the DDR2 device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.10.2.4 Placement
Figure 6-28 shows the required placement for the VCE6467T device as well as the DDR2 devices. The
dimensions for Figure 6-28 are defined in Table 6-35. The placement does not restrict the side of the PCB
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16 bit DDR memory systems, the high word DDR2
device is omitted from the placement.
X
A1
Y
OFFSET
DDR2
Device
Y
Y
DM646x
OFFSET
A1
Recommended DDR2 Device
Orientation
Figure 6-28. VCE6467T and DDR2 Device Placement
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Table 6-35. Placement Specifications
No. Parameter
Min
Max Unit
1660 Mils
1280 Mils
650 Mils
1
2
3
4
5
X(1) (2)
Y(1) (2)
Y Offset(1) (2) (3)
DDR2 Keepout Region(4)
Clearance from non-DDR2 signal to DDR2 Keepout Region(5)
4
w
(1) See Figure 6-26 for dimension defintions.
(2) Measurements from center of DSP device to center of DDR2 device.
(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.
(4) DDR2 Keepout region to encompass entire DDR2 routing area
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
6.10.2.5 DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 6-29. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in
Table 6-35.
A1
DDR2 Device
A1
Figure 6-29. DDR2 Keepout Region
NOTE
The region shown in Figure 6-29 should encompass all the DDR2 circuitry and varies
depending on placement. Non-DDR2 signals should not be routed on the DDR signal layers
within the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided
they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks
should be allowed in the reference ground layers in this region. In addition, the 1.8-V power
plane should cover the entire keep out region.
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6.10.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 6-36 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass
capacitance may be needed for other circuitry.
Table 6-36. Bulk Bypass Capacitors
No. Parameter
Min
3
Max
Unit
Devices
μF
1
2
3
4
5
6
DVDD18 Bulk Bypass Capacitor Count(1)
DVDD18 Bulk Bypass Total Capacitance
DDR#1 Bulk Bypass Capacitor Count(1)
DDR#1 Bulk Bypass Total Capacitance(1)
DDR#2 Bulk Bypass Capacitor Count(2)
DDR#2 Bulk Bypass Total Capacitance(1) (2)
30
1
Devices
μF
10
1
Devices
μF
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2) Only used on 32-bit wide DDR2 memory systems
6.10.2.7 High-Speed Bypass Capacitors
High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and
DSP/DDR ground connections. Table 6-37 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
6.10.2.8 Net Classes
Table 6-38 lists the clock net classes for the DDR2 interface. Table 6-39 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6-37. High-Speed Bypass Capacitors
No. Parameter
Min
Max
Unit
1
2
3
4
5
6
7
8
9
HS Bypass Capacitor Package Size(1)
0402 10 Mils
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
Trace length from bypass capacitor contact to connection via
Number of connection vias for each DSP device power or ground balls
Trace length from DSP device power ball to connection via
Number of connection vias for each DDR2 device power or ground balls
Trace length from DDR2 device power ball to connection via
DVDD18 HS Bypass Capacitor Count(3)
250
30
Mils
Vias
2
1
1
Mils
Vias
35
Mils
1
Vias
35
Mils
20
1.2
8
Devices
μF
10 DVDD18 HS Bypass Capacitor Total Capacitance
11 DDR#1 HS Bypass Capacitor Count(3)
Devices
μF
12 DDR#1 HS Bypass Capacitor Total Capacitance
13 DDR#2 HS Bypass Capacitor Count(3) (4)
14 DDR#2 HS Bypass Capacitor Total Capacitance(4)
0.4
8
Devices
μF
0.4
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Only used on 32-bit wide DDR2 memory systems
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Table 6-38. Clock Net Class Definitions
Clock Net Class
CK
DSP Pin Names
DDR_CLK/DDR_CLK
DDR_DQS0/DDR_DQS0
DDR_DQS1/DDR_DQS1
DDR_DQS2/DDR_DQS2
DDR_DQS3/DDR_DQS3
DQS0
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR2 memory systems.
Table 6-39. Signal Net Class Definitions
Associated Clock Net
Class
Clock Net Class
DSP Pin Names
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[14:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
DQ0
DQ1
DQS0
DDR_D[7:0], DDR_DQM0
DQS1
DDR_D[15:8], DDR_DQM1
DQ2(1)
DQ3(1)
DQGATEL
DQS2
DDR_D[23:16], DDR_DQM2
DDR_D[31:24], DDR_DQM3
DDR_DQGATE0, DDR_DQGATE1
DDR_DQGATE2, DDR_DQGATE3
DQS3
CK, DQS0, DQS1
CK, DQS2, DQS3
(1)
DQGATEH
(1) Only used on 32-bit wide DDR2 memory systems.
6.10.2.9 DDR2 Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-40 shows the specifications for the series terminators.
Table 6-40. DDR2 Signal Terminations
No. Parameter
Min
0
Typ
Max Unit
1
2
3
4
CK Net Class(1)
ADDR_CTRL Net Class(1) (2) (3)
Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3)(1) (2) (3) (4)
DQGATE Net Classes (DQGATEL, DQGATEH)(1) (2) (3)
10
Zo
Zo
Zo
Ω
Ω
Ω
Ω
0
22
22
10
0
0
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
(4) When no termination is used on data lines (0 Ωs), the DDR2 devices must be programmed to operate in 60% strength mode.
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6.10.2.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the VCE6467T’s.
VREF is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive
divider as shown in Figure 6-27. Other methods of creating VREF are not recommended. Figure 6-30
shows the layout guidelines for VREF.
VREF Bypass Capacitor
DDR2 Device
A1
VREF Nominal Minimum
DM646x
Device
Trace Width is 20 Mils
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 6-30. VREF Routing and Topology
6.10.2.11 DDR2 CK and ADDR_CTRL Routing
Figure 6-31 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
T
A
DM646x
A1
Figure 6-31. CK and ADDR_CTRL Routing and Topology
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Table 6-41. CK and ADDR_CTRL Routing Specification
No
1
Parameter
Min
Typ
Max
2w
25
Unit
Center to center CK-CK spacing
CK A to B/A to C Skew Length Mismatch(1)
2
Mils
Mils
3
CK B to C Skew Length Mismatch
25
4
Center to center CK to other DDR2 trace spacing(2)
CK/ADDR_CTRL nominal trace length(3)
4w
5
CACLM-50
CACLM
CACLM+50
100
Mils
Mils
Mils
6
ADDR_CTRL to CK Skew Length Mismatch
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
Center to center ADDR_CTRL to other DDR2 trace spacing(2)
Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(2)
ADDR_CTRL A to B/A to C Skew Length Mismatch(1)
ADDR_CTRL B to C Skew Length Mismatch
7
100
8
4w
3w
9
10
11
100
100
Mils
Mils
(1) Series terminator, if used, should be located closest to DSP.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 6-32 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
DM646x
T
E2
A1
T
E3
Figure 6-32. DQS and DQ Routing and Toplogy
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(1)
Table 6-42. DQS and DQ Routing Specification
No.
1
Parameter
Min
Typ
Max
2w
Unit
Center to center DQS-DQS spacing
2
DQS E Skew Length Mismatch
25
Mils
3
Center to center DQS to other DDR2 trace spacing(2)
DQS/DQ nominal trace length(1) (3) (4) (5)
DQ to DQS Skew Length Mismatch(3) (4) (5)
DQ to DQ Skew Length Mismatch(3) (4) (5)
DQ to DQ/DQS via count mismatch(3) (4) (5)
Center to center DQ to other DDR2 trace spacing(2) (6)
Center to center DQ to other DQ trace spacing(2) (7) (8)
DQ/DQS E Skew Length Mismatch(3) (4) (5)
4w
4
DQLM-50
DQLM
DQLM+50
Mils
Mils
Mils
Vias
5
100
100
1
6
7
8
4w
3w
9
10
100
Mils
(1) Series terminator, if used, should be located closest to DDR.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) A 16 bit DDR memory system will have two sets of data net classes, one for data byte 0, and one for data byte 1, each with an
associated DQS (2 DQS's).
(4) A 32 bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a
DQS (4 DQS's).
(5) There is no need and it is not recommended to skew match across data bytes, ie from DQS0 and data byte 0 to DQS1 and data byte 1.
(6) DQ's from other DQS domains are considered other DDR2 trace.
(7) DQ's from other data bytes are considered other DDR2 trace.
(8) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
Figure 6-33 shows the routing for the DQGATE net classes. Table 6-43 contains the routing specification.
A1
T
T
DM646x
A1
Figure 6-33. DQGATE Routing
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Table 6-43. DQGATE Routing Specification
No.
1
Parameter
DQGATEL Length F(1)
DQGATEH Length F(2) (3)
Min
Typ
Max
Unit
CKB0B1
CKB2B3
2
3
Center to center DQGATE to any other trace spacing
DQS/DQ nominal trace length
DQGATEL Skew(4)
4w
4
DQLM-50
DQLM
DQLM+50
100
Mils
Mils
Mils
5
6
DQGATEH Skew(3) (5)
100
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2) CKB2B3 is the sum of the length of the CK net plus the average length of the DQS2 and DQS3 nets.
(3) Only used in 32-bit wide DDR2 memory systems.
(4) Skew from CKB0B1
(5) Skew from CKB2B3
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6.11 Video Port Interface (VPIF)
The VCE6467T Video Port Interface (VPIF) allows the capture and display of digital video streams.
Features include:
•
•
108-MHz VPIF
Up to 2 Video Capture Channels (Channel 0 and Channel 1)
–
–
–
Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)
Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)
Single Raw Video (8-/10-/12-bit)
•
Up to 2 Video Display Channels (Channel 2 and Channel 3)
–
–
Two 8-bit SD Video Display with embedded timing codes (BT.656)
Single 16-bit HD Video Display with embedded timing codes (BT.1120)
The VPIF capture channel input data format is selectable based on the settings of the specific Channel
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings
of the Channel 0 Control Register. For more detailed information on these specific Channel Control
Registers, see the TMS320DM6467x DMSoC Video Port Interface (VPIF) User's Guide (Literature
Number SPRUER9).
6.11.1 VPIF Bus Master Memory Map
The VPIF peripheral includes a bus master interface that accesses the VCE6467T system bus to transfer
video-capture and video-display data. Table 6-44 shows the memory map for the VPIF master interface.
Table 6-44. VPIF Master Memory Map
START
ADDRESS
END
ADDRESS
SIZE
(BYTES)
VPIF MASTER INTERFACE
Reserved
0x0000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
2G
512M
512M
1G
DDR2 Memory Controller
Reserved
Reserved
6.11.2 VPIF Clock Control (Capture and Display)
The source clocks for the VPIF data channels are selectable based on the settings of the VIDCLKCTL
register (0x01C4 0038) (For the VIDCLKCTL register details, see Section 3.3.2.1, Video Clock Control
Register). The VSCLKDIS register (0x01C4 006C) is used to disable the clock inputs when changing the
clock source to ensure glitch-free operation. (For the VSCLKDIS register details, see Section 3.3.2.3,
Video and TSIF Clock Disable).
For both the VPIF dual 8-bit or 16-bit video-capture modes, Channel 0 is always clocked by VP_CLKIN0
(see Figure 6-34).
VPIF
Channel 0
Input Clock Source
VP_CLKIN0
VP_CLKIN0
VSCLKDIS.VID0
Figure 6-34. VPIF Capture Channel 0 Source Clock
Video-Capture Channel 1 is clocked by the VP_CLKIN1 signal, when the dual 8-bit capture mode is
enabled. When the 16-bit capture mode or 8-/10-/12-bit raw-capture mode is used, VP_CLKIN0 must be
selected as the clock source (VIDCLKCTL.VCH1CLK = 0) [see Figure 6-35].
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VIDCLKCTL.VCH1CLK
VP_CLKIN1
VP_CLKIN0
VPIF
Channel 1
Input Clock Source
VP_CLKIN1
VP_CLKIN0
1
0
VSCLKDIS.VID1
Figure 6-35. VPIF Capture Channel 1 Source Clock Selection
For both the dual 8-bit or 16-bit display modes, the VPIF Display Channel 2 outputs data synchronous to
VP_CLKO2. The source clock for the VP_CLKO2 output is selectable from a number of external clock
inputs or on-chip clock sources (see Figure 6-36).
VIDCLKCTL.VCH2CLK
111(A)
VP_CLKIN2
110
101
100
011
010
VP_CLKIN2
GP[4]/STC_CLKIN
VP_CLKIN0
STC_CLKIN
VP_CLKIN0
AUXCLK
PLL
Controller 1
SYSCLK8(B)
DEV_MXI/DEV_CLKIN
VPIF
Channel 2
Output Clock Source
CRG1_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
001
000
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
CRG0_VCXI
11x
10x
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
VSCLKDIS.VID2
(A) 111 = Reserved.
(B) For the -1G device, use an external clock source for the 54-/74.25-/108-MHz VPIF clock.
Figure 6-36. VPIF Display Channel 2 Source Clock Selection
For the dual 8-bit display mode, the VPIF Display Channel 3 outputs data synchronous to VP_CLKO3.
The source clock for the VP_CLKO3 output is selectable from a number of external clock inputs or on-chip
clock sources (see Figure 6-37). When the 16-bit display mode for Channel 3 is selected, the clock source
must match that of Channel 2 (VIDCLKCTL.VCH3CLK = VCH2CLK).
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VIDCLKCTL.VCH3CLK
VP_CLKIN3
111
VP_CLKIN3/TS1_CLKO
VP_CLKIN2
STC_CLKIN
VP_CLKIN0
AUXCLK
110
101
100
011
010
VP_CLKIN2
GP[4]/STC_CLKIN
VP_CLKIN0
VPIF
Channel 3
Output Clock Source
SYSCLK8(A)
PLL
Controller 1
DEV_MXI/DEV_CLKIN
CRG1_VCXI
CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
001
000
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
VSCLKDIS.VID3
(A) For the -1G device, use an external clock source for the 54-/74.25-/108-MHz VPIF clock.
Figure 6-37. VPIF Display Channel 3 Source Clock Selection
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6.11.3 VPIF Register Descriptions
Table 6-45 shows the VPIF registers.
Table 6-45. Video Port Interface (VPIF) Registers
HEX ADDRESS RANGE
0x01C1 2000
ACRONYM
PID
REGISTER NAME
Peripheral identification register
0x01C1 2004
CH0_CTRL
CH1_CTRL
CH2_CTRL
CH3_CTRL
-
Channel 0 control register
Channel 1 control register
Channel 2 control register
Channel 3 control register
Reserved
0x01C1 2008
0x01C1 200C
0x01C1 2010
0x01C1 2014 - 0x01C1 201F
0x01C1 2020
INTEN
Interrupt enable
0x01C1 2024
INTENSET
INTENCLR
INTSTAT
INTSTATCLR
EMU_CTRL
DMA_SIZE
-
Interrupt enable set
Interrupt enable clear
Interrupt status
0x01C1 2028
0x01C1 202C
0x01C1 2030
Interrupt status clear
Emulation control
0x01C1 2034
0x01C1 2038
DMA size control
0x01C1 203C - 0x01C1 203F
Reserved
CAPTURE CHANNEL 0 REGISTERS
CH0_TY_STRTADR Channel 0 Top Field luma buffer start address
0x01C1 2040
0x01C1 2044
0x01C1 2048
0x01C1 204C
0x01C1 2050
0x01C1 2054
0x01C1 2058
0x01C1 205C
0x01C1 2060
0x01C1 2064
0x01C1 2068
0x01C1 206C
0x01C1 2070
0x01C1 2074
0x01C1 2078
0x01C1 207C
CH0_BY_STRTADR
CH0_TC_STRTADR
CH0_BC_STRTADR
CH0_THA_STRTADR
CH0_BHA_STRTADR
CH0_TVA_STRTADR
CH0_BVA_STRTADR
CH0_SUBPIC_CFG
Channel 0 Bottom Field luma buffer start address
Channel 0 Top Field chroma buffer start address
Channel 0 Bottom Field chroma buffer start address
Channel 0 Top Field horizontal ancillary data buffer start address
Channel 0 Bottom Field horizontal ancillary data buffer start address
Channel 0 Top Field vertical ancillary data buffer start address
Channel 0 Bottom Field vertical ancillary data buffer start address
Channel 0 sub-picture configuration
CH0_IMG_ADD_OFST Channel 0 image data address offset
CH0_HA_ADD_OFST
CH0_HSIZE_CFG
CH0_VSIZE_CFG0
CH0_VSIZE_CFG1
CH0_VSIZE_CFG2
CH0_VSIZE
Channel 0 horizontal ancillary data address offset
Channel 0 horizontal data size configuration
Channel 0 vertical data size configuration (0)
Channel 0 vertical data size configuration (1)
Channel 0 vertical data size configuration (2)
Channel 0 vertical image size
CAPTURE CHANNEL 1 REGISTERS
0x01C1 2080
0x01C1 2084
0x01C1 2088
0x01C1 208C
0x01C1 2090
0x01C1 2094
0x01C1 2098
0x01C1 209C
0x01C1 20A0
0x01C1 20A4
0x01C1 20A8
0x01C1 20AC
CH1_TY_STRTADR
CH1_BY_STRTADR
CH1_TC_STRTADR
CH1_BC_STRTADR
CH1_THA_STRTADR
CH1_BHA_STRTADR
CH1_TVA_STRTADR
CH1_BVA_STRTADR
CH1_SUBPIC_CFG
Channel 1 Top Field luma buffer start address
Channel 1 Bottom Field luma buffer start address
Channel 1 Top Field chroma buffer start address
Channel 1 Bottom Field chroma buffer start address
Channel 1 Top Field horizontal ancillary data buffer start address
Channel 1 Bottom Field horizontal ancillary data buffer start address
Channel 1 Top Field vertical ancillary data buffer start address
Channel 1 Bottom Field vertical ancillary data buffer start address
Channel 1 sub-picture configuration
CH1_IMG_ADD_OFST Channel 1 image data address offset
CH1_HA_ADD_OFST
CH1_HSIZE_CFG
Channel 1 horizontal ancillary data address offset
Channel 1 horizontal data size configuration
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Table 6-45. Video Port Interface (VPIF) Registers (continued)
HEX ADDRESS RANGE
0x01C1 20B0
ACRONYM
REGISTER NAME
Channel 1 vertical data size configuration (0)
Channel 1 vertical data size configuration (1)
Channel 1 vertical data size configuration (2)
Channel 1 vertical image size
CH1_VSIZE_CFG0
CH1_VSIZE_CFG1
CH1_VSIZE_CFG2
CH1_VSIZE
0x01C1 20B4
0x01C1 20B8
0x01C1 20BC
DISPLAY CHANNEL 2 REGISTERS
0x01C1 20C0
0x01C1 20C4
0x01C1 20C8
0x01C1 20CC
0x01C1 20D0
0x01C1 20D4
0x01C1 20D8
0x01C1 20DC
0x01C1 20E0
0x01C1 20E4
0x01C1 20E8
0x01C1 20EC
0x01C1 20F0
0x01C1 20F4
0x01C1 20F8
0x01C1 20FC
0x01C1 2100
0x01C1 2104
0x01C1 2108
0x01C1 210C
0x01C1 2110
0x01C1 2114
0x01C1 2118
0x01C1 211C
0x01C1 2120 - 0x01C1 213F
CH2_TY_STRTADR
CH2_BY_STRTADR
CH2_TC_STRTADR
CH2_BC_STRTADR
CH2_THA_STRTADR
CH2_BHA_STRTADR
CH2_TVA_STRTADR
CH2_BVA_STRTADR
CH2_SUBPIC_CFG
Channel 2 Top Field luma buffer start address
Channel 2 Bottom Field luma buffer start address
Channel 2 Top Field chroma buffer start address
Channel 2 Bottom Field chroma buffer start address
Channel 2 Top Field horizontal ancillary data buffer start address
Channel 2 Bottom Field horizontal ancillary data buffer start address
Channel 2 Top Field vertical ancillary data buffer start address
Channel 2 Bottom Field vertical ancillary data buffer start address
Channel 2 sub-picture configuration
CH2_IMG_ADD_OFST Channel 2 image data address offset
CH2_HA_ADD_OFST
CH2_HSIZE_CFG
CH2_VSIZE_CFG0
CH2_VSIZE_CFG1
CH2_VSIZE_CFG2
CH2_VSIZE
Channel 2 horizontal ancillary data address offset
Channel 2 horizontal data size configuration
Channel 2 vertical data size configuration (0)
Channel 2 vertical data size configuration (1)
Channel 2 vertical data size configuration (2)
Channel 2 vertical image size
CH2_THA_STRTPOS
CH2_THA_SIZE
CH2_BHA_STRTPOS
CH2_BHA_SIZE
CH2_TVA_STRTPOS
CH2_TVA_SIZE
CH2_BVA_STRTPOS
CH2_BVA_SIZE
-
Channel 2 Top Field horizontal ancillary data insertion start position
Channel 2 Top Field horizontal ancillary data size
Channel 2 Bottom Field horizontal ancillary data insertion start position
Channel 2 Bottom Field horizontal ancillary data size
Channel 2 Top Field vertical ancillary data insertion start position
Channel 2 Top Field vertical ancillary data size
Channel 2 Bottom Field vertical ancillary data insertion start position
Channel 2 Bottom Field vertical ancillary data size
Reserved
DISPLAY CHANNEL 3 REGISTERS
0x01C1 2140
0x01C1 2144
0x01C1 2148
0x01C1 214C
0x01C1 2150
0x01C1 2154
0x01C1 2158
0x01C1 215C
0x01C1 2160
0x01C1 2164
0x01C1 2168
0x01C1 216C
0x01C1 2170
0x01C1 2174
0x01C1 2178
0x01C1 217C
CH3_TY_STRTADR
CH3_BY_STRTADR
CH3_TC_STRTADR
CH3_BC_STRTADR
CH3_THA_STRTADR
CH3_BHA_STRTADR
CH3_TVA_STRTADR
CH3_BVA_STRTADR
CH3_SUBPIC_CFG
Channel 3 Field 0 luma buffer start address
Channel 3 Field 1 luma buffer start address
Channel 3 Field 0 chroma buffer start address
Channel 3 Field 1 chroma buffer start address
Channel 3 Field 0 horizontal ancillary data buffer start address
Channel 3 Field 1 horizontal ancillary data buffer start address
Channel 3 Field 0 vertical ancillary data buffer start address
Channel 3 Field 1 vertical ancillary data buffer start address
Channel 3 sub-picture configuration
CH3_IMG_ADD_OFST Channel 3 image data address offset
CH3_HA_ADD_OFST
CH3_HSIZE_CFG
CH3_VSIZE_CFG0
CH3_VSIZE_CFG1
CH3_VSIZE_CFG2
CH3_VSIZE
Channel 3 horizontal ancillary data address offset
Channel 3 horizontal data size configuration
Channel 3 vertical data size configuration (0)
Channel 3 vertical data size configuration (1)
Channel 3 vertical data size configuration (2)
Channel 3 vertical image size
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Table 6-45. Video Port Interface (VPIF) Registers (continued)
HEX ADDRESS RANGE
ACRONYM
CH3_THA_STRTPOS
CH3_THA_SIZE
CH3_BHA_STRTPOS
CH3_BHA_SIZE
CH3_TVA_STRTPOS
CH3_TVA_SIZE
CH3_BVA_STRTPOS
CH3_BVA_SIZE
-
REGISTER NAME
0x01C1 2180
Channel 3 Top Field horizontal ancillary data insertion start position
Channel 3 Top Field horizontal ancillary data size
Channel 3 Bottom Field horizontal ancillary data insertion start position
Channel 3 Bottom Field horizontal ancillary data size
Channel 3 Top Field vertical ancillary data insertion start position
Channel 3 Top Field vertical ancillary data size
0x01C1 2184
0x01C1 2188
0x01C1 218C
0x01C1 2190
0x01C1 2194
0x01C1 2198
Channel 3 Bottom Field vertical ancillary data insertion start position
Channel 3 Bottom Field vertical ancillary data size
Reserved
0x01C1 219C
0x01C1 21A0 - 0x01C1 21FF
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6.11.4 VPIF Electrical Data/Timing
Table 6-46. Timing Requirements for VPIF VP_CLKINx Inputs(1) (see Figure 6-38)
-1G
MIN
NO.
UNIT
MAX
1
2
3
4
tc(VKI)
Cycle time, VP_CLKIN0/1/2/3
Pulse duration, VP_CLKINx high
Pulse duration, VP_CLKINx low
Transition time, VP_CLKINx
9.25
0.4C
0.4C
ns
ns
ns
ns
tw(VKIH)
tw(VKIL)
tt(VKI)
5
(1) C = VP_CLKINx period in ns.
4
1
2
3
VP_CLKINx
4
Figure 6-38. Video Port Capture VP_CLKINx Timing
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Table 6-47. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs
(see Figure 6-39)
-1G
NO.
UNIT
MIN
2.55
0
MAX
1
2
tsu(VDINV-VKIH)
th(VKIH-VDINV)
Setup time, VP_DINx valid before VP_CLKIN0/1 high
Hold time, VP_DINx valid after VP_CLKIN0/1 high
ns
ns
VP_CLKIN0/1
1
2
VP_DINx/FIELD/
HSYNC/VSYNC
Figure 6-39. VPIF Channels 0/1 Video Capture Data and Control Input Timing
Table 6-48. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown
With Respect to VP_CLKO2/3(1)
(see Figure 6-40)
-1G
NO.
PARAMETER
UNIT
MIN
9.25
0.4C
0.4C
MAX
1
2
3
4
tc(VKO)
Cycle time, VP_CLKO2/3
ns
ns
ns
ns
ns
tw(VKOH)
tw(VKOL)
tt(VKO)
Pulse duration, VP_CLKO2/3 high
Pulse duration, VP_CLKO2/3 low
Transition time, VP_CLKO2/3
5
11 td(VKOH-VPDOUTV)
Delay time, VP_CLKO2/3 high to VP_DOUTx valid
6.5
td(VCLKOH-
VPDOUTIV)
12
Delay time, VP_CLKO2/3 high to VP_DOUTx invalid
1.5
ns
(1) C = VP_CLKO2/3 period in ns.
2
1
VP_CLKOx
(Positive Edge
Clocking)
3
4
4
VP_CLKOx
(Negative Edge
Clocking)
12
11
VP_DOUTx
Figure 6-40. VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKO2/3
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6.12 Transport Stream Interface (TSIF)
The VCE6467T device includes two independent Transport Stream Interfaces (TSIF0 and TSIF1) with
corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery. The TSIF
peripheral supports the following features:
•
1-bit Serial and 8-bit Parallel independent receive and transmit interfaces with both synchronous and
asynchronous modes. (TSIF1 supports Serial mode only.)
•
•
•
Stream input/output (I/O) speed rate configurable by the I/O clock speed
ATS (absolute time stamp) detection, correction, and addition modes
Automatically detects PAT and PMT and reflects assignment to the internal Packet Identification (PID)
table (supported for partial Transfer Stream [TS] mode only; stream type and PID should be
one-to-one mapping)
•
•
PID filter with 7 PID filter tables and stream type assignments
BYPASS mode implemented so that not only TS data, but any other data can be received or
transmitted by the TSIF module
•
•
•
Ring buffer control for both writes (8 channels) and reads (1 channel) to/from memory
Supports “Specific Packet”, indicating boundary of plural program on TS
Supports Full-TS in only one mode–Semi-Automatic-A mode, allowing communication to the C64x+
CPU.
•
Supports Partial-TS in these modes–Semi-Automatic-B mode and Full-Automatic mode (provided
stream type and PID are one-to-one mapping)
For more detailed information on the CRGEN peripheral, see the TMS320DM646x DMSoC Clock
Reference Generator User's Guide (literature number SPRUEQ1).
6.12.1 TSIF Bus Master
The TSIF peripherals each include a bus master interface that accesses the DM646x system bus to
transfer stream receive and transmit data. Table 6-49 shows the memory map for the TSIF master
interfaces.
Table 6-49. TSIF0/1 Master Memory Map
SIZE
START ADDRESS
END ADDRESS
TSIF0/1 ACCESS
Reserved
(BYTES)
256M
64K
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x4A00 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
16256K
784M
32M
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
32M
32M
32M
32M
64M
VLYNQ (Remote Data)
Reserved
768M
512M
512M
1G
DDR2 Memory Controller
Reserved
Reserved
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6.12.2 TSIF Clock Control
The source clocks for the TSIF counters and output channels are selectable based on the settings of the
TSIFCTL register (0x01C4 0050). (For more detailed information on the TSIFCTL register, see
Section 3.3.2.2, TSIF Control.) The VSCLKDIS register (0x01C4 006C) is used to disable the clock inputs
when changing the clock source to ensure glitch-free operation. (For more detailed informaiton on the
VSCLKDIS register, see Section 3.3.2.3, Video and TSIF Clock Disable.)
TSIF0 outputs data synchronous to TS0_CLKO. The source clock for the TS0_CLKO output is selectable
from among a number of external clock inputs or on-chip clock sources (see Figure 6-41).
TSIFCTL.PTSO_CLK
CRG1_VCXI
111
110
101
100
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
TS0_CLKIN
VP_CLKIN1
VP_CLKIN0
SYSCLKBP
SYSCLK5
TS0_CLKIN
VP_CLKIN1
VP_CLKIN0
011
010
TSIF0
Output Clock Source
PLL
Controller 1
DEV_MXI/DEV_CLKIN
STC_CLKIN
CRG0_VCXI
GP[4]/STC_CLKIN
001
000
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
VSCLKDIS.TSIFTX0
Figure 6-41. TSIF0 Output Clock Source Selection
The TSIF0 system time counter may be clocked from a number of external clock inputs or on-chip clock
sources (see Figure 6-42).
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TSIFCTL.TSIF0_CNTCLK
VP_CLKIN1
101
VP_CLKIN1
VP_CLKIN0
VP_CLKIN0
CRG1_VCXI
100
011
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
TSIF0
Counter Clock
AUXCLK
PLL
Controller 1
010
001
DEV_MXI/DEV_CLKIN
STC_CLKIN
GP[4]/STC_CLKIN
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
CRG0_VCXI
000
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
VSCLKDIS.TSIFCNT0
(A) 110, 111 = Reserved.
Figure 6-42. TSIF0 Counter Clock Selection
TSIF1 outputs data synchronous to TS1_CLKO. The source clock for the TS1_CLKO output is selectable
from among a number of external clock inputs or on-chip clock sources (see Figure 6-43).
TSIFCTL.TSSO_CLK
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
CRG0_VCXI
1000
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
PINMUX0.CRGMUX
VP_CLKIN2
TS1_CLKIN
VP_CLKIN0
SYSCLKBP
SYSCLK6
0110
0101
0100
0011
0010
VP_CLKIN2
TS1_CLKIN
VP_CLKIN0
TSIF1
Output Clock Source
PLL
Controller 1
DEV_MXI/DEV_CLKIN
STC_CLKIN
CRG1_VCXI
GP[4]/STC_CLKIN
0001
0000
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
VSCLKDIS.TSIFTX1
(A) 0111, 1001–1xx1 = Reserved.
Figure 6-43. TSIF1 Output Clock Source Selection
The TSIF1 system time counter may be clocked from a number of external clock inputs or on-chip clock
sources (see Figure 6-44).
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TSIFCTL.TSIF1_CNTCLK
VP_CLKIN3
101
VP_CLKIN3/TS1_CLKO
VP_CLKIN2
VP_CLKIN2
100
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
CRG0_VCXI
011
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
TSIF1
Counter Clock
PINMUX0.CRGMUX
AUXCLK
PLL
Controller 1
010
DEV_MXI/DEV_CLKIN
STC_CLKIN
CRG1_VCXI
GP[4]/STC_CLKIN
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
001
000
VSCLKDIS.TSIFCNT1
(A) 110, 111 = Reserved.
Figure 6-44. TSIF1 Counter Clock Selection
6.12.3 TSIF Peripheral Register Description(s)
The TSIF0 and TSIF1 registers are shown in Table 6-50 and Table 6-51, respectively.
Table 6-50. TSIF0 Registers
HEX ADDRESS RANGE
0x01C1 3000
ACRONYM
PID
REGISTER NAME
TSIF0 peripheral identification (PID) register
Control register 0 register
0x01C1 3004
0x01C1 3008
0x01C1 300C
0x01C1 3010
0x01C1 3014
0x01C1 3018
0x01C1 301C
0x01C1 3020
0x01C1 3024
0x01C1 3028
0x01C1 302C
0x01C1 3030
0x01C1 3034
0x01C1 3038
0x01C1 303C
0x01C1 3040
0x01C1 3044
0x01C1 3048
0x01C1 304C
0x01C1 3050
0x01C1 3054
CTRL0
CTRL1
Control register 1 register
INTEN
Interrupt enable register
INTEN_SET
Interrupt enable set register
INTEN_CLR
Interrupt enable clear register
INTSTAT
Interrupt status register
INTSTAT_CLR
EMU_CTRL
Interrupt status clear register
Emulation control register
ASYNC_TX_WAIT
PAT_SEN_CFG
PAT_STR_ADDR
PMT_SEN_CFG
PMT_STR_ADDR
BSP_IN
Asynchronous transmit wait time register
Program association table (PAT) sense configuration register
PAT store address register
Program map table (PMT) sense configuration register
PMT store address register
Boundary sensing packet (BSP) in register
BSP in store address register
BSP_STORE_ADDR
PCR_SENSE_CFG
PID0_FILT_CFG
PID1_FILT_CFG
PID2_FILT_CFG
PID3_FILT_CFG
PID4_FILT_CFG
Program clock reference (PCR) sense configuration register
Packet Identifier (PID) 0 (PID0) filter configuration register
PID1 filter configuration register
PID2 filter configuration register
PID3 filter configuration register
PID4 filter configuration register
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Table 6-50. TSIF0 Registers (continued)
HEX ADDRESS RANGE
0x01C1 3058
ACRONYM
PID5_FILT_CFG
PID6_FILT_CFG
BYPASS_CFG
TX_ATS_INIT
TX_ATS_MON
–
REGISTER NAME
PID5 filter configuration register
0x01C1 305C
PID6 filter configuration register
0x01C1 3060
Bypass mode configuration register
Transmit Arrival Time Stamp (ATS) initialization register
Transmit ATS monitor register
0x01C1 3064
0x01C1 3068
0x01C1 306C
Reserved
0x01C1 3070
RX_PKT_STAT
–
Receive packet status register
0x01C1 3074 - 0x01C1 307F
0x01C1 3080
Reserved
STC_INIT_CTRL
STC_INIT_VAL
STC_INT0
System Time Clock (STC) initialization control register
STC initialization value register
0x01C1 3084
0x01C1 3088
STC interrupt entry 0 register
0x01C1 308C
STC_INT1
STC interrupt entry 1 register
0x01C1 3090
STC_INT2
STC interrupt entry 2 register
0x01C1 3094
STC_INT3
STC interrupt entry 3 register
0x01C1 3098
STC_INT4
STC interrupt entry 4 register
0x01C1 309C
STC_INT5
STC interrupt entry 5 register
0x01C1 30A0
STC_INT6
STC interrupt entry 6 register
0x01C1 30A4
STC_INT7
STC interrupt entry 7 register
0x01C1 30A8 - 0x01C1 30BF
0x01C1 30C0
–
Reserved
WRB_CTRL
WRB0_STRT_ADDR
WRB0_END_ADDR
WRB0_RDPTR
WRB0_SUB
WRB0_WRPTR
–
Write ring buffer channel control register
Write ring buffer channel 0 start address register
Write ring buffer channel 0 end address register
Write ring buffer channel 0 read pointer register
Write ring buffer channel 0 subtraction register
Write ring buffer channel 0 write pointer register
Reserved
0x01C1 30C4
0x01C1 30C8
0x01C1 30CC
0x01C1 30D0
0x01C1 30D4
0x01C1 30D8 - 0x01C1 30DF
0x01C1 30E0
WRB1_STRT_ADDR
WRB1_END_ADDR
WRB1_RDPTR
WRB1_SUB
WRB1_WRPTR
–
Write ring buffer channel 1 start address register
Write ring buffer channel 1 end address register
Write ring buffer channel 1 read pointer register
Write ring buffer channel 1 subtraction register
Write ring buffer channel 1 write pointer register
Reserved
0x01C1 30E4
0x01C1 30E8
0x01C1 30EC
0x01C1 30F0
0x01C1 30F4 - 0x01C1 30FF
0x01C1 3100
WRB2_STRT_ADDR
WRB2_END_ADDR
WRB2_RDPTR
WRB2_SUB
WRB2_WRPTR
–
Write ring buffer channel 2 start address register
Write ring buffer channel 2 end address register
Write ring buffer channel 2 read pointer register
Write ring buffer channel 2 subtraction register
Write ring buffer channel 2 write pointer register
Reserved
0x01C1 3104
0x01C1 3108
0x01C1 310C
0x01C1 3110
0x01C1 3114 - 0x01C1 311F
0x01C1 3120
WRB3_STRT_ADDR
WRB3_END_ADDR
WRB3_RDPTR
WRB3_SUB
WRB3_WRPTR
–
Write ring buffer channel 3 start address register
Write ring buffer channel 3 end address register
Write ring buffer channel 3 read pointer register
Write ring buffer channel 3 subtraction register
Write ring buffer channel 3 write pointer register
Reserved
0x01C1 3124
0x01C1 3128
0x01C1 312C
0x01C1 3130
0x01C1 3134 - 0x01C1 313F
0x01C1 3140
WRB4_STRT_ADDR
WRB4_END_ADDR
WRB4_RDPTR
Write ring buffer channel 4 start address register
Write ring buffer channel 4 end address register
Write ring buffer channel 4 read pointer register
0x01C1 3144
0x01C1 3148
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Table 6-50. TSIF0 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
WRB4_SUB
WRB4_WRPTR
–
REGISTER NAME
Write ring buffer channel 4 subtraction register
0x01C1 314C
0x01C1 3150
Write ring buffer channel 4 write pointer register
Reserved
0x01C1 3154 - 0x01C1 315F
0x01C1 3160
WRB5_STRT_ADDR
WRB5_END_ADDR
WRB5_RDPTR
WRB5_SUB
WRB5_WRPTR
–
Write ring buffer channel 5 start address register
Write ring buffer channel 5 end address register
Write ring buffer channel 5 read pointer register
Write ring buffer channel 5 subtraction register
Write ring buffer channel 5 write pointer register
Reserved
0x01C1 3164
0x01C1 3168
0x01C1 316C
0x01C1 3170
0x01C1 3174 - 0x01C1 317F
0x01C1 3180
WRB6_STRT_ADDR
WRB6_END_ADDR
WRB6_RDPTR
WRB6_SUB
WRB6_WRPTR
–
Write ring buffer channel 6 start address register
Write ring buffer channel 6 end address register
Write ring buffer channel 6 read pointer register
Write ring buffer channel 6 subtraction register
Write ring buffer channel 6 write pointer register
Reserved
0x01C1 3184
0x01C1 3188
0x01C1 318C
0x01C1 3190
0x01C1 3194 - 0x01C1 319F
0x01C1 31A0
WRB7_STRT_ADDR
WRB7_END_ADDR
WRB7_RDPTR
WRB7_SUB
WRB7_WRPTR
–
Write ring buffer channel 7 start address register
Write ring buffer channel 7 end address register
Write ring buffer channel 7 read pointer register
Write ring buffer channel 7 subtraction register
Write ring buffer channel 7 write pointer register
Reserved
0x01C1 31A4
0x01C1 31A8
0x01C1 31AC
0x01C1 31B0
0x01C1 31B4 - 0x01C1 31BF
0x01C1 31C0
RRB_CTRL
Read ring buffer channel control register
Read ring buffer channel start address register
Read ring buffer channel end address register
Read ring buffer channel write pointer register
Read ring buffer channel subtraction register
Read ring buffer channel read pointer register
Packet counter value register
0x01C1 31C4
RRB_STRT_ADDR
RRB_END_ADDR
RRB_WRPTR
RRB_SUB
0x01C1 31C8
0x01C1 31CC
0x01C1 31D0
0x01C1 31D4
RRB_RDPTR
PKT_CNT
0x01C1 31D8
0x01C1 31DC - 0x01C1 31FF
–
Reserved
Table 6-51. TSIF1 Registers
HEX ADDRESS RANGE
0x01C1 3400
0x01C1 3404
0x01C1 3408
0x01C1 340C
0x01C1 3410
0x01C1 3414
0x01C1 3418
0x01C1 341C
0x01C1 3420
0x01C1 3424
0x01C1 3428
0x01C1 342C
0x01C1 3430
0x01C1 3434
0x01C1 3438
ACRONYM
PID
REGISTER NAME
TSIF1 peripheral identification (PID) register
Control register 0 register
CTRL0
CTRL1
Control register 1 register
INTEN
Interrupt enable register
INTEN_SET
INTEN_CLR
INTSTAT
Interrupt enable set register
Interrupt enable clear register
Interrupt status register
INTSTAT_CLR
EMU_CTRL
ASYNC_TX_WAIT
PAT_SEN_CFG
PAT_STR_ADDR
PMT_SEN_CFG
PMT_STR_ADDR
BSP_IN
Interrupt status clear register
Emulation control register
Asynchronous transmit wait time register
Program association table (PAT) sense configuration register
PAT store address register
Program map table (PMT) sense configuration register
PMT store address register
Boundary sensing packet (BSP) in register
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Table 6-51. TSIF1 Registers (continued)
HEX ADDRESS RANGE
0x01C1 343C
ACRONYM
BSP_STORE_ADDR
PCR_SENSE_CFG
PID0_FILT_CFG
PID1_FILT_CFG
PID2_FILT_CFG
PID3_FILT_CFG
PID4_FILT_CFG
PID5_FILT_CFG
PID6_FILT_CFG
BYPASS_CFG
TX_ATS_INIT
TX_ATS_MON
–
REGISTER NAME
BSP in store address register
0x01C1 3440
Program clock reference (PCR) sense configuration register
Packet Identifier (PID) 0 (PID0) filter configuration register
PID1 filter configuration register
0x01C1 3444
0x01C1 3448
0x01C1 344C
PID2 filter configuration register
0x01C1 3450
PID3 filter configuration register
0x01C1 3454
PID4 filter configuration register
0x01C1 3458
PID5 filter configuration register
0x01C1 345C
PID6 filter configuration register
0x01C1 3460
Bypass mode configuration register
Transmit Arrival Time Stamp (ATS) initialization register
Transmit ATS monitor register
0x01C1 3064
0x01C1 3468
0x01C1 346C
Reserved
0x01C1 3470
RX_PKT_STAT
–
Receive packet status register
0x01C1 3474 - 0x01C1 347F
0x01C1 3480
Reserved
STC_INIT_CTRL
STC_INIT_VAL
STC_INT0
System Time Clock (STC) initialization control register
STC initialization value register
0x01C1 3484
0x01C1 3488
STC interrupt entry 0 register
0x01C1 348C
STC_INT1
STC interrupt entry 1 register
0x01C1 3490
STC_INT2
STC interrupt entry 2 register
0x01C1 3494
STC_INT3
STC interrupt entry 3 register
0x01C1 3498
STC_INT4
STC interrupt entry 4 register
0x01C1 349C
STC_INT5
STC interrupt entry 5 register
0x01C1 34A0
STC_INT6
STC interrupt entry 6 register
0x01C1 34A4
STC_INT7
STC interrupt entry 7 register
0x01C1 34A8 - 0x01C1 34BF
0x01C1 34C0
–
Reserved
WRB_CTRL
Write ring buffer channel control register
Write ring buffer channel 0 start address register
Write ring buffer channel 0 end address register
Write ring buffer channel 0 read pointer register
Write ring buffer channel 0 subtraction register
Write ring buffer channel 0 write pointer register
Reserved
0x01C1 34C4
WRB0_STRT_ADDR
WRB0_END_ADDR
WRB0_RDPTR
WRB0_SUB
0x01C1 34C8
0x01C1 34CC
0x01C1 34D0
0x01C1 34D4
WRB0_WRPTR
–
0x01C1 34D8 - 0x01C1 34DF
0x01C1 34E0
WRB1_STRT_ADDR
WRB1_END_ADDR
WRB1_RDPTR
WRB1_SUB
Write ring buffer channel 1 start address register
Write ring buffer channel 1 end address register
Write ring buffer channel 1 read pointer register
Write ring buffer channel 1 subtraction register
Write ring buffer channel 1 write pointer register
Reserved
0x01C1 34E4
0x01C1 34E8
0x01C1 34EC
0x01C1 34F0
WRB1_WRPTR
–
0x01C1 34F4 - 0x01C1 34FF
0x01C1 3500
WRB2_STRT_ADDR
WRB2_END_ADDR
WRB2_RDPTR
WRB2_SUB
Write ring buffer channel 2 start address register
Write ring buffer channel 2 end address register
Write ring buffer channel 2 read pointer register
Write ring buffer channel 2 subtraction register
Write ring buffer channel 2 write pointer register
Reserved
0x01C1 3504
0x01C1 3508
0x01C1 350C
0x01C1 3510
WRB2_WRPTR
–
0x01C1 3514 - 0x01C1 351F
0x01C1 3520
WRB3_STRT_ADDR
WRB3_END_ADDR
Write ring buffer channel 3 start address register
Write ring buffer channel 3 end address register
0x01C1 3524
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Table 6-51. TSIF1 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
WRB3_RDPTR
WRB3_SUB
REGISTER NAME
Write ring buffer channel 3 read pointer register
0x01C1 3528
0x01C1 352C
Write ring buffer channel 3 subtraction register
Write ring buffer channel 3 write pointer register
Reserved
0x01C1 3530
WRB3_WRPTR
–
0x01C1 3534 - 0x01C1 353F
0x01C1 3540
WRB4_STRT_ADDR
WRB4_END_ADDR
WRB4_RDPTR
WRB4_SUB
Write ring buffer channel 4 start address register
Write ring buffer channel 4 end address register
Write ring buffer channel 4 read pointer register
Write ring buffer channel 4 subtraction register
Write ring buffer channel 4 write pointer register
Reserved
0x01C1 3544
0x01C1 3548
0x01C1 354C
0x01C1 3550
WRB4_WRPTR
–
0x01C1 3554 - 0x01C1 355F
0x01C1 3560
WRB5_STRT_ADDR
WRB5_END_ADDR
WRB5_RDPTR
WRB5_SUB
Write ring buffer channel 5 start address register
Write ring buffer channel 5 end address register
Write ring buffer channel 5 read pointer register
Write ring buffer channel 5 subtraction register
Write ring buffer channel 5 write pointer register
Reserved
0x01C1 3564
0x01C1 3568
0x01C1 356C
0x01C1 3570
WRB5_WRPTR
–
0x01C1 3574 - 0x01C1 357F
0x01C1 3580
WRB6_STRT_ADDR
WRB6_END_ADDR
WRB6_RDPTR
WRB6_SUB
Write ring buffer channel 6 start address register
Write ring buffer channel 6 end address register
Write ring buffer channel 6 read pointer register
Write ring buffer channel 6 subtraction register
Write ring buffer channel 6 write pointer register
Reserved
0x01C1 3584
0x01C1 3588
0x01C1 358C
0x01C1 3590
WRB6_WRPTR
–
0x01C1 3594 - 0x01C1 359F
0x01C1 35A0
WRB7_STRT_ADDR
WRB7_END_ADDR
WRB7_RDPTR
WRB7_SUB
Write ring buffer channel 7 start address register
Write ring buffer channel 7 end address register
Write ring buffer channel 7 read pointer register
Write ring buffer channel 7 subtraction register
Write ring buffer channel 7 write pointer register
Reserved
0x01C1 35A4
0x01C1 35A8
0x01C1 35AC
0x01C1 35B0
WRB7_WRPTR
–
0x01C1 35B4 - 0x01C1 35BF
0x01C1 35C0
RRB_CTRL
Read ring buffer channel control register
Read ring buffer channel start address register
Read ring buffer channel end address register
Read ring buffer channel write pointer register
Read ring buffer channel subtraction register
Read ring buffer channel read pointer register
Packet counter value register
0x01C1 35C4
RRB_STRT_ADDR
RRB_END_ADDR
RRB_WRPTR
RRB_SUB
0x01C1 35C8
0x01C1 35CC
0x01C1 35D0
0x01C1 35D4
RRB_RDPTR
PKT_CNT
0x01C1 35D8
0x01C1 35DC - 0x01C1 35FF
–
Reserved
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6.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing
Table 6-52. Timing Requirements for TSIF Input (see Figure 6-45)
-1G
SERIAL
INPUT
PARALLEL
INPUT(1)
NO.
UNIT
MIN
10
MAX
MIN
16.7
0.4C
MAX
1
2
3
tc(TSCLKIN)
tw(TSCLKIN)
tt(TSCLKIN)
Cycle time, TSx_CLKIN
Pulse duration, TSx_CLKIN high/low(2)
ns
ns
ns
ns
0.4C
Transition time, TSx_CLKIN
3(3)
3(3)
All Others
4
4
Setup time, TSx_CTL/TSx_DATA(4) input valid
before TSx_CLKIN edge
4
5
tsu(TSDATAIN-TSCLKINV)
TSx_WAIT
IN
13
13
ns
ns
Hold time, TSx_CTL/TSx_DATA(4) input valid after
TSx_CLKIN edge
th(TSCLKINV-TSDATAIN)
0
0
(1) TSIF1 supports SERIAL INPUT mode only.
(2) C = TSx_CLKIN period (cycle time) in ns.
(3) For a 4-inch transmission line with 4-pF load capacitance at the device pin.
(4) TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel input. For a serial
input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and TS0_DIN7 or TS1_DIN.
1
2
2
3
3
TSx_CLKIN
(Positive Edge Clocking)
TSx_CLKIN
(Negative Edge Clocking)
4
5
TSx_CTL/
TSx_DATA(A)
A. TSx_CTL/TSx_DATA input includes: TS0_EN_WAITO, TS0_WAITIN, TS0_PSTIN, and TS0_DIN[7:0] for a parallel
input. For a serial input, TSx_CTL/TSx_DATA input includes: TSx_EN_WAITO, TSx_WAITIN, TSx_PSTIN, and
TS0_DIN7 or TS1_DIN.
Figure 6-45. TSIF Input Timing
Table 6-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output
(see Figure 6-46)
-1G
SERIAL
OUTPUT
PARALLEL
OUTPUT(1)
NO.
UNIT
MIN MAX
MIN MAX
16.7
6
7
8
tc(TSCLKO)
tw(TSCLKO)
tt(TSCLKO)
Cycle time, TSx_CLKO
Pulse duration, TSx_CLKO high/low(2)
10
0.4C
3(3)
ns
ns
ns
0.4C
Transition time, TSx_CLKO
3(3)
(1) TSIF1 supports SERIAL OUTPUT mode only.
(2) C = TSx_CLKO period (cycle time) in ns.
(3) For a 4-inch transmission line with 4-pF load capacitance at the device pin.
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Table 6-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output
(see Figure 6-46) (continued)
-1G
SERIAL
OUTPUT
PARALLEL
OUTPUT(1)
NO.
UNIT
MIN MAX
MIN MAX
All Others
1
7.5
1
7.5
ns
ns
Delay time, TSx_CLKO edge to
9
td(TSCLKOV-TSDATAO)
TSx_CTL/TSx_DATA(4) output valid
TS0_WAITO,
TSx_EN_WAITO
1
16.5
1
16.5
(4) TSx_CTL/TSx_DATA output includes: TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] for a parallel output. For a serial
output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and TS0_DOUT7 or TS1_DOUT.
6
7
7
8
8
TSx_CLKO
(Positive Edge Clocking)
TSx_CLKO
(Negative Edge Clocking)
9
9
TSx_CTL/
TSx_DATA(A)
A. TSx_CTL/TSx_DATA output includes: TS0_ENAO, TS0_WAITO, TS0_PSTO, and TS0_DOUT[7:0] for a parallel
output. For a serial output, TSx_CTL/TSx_DATA output includes: TSx_ENAO, TSx_EN_WAITO, TSx_PSTO, and
TS0_DOUT7 or TS1_DOUT.
Figure 6-46. TSIF Output Timing
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6.13 Clock Recovery Generator (CRGEN)
Each TSIF module has an associated CRGEN module which can adjust the local system time clock based
upon the received Program Clock Reference (PCR) packets. CRGEN0 may only be used with TSIF 0 and
CRGEN 1 may only be used with TSIF 1.
Each CRGEN module features:
•
•
•
•
•
Automatic load of received PCR packet values from associated TSIF module
Local System Time Clock (STC) counter
PCR/STC difference generator (subtractor)
Loop Filter (LPF)
1-bit sigma/delta modulator digital-to-analog converter (DAC) output for external VCXO control
6.13.1 CRGEN Peripheral Register Description(s)
The CRGEN0 and CRGEN1 registers are shown in Table 6-54 and Table 6-55, respectively.
Table 6-54. CRGEN0 Registers
HEX ADDRESS RANGE
0x01C2 6000
ACRONYM
PID
REGISTER NAME
CRGEN Peripheral Identification Register
CRGEN control register
0x01C2 6004
0x01C2 6008
0x01C2 600C
0x01C2 6010
CONTROL
STC_HI
System Time Clock (STC) current value (upper 17 bits)
STC current value (lower 16 bits plus extension)
STC value (upper 17 bits) on TSIF0 PCR packet detection
STC_LO
STC_VAL_HI
STC value (lower 16 bits plus extension) on TSIF0 PCR packet
detection
0x01C2 6014
0x01C2 6018
0x01C2 601C
STC_VAL_LO
PCR_HI
Program Clock Reference (PCR) value (upper 17 bits) from
TSIF0 Receive packet
PCR value (lower 16 bits plus extension) from TSIF0 Receive
packet
PCR_LO
0x01C2 6020
0x01C2 6024
PCR_PKT_STAT
LOOP_FILTER
PCR packet status
Loop filter (LPF) interface
Offset value of the STC counter for the higher (upper) 17 bits.
This value is detected in the STC counter with the first PCR
loading pulse signal.
0x01C2 6028
STC_OFFSET_HI
Offset value of the STC counter for the lower 16 bits. The role
of this register is same as the STC_LO register 0x01C2 600C.
0x01C2 602C
STC_OFFSET_LO
0x01C2 6030 - 0x01C2 603F
0x01C2 6040
-
Reserved
INTEN
Interrupt enable
Interrupt enable set
Interrupt enable clear
Interrupt status
Interrupt status clear
Emulation control
Reserved
0x01C2 6044
INTEN_SET
INTEN_CLR
INTSTAT
INTSTAT_CLR
EMU_CTRL
-
0x01C2 6048
0x01C2 604C
0x01C2 6050
0x01C2 6054
0x01C2 6058 - 0x01C2 607F
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Table 6-55. CRGEN1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C2 6400
0x01C2 6404
0x01C2 6408
0x01C2 640C
0x01C2 6410
PID
CRGEN Peripheral Identification Register
CRGEN control register
CONTROL
STC_HI
System Time Clock (STC) current value (upper 17 bits)
STC current value (lower 16 bits plus extension)
STC value (upper 17 bits) on TSIF1 PCR packet detection
STC_LO
STC_VAL_HI
STC value (lower 16 bits plus extension) on TSIF1 PCR packet
detection
0x01C2 6414
0x01C2 6418
0x01C2 641C
STC_VAL_LO
PCR_HI
Program Clock Reference (PCR) value (upper 17 bits) from
TSIF1 Receive packet
PCR value (lower 16 bits plus extension) from TSIF1 Receive
packet
PCR_LO
0x01C2 6420
0x01C2 6424
PCR_PKT_STAT
LOOP_FILTER
PCR packet status
Loop filter (LPF) interface
Offset value of the STC counter for the higher 17 bits. This
value is detected in the STC counter with the first PCR loading
pulse signal.
0x01C2 6428
STC_OFFSET_HI
Offset value of the STC counter for the lower 16 bits. The role
of this register is same as the STC_LO register 0x01C2 640C.
0x01C2 642C
STC_OFFSET_LO
0x01C2 6430 - 0x01C2 643F
0x01C2 6440
-
Reserved
INTEN
Interrupt enable
Interrupt enable set
Interrupt enable clear
Interrupt status
Interrupt status clear
Emulation control
Reserved
0x01C2 6444
INTEN_SET
INTEN_CLR
INTSTAT
INTSTAT_CLR
EMU_CTRL
-
0x01C2 6448
0x01C2 644C
0x01C2 6450
0x01C2 6454
0x01C2 6458 - 0x01C2 647F
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6.13.2 CRGEN Electrical Data/Timing
Table 6-56. Timing Requirements for CRGx_VCXI Input (see Figure 6-47)
-1G
NOM
37.037
NO.
UNIT
MIN
29.63
0.4P
MAX
1
2
3
4
tc(VCXI)
tw(VCXIH)
tw(VCXIL)
tt(VCXI)
Cycle time, CRGx_VCXI
44.44
ns
ns
ns
ns
Pulse duration, CRGx_VCXI high
Pulse duration, CRGx_VCXI low
Transition time, CRGx_VCXI
0.4P
5
4
1
2
3
CRGx_VCXI
4
Figure 6-47. CRGx_VCXI Input Timing
Table 6-57. Switching Characteristics Over Recommended Operating Conditions for CRGx_PO Output
(see Figure 6-48)
-1G
NO.
PARAMETER
UNIT
MIN
59.26
59.26
MAX
1
2
3
tw(POH)
tw(POL)
tt(PO)
Pulse duration, CRGx_PO high
ns
ns
ns
Pulse duration, CRGx_PO low
Transition time, CRGx_PO
5
1
2
CRGx_PO
3
3
Figure 6-48. CRGx_PO Output Timing
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6.14 Video Data Conversion Engine (VDCE)
The VCE6467T Video Data Conversion Engine (VDCE) supports the following features:
•
Resize function on horizontal (HRSZ) and vertical (VRSZ) with ratio defined by 256/N (N is a natural
number that ranges from 256 to 2048) with 4 taps interpolation. Magnification ratio of horizontal resize
and vertical resize can be configured separately (different value can be configured).
•
•
Anti-alias filter (combination of two kinds of low-pass filter) with horizontal 7 taps, and vertical direction.
Chrominance signal format conversion (CCV) on both directions, one is from 4:2:2 to 4:2:0 and one is
from 4:2:0 to 4:2:2. This function also uses 4 taps interpolation. MPEG-1 specific format (half-pixel
phased from even pixel position of luminance) is also supported.
•
Edge padding for preparation of MC with unrestricted motion vector (required by MPEG-4, H.264,
VC-1). All modes (progressive, interlace frame, and interlace field) are supported (macro-block level
control that is required in H.264 is not currently supported).
•
•
VC-1 range mapping in advanced profile (in case of displaying decoded reference image or
trans-coding from VC-1 to any other format of video codec).
2-bit hardware menu overlay with 256 steps of blending for each color.
6.14.1 VDCE Bus Master
The VDCE includes a bus master interface that accesses the DM646x system bus to transfer data.
Table 6-58 shows the memory map for the VDCE interface.
Table 6-58. VDCE Master Memory Map
SIZE
START ADDRESS
END ADDRESS
VDCE ACCESS
Reserved
(BYTES)
256M
64K
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x4A00 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
16256K
784M
32M
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
32M
32M
32M
32M
64M
VLYNQ (Remote Data)
Reserved
768M
512M
512M
1G
DDR2 Memory Controller
Reserved
Reserved
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6.14.2 VDCE Register Description(s)
Table 6-59 shows the VDCE registers.
Table 6-59. VDCE Registers
HEX ADDRESS RANGE
0x01C1 2800
ACRONYM
PID
REGISTER NAME
VDCE peripheral identification register
VDCE control register
0x01C1 2804
0x01C1 2808
0x01C1 280C
0x01C1 2810
0x01C1 2814
0x01C1 2818
0x01C1 281C
0x01C1 2820
0x01C1 2824
0x01C1 2828
0x01C1 282C - 0x01C1 283F
0x01C1 2840
0x01C1 2844
0x01C1 2848
0x01C1 284C
0x01C1 2850
0x01C1 2854
0x01C1 2858
0x01C1 285C
0x01C1 2860
0x01C1 2864
0x01C1 2868
0x01C1 286C
0x01C1 2870
0x01C1 2874
0x01C1 2878
0x01C1 287C
0x01C1 2880
0x01C1 2884
0x01C1 2888
0x01C1 288C
0x01C1 2890
0x01C1 2894
0x01C1 2898
0x01C1 289C
0x01C1 28A0
0x01C1 28A4
0x01C1 28A8
0x01C1 28AC
0x01C1 28B0 - 0x01C1 28BF
0x01C1 28C0
0x01C1 28C4
0x01C1 28C8
CTRL
INTEN
Interrupt enable register
INTEN_SET
Interrupt enable set register
Interrupt enable clear register
Interrupt status register
INTEN_CLR
INTSTAT
INTSTAT_CLR
EMU_CTRL
Interrupt status clear register
Emulation control register
SRD_FRMT
Source/Result data store format register
Request unit size register
REQ_SIZE
PROC_SIZE
Processing unit size register
Reserved
–
TY_SRCADDR
TY_SRCSPSIZE
TY_SRCOFFSET
BY_SRCADDR
BY_SRCSPSIZE
BY_SRCOFFSET
TC_SRCADDR
TC_SRCSPSIZE
TC_SRCOFFSET
BC_SRCADDR
BC_SRCSPSIZE
BC_SRCOFFSET
TBMP_SRCADDR
TBMP_SRCOFFSET
BBMP_SRCADDR
BBMP_SRCOFFSET
TY_RESADDR
TY_RESSPSIZE
TY_RESOFFSET
BY_RESADDR
BY_RESSPSIZE
BY_RESOFFSET
TC_RESADDR
TC_RESSPSIZE
TC_RESOFFSET
BC_RESADDR
BC_RESSPSIZE
BC_RESOFFSET
–
Luma top field source start address register
Luma top field source sub-picture size register
Luma top field line source address offset size register
Luma bottom field source start address register
Luma bottom field source sub-picture size register
Luma bottom field line source address offset size register
Chroma top field source start address register
Chroma top field source sub-picture size register
Chroma top field line source address offset size register
Chroma bottom field source start address register
Chroma bottom field source sub-picture size register
Chroma bottom field line source address offset size register
Bitmap top field source start address register
Bitmap top field line source address offset register
Bitmap bottom field source start address register
Bitmap bottom field line source address offset register
Luma top field result start address register
Luma top field result sub-picture size register
Luma top field line result address offset size register
Luma bottom field result start address register
Luma bottom field result sub-picture size register
Luma bottom field line result address offset size register
Chroma top field result start address register
Chroma top field result sub-picture size register
Chroma top field result line address offset size register
Chroma bottom field result start address register
Chroma bottom field result sub-picture size register
Chroma bottom field line result address offset size register
Reserved
IMG_Y_SRCSTRTPOS
IMG_Y_SRCSIZE
IMG_C_SRCSTRTPOS
Luminance source image start position register
Luminance source image size register
Chrominance source image start position register
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Table 6-59. VDCE Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01C1 28CC
IMG_C_SRCSIZE
IMG_BMP_SRCSTRTPOS
IMG_BMP_SRCSIZE
–
Chrominance source image size register
Bitmap source image start position register
Bitmap source image size register
Reserved
0x01C1 28D0
0x01C1 28D4
0x01C1 28D8 - 0x01C1 28DF
0x01C1 28E0
IMG_Y_RESSTRTPOS
IMG_Y_RESSIZE
IMG_C_RESSTRTPOS
IMG_C_RESSIZE
IMG_BMP_RESSTRTPOS
–
Luminance result image start position register
Luminance result image size register
Chrominance result image start position register
Chrominance result image size register
Bitmap result image start position (location) register
Reserved
0x01C1 28E4
0x01C1 28E8
0x01C1 28EC
0x01C1 28F0
0x01C1 28F4 - 0x01C1 28FF
0x01C1 2900
RSZ_MODE
RSZ_HMAG
RSZ_VMAG
Resize mode definition register
Horizontal resize magnification ratio control register
Vertical resize magnification ratio control register
Phase of initial pixel on horizontal resize register
Phase of initial pixel on vertical resize register
Horizontal anti-aliasing (flicker) filter control register
Reserved
0x01C1 2904
0x01C1 2908
0x01C1 290C
RSZ_HPHASE
RSZ_VPHASE
RSZ_AFILTER
–
0x01C1 2910
0x01C1 2914
0x01C1 2918 - 0x01C1 291F
0x01C1 2920
CCV_MODE
–
Chrominance conversion mode control register
Reserved
0x01C1 2924 - 0x01C1 293F
0x01C1 2940
BLD_LUT_00
BLD_LUT_01
BLD_LUT_02
BLD_LUT_03
–
Look-up table for index 00 register
Look-up table for index 01 register
Look-up table for index 02 register
Look-up table for index 03 register
Reserved
0x01C1 2944
0x01C1 2948
0x01C1 294C
0x01C1 2950 - 0x01C1 295F
0x01C1 2960
RGMP_CTRL
–
Ramp mapping control reigster
Reserved
0x01C1 2964 - 0x01C1 2983
0x01C1 2984
EPD_LUMA_WIDTH
EPD_CHROMA_WIDTH
–
Edge padding width for luminance register
Edge padding width for chrominance register
Reserved
0x01C1 2988
0x01C1 298C - 0x01C1 291F
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6.15 Peripheral Component Interconnect (PCI)
The VCE6467T DMSoC supports connections to PCI-compliant devices via the integrated PCI
master/slave bus interface. The PCI port interfaces to DSP internal resources via the data switched
central resource. The data switched central resource is described in more detail in Section 4, System
Interconnect.
For more detailed information on the PCI port peripheral module, see the TMS320DM643x DMP
Peripheral Component Interconnect (PCI) User's Guide (literature number SPRU985).
6.15.1 PCI Device-Specific Information
The PCI peripheral on the VCE6467T DMSoC conforms to the PCI Local Bus Specification Revision 2.3.
The PCI peripheral can act both as a PCI bus master and as a target. It supports PCI bus operation of
speeds up to 66 MHz and uses a 32-bit data/address bus.
On the VCE6467T device, the pins of the PCI peripheral are multiplexed with the pins of the EMIFA,
GPIO, HPI, and ATA peripherals. For more detailed information on how to select PCI, see Section 3,
Device Configurations.
The VCE6467T device provides an initialization mechanism through which the default values for some of
the PCI configuration registers can be read from an I2C EEPROM. Table 6-60 shows the registers which
can be initialized through the PCI auto-initialization. The default value of these registers when PCI
auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with
auto-initialization. For information on how to select PCI boot with auto-initialization, see Section 3.4.1, Boot
Modes. For more information on PCI auto-initialization, see the TMS320DM646x DMSoC Peripheral
Component Interconnect (PCI) User's Guide (literature number SPRUER2) and the Using the
TMIS320DM646x Bootloader Application Report (literature number SPRAAS0).
The PCI peripheral is a master peripheral within the VCE6467T DMSoC.
Table 6-60. Default Values for PCI Configuration Registers
REGISTER
DEFAULT VALUE (HEX)
B002 104Ch
0x01C1 A000—Vendor ID/Device ID Register (PCIVENDEV)
Device ID
B002h
104Ch
1180 0001h
80h
Vendor ID
0x01C1 A008—Class Code/Revision ID Register (PCICLREV)
Class Code
Revision ID
01h
0x01C1 A02C—System Vendor ID/Subsystem ID (PCISUBID)
0000 0000h
0000
Subsystem ID
System Vendor ID
0000
0x01C1 A03C—Max Latency/Min Grant/Interrupt Pin/Interrupt Line 0000 0100h
Max Latency
Min Grant
00
00
01
00
Interrupt Pin
Interrupt Line
The on-chip Bootloader supports a host boot which allows an external PCI device to load application code
into the DMSoC's memory space.
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6.15.2 PCI External Master Memory Map
The PCI port includes a local DMA interface that allows external PCI master device intiated transfers to
access the DM646x system bus. Table 6-61 shows the memory map for the PCI interface.
Table 6-61. PCI DMA Master Memory Map
SIZE
START ADDRESS
END ADDRESS
PCI DMA ACCESS
Reserved
(BYTES)
28M
228M
16K
0x0000 0000
0x01C0 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x01BF FFFF
0x0FFF FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
CFG Bus Peripherals
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
16256K
4M
1M
1M
Reserved
1M
1M
64K
32K
128K
800K
5M
C64x+ L2 RAM/Cache
Reserved
32K
C64x+ L1P RAM/Cache
Reserved
992K
32K
C64x+ L1D RAM/Cache
992K
928M
64M
768M
512M
512M
1G
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
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6.15.3 PCI Peripheral Register Description(s)
Table 6-62. PCI Back End Configuration Registers
DMSoC ACCESS
HEX ADDRESS RANGE
ACRONYM
DMSoC ACCESS REGISTER NAME
01C1 A000 - 01C1 A00F
01C1 A010
-
Reserved
PCISTATSET
PCI Status Set Register
01C1 A014
PCISTATCLR
PCI Status Clear Register
01C1 A018 - 01C1 A01F
01C1 A020
-
Reserved
PCIHINTSET
PCI Host Interrupt Enable Set Register
PCI Host Interrupt Enable Clear Register
Reserved
01C1 A024
PCIHINTCLR
01C1 A028 - 01C1 A02F
01C1 A030
-
PCIBINTSET
PCI Back End Application Interrupt Enable Set Register
PCI Back End Application Interrupt Enable Clear Register
Reserved
01C1 A034
PCIBINTCLR
01C1 A038
-
-
01C1 A03C - 01C1 A0FF
01C1 A100
Reserved
PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register
01C1 A104
PCICSRMIR
PCICLREVMIR
PCICLINEMIR
PCIBAR0MSK
PCIBAR1MSK
PCIBAR2MSK
PCIBAR3MSK
PCIBAR4MSK
PCIBAR5MSK
-
PCI Command/Status Mirror Register
PCI Class Code/Revision ID Mirror Register
PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
PCI Base Address Mask Register 0
PCI Base Address Mask Register 1
PCI Base Address Mask Register 2
PCI Base Address Mask Register 3
PCI Base Address Mask Register 4
PCI Base Address Mask Register 5
Reserved
01C1 A108
01C1 A10C
01C1 A110
01C1 A114
01C1 A118
01C1 A11C
01C1 A120
01C1 A124
01C1 A128 - 01C1 A12B
01C1 A12C
PCISUBIDMIR
-
PCI Subsystem Vendor ID/Subsystem ID Mirror Register
Reserved
01C1 A130
01C1 A134
PCICPBPTRMIR PCI Capabilities Pointer Mirror Register
01C1 A138 - 01C1 A13B
01C1 A13C
-
Reserved
PCILGINTMIR
-
PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
Reserved
01C1 A140 - 01C1 A17F
01C1 A180
PCISLVCNTL
-
PCI Slave Control Register
01C1 A184 - 01C1 A1BF
01C1 A1C0
Reserved
PCIBAR0TRL
PCIBAR1TRL
PCIBAR2TRL
PCIBAR3TRL
PCIBAR4TRL
PCIBAR5TRL
-
PCI Slave Base Address 0 Translation Register
PCI Slave Base Address 1 Translation Register
PCI Slave Base Address 2 Translation Register
PCI Slave Base Address 3 Translation Register
PCI Slave Base Address 4 Translation Register
PCI Slave Base Address 5 Translation Register
Reserved
01C1 A1C4
01C1 A1C8
01C1 A1CC
01C1 A1D0
01C1 A1D4
01C1 A1D8 - 01C1 A1DF
01C1 A1E0
PCIBAR0MIR
PCIBAR1MIR
PCIBAR2MIR
PCIBAR3MIR
PCIBAR4MIR
PCIBAR5MIR
-
PCI Base Address Register 0 Mirror Register
PCI Base Address Register 1 Mirror Register
PCI Base Address Register 2 Mirror Register
PCI Base Address Register 3 Mirror Register
PCI Base Address Register 4 Mirror Register
PCI Base Address Register 5 Mirror Register
Reserved
01C1 A1E4
01C1 A1E8
01C1 A1EC
01C1 A1F0
01C1 A1F4
01C1 A1F8 - 01C1 A2FF
01C1 A300
PCIMCFGDAT
PCI Master Configuration/IO Access Data Register
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Table 6-62. PCI Back End Configuration Registers (continued)
DMSoC ACCESS
HEX ADDRESS RANGE
ACRONYM
DMSoC ACCESS REGISTER NAME
01C1 A304
PCIMCFGADR
PCIMCFGCMD
-
PCI Master Configuration/IO Access Address Register
PCI Master Configuration/IO Access Command Register
Reserved
01C1 A308
01C1 A30C - 01C1 A30F
01C1 A310
PCIMSTCFG
PCI Master Configuration Register
Table 6-63. DMSoC-to-PCI Address Translation Registers
DMSoC ACCESS
HEX ADDRESS RANGE
ACRONYM
DMSoC ACCESS REGISTER NAME
PCI Address Substitute 0 Register
01C1 A314
01C1 A318
01C1 A31C
01C1 A320
01C1 A324
01C1 A328
01C1 A32C
01C1 A330
01C1 A334
01C1 A338
01C1 A33C
01C1 A340
01C1 A344
01C1 A348
01C1 A34C
01C1 A350
01C1 A354
01C1 A358
01C1 A35C
01C1 A360
01C1 A364
01C1 A368
01C1 A36C
01C1 A370
01C1 A374
01C1 A378
01C1 A37C
01C1 A380
01C1 A384
01C1 A388
01C1 A38C
01C1 A390
PCIADDSUB0
PCIADDSUB1
PCIADDSUB2
PCIADDSUB3
PCIADDSUB4
PCIADDSUB5
PCIADDSUB6
PCIADDSUB7
PCIADDSUB8
PCIADDSUB9
PCIADDSUB10
PCIADDSUB11
PCIADDSUB12
PCIADDSUB13
PCIADDSUB14
PCIADDSUB15
PCIADDSUB16
PCIADDSUB17
PCIADDSUB18
PCIADDSUB19
PCIADDSUB20
PCIADDSUB21
PCIADDSUB22
PCIADDSUB23
PCIADDSUB24
PCIADDSUB25
PCIADDSUB26
PCIADDSUB27
PCIADDSUB28
PCIADDSUB29
PCIADDSUB30
PCIADDSUB31
PCI Address Substitute 1 Register
PCI Address Substitute 2 Register
PCI Address Substitute 3 Register
PCI Address Substitute 4 Register
PCI Address Substitute 5 Register
PCI Address Substitute 6 Register
PCI Address Substitute 7 Register
PCI Address Substitute 8 Register
PCI Address Substitute 9 Register
PCI Address Substitute 10 Register
PCI Address Substitute 11 Register
PCI Address Substitute 12 Register
PCI Address Substitute 13 Register
PCI Address Substitute 14 Register
PCI Address Substitute 15 Register
PCI Address Substitute 16 Register
PCI Address Substitute 17 Register
PCI Address Substitute 18 Register
PCI Address Substitute 19 Register
PCI Address Substitute 20 Register
PCI Address Substitute 21 Register
PCI Address Substitute 22 Register
PCI Address Substitute 23 Register
PCI Address Substitute 24 Register
PCI Address Substitute 25 Register
PCI Address Substitute 26 Register
PCI Address Substitute 27 Register
PCI Address Substitute 28 Register
PCI Address Substitute 29 Register
PCI Address Substitute 30 Register
PCI Address Substitute 31 Register
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Table 6-64. PCI Hook Configuration Registers
DMSoC ACCESS
HEX ADDRESS RANGE
ACRONYM
DMSoC ACCESS REGISTER NAME
01C1 A394
PCIVENDEVPRG PCI Vendor ID and Device ID Program Register
01C1 A398
–
Reserved
01C1 A39C
PCICLREVPRG
PCISUBIDPRG
PCI Class Code and Revision ID Program Register
PCI Subsystem Vendor ID and Subsystem ID Program Register
01C1 A3A0
01C1 A3A4
PCIMAXLGPRG PCI Max Latency and Min Grant Program Register
01C1 A3A8
–
Reserved
01C1 A3AC
PCICFGDONE
PCI Configuration Done Register
01C1 A3B0 - 01C1 A3FB
01C1 A3FC - 01C1 A3FF
01C1 A400 - 01C1 A7FF
–
–
–
Reserved
Reserved
Reserved
Table 6-65. PCI External Memory Space
DMSoC HEX ADDRESS
RANGE
ACRONYM
DESCRIPTION
3000 0000 - 307F FFFF
3080 0000 - 30FF FFFF
3100 0000 - 317F FFFF
3180 0000 - 31FF FFFF
3200 0000 - 327F FFFF
3280 0000 - 32FF FFFF
3300 0000 - 337F FFFF
3380 0000 - 33FF FFFF
3400 0000 - 347F FFFF
3480 0000 - 34FF FFFF
3500 0000 - 357F FFFF
3580 0000 - 35FF FFFF
3600 0000 - 367F FFFF
3680 0000 - 36FF FFFF
3700 0000 - 377F FFFF
3780 0000 - 37FF FFFF
3800 0000 - 387F FFFF
3880 0000 - 38FF FFFF
3900 0000 - 397F FFFF
3980 0000 - 39FF FFFF
3A00 0000 - 3A7F FFFF
3A80 0000 - 3AFF FFFF
3B00 0000 - 3B7F FFFF
3B80 0000 - 3BFF FFFF
3C00 0000 - 3C7F FFFF
3C80 0000 - 3CFF FFFF
3D00 0000 - 3D7F FFFF
3D80 0000 - 3DFF FFFF
3E00 0000 - 3E7F FFFF
3E80 0000 - 3EFF FFFF
3F00 0000 - 3F7F FFFF
3F80 0000 - 3FFF FFFF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PCI Master Window 0
PCI Master Window 1
PCI Master Window 2
PCI Master Window 3
PCI Master Window 4
PCI Master Window 5
PCI Master Window 6
PCI Master Window 7
PCI Master Window 8
PCI Master Window 9
PCI Master Window 10
PCI Master Window 11
PCI Master Window 12
PCI Master Window 13
PCI Master Window 14
PCI Master Window 15
PCI Master Window 16
PCI Master Window 17
PCI Master Window 18
PCI Master Window 19
PCI Master Window 20
PCI Master Window 21
PCI Master Window 22
PCI Master Window 23
PCI Master Window 24
PCI Master Window 25
PCI Master Window 26
PCI Master Window 27
PCI Master Window 28
PCI Master Window 29
PCI Master Window 30
PCI Master Window 31
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6.15.4 PCI Electrical Data/Timing
Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI
peripheral meets all AC timing specifications as required by the PCI Local Bus Specification Revision 2.3.
Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing
specifications, see Section 4.2.3, Timing Specification (66-MHz timing) of the PCI Local Bus Specification
Revision 2.3. Note: The VCE6467T PCI peripheral only supports 3.3-V signaling and up to 66-MHz
operation.
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6.16 Ethernet MAC (EMAC)
The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the
VCE6467T and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and
100BaseTX (100 Mbps), in either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex
mode, with hardware flow control and quality-of-service (QOS) support.
The EMAC controls the flow of packet data from the VCE6467T device to the PHY. The MDIO module
controls the PHY configuration and status monitoring.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviating from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network. In addition, the EMAC I/Os operate at 3.3 V and are not
compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O interface should be
used.
Both the EMAC and MDIO modules interface to the VCE6467T device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module. The EMAC control module contains the necessary components to allow the EMAC to make
efficient use of device memory, plus it controls device interrupts. The EMAC control module incorporates
8K bytes of internal RAM to hold EMAC buffer descriptors.
For more detailed information on the EMAC, see the TMS320DM646x DMSoC Ethernet Media Access
Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature number
SPRUEQ6).
6.16.1 EMAC Device-Specific Information
The EMAC module on the VCE6467T supports two interface modes: Media Independent Interface (MII)
and Gigabit Media Independent Interface (GMII). The MII and GMII interface modes are defined in the
IEEE 802.3-2002 standard.
The VCE6467T EMAC uses the same pins for the MII and GMII modes of operation. Only one mode can
be used at a time. The mode used is selected at device reset based on the GMIIEN bit in the
MACCONTROL register. For more detailed information on the EMAC GMIIEN bit, see the
TMS320DM646x DMSoC Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO) Module User's Guide (literature number SPRUEQ6).
The MII and GMII modes-of-operation pins are as follows:
•
MII: MTCLK, MRCLK, MTXD[3:0], MRXD[3:0], MTXEN, MRXDV, MRXER, MCOL, MCRS, MDCLK,
and MDIO.
•
GMII: RFTCLK, GMTCLK, MTCLK, MRCLK, MTXD[7:0], MRXD[7:0], MTXEN, MRXDV, MRXER,
MCOL, MCRS, MDCLK, and MDIO.
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6.16.2 EMAC Bus Master Memory Map
The EMAC control module includes a multi-channel DMA engine which is used to transfer receive and
transmit packets between the EMAC and VCE6467T memory. Table 6-66 shows the memory map for the
EMAC DMA.
Table 6-66. EMAC DMA Master Memory Map
SIZE
(BYTES)
START ADDRESS
END ADDRESS
EMAC DMA ACCESS
Reserved
0x0000 0000
0x4000 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x3FFF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
1G
192M
64M
Reserved
VLYNQ (Remote Data)
Reserved
768M
512M
512M
1G
DDR2 Memory Controller
Reserved
Reserved
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6.16.3 EMAC Peripheral Register Description(s)
Table 6-67. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
0x01C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit identification and version register
0x01C8 0004
TXCONTROL
TXTEARDOWN
–
Transmit control register
0x01C8 0008
Transmit teardown register
0x01C8 000C - 0x01C8 000F
0x01C8 0010
Reserved
RXIDVER
Receive identification and version register
Receive control register
0x01C8 0014
RXCONTROL
0x01C8 0018
RXTEARDOWN
–
Receive teardown register
0x01C8 001C - 0x01C8 007F
0x01C8 0080
Reserved
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACEOIVECTOR
–
Transmit interrupt status (unmasked) register
Transmit interrupt status (masked) register
Transmit interrupt mask set register
Transmit interrupt mask clear register
MAC input vector register
0x01C8 0084
0x01C8 0088
0x01C8 008C
0x01C8 0090
0x01C8 0094
MAC end of interrupt vector register
Reserved
0x01C8 0098 - 0x01C8 009F
0x01C8 00A0
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
–
Receive interrupt status (unmasked) register
Receive interrupt status (masked) register
Receive interrupt mask set register
Receive interrupt mask clear register
MAC interrupt status (unmasked) register
MAC interrupt status (masked) register
MAC interrupt mask set register
MAC interrupt mask clear register
Reserved
0x01C8 00A4
0x01C8 00A8
0x01C8 00AC
0x01C8 00B0
0x01C8 00B4
0x01C8 00B8
0x01C8 00BC
0x01C8 00C0 - 0x01C8 00FF
0x01C8 0100
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive multicast/broadcast/promiscuous channel enable register
Receive unicast enable set register
0x01C8 0104
0x01C8 0108
Receive unicast clear register
0x01C8 010C
Receive maximum length register
0x01C8 0110
RXBUFFEROFFSET
RXFILTERLOWTHRESH
–
Receive buffer offset register
0x01C8 0114
Receive filter low priority frame threshold register
Reserved
0x01C8 0118 - 0x01C8 011F
0x01C8 0120
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
Receive channel 0 flow control threshold register
Receive channel 1 flow control threshold register
Receive channel 2 flow control threshold register
Receive channel 3 flow control threshold register
Receive channel 4 flow control threshold register
Receive channel 5 flow control threshold register
Receive channel 6 flow control threshold register
Receive channel 7 flow control threshold register
Receive channel 0 free buffer count register
Receive channel 1 free buffer count register
Receive channel 2 free buffer count register
Receive channel 3 free buffer count register
Receive channel 4 free buffer count register
Receive channel 5 free buffer count register
0x01C8 0124
0x01C8 0128
0x01C8 012C
0x01C8 0130
0x01C8 0134
0x01C8 0138
0x01C8 013C
0x01C8 0140
0x01C8 0144
0x01C8 0148
0x01C8 014C
0x01C8 0150
0x01C8 0154
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Table 6-67. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
–
REGISTER NAME
0x01C8 0158
Receive channel 6 free buffer count register
Receive channel 7 free buffer count register
MAC control register
0x01C8 015C
0x01C8 0160
0x01C8 0164
MAC status register
0x01C8 0168
Emulation control register
0x01C8 016C
FIFO control register (transmit and receive)
MAC configuration register
0x01C8 0170
0x01C8 0174
Soft reset register
0x01C8 0178 - 0x01C8 01CF
0x01C8 01D0
Reserved
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
–
MAC source address low bytes register (lower 16-bits)
MAC source address high bytes register (upper 32-bits)
MAC hash address register 1
0x01C8 01D4
0x01C8 01D8
0x01C8 01DC
0x01C8 01E0
MAC hash address register 2
Back off test register
0x01C8 01E4
Transmit pacing algorithm test register
Receive pause timer register
0x01C8 01E8
0x01C8 01EC
Transmit pause timer register
0x01C8 01F0 - 0x01C8 01FF
0x01C8 0200 - 0x01C8 02FF
0x01C8 0300 - 0x01C8 04FF
0x01C8 0500
Reserved
(see Table 6-68)
–
EMAC statistics registers
Reserved
MACADDRLO
MACADDRHI
MACINDEX
–
MAC address low bytes register (used in receive address matching)
MAC address high bytes register (used in receive address matching)
MAC index register
0x01C8 0504
0x01C8 0508
0x01C8 050C - 0x01C8 05FF
0x01C8 0600
Reserved
TX0HDP
Transmit channel 0 DMA head descriptor pointer register
Transmit channel 1 DMA head descriptor pointer register
Transmit channel 2 DMA head descriptor pointer register
Transmit channel 3 DMA head descriptor pointer register
Transmit channel 4 DMA head descriptor pointer register
Transmit channel 5 DMA head descriptor pointer register
Transmit channel 6 DMA head descriptor pointer register
Transmit channel 7 DMA head descriptor pointer register
Receive channel 0 DMA head descriptor pointer register
Receive channel 1 DMA head descriptor pointer register
Receive channel 2 DMA head descriptor pointer register
Receive channel 3 DMA head descriptor pointer register
Receive channel 4 DMA head descriptor pointer register
Receive channel 5 DMA head descriptor pointer register
Receive channel 6 DMA head descriptor pointer register
Receive channel 7 DMA head descriptor pointer register
0x01C8 0604
TX1HDP
0x01C8 0608
TX2HDP
0x01C8 060C
TX3HDP
0x01C8 0610
TX4HDP
0x01C8 0614
TX5HDP
0x01C8 0618
TX6HDP
0x01C8 061C
TX7HDP
0x01C8 0620
RX0HDP
0x01C8 0624
RX1HDP
0x01C8 0628
RX2HDP
0x01C8 062C
RX3HDP
0x01C8 0630
RX4HDP
0x01C8 0634
RX5HDP
0x01C8 0638
RX6HDP
0x01C8 063C
RX7HDP
Transmit channel 0 completion pointer (interrupt acknowledge)
register
0x01C8 0640
0x01C8 0644
0x01C8 0648
0x01C8 064C
TX0CP
TX1CP
TX2CP
TX3CP
Transmit channel 1 completion pointer (interrupt acknowledge)
register
Transmit channel 2 completion pointer (interrupt acknowledge)
register
Transmit channel 3 completion pointer (interrupt acknowledge)
register
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Table 6-67. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Transmit channel 4 completion pointer (interrupt acknowledge)
register
0x01C8 0650
TX4CP
Transmit channel 5 completion pointer (interrupt acknowledge)
register
0x01C8 0654
0x01C8 0658
0x01C8 065C
0x01C8 0660
0x01C8 0664
0x01C8 0668
0x01C8 066C
0x01C8 0670
0x01C8 0674
0x01C8 0678
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
Transmit channel 6 completion pointer (interrupt acknowledge)
register
Transmit channel 7 completion pointer (interrupt acknowledge)
register
Receive channel 0 completion pointer (interrupt acknowledge)
register
Receive channel 1 completion pointer (interrupt acknowledge)
register
Receive channel 2 completion pointer (interrupt acknowledge)
register
Receive channel 3 completion pointer (interrupt acknowledge)
register
Receive channel 4 completion pointer (interrupt acknowledge)
register
Receive channel 5 completion pointer (interrupt acknowledge)
register
Receive channel 6 completion pointer (interrupt acknowledge)
register
Receive channel 7 completion pointer (interrupt acknowledge)
register
0x01C8 067C
RX7CP
–
0x01C8 0680 - 0x01C8 07FF
Reserved
Table 6-68. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Good receive frames register
0x01C8 0200
RXGOODFRAMES
Broadcast receive frames register
(Total number of good broadcast frames received)
0x01C8 0204
RXBCASTFRAMES
Multicast receive frames register
(Total number of good multicast frames received)
0x01C8 0208
0x01C8 020C
0x01C8 0210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause receive frames register
Receive CRC errors register
(Total number of frames received with CRC errors)
Receive alignment/code errors register
(Total number of frames received with alignment/code errors)
0x01C8 0214
0x01C8 0218
0x01C8 021C
0x01C8 0220
RXALIGNCODEERRORS
RXOVERSIZED
Receive oversized frames register
(Total number of oversized frames received)
Receive jabber frames register
(Total number of jabber frames received)
RXJABBER
Receive undersized frames register
(Total number of undersized frames received)
RXUNDERSIZED
0x01C8 0224
0x01C8 0228
0x01C8 022C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered receive frames register
RXQOSFILTERED
Received QOS filtered frames register
Receive octet frames register
(Total number of received bytes in good frames)
0x01C8 0230
0x01C8 0234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
0x01C8 0238
0x01C8 023C
0x01C8 0240
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
Broadcast transmit frames register
Multicast transmit frames register
Pause transmit frames register
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Table 6-68. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE
ACRONYM
TXDEFERRED
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
REGISTER NAME
0x01C8 0244
0x01C8 0248
0x01C8 024C
0x01C8 0250
0x01C8 0254
0x01C8 0258
0x01C8 025C
0x01C8 0260
0x01C8 0264
0x01C8 0268
0x01C8 026C
0x01C8 0270
0x01C8 0274
0x01C8 0278
0x01C8 027C
0x01C8 0280
0x01C8 0284
0x01C8 0288
0x01C8 028C
0x01C8 0290 - 0x01C8 02FF
Deferred transmit frames register
Transmit collision frames register
Transmit single collision frames register
Transmit multiple collision frames register
Transmit excessive collision frames register
Transmit late collision frames register
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit underrun error register
Transmit carrier sense errors register
Transmit octet frames register
FRAME64
Transmit and receive 64 octet frames register
Transmit and receive 65 to 127 octet frames register
Transmit and receive 128 to 255 octet frames register
Transmit and receive 256 to 511 octet frames register
Transmit and receive 512 to 1023 octet frames register
Transmit and receive 1024 to 1518 octet frames register
Network octet frames register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
–
Receive FIFO or DMA start of frame overruns register
Receive FIFO or DMA middle of frame overruns register
Receive DMA start of frame and middle of frame overruns register
Reserved
Table 6-69. EMAC Control Module Registers
HEX ADDRESS RANGE
0x01C8 1000
ACRONYM
REGISTER NAME
Identification and version register
Software reset register
CMIDVER
CMSOFTRESET
CMEMCONTROL
CMINTCTRL
CMRXTHRESHINTEN
CMRXINTEN
CMTXINTEN
CMMISCINTEN
–
0x01C8 1004
0x01C8 1008
Emulation control register
0x01C8 100C
Interrupt control register
0x01C8 1010
Receive threshold interrupt enable register
Receive interrupt enable register
Transmit interrupt enable register
Miscellaneous interrupt enable register
Reserved
0x01C8 1014
0x01C8 1018
0x01C8 101C
0x01C8 1020 - 0x01C8 103F
0x01C8 1040
CMRXTHRESHINTSTAT
CMRXINTSTAT
CMTXINTSTAT
CMMISCINTSTAT
–
Receive threshold interrupt status register
Receive interrupt status register
Transmit interrupt status register
Miscellaneous interrupt status register
Reserved
0x01C8 1044
0x01C8 1048
0x01C8 104C
0x01C8 1050 - 0x01C8 106F
0x01C8 1070
CMRXINTMAX
CMTXINTMAX
–
Receive interrupts per millisecond register
Transmit interrupts per millisecond register
Reserved
0x01C8 1074
0x01C8 1078 - 0x01C8 10FF
0x01C8 1100 - 0x01C8 1FFF
–
Reserved
Table 6-70. EMAC Descriptor Memory
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
EMAC Control Module Descriptor Memory
0x01C8 2000 - 0x01C8 3FFF
–
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6.16.4 EMAC Electrical Data/Timing
Table 6-71. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 6-49)
-1G
1000 Mbps
(GMII Only)
NO.
100 Mbps
10 Mbps
UNIT
MIN
8
MAX
MIN
40
MAX
MIN
400
140
140
MAX
1
2
3
4
tc(MRCLK)
tw(MRCLKH)
tw(MRCLKL)
tt(MRCLK)
Cycle time, MRCLK
ns
ns
ns
Pulse duration, MRCLK high
Pulse duration, MRCLK low
Transition time, MRCLK
2.8
2.8
14
14
1
3
3
ns
4
1
4
2
3
MRCLK
(Input)
Figure 6-49. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 6-72. Timing Requirements for MTCLK - MII and GMII Operation (see Figure 6-50)
-1G
NO.
100 Mbps
10 Mbps
MIN
UNIT
MIN
40
MAX
MAX
1
2
3
4
tc(MTCLK)
tw(MTCLKH)
tw(MTCLKL)
tt(MTCLK)
Cycle time, MTCLK
400
ns
ns
ns
ns
Pulse duration, MTCLK high
Pulse duration, MTCLK low
Transition time, MTCLK
14
140
14
140
3
3
4
1
4
2
3
MTCLK
(Input)
Figure 6-50. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
Table 6-73. Timing Requirements for RFTCLK - GMII Operation (see Figure 6-51)
-1G
1000 Mbps
MIN
NO.
UNIT
MAX
1
2
3
4
tc(RFTCLK)
tw(RFTCLKH)
tw(RFTCLKL)
tt(RFTCLK)
Cycle time, RFTCLK
8
2.8
2.8
ns
ns
ns
ns
Pulse duration, RFTCLK high
Pulse duration, RFTCLK low
Transition time, RFTCLK
1
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4
1
4
2
3
RFTCLK
(Input)
Figure 6-51. RFTCLK Timing [GMII Operation]
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Table 6-74. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII
Operation (see Figure 6-52)
-1G
NO.
PARAMETER
1000 Mbps
UNIT
MIN
8
MAX
1
2
3
4
tc(GMTCLK)
tw(GMTCLKH)
tw(GMTCLKL)
tt(GMTCLK)
Cycle time, GMTCLK
ns
ns
ns
ns
Pulse duration, GMTCLK high
Pulse duration, GMTCLK low
Transition time, GMTCLK
2.8
2.8
1
4
1
4
2
3
GMTCLK
(Output)
Figure 6-52. GMTCLK Timing (EMAC – Transmit) [GMII Operation]
Table 6-75. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s(1) (see Figure 6-53)
-1G
NO.
1000 Mbps
MIN
100/10 Mbps
MIN
UNIT
MAX
MAX
Setup time, receive selected signals valid before
MRCLK high
1
2
tsu(MRXD-MRCLKH)
th(MRCLKH-MRXD)
2
0
8
8
ns
ns
Hold time, receive selected signals valid after
MRCLK high
(1) For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER.
For GMII, Receive selected signals include: MRXD[7:0], MRXDV, and MRXER.
1
2
MRCLK (Input)
MRXD7−MRXD4(GMII only),
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-53. EMAC Receive Interface Timing [MII and GMII Operation]
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Table 6-76. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII
Transmit 10/100 Mbit/s(1) (see Figure 6-54)
-1G
NO.
PARAMETER
100/10 Mbps
UNIT
MIN
MAX
1
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
5
25
ns
(1) For MII, Transmit selected signals include: MTXD[3:0] and MTXEN.
For GMII, Transmit selected signals include: MTXD[7:0] and MTXEN.
1
MTCLK (Input)
MTXD7−MTXD4(GMII only),
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-54. EMAC Transmit Interface Timing [MII and GMII Operation]
Table 6-77. Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit
1000 Mbit/s(1) (see Figure 6-55)
-1G
NO.
PARAMETER
1000 Mbps
MIN
UNIT
MAX
1
td(GMTCLKH-MTXD) Delay time, GMTCLK high to transmit selected signals valid
0.5
5
ns
(1) For GMII, Transmit selected signals include: MTXD[7:0] and MTXEN.
1
GMTCLK (Output)
MTXD7−MTXD0,
MTXEN (Outputs)
Figure 6-55. EMAC Transmit Interface Timing [GMII Operation]
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6.17 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the TMS320DM646x DMSoC Ethernet Media
Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature
number SPRUEQ6) . For a list of supported registers and register fields, see Table 6-78, MDIO Registers
in this data manual.
6.17.1 MDIO Peripheral Register Description(s)
Table 6-78. MDIO Registers
HEX ADDRESS RANGE
0x01C8 4000
ACRONYM
VERSION
REGISTER NAME
MDIO version register
MDIO control register
0x01C8 4004
CONTROL
0x01C8 4008
ALIVE
MDIO PHY alive status register
0x01C8 400C
LINK
MDIO PHY link status register
0x01C8 4010
LINKINTRAW
LINKINTMASKED
–
MDIO link status change interrupt (unmasked) register
MDIO link status change interrupt (masked) register
Reserved
0x01C8 4014
0x01C8 4018 - 0x01C8 401F
0x01C8 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
MDIO user command complete interrupt (unmasked) register
MDIO user command complete interrupt (masked) register
MDIO user command complete interrupt mask set register
0x01C8 4024
0x01C8 4028
0x01C8 402C
USERINTMASKCLEAR MDIO user command complete interrupt mask clear register
0x01C8 4030 - 0x01C8 407F
0x01C8 4080
–
Reserved
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO user access register 0
MDIO user PHY select register 0
MDIO user access register 1
MDIO user PHY select register 1
Reserved
0x01C8 4084
0x01C8 4088
0x01C8 408C
0x01C8 4090 - 0x01C8 47FF
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6.17.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-79. Timing Requirements for MDIO Input (see Figure 6-56 and Figure 6-57)
-1G
MIN
NO.
UNIT
MAX
1
2
3
4
5
tc(MDCLK)
Cycle time, MDCLK
400
180
ns
ns
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high/low
tt(MDCLK)
Transition time, MDCLK
5
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
10
0
1
3
3
MDCLK
4
5
MDIO
(input)
Figure 6-56. MDIO Input Timing
Table 6-80. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-57)
-1G
NO.
PARAMETER
UNIT
ns
MIN
MAX
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
100
1
MDCLK
7
MDIO
(output)
Figure 6-57. MDIO Output Timing
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6.18 Host-Port Interface (HPI) Peripheral
The HPI is a parallel port through which a host processor can directly access the CPU memory space.
The host device functions as a master to the interface, which increases ease of access. The host and
CPU can exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the EDMA3
controller.
6.18.1 HPI Device-Specific Information
The VCE6467T device includes a user-configurable 32- or 16-bit Host-port interface (HPI32/HPI16).
•
•
•
•
•
•
•
Multiplexed (address/data) operation
Configurable single full-word cycle and dual half-word cycle access modes
Bursting available utilizing 8-word read and write FIFOs
HPIA register supports auto-incrementing
HPID register/FIFOs providing data-path between external host interface and system bus
Multiple strobes and control signals to allow flexible host connection
Configurable asynchronous HRDY output to allow HPI to insert wait states to the Host [System Module
Register HPICTL.HRDYMODE]
•
•
•
Software control of data prefetching to the HPID/FIFOs
DMSoC-to-Host interrupt output signal controlled by HPIC accesses
Host-to-DMSoC interrupt controlled by HPIC accesses
NOTE: The VCE6467T HPI does not support the HAS feature. For proper HPI operation if the HAS pin
(D4) is routed out, the HAS pin must be pulled up via an external resistor.
The VCE6467T HPICTL register (0x01C4 0030) is part of the System Module Registers. The HPICTL
register controls write access to the HPI peripheral control and address registers as well as determines
the host time-out value. The HPICTL System Module Register also determines the operation of the HRDY
output which allows the HPI to insert wait states to the Host. For more detailed information on the HPICTL
System Module Register, see Section 3.6.2, Peripheral Selection After Device Reset.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface
(HPI) User's Guide (literature number SPRUES1).
6.18.2 HPI Bus Master
The HPI peripheral includes a bus master interface that allows external device initiated transfers to access
the VCE6467T system bus. Table 6-81 shows the memory map for the HPI master interface.
Table 6-81. HPI Master Memory Map
SIZE
(BYTES)
START ADDRESS
END ADDRESS
HPI ACCESS
0x0000 0000
0x01C0 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x01BF FFFF
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
28M
Reserved
228M
64K
CFG Bus Peripherals
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
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Table 6-81. HPI Master Memory Map (continued)
SIZE
START ADDRESS
END ADDRESS
HPI ACCESS
(BYTES)
16256K
4M
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
1M
1M
Reserved
1M
1M
64K
32K
128K
800K
5M
C64x+ L2 RAM/Cache
Reserved
32K
C64x+ L1P RAM/Cache
Reserved
992K
32K
C64x+ L1D RAM/Cache
992K
928M
64M
768M
512M
512M
1G
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
6.18.3 HPI Peripheral Register Description(s)
Table 6-82. HPI Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
01C6 7800
PID
Peripheral Identification Register
The ARM/C64x+ has
01C6 7804
PWREMU_MGMT
-
HPI power and emulation management register
Reserved
read/write access to the
PWREMU_MGMT register.
01C6 7808 - 01C6 782F
The Host and the
ARM/C64x+ both have
read/write access to the
HPIC register.
01C6 7830
01C6 7834
HPIC
HPI control register
HPIA
HPI address register
(Write)
The Host has read/write
access to the HPIA registers.
The ARM/C64x+ has only
read access to the HPIA
registers.
(HPIAW)(1)
HPIA
HPI address register
(Read)
01C6 7838
(HPIAR)(1)
01C6 783C - 01C6 7FFF
-
Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The ARM/C64x+ can access HPIAW and HPIAR independently. For more details about the HPIA registers and
their modes, see the TMS320DM646x DMSoC Host Port Interface (HPI) User's Guide (literature number SPRUES1).
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6.18.4 HPI Electrical Data/Timing
Table 6-83. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-58 through
Figure 6-61)
-1G
NO.
UNIT
MIN
5
MAX
1
2
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tw(HSTBL)
Setup time, select signals(3) valid before HSTROBE low
Hold time, select signals(3) valid after HSTROBE low
Pulse duration, HSTROBE active low
ns
ns
ns
ns
ns
ns
2
3
15
2M
5
4
tw(HSTBH)
Pulse duration, HSTROBE inactive high between consecutive accesses
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
11
12
tsu(HDV-HSTBH)
th(HSTBH-HDV)
0.15
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
13
th(HRDYL-HSTBL)
0
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) M = SYSCLK3 period = (CPU clock frequency)/4 in ns. For example, when running parts at 1 GHz, use M = 4 ns.
(3) Select signals include: HCNTL[1:0], HR/W. For HPI16 mode only, select signals also includes HHWIL.
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Table 6-84. Switching Characteristics for Host-Port Interface Cycles(1) (2) (3)
(see Figure 6-58 through Figure 6-61)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full
or flushing (can be either first or
second half-word)
Case 4: HPIA write and Write FIFO not
empty
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with
Delay time, HSTROBE low to
HRDY valid
5
td(HSTBL-HRDYV)
12
ns
auto-increment) and data not in Read
FIFO (can only happen to first
half-word of HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6
7
ten(HSTBL-HD)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDV)
Enable time, HD driven from HSTROBE low
Delay time, HRDY low to HD valid
2
ns
ns
ns
ns
0
8
Output hold time, HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
1.5
14
12
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is
already in Read FIFO
Delay time, HSTROBE low to
HD valid
15
td(HSTBL-HDV)
12
ns
Case 3: Second half-word of HPID
read with or without auto-increment
(1) M = SYSCLK3 period = (CPU clock frequency)/4 in ns. For example, when running parts at 1 GHz, use 4 ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
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HCS
(D)
HAS
2
2
1
1
1
1
HCNTL[1:0]
HR/W
2
2
2
2
1
1
HHWIL
4
3
3
(A)(C)
HSTROBE
15
6
15
14
14
8
6
8
HD[15:0]
(output)
13
7
1st Half-Word
2nd Half-Word
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s
Guide (literature number SPRUES1).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are
reflected by parameters for HSTROBE.
D. For proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-58. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
(D)
HAS
1
1
1
1
1
1
2
2
2
2
2
HCNTL[1:0]
HR/W
2
HHWIL
3
3
4
(A)(C)
HSTROBE
11
11
12
12
HD[15:0]
(input)
1st Half-Word
2nd Half-Word
5
13
13
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s Guide (literature
number SPRUES1).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected by
parameters for HSTROBE.
D. For proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-59. HPI16 Write Timing (HAS Not Used, Tied High)
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2
1
HCNTL[1:0] (input)
HR/W (Input)
3
HSTROBE(A)(C) (Input)
HCS (input)
14
15
8
6
HD[31:0] (output)
13
7
5
HRDY(B) (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User's Guide
(literature number SPRUES1).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are
reflected by parameters for HSTROBE.
D. For Proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-60. HPI32 Read Timing (HAS Not Used, Tied High)
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(D)
HAS (input)
2
1
HCNTL[1:0] (input)
HR/W (input)
3
(A)(C)
HSTROBE
(input)
HCS (input)
12
11
HD[31:0] (input)
13
5
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Dependingon the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and
the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface (HPI) User’s Guide
(literaturenumber SPRUES1).
C. HCS reflects typical HCS behavior when HSTROBE assertion is caused by HDS1 or HDS2. HCS timing requirements are reflected
by parameters for HSTROBE.
D. For proper HPI operation, HAS must be pulled up via an external resistor.
Figure 6-61. HPI32 Write Timing (HAS Not Used, Tied High)
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6.19 USB 2.0 [see Note]
The VCE6467T USB2.0 peripheral supports the following features:
•
•
•
USB 2.0 peripheral at speeds: high-speed (HS: 480 Mb/s) and full-speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
Each endpoint (other than endpoint 0) can support all transfer modes (control, bulk, interrupt, and
isochronous)
•
•
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
Connects to a standard UTMI+ PHY with a 60-MHz, 8-bit interface
External 5-V power supply for VBUS, when operating as Host, enabled directly by the USB controller
via a dedicated signal
•
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Note: USB2.0 is not supported on -1G parts that are dated prior to May 1, 2010. See the
TMS320DM6467T Silicon Errata (Literature Number: SPRZ307) for more details on how to decode the
date from package markings.
6.19.1 USB DMA Master
The USB2.0 peripheral interface includes a master DMA engine that allows the USB to access the
VCE6467T system bus. Table 6-85 shows the memory map for the USB2.0 DMA engine.
Table 6-85. USB2.0 DMA Master Memory Map
SIZE
START ADDRESS
END ADDRESS
USB2.0 DMA ACCESS
Reserved
(BYTES)
256M
64K
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4C00 0000
0x5000 0000
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
16256K
4M
1M
1M
Reserved
1M
1M
64K
32K
128K
800K
5M
C64x+ L2 RAM/Cache
Reserved
32K
C64x+ L1P RAM/Cache
Reserved
992K
32K
C64x+ L1D RAM/Cache
992K
928M
64M
768M
Reserved
VLYNQ (Remote Data)
Reserved
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Table 6-85. USB2.0 DMA Master Memory Map (continued)
SIZE
START ADDRESS
END ADDRESS
USB2.0 DMA ACCESS
(BYTES)
512M
512M
1G
0x8000 0000
0xA000 0000
0xC000 0000
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
DDR2 Memory Controller
Reserved
Reserved
6.19.2 USB2.0 Device-Specific Information
The VCE6467T USBCTL register (0x01C4 00034) is part of the System Module Registers. The USBCTL
register controls the USB data polarity, host/peripheral mode, and VBUS sense, along with the PHY power
and clock good, PHY PLL suspend override, and PHY power down. For more detailed information on the
USBCTL System Module Register, see Section 3.6.2, Peripheral Selection After Device Reset
For more detailed information on the USB2.0 peripheral, see the TMS320DM646x DMSoC Universal
Serial Bus (USB) Controller User's Guide (literature number SPRUER7).
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6.19.3 USB2.0 Peripheral Register Description(s)
Table 6-86 shows the USB perripheral register memory mapping.
Table 6-86. USB2.0 Registers
HEX ADDRESS
ACRONYM
RANGE
REGISTER NAME
0x01C6 4000
0x01C6 4004
0x01C6 4008
REVR
CTRLR
STATR
Revision Register
Control Register
Status Register
Reserved
0x01C6 400C -
0x01C6 400F
–
0x01C6 4010
0x01C6 4014
RNDISR
RNDIS Register
Auto Request Register
Reserved
AUTOREQ
0x01C6 4018 -
0x01C6 401F
–
0x01C6 4020
0x01C6 4024
0x01C6 4028
0x01C6 402C
0x01C6 4030
0x01C6 4034
0x01C6 4038
0x01C6 403C
0x01C6 4040
INTSRCR
INTSETR
USB Interrupt Source Register
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
USB Interrupt Mask Register
USB Interrupt Mask Set Register
USB Interrupt Mask Clear Register
USB Interrupt Source Masked Register
USB End of Interrupt Register
USB Interrupt Vector Register
Reserved
INTCLRR
INTMSKR
INTMSKSETR
INTMSKCLRR
INTMASKEDR
EOIR
INTVECTR
0x01C6 4044 -
0x01C6 407F
–
0x01C6 4080
0x01C6 4084
0x01C6 4088
0x01C6 408C
0x01C6 4090
0x01C6 4094
0x01C6 4098
0x01C6 409C
TCPPICR
TCPPITDR
TX CPPI Control Register
TX CPPI Teardown Register
TCPPIEOIR
TX CPPI DMA Controller End of Interrupt Register
TX CPPI DMA Controller Interrupt Vector Register
TX CPPI Masked Status Register
TX CPPI Raw Status Register
TCPPIIVECTR
TCPPIMSKSR
TCPPIRAWSR
TCPPIIENSETR
TCPPIIENCLRR
TX CPPI Interrupt Enable Set Register
TX CPPI Interrupt Enable Clear Register
Reserved
0x01C6 40A0 -
0x01C6 40BF
–
RCPPICR
–
0x01C6 40C0
RX CPPI Control Register
Reserved
0x01C6 40C4 -
0x01C6 40CF
0x01C6 40D0
0x01C6 40D4
0x01C6 40D8
0x01C6 40DC
0x01C6 40E0
0x01C6 40E4
0x01C6 40E8
0x01C6 40EC
RCPPIMSKSR
RCPPIRAWSR
RCPPIENSETR
RCPPIIENCLRR
RBUFCNT0
RX CPPI Masked Status Register
RX CPPI Raw Status Register
RX CPPI Interrupt Enable Set Register
RX CPPI Interrupt Enable Clear Register
RX Buffer Count 0 Register
RX Buffer Count 1 Register
RX Buffer Count 2 Register
RX Buffer Count 3 Register
Reserved
RBUFCNT1
RBUFCNT2
RBUFCNT3
0x01C6 40F0 -
0x01C6 40FF
–
TX/RX CCPI Channel 0 State Block
0x01C6 4100
TCPPIDMASTATEW0
TX CPPI DMA State Word 0
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
RANGE
0x01C6 4104
0x01C6 4108
0x01C6 410C
0x01C6 4110
0x01C6 4114
0x01C6 4118
0x01C6 411C
0x01C6 4120
0x01C6 4124
0x01C6 4128
0x01C6 412C
0x01C6 4130
0x01C6 4134
0x01C6 4138
0x01C6 413C
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
–
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
Reserved
TCPPICOMPPTR
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 1 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
Reserved
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 4140
0x01C6 4144
0x01C6 4148
0x01C6 414C
0x01C6 4150
0x01C6 4154
0x01C6 4158
0x01C6 415C
0x01C6 4160
0x01C6 4164
0x01C6 4168
0x01C6 416C
0x01C6 4170
0x01C6 4174
0x01C6 4178
0x01C6 417C
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
–
TCPPICOMPPTR
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 2 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
Rserved
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 4180
0x01C6 4184
0x01C6 4188
0x01C6 418C
0x01C6 4190
0x01C6 4194
0x01C6 4198
0x01C6 419C
0x01C6 41A0
0x01C6 41A4
0x01C6 41A8
0x01C6 41AC
0x01C6 41B0
0x01C6 41B4
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
–
TCPPICOMPPTR
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
0x01C6 41B8
0x01C6 41BC
RCPPIDMASTATEW6
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
TX/RX CCPI Channel 3 State Block
TX CPPI DMA State Word 0
TX CPPI DMA State Word 1
TX CPPI DMA State Word 2
TX CPPI DMA State Word 3
TX CPPI DMA State Word 4
TX CPPI DMA State Word 5
Rserved
RCPPICOMPPTR
0x01C6 41C0
0x01C6 41C4
0x01C6 41C8
0x01C6 41CC
0x01C6 41D0
0x01C6 41D4
0x01C6 41D8
0x01C6 41DC
0x01C6 41E0
0x01C6 41E4
0x01C6 41E8
0x01C6 41EC
0x01C6 41F0
0x01C6 41F4
0x01C6 41F8
0x01C6 41FC
TCPPIDMASTATEW0
TCPPIDMASTATEW1
TCPPIDMASTATEW2
TCPPIDMASTATEW3
TCPPIDMASTATEW4
TCPPIDMASTATEW5
–
TCPPICOMPPTR
TX CPPI Completion Pointer
RX CPPI DMA State Word 0
RX CPPI DMA State Word 1
RX CPPI DMA State Word 2
RX CPPI DMA State Word 3
RX CPPI DMA State Word 4
RX CPPI DMA State Word 5
RX CPPI DMA State Word 6
RX CPPI Completion Pointer
Reserved
RCPPIDMASTATEW0
RCPPIDMASTATEW1
RCPPIDMASTATEW2
RCPPIDMASTATEW3
RCPPIDMASTATEW4
RCPPIDMASTATEW5
RCPPIDMASTATEW6
RCPPICOMPPTR
0x01C6 4200 -
0x01C6 43FF
–
Core Registers
0x01C6 4400
0x01C6 4401
0x01C6 4402
0x01C6 4404
0x01C6 4406
0x01C6 4408
0x01C6 440A
0x01C6 440B
0x01C6 440C
0x01C6 440E
0x01C6 440F
FADDR
POWER
Function Address Register
Power Management Register
INTRTX
Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4
Interrupt Register for RX Endpoints 1 to 4
Interrupt Enable Register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts
Interrupt Enable Register for INTRUSB
Frame Number Register
INTRRX
INTRTXE
INTRRXE
INTRUSB
INTRUSBE
FRAME
INDEX
Index register for selecting the endpoint status and control registers
Register to enable the USB 2.0 test modes
TESTMODE
Maximum packet size for peripheral/host TX endpoint (Index register set to select
Endpoints 1 - 4 only)
0x01C6 4410
TXMAXP
PERI_CSR0
HOST_CSR0
PERI_TXCSR
HOST_TXCSR
RXMAXP
Control Status register for Endpoint 0 in Peripheral mode. (Index register set to
select Endpoint 0)
Control Status register for Endpoint 0 in Host mode. (Index register set to select
Endpoint 0)
0x01C6 4412
Control Status register for peripheral TX endpoint. (Index register set to select
Endpoints 1 - 4)
Control Status register for host TX endpoint. (Index register set to select
Endpoints 1 - 4)
Maximum packet size for peripheral/host RX endpoint (Index register set to select
Endpoints 1 - 4 only)
0x01C6 4414
0x01C6 4416
Control Status register for peripheral RX endpoint. (Index register set to select
Endpoints 1 - 4)
PERI_RXCSR
HOST_RXCSR
Control Status register for host RX endpoint. (Index register set to select
Endpoints 1 - 4)
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
RANGE
Number of received bytes in Endpoint 0 FIFO. (Index register set to select
Endpoint 0)
COUNT0
0x01C6 4418
Number of bytes in host RX endpoint FIFO. (Index register set to select
Endpoints 1 - 4)
RXCOUNT
HOST_TYPE0
HOST_TXTYPE
0x01C6 441A
0x01C6 441A
Defines the speed of Endpoint 0
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint. (Index register set to select Endpoints 1 - 4 only)
Sets the NAK response timeout on Endpoint 0. (Index register set to select
Endpoint 0)
0x01C6 441B
0x01C6 441B
0x01C6 441C
0x01C6 441D
HOST_NAKLIMIT0
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint. (Index register set to select
Endpoints 1 - 4 only)
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint. (Index register set to select Endpoints 1 - 4 only)
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint. (Index register set to select
Endpoints 1 - 4 only)
HOST_RXINTERVAL
0x01C6 441F
0x01C6 4420
0x01C6 4424
0x01C6 4428
0x01C6 442C
0x01C6 4430
0x01C6 4460
0x01C6 4462
0x01C6 4463
0x01C6 4464
0x01C6 4466
CONFIGDATA
FIFO0
Returns details of core configuration (Index register set to select Endpoint 0)
TX and RX FIFO Register for Endpoint 0
FIFO1
TX and RX FIFO Register for Endpoint 1
FIFO2
TX and RX FIFO Register for Endpoint 2
FIFO3
TX and RX FIFO Register for Endpoint 3
FIFO4
TX and RX FIFO Register for Endpoint 4
DEVCTL
TXFIFOSZ
RXFIFOSZ
TXFIFOADDR
RXFIFOADDR
Device Control Register
TX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only)
RX Endpoint FIFO Size (Index register set to select Endpoints 0 - 4 only)
TX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only)
RX Endpoint FIFO Address (Index register set to select Endpoints 0 - 4 only)
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG0
Address of the target function that has to be accessed through the associated TX
Endpoint
0x01C6 4480
0x01C6 4482
TXFUNCADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
TXHUBADDR
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 4483
0x01C6 4484
0x01C6 4486
TXHUBPORT
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high speed hub
0x01C6 4487
RXHUBPORT
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG1
Address of the target function that has to be accessed through the associated TX
Endpoint
0x01C6 4488
0x01C6 448A
TXFUNCADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
TXHUBADDR
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 448B
TXHUBPORT
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
Address of the target function that has to be accessed through the associated RX
Endpoint
0x01C6 448C
RXFUNCADDR
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high speed hub
0x01C6 448E
RXHUBADDR
RXHUBPORT
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high-speed hub.
0x01C6 448F
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG2
Address of the target function that has to be accessed through the associated TX
Endpoint
0x01C6 4490
0x01C6 4492
TXFUNCADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
TXHUBADDR
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 4493
0x01C6 4494
0x01C6 4496
TXHUBPORT
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 4497
RXHUBPORT
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG3
Address of the target function that has to be accessed through the associated TX
Endpoint
0x01C6 4498
0x01C6 449A
TXFUNCADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
TXHUBADDR
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full -peed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 449B
0x01C6 449C
0x01C6 449E
TXHUBPORT
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 449F
RXHUBPORT
Target Endpoint Control Registers (Valid Only in Host Mode) - EPTRG4
Address of the target function that has to be accessed through the associated TX
Endpoint
0x01C6 44A0
0x01C6 44A2
TXFUNCADDR
Address of the hub that has to be accessed through the associated TX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
TXHUBADDR
Port of the hub that has to be accessed through the associated TX Endpoint. This
is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 44A3
0x01C6 44A4
0x01C6 44A6
TXHUBPORT
RXFUNCADDR
RXHUBADDR
Address of the target function that has to be accessed through the associated RX
Endpoint
Address of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
RANGE
Port of the hub that has to be accessed through the associated RX Endpoint.
This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
0x01C6 44A7
RXHUBPORT
Control and Status Register for Endpoint 0 - EOCSR0
PERI_CSR0
HOST_CSR0
COUNT0
Control Status Register for Endpoint 0 in Peripheral mode
Control Status Register for Endpoint 0 in Host mode
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
0x01C6 4502
0x01C6 4508
0x01C6 450A
0x01C6 450B
0x01C6 450F
HOST_TYPE0
HOST_NAKLIMIT0
CONFIGDATA
Sets the NAK response timeout on Endpoint 0.
Returns details of core configuration
Control and Status Register for Endpoint 1 - EOCSR1
0x01C6 4510
0x01C6 4512
0x01C6 4514
0x01C6 4516
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4518
0x01C6 451A
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
HOST_TXTYPE
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
0x01C6 451B
0x01C6 451C
0x01C6 451D
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
HOST_RXINTERVAL
Control and Status Register for Endpoint 2 - EOCSR2
0x01C6 4520
0x01C6 4522
0x01C6 4524
0x01C6 4526
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4528
0x01C6 452A
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
HOST_TXTYPE
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
0x01C6 452B
0x01C6 452C
0x01C6 452D
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
HOST_RXINTERVAL
Control and Status Register for Endpoint 3 - EOCSR3
0x01C6 4530
0x01C6 4532
0x01C6 4534
0x01C6 4536
0x01C6 4538
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_RXCSR
HOST_RXCSR
RXCOUNT
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Table 6-86. USB2.0 Registers (continued)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
0x01C6 453A
HOST_TXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
0x01C6 453B
0x01C6 453C
0x01C6 453D
HOST_TXINTERVAL
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
HOST_RXINTERVAL
Control and Status Register for Endpoint 4 - EOCSR4
0x01C6 4540
0x01C6 4542
0x01C6 4544
0x01C6 4546
TXMAXP
PERI_TXCSR
HOST_TXCSR
RXMAXP
Maximum Packet Size for Peripheral/Host TX Endpoint
Control Status Register for Peripheral TX Endpoint
Control Status Register for Host TX Endpoint
Maximum Packet Size for Peripheral/Host RX Endpoint
Control Status Register for Peripheral RX Endpoint
Control Status Register for Host RX Endpoint
Number of Bytes in Host RX Endpoint FIFO
PERI_RXCSR
HOST_RXCSR
RXCOUNT
0x01C6 4548
0x01C6 454A
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host TX endpoint.
HOST_TXTYPE
HOST_TXINTERVAL
HOST_RXTYPE
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host TX endpoint.
0x01C6 454B
0x01C6 454C
0x01C6 454D
Sets the operating speed, transaction protocol and peripheral endpoint number
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host RX endpoint.
HOST_RXINTERVAL
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6.19.4 USB2.0 Electrical Data/Timing
Table 6-87. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-62)
-1G
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
NO.
PARAMETER
UNIT
MIN
75
MAX
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
3
4
5
tr(D)
Rise time, USB_DP and USB_DN signals(1)
Fall time, USB_DP and USB_DN signals(1)
Rise/Fall time, matching(2)
Output signal cross-over voltage(1)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter
Pulse duration, EOP receiver
300
300
125
2
20
20
ns
ns
%
tf(D)
75
4
trfM
80
90 111.11
–
VCRS
1.3
1.3
2
2
–
–
(3)
V
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
2
ns
ns
ns
ns
ns
ns
(3)
(3)
(3)
25
2
6
1
1
10
1
7
8
9
1250
670
1500
160
82
175
–
–
–
Data Rate
1.5
–
12
49.5
10.1
480 Mb/s
49.5
10.1 kΩ
10 ZDRV
Driver Output Resistance
–
28
40.5
9.9
Ω
11 USB_R1
USB reference resistor
9.9
10.1
9.9
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
t
t
per − jr
USB_DN
90% V
OH
V
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 6-62. USB2.0 Integrated Transceiver Interface Timing
USB
USB_VSSREF
USB_R1
10 K Ω 1ꢀ(A)
A. Place the 10 K Ω 1ꢀ aꢁ clꢂꢁe tꢂ the ꢃeꢄvce aꢁ ꢅꢂꢁꢁvile.
Figure 6-63. USB Reference Resistor Routing
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6.20 ATA Controller
The ATA peripheral supports the following features:
•
•
•
•
•
•
PIO, multiword DMA, and Ultra ATA 33/66/100
Up to mode 4 timings on PIO mode
Up to mode 2 timings on multiword DMA
Up to mode 5 timings on Ultra ATA
Programmable timing parameters
Supports TrueIDE mode for Compact Flash
6.20.1 ATA Bus Master Memory Map
The ATA Controller supports multiword DMA transfers between external IDE/ATAPI devices and a system
memory bus interface. Table 6-88 shows the memory map for the ATA DMA engine.
Table 6-88. ATA DMA Master Memory Map
SIZE
START ADDRESS
END ADDRESS
ATA DMA ACCESS
Reserved
(BYTES)
256M
64K
0x0000 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x1002 0000
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
16256K
4M
1M
1M
Reserved
1M
1M
64K
32K
128K
800K
5M
C64x+ L2 RAM/Cache
Reserved
32K
C64x+ L1P RAM/Cache
Reserved
992K
32K
C64x+ L1D RAM/Cache
992K
928M
64M
768M
512M
512M
1G
Reserved
VLYNQ (Remote Data)
Reserved
DDR2 Memory Controller
Reserved
Reserved
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6.20.2 ATA Peripheral Register Description(s)
Table 6-89 shows the ATA registers.
Table 6-89. ATA Register Memory Map
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
ATA Bus Master Interface DMA Engine Registers
0x01C6 6000
BMICP
Primary IDE Channel DMA Control Register
Primary IDE Channel DMA Status Register
0x01C6 6002
BMISP
BMIDTP
–
0x01C6 6004
Primary IDE Channel DMA Descriptor Table Pointer Register
Reserved
0x01C6 6008 - 0x01C6 603F
ATA Configuration Registers
Primary IDE Channel Timing Register
Reserved
0x01C6 6040
IDETIMP
–
0x01C6 6042 - 0x01C6 6046
0x01C6 6047
IDESTAT
IDE Controller Status Register
0x01C6 6048
UDMACTL Ultra-DMA Control Register
0x01C6 604A
–
Reserved
0x01C6 6050
MISCCTL
REGSTB
Miscellaneous Control Register
Task File Register Strobe Timing Register
0x01C6 6054
0x01C6 6058
REGRCVR Task File Register Recovery Timing Register
DATSTB Data Register Access PIO Strobe Timing Register
DATRCVR Data Register Access PIO Recovery Timing Register
DMASTB Multiword DMA Strobe Timing Register
0x01C6 605C
0x01C6 6060
0x01C6 6064
0x01C6 6068
DMARCVR Multiword DMA Recovery Timing Register
UDMASTB Ultra-DMA Strobe Timing Register
0x01C6 606C
0x01C6 6070
UDMATRP Ultra-DMA Ready-to-Pause Timing Register
UDMATENV Ultra-DMA Timing Envelope Register
IORDYTMP Primary I/O Ready Timer Configuration Register
0x01C6 6074
0x01C6 6078
0x01C6 607C - 0x01C6 67FF
–
Reserved
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6.20.3 ATA Electrical Data/Timing
All ATA AC timing data described in Section 6.20.3.1 – Section 6.20.3.3 is provided at the VCE6467T
device pins. For more details, see Section 6.1, Parameter Information.
The AC timing specifications described in Section 6.20.3.1 – Section 6.20.3.3 assume correct
configuration of the ATA memory-mapped control registers for the selected ATA frequency of operation.
6.20.3.1 ATA PIO Data Transfer AC Timing
Table 6-90. Timings for ATA Module — PIO Data Transfer(1) (2) (see Figure 6-64)
-1G
NO.
UNIT
MODE
0-4(3)
0-4(3)
0-4(3)
0-2
MIN
(DATSTB + DATRCVR + 2)P -0.5
12P - 1.6
MAX
1
2
3
t0
t1
t2
Cycle time
ns
ns
Address valid to DIOW/DIOR setup
DIOW/DIOR pulse duration low
(DATSTB + 1)P - 1
–
ns
ns
4
t2i
DIOW/DIOR recovery time, pulse duration high
3-4(3)
(DATRCVR + 1)P - 1
ns
DIOW data setup time, DD[15:0] valid before
DIOW rising edge
5
6
t3
t4
0-4(3)
0-4(3)
(DATSTB + 1)P
ns
DIOW data hold time, DD[15:0] valid after DIOW
rising edge
(HWNHLD + 1)P + 1
ns
0
1
50
35
20
ns
ns
ns
DIOR data setup time, DD[15:0] valid before DIOR
rising edge
7
t5
2-4(3)
DIOR data hold time, DD[15:0] valid after DIOR
rising edge
8
9
t6
0-4(3)
5
ns
Output data 3-state, DD[15:0] 3-state after DIOR
rising edge
t6Z
0-4(3)
0-4(3)
0-4(3)
30
ns
ns
ns
10 t9
DIOW/DIOR to address valid hold
(HWNHLD + 1)P - 2.1
0
Read data setup time, DD[15:0] valid before
IORDY active
11 tRD
12 tA
13 tB
14 tC
IORDY setup
0-4(3) (4)
0-4(3)
0-4(3)
35
1250
5
ns
ns
ns
IORDY pulse width
IORDY assertion to release
(1) P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2) DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in
the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
SPRUEQ3).
(3) The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information,
see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number SPRUEQ3).
(4) The tA parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order
to meet the tA parameter, a minimum frequency for SYSCLK4 is specified for each PIO as follows:
•
•
•
•
•
PIO mode 0, MIN frequency = 15 MHz
PIO mode 1, MIN frequency = 22 MHz
PIO mode 2, MIN frequency = 31 MHz
PIO mode 3, MIN frequency = 45 MHz
PIO mode 4, MIN frequency = 57 MHz
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t
0
DA[2:0],
ATA_CS0,
ATA_CS1
t
1
t
2
t
9
DIOW/DIOR
t
2i
t
3
t
4
DD[15:0](OUT)
t
6
t
5
DD[15:0] (IN)
t
6Z
(A)
IORDY
t
A
t
RD
t
C
(B)
IORDY
t
C
t
B
(C)
IORDY
A. IORDY is not negated for transfer (no wait generated)
B. IORDY is negative but is re-asserted before t (no wait is generated)
A
C. IORDY is negative before t and remains asserted until t ; data is driven valid at t (wait is generated)
A
B
RD
Figure 6-64. ATA PIO Data Transfer Timing
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6.20.3.2 ATA Multiword DMA Timing
Table 6-91. Timings for ATA Module — Multiword DMA AC Timing(1) (2) (see Figure 6-65)
-1G
NO.
UNIT
MODE
MIN
MAX
1
2
t0
Cycle time
0-2
0-2
0
(DMASTB + DMARCVR + 2)P - 0.5
(DMASTB + 1)P - 1
ns
ns
ns
ns
ns
tD
DIOW/DIOR active low pulse duration
150
60
DIOR data access, DIOR falling edge to DD[15:0]
valid
3
4
tE
1
2
50
DIOR data hold time, DD[15:0] valid after DIOR
rising edge
tF
0-2
0-2
5
ns
ns
DIOW/DIOR data setup time, DD[15:0] (OUT) valid
before DIOW/DIOR rising edge
(DMASTB)P
0
1
2
100
30
ns
ns
ns
5
6
tG
DIOW/DIOR data setup time, DD[15:0] (IN) valid
before DIOW/DIOR rising edge
20
DIOW data hold time, DD[15:0] valid after DIOW
rising edge
tH
0-2
(HWNHLD + 1)P + 1
ns
7
8
9
tI
DMACK to DIOW/DIOR setup
DIOW/DIOR to DMACK hold
DIOR negated pulse width
DIOW negated pulse width
0-2
0-2
0-2
0-2
0
(DMARCVR + 1)P - 1.7
5P - 5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJ
tKR
(DMARCVR + 1)P - 1
(DMARCVR + 1)P - 1
10 tKW
120
45
35
40
35
11 tLR
DIOR to DMARQ delay
1
2
0-1
2
12 tLW
DIOW to DMARQ delay
13 tM
14 tN
ATA_CSx valid to DIOW/DIOR setup
0-2
0-2
0
(DATRCVR)P - 1.7
5P - 1.7
ATA_CSx valid after DIOW/DIOR rising edge hold
20
25
15 tZ
DMACK to read data (DD[15:0]) released
1-2
(1) P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2) DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed
in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
SPRUEQ3).
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DA[2:0],
ATA_CS0,
ATA_CS1
t
0
t
M
t
N
DMARQ
DMACK
t
L
t
I
t
J
t
D
t
K
DIOW/DIOR
t
H
t
G
DD[15:0](OUT)
t
G
t
Z
t
F
t
E
DD[15:0] (IN)
Figure 6-65. ATA Multiword DMA Timing
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6.20.3.3 ATA Ultra DMA Timing
Table 6-92. Timings for ATA Module — Ultra DMA AC Timing(1) (2)
(see Figure 6-66 through Figure 6-75)
-1G
NO.
UNIT
MODE
MIN
25
MAX
28 f(SYSCLK4)
Operating frequency, SYSCLK4
0-5
0
MHz
ns
240
160
120
90
1
ns
2
ns
1
t2CYCTYP
Typical sustained average two cycle time
Cycle time, Strobe edge to Strobe edge
3
ns
4
60
ns
5
40
ns
2
3
tCYC
0-5
(UDMASTB + 1)P
ns
Two cycle time, rising to rising edge or falling to
falling edge
t2CYC
0-5
2(UDMASTB + 1)P
ns
0
1
15
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
tDS
Data setup, data valid before STROBE edge
Data hold, data valid after STROBE edge
2-3
4
5
5
4
0-4
5
5
tDH
4.6
70
48
31
20
6.7
4.8
0
1
2
Data valid INPUT setup time, data valid before
STROBE
3
6
tDVS
4
5
Data valid OUTPUT setup time, data valid before
STROBE
0-5
(UDMASTB)P - 3.1
ns
0-4
5
6.2
4.8
ns
ns
Data valid INPUT hold time, data valid after
STROBE
7
tDVH
Data valid OUTPUT hold time, data valid after
STROBE
0-5
0-5
0-5
1P - 2
P
ns
ns
ns
CRC word valid setup time at host, CRC valid
before DMACK negation
10 tCVS
11 tCVH
CRC word valid hold time at sender, CRC valid
after DMACK negation
2P
0-4
5
0
ns
ns
ns
ns
ns
ns
ns
ns
Time from STROBE output released-to-driving
until the first transition of critical timing
12 tZFS
35
70
48
31
20
6.7
25
0
1
2
Time from data output released-to-driving until
the first transition of critical timing
13 tDZFS
3
4
5
(1) P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2) UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value
programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in
the UDMATENV register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature
number SPRUEQ3).
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Table 6-92. Timings for ATA Module — Ultra DMA AC Timing
(see Figure 6-66 through Figure 6-75) (continued)
-1G
NO.
UNIT
MODE
MIN
MAX
230
200
170
130
120
90
0
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
14 tFS
First STROBE time
3
4
5
0-2
3-4
5
0
0
150
100
75
15 tLI
Limited interlock time
0
16 tMLI
17 tUI
Interlock time with minimum
Unlimited interlock time
0-5
0-5
20
0
Maximum time allowed for output drivers to
release
18 tAZ
19 tZAH
20 tZAD
0-5
0-5
0-5
10
ns
ns
ns
Minimum delay time required for output
20
0
Minimum delay time for driver to assert or negate
(from released)
Envelope time, DMACK to STOP and DMACK to
HDMARDY during in-burst initiation and from
DMACK to STOP during data out burst initiation
21 tENV
0-5
(TENV + 1)P - 0.5
(TENV + 1)P + 1.4
ns
0
1
75
70
60
50
ns
ns
ns
ns
22 tRFS
Ready-to-final-STROBE time
2-4
5
Ready to pause time, (HDMARDY (DIOR) to
STOP (DIOW))
0-5
(UDMATRP + 1)P - 0.8
ns
0
1
160
125
100
85
ns
ns
ns
ns
ns
ns
23 tRP
Ready to pause time, (DDMARDY (IORDY) to
DMARQ)
2-4
5
24 tIORDYZ
25 tZIORDY
Maximum time before releasing IORDY
Minimum time before driving IORDY
0-5
0-5
20
0
Setup and hold time for DMACK (before
assertion or negation)
26 tACK
0-5
20
ns
STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a
burst)
27 tSS
0-5
50
ns
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DMARQ
t
UI
t
t
FS
DMACK
t
ACK
t
ENV
t
ZAD
(A)
STOP (DIOW)
t
ACK
t
ENV
FS
(A)
HDMARDY (DIOR)
t
ZIORDY
t
ZAD
t
ZFS
(A)
DSTROBE (IORDY)
t
DZFS
t
DVH
t
AZ
t
DVS
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
A. The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-66. ATA Initiating an Ultra DMA Data-In Burst Timing
t
2CYC
(A)
CYC
t
(A)
CYC
t
DSTROBE
(IORDY)
t
DS
t
DH
t
DS
t
DH
t
DH
DD[15:0]
A. While DSTROBE (IORDY) timing is tCYC at the device, it may be different at the host due to propagation delay
differences on the cable.
Figure 6-67. ATA Sustained Ultra DMA Data-In Data Transfer Timing
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DMARQ
DMACK
STOP (DIOW)
t
RP
HDMARDY
(DIOR)
t
RFS
DSTROBE
(IORDY)
DD[15:0]
Figure 6-68. ATA Host Pausing an Ultra DMA Data-In Burst Timing
DMARQ
DMACK
t
MLI
t
LI
t
ACK
t
LI
STOP (DIOW)
t
LI
t
ACK
HDMARDY
(DIOR)
t
SS
t
IORDYZ
DSTROBE
(IORDY)
t
t
ZAH
CVH
t
t
AZ
CVS
CRC
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-69. ATA Device Terminating an Ultra DMA Data-In Burst Timing
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DMARQ
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t
LI
t
MLI
DMACK
t
ACK
t
RP
STOP (DIOW)
t
ZAH
t
ACK
t
AZ
HDMARDY
(DIOR)
t
LI
t
t
MLI
RFS
t
IORDYZ
DSTROBE
(IORDY)
t
CVS
t
CVH
CRC
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-70. ATA Host Terminating an Ultra DMA Data-In Burst Timing
DMARQ
t
UI
DMACK
t
ACK
t
ENV
(A)
STOP (DIOW)
t
LI
t
t
UI
ZIORDY
(A)
(A)
DDMARDY (IORDY)
HSTROBE (DIOR)
t
ACK
t
DZFS
t
DVH
t
DVS
DD[15:0]
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
A. The definitions for the DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-71. ATA Initiating an Ultra DMA Data-Out Burst Timing
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t
2CYC
t
2CYC
(A)
CYC
t
(A)
CYC
t
HSTROBE (DIOR)
t
DVS
t
DVH
t
DVH
t
t
DVS
DVH
DD[15:0] (OUT)
A. While HSTROBE (DIOR) timing is tCYC at the host, it may be different at the device due to propagation delay
differences on the cable.
Figure 6-72. ATA Sustained Ultra DMA Data-Out Transfer Timing
DMARQ
t
RP
DMACK
STOP (DIOW)
DDMARDY (IORDY)
t
RFS
HSTROBE
(DIOR)
DD[15:0]
Figure 6-73. ATA Device Pausing an Ultra DMA Data-Out Burst Timing
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t
LI
DMARQ
DMACK
t
MLI
t
LI
t
ACK
t
SS
STOP (DIOW)
t
LI
t
IORDYZ
DDMARDY (IORDY)
HSTROBE (DIOR)
t
ACK
t
CVS
t
CVH
DD[15:0]
CRC
t
ACK
DA[2:0],
ATA_CS0, ATA_CS1
Figure 6-74. ATA Host Terminating an Ultra DMA Data-Out Burst Timing
DMARQ
DMACK
t
t
LI
ACK
t
MLI
STOP (DIOW)
t
RP
t
IORDYZ
DDMARDY
(IORDY)
t
RFS
t
ACK
t
LI
t
MLI
HSTROBE
(DIOR)
t
CVS
t
CVH
DD[15:0]
CRC
t
ACK
DA[2:0],
ATA_CS0,
ATA_CS1
Figure 6-75. ATA Device Terminating an Ultra DMA Data-Out Burst Timing
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6.20.3.4 ATA HDDIR Timing
Figure 6-76 through Figure 6-79 show the behavior of HDDIR for the different types of transfers.
Table 6-93. Timing Requirements for HDDIR(1)
-1G
NO.
UNIT
MIN
MAX
1
tc
Cycle time, ATA_CS[1:0] to HDDIR low
E - 3.1
ns
(1) E = ATA clock cycle
DA[2:0],
ATA_CS0,
ATA_CS1
(A)
t
C
(A)
t
C
HDDIR
DIOW
DD[15:0] (OUT)
A.
t
C
≥ one cycle
Figure 6-76. ATA HDDIR Taskfile Write/Single PIO Write Timing
DA[2:0],
ATA_CS0,
ATA_CS1
(A)
t
C
(A)
t
C
HDDIR
DIOW
DD[15:0] (OUT)
A.
t ≥ one cycle
C
Figure 6-77. ATA HDDIR PIO Postwrite Start Timing
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DA[2:0],
ATA_CS0,
ATA_CS1
DMACK
HDDIR
(A)
(A)
t
C
t
C
DIOW
DD[15:0] (OUT)
A.
t
C
≥ one cycle
Figure 6-78. ATA HDDIR Multiword DMA Write Transfer Timing
DA[2:0],
ATA_CS0,
ATA_CS1
DMACK
HDDIR
(A)
t
C
DIOW
DD[15:0] (OUT)
A. ≥ one cycle
CRC
t
C
Figure 6-79. ATA HDDIR Ultra DMA Write Transfer Timing
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6.21 VLYNQ
The VCE6467T VLYNQ peripheral provides a high speed serial communications interface with the
following features.
•
•
•
Low Pin Count
Scalable Performance/Support
Simple Packet Based Transfer Protocol for Memory Mapped Access
–
–
–
–
Write Request/Data Packet
Read Request Packet
Read Response Data Packet
Interrupt Request Packet
•
Supports both Symmetric and Asymmetric Operation
–
–
–
Tx pins on first device connect to Rx pins on second device and vice versa
Data pin widths are automatically detected after reset
Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins
–
Supports both Host/Peripheral and Peer-to-Peer communication
•
•
Simple Block Code Packet Formatting (8-bit/10-bit)
In Band Flow Control
–
–
–
No extra pins needed
Allows receiver to momentarily throttle back transmitter when overflow is about to occur
Uses built in special code capability of block code to seamlessly interleave flow control information
with user data
–
Allows system designer to balance cost of data buffering versus performance
•
•
•
Multiple outstanding transactions
Automatic packet formatting optimizations
Internal loop-back mode
6.21.1 VLYNQ Bus Master Memory Map
The VLYNQ peripheral includes a bus master interface that allows external device initiated transfers to
access the VCE6467T system bus. Table 6-94 shows the memory map for the VLYNQ master interface.
Table 6-94. VLYNQ Master Memory Map
SIZE
(BYTES)
START ADDRESS
END ADDRESS
HPI ACCESS
0x0000 0000
0x01C0 0000
0x1000 0000
0x1001 0000
0x1001 4000
0x1001 8000
0x01BF FFFF
0x0FFF FFFF
0x1000 FFFF
0x1001 3FFF
0x1001 7FFF
0x1001 FFFF
28M
Reserved
228M
64K
CFG Bus Peripherals
Reserved
16K
ARM RAM 0 (Data)
ARM RAM 1 (Data)
ARM ROM (Data)
16K
32K
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Table 6-94. VLYNQ Master Memory Map (continued)
SIZE
START ADDRESS
END ADDRESS
HPI ACCESS
(BYTES)
16256K
4M
0x1002 0000
0x10FF FFFF
0x113F FFFF
0x114F FFFF
0x115F FFFF
0x116F FFFF
0x117F FFFF
0x1180 FFFF
0x1181 7FFF
0x1183 7FFF
0x118F FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x11FF FFFF
0x41FF FFFF
0x43FF FFFF
0x45FF FFFF
0x47FF FFFF
0x49FF FFFF
0x7FFF FFFF
0x9FFF FFFF
0xBFFF FFFF
0xFFFF FFFF
0x1100 0000
0x1140 0000
0x1150 0000
0x1160 0000
0x1170 0000
0x1180 0000
0x1181 0000
0x1181 8000
0x1183 8000
0x1190 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x1200 0000
0x4200 0000
0x4400 0000
0x4600 0000
0x4800 0000
0x4A00 0000
0x8000 0000
0xA000 0000
0xC000 0000
1M
1M
Reserved
1M
1M
64K
32K
128K
800K
5M
C64x+ L2 RAM/Cache
Reserved
32K
C64x+ L1P RAM/Cache
Reserved
992K
32K
C64x+ L1D RAM/Cache
992K
768M
32M
32M
32M
32M
864M
512M
512M
1G
Reserved
EMIFA Data (CS2)
EMIFA Data (CS3)
EMIFA Data (CS4)
EMIFA Data (CS5)
Reserved
DDR2 Memory Controller
Reserved
Reserved
6.21.2 VLYNQ Peripheral Register Description(s)
Table 6-95. VLYNQ Registers
HEX ADDRESS RANGE
0x2001 0000
0x2001 0004
0x2001 0008
0x2001 000C
0x2001 0010
0x2001 0014
0x2001 0018
0x2001 001C
0x2001 0020
0x2001 0024
0x2001 0028
0x2001 002C
0x2001 0030
0x2001 0034
0x2001 0038
0x2001 003C
0x2001 0040
ACRONYM
REGISTER NAME
REVID
CTRL
VLYNQ Revision Register
VLYNQ Local Control Register
STAT
VLYNQ Local Status Register
INTPRI
VLYNQ Local Interrupt Priority Vector Status/Clear Register
VLYNQ Local Unmasked Interrupt Status/Clear Register
VLYNQ Local Interrupt Pending/Set Register
VLYNQ Local Interrupt Pointer Register
INTSTATCLR
INTPENDSET
INTPTR
XAM
VLYNQ Local Transmit Address Map Register
VLYNQ Local Receive Address Map Size 1 Register
VLYNQ Local Receive Address Map Offset 1 Register
VLYNQ Local Receive Address Map Size 2 Register
VLYNQ Local Receive Address Map Offset 2 Register
VLYNQ Local Receive Address Map Size 3 Register
VLYNQ Local Receive Address Map Offset 3 Register
VLYNQ Local Receive Address Map Size 4 Register
VLYNQ Local Receive Address Map Offset 4 Register
VLYNQ Local Chip Version Register
RAMS1
RAMO1
RAMS2
RAMO2
RAMS3
RAMO3
RAMS4
RAMO4
CHIPVER
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Table 6-95. VLYNQ Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x2001 0044
0x2001 0048
AUTNGO
VLYNQ Local Auto Negotiation Register
Reserved
–
0x2001 004C
–
Reserved
0x2001 0050 - 0x2001 005C
0x2001 0060
–
–
Reserved
Reserved
0x2001 0064
–
Reserved
0x2001 0068 - 0x2001 007C
0x2001 0080
–
Reserved for future use
VLYNQ Remote Revision Register
VLYNQ Remote Control Register
VLYNQ Remote Status Register
RREVID
RCTRL
RSTAT
RINTPRI
0x2001 0084
0x2001 0088
0x2001 008C
VLYNQ Remote Interrupt Priority Vector Status/Clear Register
0x2001 0090
RINTSTATCLR VLYNQ Remote Unmasked Interrupt Status/Clear Register
RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register
0x2001 0094
0x2001 0098
RINTPTR
RXAM
VLYNQ Remote Interrupt Pointer Register
0x2001 009C
VLYNQ Remote Transmit Address Map Register
0x2001 00A0
RRAMS1
RRAMO1
RRAMS2
RRAMO2
RRAMS3
RRAMO3
RRAMS4
RRAMO4
VLYNQ Remote Receive Address Map Size 1 Register
VLYNQ Remote Receive Address Map Offset 1 Register
VLYNQ Remote Receive Address Map Size 2 Register
VLYNQ Remote Receive Address Map Offset 2 Register
VLYNQ Remote Receive Address Map Size 3 Register
VLYNQ Remote Receive Address Map Offset 3 Register
VLYNQ Remote Receive Address Map Size 4 Register
VLYNQ Remote Receive Address Map Offset 4 Register
0x2001 00A4
0x2001 00A8
0x2001 00AC
0x2001 00B0
0x2001 00B4
0x2001 00B8
0x2001 00BC
VLYNQ Remote Chip Version Register (values on the device_id and
device_rev pins of remote VLYNQ)
0x2001 00C0
RCHIPVER
0x2001 00C4
0x2001 00C8
RAUTNGO
RMANNGO
RNGOSTAT
–
VLYNQ Remote Auto Negotiation Register
VLYNQ Remote Manual Negotiation Register
VLYNQ Remote Negotiation Status Register
Reserved
0x2001 00CC
0x2001 00D0 - 0x2001 00DC
VLYNQ Remote Interrupt Vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of
remote VLYNQ)
0x2001 00E0
0x2001 00E4
RINTVEC0
RINTVEC1
VLYNQ Remote Interrupt Vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of
remote VLYNQ)
0x2001 00E8 - 0x2001 00FC
0x2001 0100 - 0x2001 0FFF
–
–
Reserved for future use
Reserved
VLYNQ Remote Devices
64 MB Remote Data Region. Translated into one of four mapped registers on
the remote device.
0x4C00 0000 - 0x4FFF FFFF
VLYNQREMOTE
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6.21.3 VLYNQ Electrical Data/Timing
Table 6-96. Timing Requirements for VLYNQ_CLOCK Input (see Figure 6-80)
-1G
MIN
NO.
UNIT
MAX
1
2
3
4
tc(VCLK)
tw(VCLKH)
tw(VCLKL)
tt(VCLK)
Cycle time, VLYNQ_CLOCK
9.6
3
ns
ns
ns
ns
Pulse duration, VLYNQ_CLOCK high
Pulse duration, VLYNQ_CLK low
Transition time, VLYNQ_CLOCK
3
3
Table 6-97. Switching Characteristics Over Recommended Operating Conditions for VLYNQ_CLOCK
Output (see Figure 6-80)
-1G
NO.
PARAMETER
UNIT
MIN
9.6
4
MAX
1
2
3
4
tc(VCLK)
tw(VCLKH)
tw(VCLKL)
tt(VCLK)
Cycle time, VLYNQ_CLOCK
ns
ns
ns
ns
Pulse duration, VLYNQ_CLOCK high
Pulse duration, VLYNQ_CLOCK low
Transition time, VLYNQ_CLOCK
4
3
1
4
2
VLYNQ_CLOCK
4
3
Figure 6-80. VLYNQ_CLOCK Timing for VLYNQ
Table 6-98. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the
VLYNQ Module (see Figure 6-81)
-1G
NO
.
PARAMETER
FAST MODE
SLOW MODE
UNIT
MIN
MAX
MIN
MAX
td(VCLKH-
TXDI)
1
2
Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] invalid
Delay time, VLYNQ_CLOCK high to VLYNQ_TXD[3:0] valid
1
2.21
ns
ns
td(VCLKH-
TXDV)
7.14
8.5
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Table 6-99. Timing Requirements for Receive Data for the VLYNQ Module(1) (see Figure 6-81)
-1G
MIN
NO.
UNIT
MAX
RTM disabled, RTM sample = 3
RTM enabled
0.2
(1)
ns
ns
ns
ns
Setup time, VLYNQ_RXD[3:0] valid before
VLYNQ_CLOCK high
3
4
tsu(RXDV-VCLKH)
RTM disabled, RTM sample = 3
RTM enabled
2
(1)
Hold time, VLYNQ_RXD[3:0] valid after
VLYNQ_CLOCK high
th(VCLKH-RXDV)
(1) The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see Table 6-100). When
RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.
Table 6-100. RTM RX Data Flop Hold/Setup Timing
Constraints
RX Data Flop
HOLD (Y)
0.62
SETUP (X)
1.3
0
1
2
3
4
5
6
7
1.43
0.8
1.66
0.4
2.12
0.2
2.5
0
3.18
-0.3
-0.5
-0.7
3.87
4.25
1
VLYNQ_CLOCK
2
Data
Data
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
4
3
Figure 6-81. VLYNQ Transmit/Receive Timing
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6.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
6.22.1 McASP Device-Specific Information
The VCE6467T device includes two multichannel audio serial port (McASP) interface peripherals
(McASP0 and McASP1). The McASP0 module consists of a transmit and receive section. These sections
can operate completely independently with different data formats, separate master clocks, bit clocks, and
frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP0 module
also includes a pool of 4 shift registers that may be configured to operate as either transmit data or
receive data.
The transmit section of the McASP0 can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP0 peripheral supports
the TDM synchronous serial format.
The McASP0 module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format. However, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode which is useful for non-audio data (for example,
passing control information between two DSPs).
The McASP0 peripheral has additional capability for flexible clock generation, and error
detection/handling, as well as error management.
The VCE6467T McASP1 module is a reduced feature version of the McASP peripheral. The McASP1
module provides a single transmit-only shift register and can transmit data in DIT format only.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320DM646x
DMSoC Multichannel Audio Serial Port (McASP) User's Guide (literature number SPRUER1).
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6.22.2 McASP0 and McASP1 Peripheral Register Description(s)
Table 6-101. McASP0 Control Registers
HEX ADDRESS RANGE
01D0 1000
ACRONYM
REGISTER NAME
PID
Peripheral Identification register [Register value: 0x0010 0101]
01D0 1004
–
Reserved
01D0 1008
–
Reserved
01D0 100C
–
Reserved
01D0 1010
PFUNC
Pin function register
Pin direction register
Reserved
01D0 1014
PDIR
01D0 1018
–
01D0 101C
–
–
Reserved
01D0 1020
Reserved
01D0 1024 – 01D0 1040
01D0 1044
–
Reserved
GBLCTL
AMUTE
DLBCTL
DITCTL
–
Global control register
Mute control register
Digital Loop-back control register
DIT mode control register
Reserved
01D0 1048
01D0 104C
01D0 1050
01D0 1054 – 01D0 105C
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
01D0 1060
RGBLCTL
01D0 1064
01D0 1068
RMASK
RFMT
Receiver format UNIT bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
01D0 106C
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
01D0 1070
01D0 1074
High-frequency receive clock control register
Receive TDM slot 0–31 register
Receiver interrupt control register
Status register – Receiver
01D0 1078
01D0 107C
RINTCTL
RSTAT
01D0 1080
01D0 1084
RSLOT
Current receive TDM slot register
Receiver clock check control register
Receiver DMA event control register
Reserved
01D0 1088
RCLKCHK
REVTCTL
–
01D0 108C
01D0 1090 – 01D0 109C
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
01D0 10A0
XGBLCTL
01D0 10A4
01D0 10A8
01D0 10AC
01D0 10B0
01D0 10B4
01D0 10B8
01D0 10BC
01D0 10C0
01D0 10C4
01D0 10C8
01D0 10CC
XMASK
XFMT
Transmit format UNIT bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
High-frequency Transmit clock control register
Transmit TDM slot 0–31 register
Transmit interrupt control register
Status register – Transmitter
XINTCTL
XSTAT
XSLOT
Current transmit TDM slot
XCLKCHK
XEVTCTL
Transmit clock check control register
Transmit DMA event control register
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Table 6-101. McASP0 Control Registers (continued)
HEX ADDRESS RANGE
01D0 10D0 – 01D0 10FC
01D0 1100
ACRONYM
–
REGISTER NAME
Reserved
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
–
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Reserved
01D0 1104
01D0 1108
01D0 110C
01D0 1110
01D0 1114
01D0 1118
01D0 111C
01D0 1120
01D0 1124
01D0 1128
01D0 112C
01D0 1130
01D0 1134
01D0 1138
01D0 113C
01D0 1140
01D0 1144
01D0 1148
01D0 114C
01D0 1150
01D0 1154
01D0 1158
01D0 115C
01D0 1160 – 01D0 117C
01D0 1180
SRCTL0
SRCTL1
SRCTL2
SRCTL3
–
Serializer 0 control register
01D0 1184
Serializer 1 control register
01D0 1188
Serializer 2 control register
01D0 118C
Serializer 3 control register
01D0 1190 – 01D0 11FC
01D0 1200
Reserved
XBUF0
Transmit Buffer for Serializer 0
01D0 1204
XBUF1
Transmit Buffer for Serializer 1
01D0 1208
XBUF2
Transmit Buffer for Serializer 2
01D0 120C
XBUF3
Transmit Buffer for Serializer 3
01D0 1210 – 01D0 127C
01D0 1280
–
Reserved
RBUF0
Receive Buffer for Serializer 0
01D0 1284
RBUF1
Receive Buffer for Serializer 1
01D0 1288
RBUF2
Receive Buffer for Serializer 2
01D0 128C
RBUF3
Receive Buffer for Serializer 3
01D0 1290 – 01D0 13FF
–
Reserved
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Table 6-102. McASP0 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT registers,
respectively].)
McASP0 receive buffers or McASP0 transmit buffers via
the Peripheral Data Bus.
01D0 1400 – 01D0 17FF RBUF0/XBUF0
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Table 6-103. McASP1 Control Registers
HEX ADDRESS RANGE
01D0 1800
ACRONYM
REGISTER NAME
PID
Peripheral Identification register [Register value: 0x0010 0101]
01D0 1804
–
Reserved
01D0 1808
–
Reserved
01D0 180C
–
Reserved
01D0 1810
PFUNC
Pin function register
Pin direction register
Reserved
01D0 1814
PDIR
01D0 1818
–
01D0 181C
–
Reserved
01D0 1820
–
Reserved
01D0 1824 – 01D0 1843
01D0 1844
–
GBLCTL
–
Reserved
Global control register
Reserved
01D0 1848
01D0 184C
DLBCTL
DITCTL
–
Digital Loop-back control register
DIT mode control register
Reserved
01D0 1850
01D0 1854 – 01D0 185F
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
01D0 1860
RGBLCTL
01D0 1864
01D0 1868
–
Reserved
–
Reserved
01D0 186C
–
Reserved
01D0 1870
–
Reserved
01D0 1874
–
Reserved
01D0 1878
–
Reserved
01D0 187C
RINTCTL
Receiver interrupt control register
Status register – Receiver
01D0 1880
RSTAT
01D0 1884
–
–
–
–
01D0 1888
01D0 188C
01D0 1890 – 01D0 189F
Reserved
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
01D0 18A0
XGBLCTL
01D0 18A4
01D0 18A8
01D0 18AC
01D0 18B0
01D0 18B4
01D0 18B8
01D0 18BC
01D0 18C0
01D0 18C4
01D0 18C8
01D0 18CC
XMASK
XFMT
Transmit format UNIT bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
High-frequency Transmit clock control register
Transmit TDM slot 0–31 register
Transmit interrupt control register
Status register – Transmitter
XINTCTL
XSTAT
XSLOT
Current transmit TDM slot
XCLKCHK
XEVTCTL
Transmit clock check control register
Transmit DMA event control register
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Table 6-103. McASP1 Control Registers (continued)
HEX ADDRESS RANGE
01D0 18D0 – 01D0 18FF
01D0 1900
ACRONYM
–
REGISTER NAME
Reserved
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
–
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Reserved
01D0 1904
01D0 1908
01D0 190C
01D0 1910
01D0 1914
01D0 1918
01D0 191C
01D0 1920
01D0 1924
01D0 1928
01D0 192C
01D0 1930
01D0 1934
01D0 1938
01D0 193C
01D0 1940
01D0 1944
01D0 1948
01D0 194C
01D0 1950
01D0 1954
01D0 1958
01D0 195C
01D0 1960 – 01D0 197F
01D0 1980
SRCTL0
Serializer 0 control register
01D0 1984 – 01D0 19FF
01D0 1A00
–
Reserved
XBUF0
Transmit Buffer for Serializer 0
01D0 1A04 – 01D0 13FF
–
Reserved
Table 6-104. McASP1 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when XSEL bits = 0
[these bits are located in the
XFMT register].)
01D0 1C00 – 01D0 1FFF
XBUF1
McASP1 transmit buffers via the Peripheral Data Bus.
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6.22.3 McASP0 and McASP1 Electrical Data/Timing
6.22.3.1 Multichannel Audio Serial Port (McASP0) Timing
Table 6-105. Timing Requirements for McASP0 (see Figure 6-82 and Figure 6-83)(1)
-1G
MAX
NO.
UNIT
MIN
20.8
1
2
3
4
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKR/X
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
8.3
37
15
15
3
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR int
tw(CKRX)
Pulse duration, ACLKR/X high or low
5
6
tsu(FRX-CKRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
0
th(CKRX-FRX)
3
15
14
3
7
8
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
ACLKX int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
3
th(CKRX-AXR)
3
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
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Table 6-106. Switching Characteristics Over Recommended Operating Conditions for McASP0(1) (2) (3)
(see Figure 6-82 and Figure 6-83)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
9
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKR/X
41.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
AH - 2.5
ACLKR/X int
ACLKR/X int
ACLKR int
ACLKX int
41.7
tw(CKRX)
Pulse duration, ACLKR/X high or low
A - 2.5
-2
-1
0
5
5
13
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR ext
ACLKX ext
ACLKX int
15
16
5
0
-2
0
14
15
td(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKX ext
ACLKR/X int
ACLKR/X ext
16
8
-3
-3
Disable time, AXR high impedance following last data bit
from ACLKR/X transmit edge
tdis(CKRX-AXRHZ)
15
(1) A = (ACLKR/X period)/2 in ns. For example, when ACLKR/X period is 25 ns, use A = 12.5 ns.
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.
(3) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-82. McASP0 and McASP1 Input Timings
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 6-83. McASP0 and McASP1 Output Timings
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6.22.3.2 Multichannel Audio Serial Port (McASP1) DIT Timing
Table 6-107. Timing Requirements for McASP1 (see Figure 6-82 and Figure 6-83)(1)
-1G
MAX
NO.
UNIT
MIN
20.8
1
2
3
4
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKX
ns
ns
ns
ns
Pulse duration, AHCLKX high or low
Cycle time, ACLKX
8.3
37
15
ACLKX ext
ACLKX ext
tw(CKRX)
Pulse duration, ACLKX high or low
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
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Table 6-108. Switching Characteristics Over Recommended Operating Conditions for McASP1(1) (2) (3)
(see Figure 6-82 and Figure 6-83)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
9
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKX
41.7
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
Pulse duration, AHCLKX high or low
Cycle time, ACLKX
AH - 2.5
41.7
tw(CKRX)
Pulse duration, ACLKX high or low
ACLKR/X int
ACLKX int
ACLKX ext
ACLKX int
ACLKX ext
A - 2.5
-1
0
5
14
15
td(CKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
16
8
-3
-3
Disable time, AXR high impedance following last data bit
from ACLKX transmit edge
tdis(CKRX-AXRHZ)
15
(1) A = (ACLKX period)/2 in ns. For example, when ACLKX period is 25 ns, use A = 12.5 ns.
(2) AH = (AHCLKX period)/2 in ns. For example, when AHCLKX period is 25 ns, use AH = 12.5 ns.
(3) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
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6.23 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (2-to-16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the TMS320DM646x DMSoC and external peripherals. Typical
applications inlcude a interface to external I/O or peripheral expansion via devices such as shift regisers,
display drivers, SPI EEPROMs, and Analog-to-Digital Converters (ADCs).
6.23.1 SPI Device-Specific Information
The VCE6467T SPI supports the following features:
•
•
•
•
•
•
•
Master/slave operation
2 chip selects for interfacing/control to multiple SPI slave devices
3-, 4-, 5-wire interface [The VCE6467T supports 3-pin mode, 2 4-pin modes, and the 5-pin mode.]
16-bit shift register
Receive buffer register
8-bit clock prescaler
Programmable SPI clock frequency range, character length, and clock phase and polarity
6.23.2 SPI Peripheral Register Description(s)
Table 6-109 shows the SPI registers.
Table 6-109. SPI Registers
HEX ADDRESS RANGE
01C6 6800
ACRONYM
SPIGCR0
SPIGCR1
SPIINT
REGISTER NAME
SPI Global Control Register 0
SPI Global Control Register 1
SPI Interrupt Register
01C6 6804
01C6 5808
01C6 680C
SPIILVL
SPIFLG
SPIPC0
–
SPI Interrupt Level Register
SPI Flag Status Register
SPI Pin Control Register 0
Reserved
01C6 6810
01C6 6814
01C6 6818
01C6 681C
SPIPC2
–
SPI Pin Control Register 2
Reserved
01C6 6820 – 01C6 6838
01C6 683C
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
INTVEC0
INTVEC1
–
SPI Shift Register 1
01C6 6840
SPI Buffer Register
01C6 6844
SPI Emulation Register
SPI Delay Register
01C6 6848
01C6 684C
SPI Default Chip Select Register
SPI Data Format Register 0
SPI Data Format Register 1
SPI Data Format Register 2
SPI Data Format Register 3
SPI Interrupt Vector Register 0
SPI Interrupt Vector Register 1
Reserved
01C6 6850
01C6 6854
01C6 6858
01C6 685C
01C6 6860
01C6 6864
01C6 6868 – 01C6 6FFF
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6.23.3 SPI Electrical Data/Timing
Master Mode — General
Table 6-110. General Switching Characteristics in Master Mode(1)
-1G
MIN
NO.
PARAM2ETER
UNIT
MAX
1
2
3
tc(CLK)
Cycle time, SPI_CLK
2P
P
ns
ns
ns
tw(CLKH)
tw(CLKL)
Pulse width, SPI_CLK high
Pulse width, SPI_CLK low
P
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_CLK
rising edge, 3-/4-/5-pin mode,
polarity = 0, phase = 0
2P
0.5T + 2P
2P
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_CLK
rising edge, 3-/4-/5-pin mode,
polarity = 0, phase = 1
4
5
6
tosu(SIMO-CLK)
td(CLK-SIMO)
toh(CLK-SIMO)
ns
ns
ns
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_CLK
falling edge, 3-/4-/5-pin mode,
polarity = 1, phase = 0
Output setup time, SPI_SIMO valid (1st bit) before initial SPI_CLK
falling edge, 3-/4-/5-pin mode,
polarity = 1, phase = 1
0.5T + 2P
Delay time, SPI_CLK transmit rising edge to SPI_SIMO output valid
(subsequent bit driven), 3-/4-/5-pin mode, polarity = 0, phase = 0
5
5
Delay time, SPI_CLK transmit falling edge to SPI_SIMO output
valid (subsequent bit driven), 3-/4-/5-pin mode, polarity = 0, phase
= 1
Delay time, SPI_CLK transmit falling edge to SPI_SIMO output
valid (subsequent bit driven), 3-/4-/5-pin mode, polarity = 1, phase
= 0
5
5
Delay time, SPI_CLK transmit rising edge to SPI_SIMO output valid
(subsequent bit driven), 3-/4-/5-pin mode, polarity = 1, phase = 1
Output hold time, SPI_SIMO valid (except final bit) after receive
falling edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 0, phase = 0
0.5T – 4
0.5T – 4
0.5T – 4
0.5T – 4
Output hold time, SPI_SIMO valid (except final bit) after receive
rising edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 0, phase = 1
Output hold time, SPI_SIMO valid (except final bit) after receive
rising edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 1, phase = 0
Output hold time, SPI_SIMO valid (except final bit) after receive
falling edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 1, phase = 1
(1) T = period of SPI_CLK; P = period of SPI core clock
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UNIT
Table 6-111. General Input Timing Requirements in Master Mode
-1G
MIN
NO.
MAX
Setup time, SPI_SOMI valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 0, phase = 0
4
4
4
4
Setup time, SPI_SOMI valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 0, phase = 1
7
tsu(SOMI-CLK)
ns
Setup time, SPI_SOMI valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 1, phase = 0
Setup time, SPI_SOMI valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 1, phase = 1
Hold time, SPI_SOMI valid after receive falling edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 0, phase = 0
2
2
2
2
Hold time, SPI_SOMI valid after receive rising edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 0, phase = 1
8
th(CLK-SOMI)
ns
Hold time, SPI_SOMI valid after receive rising edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 1, phase = 0
Hold time, SPI_SOMI valid after receive falling edge of SPI_CLK,
3-/4-/5-pin mode, polarity = 1, phase = 1
314
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Slave Mode — General
Table 6-112. General Switching Characteristics in Slave Mode (For 3-/4-/5-Pin Modes)(1)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, transmit rising edge of SPI_CLK to SPI_SOMI output
valid, 3-/4-/5-pin mode, polarity = 0, phase = 0
15
15
15
15
Delay time, transmit falling edge of SPI_CLK to SPI_SOMI output
valid, 3-/4-/5-pin mode, polarity = 0, phase = 1
13
td(CLK-SOMI)
ns
Delay time, transmit falling edge of SPI_CLK to SPI_SOMI output
valid, 3-/4-/5-pin mode, polarity = 1, phase = 0
Delay time, transmit rising edge of SPI_CLK to SPI_SOMI output
valid, 3-/4-/5-pin mode, polarity = 1, phase = 1
Output hold time, SPI_SOMI valid (except final bit) after receive
falling edge of SPI_CLK, 3-/4-/5-pin mode, polarity = 0, phase = 0
0.5T – 4
0.5T – 4
0.5T – 4
0.5T – 4
Output hold time, SPI_SOMI valid (except final bit) after receive
rising edge of SPI_CLK, 3-/4-/5-pin mode, polarity = 0, phase = 1
14
toh(CLK-SOMI)
ns
Output hold time, SPI_SOMI valid (except final bit) after receive
rising edge of SPI_CLK, 3-/4-/5-pin mode, polarity = 1, phase = 0
Output hold time, SPI_SOMI valid (except final bit) after receive
falling edge of SPI_CLK, 3-/4-/5-pin mode, polarity = 1, phase = 1
(1) T = period of SPI_CLK
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UNIT
Table 6-113. General Input Timing Requirements in Slave Mode(1)
-1G
MIN
NO.
MAX
9
tc(CLK)
Cycle time, SPI_CLK
2P
P
ns
ns
ns
10
11
tw(CLKH)
tw(CLKL)
Pulse width, SPI_CLK high
Pulse width, SPI_CLK low
P
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 0, phase = 0
2P
2P
2P
2P
2
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 0, phase = 1
15
tsu(SIMO-CLK)
ns
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 1, phase = 0
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 1, phase = 1
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
polarity = 0, phase = 0
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 0, phase = 1
16
th(CLK-SIMO)
ns
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 1, phase = 0
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
2
polarity = 1, phase = 1
(1) P = period of SPI core clock
316
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Master Mode — Additional
Table 6-114. Additional Output Switching Characteristics of 4-Pin Enable Option in Master Mode(1) (2)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 0
3P + 6
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 1
0.5T + 3P + 6
3P + 6
17
td(EN-CLK)
ns
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 0
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 1
0.5T + 3P + 6
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-86 shows only polarity = 0, phase = 0 as an example. In this case, the Master SPI is ready with new data before SPI_EN
assertion.
Table 6-115. Additional Input Timing Requirements of 4-Pin Enable Option in Master Mode(1) (2)
-1G
MIN
NO.
UNIT
MAX
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK falling edge, 4-pin mode,polarity = 0, phase = 0
0.5T + P
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK falling edge, 4-pin mode,polarity = 0, phase = 1
P
0.5T + P
P
18
td(CLK-EN)
ns
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK rising edge, 4-pin mode,polarity = 1, phase = 0
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK rising edge, 4-pin mode,polarity = 1, phase = 1
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-86 shows only polarity = 0, phase = 0 as an example. In this case, the Master SPI is ready with new data before SPI_EN
deassertion.
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Table 6-116. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode(1)(2)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
Output setup time, SPI_CS[n] active before first
SPI_CLK rising edge, polarity = 0, phase = 0,
SPIDELAY.C2TDELAY = 0
(C2TDELAY + 2) * P - 6
Output setup time, SPI_CS[n] active before first
SPI_CLK rising edge, polarity = 0, phase = 1,
SPIDELAY.C2TDELAY = 0
(C2TDELAY + 2) * P - 6
(C2TDELAY + 2) * P - 6
(C2TDELAY + 2) * P - 6
(3)
19
tosu(CS-CLK)
ns
Output setup time, SPI_CS[n] active before first
SPI_CLK falling edge, polarity = 1, phase = 0,
SPIDELAY.C2TDELAY = 0
Output setup time, SPI_CS[n] active before first
SPI_CLK falling edge, polarity = 1, phase = 1,
SPIDELAY.C2TDELAY = 0
Delay time, final SPI_CLK falling edge to master
deasserting SPI_CS[n], polarity = 0, phase = 0,
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD
not enabled
(T2CDELAY + 1) * P - 6
(T2CDELAY + 1) * P - 6
(T2CDELAY + 1) * P - 6
(T2CDELAY + 2) * P - 6
Delay time, final SPI_CLK falling edge to master
deasserting SPI_CS[n], polarity = 0, phase = 1,
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD
not enabled
20
td(CLK-CS)
ns
Delay time, final SPI_CLK rising edge to master
deasserting SPI_CS[n], polarity = 1, phase = 0,
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD
not enabled
Delay time, final SPI_CLK rising edge to master
deasserting SPI_CS[n], polarity = 1, phase = 1,
SPIDELAY.T2CDELAY = 0, SPIDAT1.CSHOLD
not enabled
(1) P = period of SPI core clock
(2) Figure 6-86 shows only polarity = 0, phase = 0 as an example.
(3) The Master SPI is ready with new data before SPI_CS[n] assertion.
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Table 6-117. Additional Output Switching Characteristics of 5-Pin Option in Master Mode(1)
-1G
MIN
NO.
PARAMETER
UNIT
MAX
Delay time, final SPI_CLK falling edge to
master deasserting SPI_CS[n],
polarity = 0, phase = 0,
SPIDELAY.T2CDELAY = 0,
SPIDAT1.CSHOLD not enabled
(T2CDELAY + 2) * P - 6
(T2CDELAY + 2) * P - 6
(T2CDELAY + 2) * P - 6
(T2CDELAY + 2) * P - 6
Delay time, final SPI_CLK rising edge to
master deasserting SPI_CS[n],
polarity = 0, phase = 1,
SPIDELAY.T2CDELAY[4:0] = 0,
SPIDAT1.CSHOLD not enabled
(2)
32
td(CLK-CS)
ns
Delay time, final SPI_CLK rising edge to
master deasserting SPI_CS[n],
polarity = 1, phase = 0,
SPIDELAY.T2CDELAY = 0,
SPIDAT1.CSHOLD not enabled
Delay time, final SPI_CLK falling edge to
master deasserting SPI_CS[n],
polarity = 1, phase = 1,
SPIDELAY.T2CDELAY = 0,
SPIDAT1.CSHOLD not enabled
Output setup time, SPI_CS[n] active before
first SPI_CLK rising edge, polarity = 0,
phase = 0, SPIDELAY.C2TDELAY = 0
(C2TDELAY + 2) * P - 6
(C2TDELAY + 2) * P - 6
(C2TDELAY + 2) * P - 6
(C2TDELAY + 2) * P - 6
Output setup time, SPI_CS[n] active before
first SPI_CLK rising edge, polarity = 0,
phase = 1, SPIDELAY.C2TDELAY = 0
(2) (3)
22
tosu(CS-CLK)
ns
Output setup time, SPI_CS[n] active before
first SPI_CLK falling edge, polarity = 1,
phase = 0, SPIDELAY.C2TDELAY = 0
Output setup time, SPI_CS[n] active before
first SPI_CLK falling edge, polarity = 1,
phase = 1, SPIDELAY.C2TDELAY = 0
Delay time, SPI_EN assertion low to first
SPI_CLK rising edge, polarity = 0,
phase = 0, SPI_EN was initially deasserted
and SPI_CLK delayed
0.5T + P
Delay time, SPI_EN assertion low to first
SPI_CLK rising edge, polarity = 0,
phase = 1, SPI_EN was initially deasserted
and SPI_CLK delayed
P
0.5T + P
P
(2)
23
td(CLK-EN)
ns
Delay time, SPI_EN assertion low to first
SPI_CLK falling edge, polarity = 1,
phase = 0, SPI_EN was initially deasserted
and SPI_CLK delayed
Delay time, SPI_EN assertion low to first
SPI_CLK falling edge, polarity = 1,
phase = 1, SPI_EN was initially deasserted
and SPI_CLK delayed
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-86 shows only polarity = 0, phase = 0 as an example.
(3) SPI_EN is immediately asserted, the SPI Master is ready with new data before SPI_CS[n] assertion.
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Table 6-118. Additional Input Timing Requirements of 5-Pin Option in Master Mode(1)
-1G
MAX
NO.
UNIT
MIN
MIN
MAX
Delay time, max delay for slave
SPI to drive SPI_ENA valid after
master asserts SPI_CS[n] to
delay the master from beginning
the next transfer
21
td(CSL-ENA)
0.5P
0.5D ns
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK falling edge, 5-pin
mode, polarity = 0, phase = 0
0.5T
0
0.5T
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK falling edge, 5-pin
mode, polarity = 0, phase = 1
0
(2) (3)
31
td(CLK-ENA)
ns
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK rising edge, 5-pin
mode, polarity = 1, phase = 0
0.5T
0
0.5T
Delay time, max delay for slave
to deassert SPI_ENA after final
SPI_CLK rising edge, 5-pin
mode, polarity = 1, phase = 1
0
(1) T = period of SPI_CLK; P = period of SPI core clock; D = period of 24-MHz clock
(2) SPI master is ready with new data before SPI_ENA deassertion.
(3) Figure 6-86 shows only polarity = 0, phase = 0 as an example.
Slave Mode — Additional
Table 6-119. Additional Output Switching Characteristics of 4-Pin Enable Option in Slave Mode(1)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, final SPI_CLK falling edge to
slave deasserting SPI_EN, polarity = 0,
phase = 0
P – 6
3P + 15
Delay time, final SPI_CLK falling edge to
slave deasserting SPI_EN, polarity = 0,
phase = 1
0.5T + P – 6
P – 6
0.5T + 3P + 15
3P + 15
(2)
SPI24
td(CLK-EN)
ns
Delay time, final SPI_CLK rising edge to slave
deasserting SPI_EN, polarity = 1,
phase = 0
Delay time, final SPI_CLK rising edge to slave
deasserting SPI_EN, polarity = 1,
phase = 1
0.5T + P – 6
0.5T + 3P + 15
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
Table 6-120. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Slave Mode(1)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, master asserting SPI_CS[n] to slave driving SPI_SOMI
data valid
27
28
td(CSL-SOMI)
P + 6
ns
ns
Disable time, master deasserting SPI_CS[n] to slave driving
SPI_SOMI high impedance
tdis(CSH-SOMI)
P + 6
(1) T = period of SPI_CLK; P = period of SPI core clock
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Table 6-121. Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode(1)
-1G
NO.
UNIT
MIN
MAX
Setup time, SPI_CS[n] asserted at slave to first SPI_CLK edge
(rising or falling) at slave
25
tsu(CSL-CLK)
2P + 6
ns
Delay time, final falling edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 0, phase = 0
0.5T + P + 6
P + 6
Delay time, final falling edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 0, phase = 1
(2)
26
td(CLK-CSH)
ns
Delay time, final rising edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 1, phase = 0
0.5T + P + 6
P + 6
Delay time, final rising edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 1, phase = 1
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
Table 6-122. Additional Output Switching Characteristics of 5-Pin Option in Slave Mode(1)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
P + 6
Enable time, master asserting SPI_CS[n] to slave driving
SPI_SOMI valid
SPI33
ten(CSL-SOMI)
ns
Disable time, master deasserting SPI_CS[n] to slave driving
SPI_SOMI high impedance
SPI34
SPI29
tdis(CSH-SOMI)
ten(CSL-EN)
P + 6
6
ns
ns
Enable time, master asserting SPI_CS[n] to slave driving SPI_EN
Disable time, final clock receive falling edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 0, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
1.5P + 6
1.5P + 6
1.5P + 6
1.5P + 6
P + 6
Disable time, final clock receive rising edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 0, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
(2)
SPI30
tdis(CLK-ENZ)
ns
Disable time, final clock receive rising edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 1, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, final clock receive falling edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 1, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 0, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 0, phase = 1,
P + 6
SPIINT0.ENABLE HIGHZ = 1
(2)
37
tdis(CSH-ENH)
ns
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 1, phase = 0,
P + 6
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 1, phase = 1,
P + 6
SPIINT0.ENABLE HIGHZ = 1
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
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Table 6-122. Additional Output Switching Characteristics of 5-Pin Option in Slave Mode (continued)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
3P + 15
Delay time, final clock receive edge on SPI_CLK to slave
deasserting SPI_EN, polarity = 0, phase = 0,
SPIINT0.ENABLE HIGHZ = 0
Delay time, final clock receive edge on SPI_CLK to slave
deasserting SPI_EN, polarity = 0, phase = 1,
SPIINT0.ENABLE HIGHZ = 0
0.5T + 3P +
15
(2)
38
td(CLK-ENZ)
ns
Delay time, final clock receive edge on SPI_CLK to slave
deasserting SPI_EN, polarity = 1, phase = 0,
SPIINT0.ENABLE HIGHZ = 0
3P + 15
Delay time, final clock receive edge on SPI_CLK to slave
deasserting SPI_EN, polarity = 1, phase = 1,
SPIINT0.ENABLE HIGHZ = 0
0.5T + 3P +
15
Delay time, SPI_CS[n] deassertion to slave deasserting SPI_EN,
polarity = 0, phase = 0, SPIINT0.ENABLE HIGHZ = 0
6
6
6
6
Delay time, SPI_CS[n] deassertion to slave deasserting SPI_EN,
polarity = 0, phase = 1, SPIINT0.ENABLE HIGHZ = 0
(2)
39
td(CSH-ENH)
ns
Delay time, SPI_CS[n] deassertion to slave deasserting SPI_EN,
polarity = 1, phase = 0, SPIINT0.ENABLE HIGHZ = 0
Delay time, SPI_CS[n] deassertion to slave deasserting SPI_EN
polarity = 1, phase = 1, SPIINT0.ENABLE HIGHZ = 0
Table 6-123. Additional Input Timing Requirements of 5-Pin Option in Slave Mode(1)
-1G
NO.
UNIT
MIN
MAX
Delay time, SPI_CS[n] asserted at slave to first clock edge (rising
or falling) of SPI_CLK at slave
35
td(CSL-CLK)
P
0.5T + P + 6
P + 6
ns
Delay time, SPI_CLK falling edge to SPI_CS[n] deasserted,
polarity = 0, phase = 0
Delay time, SPI_CLK falling edge to SPI_CS[n] deasserted,
polarity = 0, phase = 1
(2)
36
td(CLK-CSH)
ns
Delay time, SPI_CLK rising edge to SPI_CS[n] deasserted, polarity
= 1, phase = 0
0.5T + P + 6
P + 6
Delay time, SPI_CLK rising edge to SPI_CS[n] deasserted, polarity
= 1, phase = 1
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
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MASTER MODE
POLARITY = 0 PHASE = 0
1
2
3
SPI_CLK
SPI_SIMO
SPI_SOMI
5
4
6
MO(0)
MO(1)
MO(n-1)
MI(n-1)
MO(n)
7
8
MI(0)
MI(1)
MI(n)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPI_CLK
SPI_SIMO
SPI_SOMI
5
6
MO(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
7
8
MI(0)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 0
4
SPI_CLK
SPI_SIMO
SPI_SOMI
5
6
MO(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
7
8
MI(0)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPI_CLK
SPI_SIMO
SPI_SOMI
6
4
5
MO(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
7
8
MI(0)
MI(n)
Figure 6-84. SPI Timings—Master Mode
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SLAVE MODE
POLARITY = 0 PHASE = 0
9
10
11
16
SPI_CLK
SPI_SIMO
SPI_SOMI
15
SI(0)
SI(1)
SI(n)
SI(n-1)
13
SO(1)
14
SO(0)
SO(n-1)
SO(n)
SLAVE MODE
POLARITY = 0 PHASE = 1
SPI_CLK
SPI_SIMO
SPI_SOMI
15
16
SI(0)
SI(n-1)
SI(n)
SI(1)
13
14
SO(0)
SO(1)
SO(n-1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
SPI_CLK
SPI_SIMO
SPI_SOMI
15
16
SI(0)
SI(1)
SI(n-1)
SI(n)
13
SO(1)
14
SO(0)
SO(n-1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
SPI_CLK
SPI_SIMO
SPI_SOMI
15
16
SI(0)
SI(n-1)
SI(n)
SI(1)
13
14
SO(0)
SO(1)
SO(n-1)
SO(n)
A. The first bit of transmit data becomes valid on the SPI_SOMI pin when software writes to the SPIDAT0/1 register(s).
See the TMS320DM646x DMSoC Serial Peripheral Interface (SPI) User's Guide (literature number SPRUER4).
Figure 6-85. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPI_CLK
SPI_SIMO
SPI_SOMI
SPI_EN
MO(0)
MI(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
MI(n)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPI_CLK
SPI_SIMO
SPI_SOMI
SPI_CS[n]
MO(0)
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
MI(n)
MI(0)
MASTER MODE 5 PIN
22
32
31
23
SPI_CLK
SPI_SIMO
SPI_SOMI
MO(1)
MI(1)
MO(n-1)
MI(n-1)
MO(n)
MI(n)
MO(0)
MI(0)
21
(A)
(A)
DESEL
DESEL
SPI_EN
SPI_CS[n]
A. Deselected is programmable either high or 3-state (requires external pullup)
Figure 6-86. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPI_CLK
SPI_SOMI
SPI_SIMO
SPI_EN
SO(0)
SI(0)
SO(1)
SI(1)
SO(n-1)
SI(n-1)
SO(n)
SI(n)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPI_CLK
28
27
SO(n-1)
SI(n-1)
SPI_SOMI
SPI_SIMO
SPI_CS[n]
SO(0)
SI(0)
SO(1)
SI(1)
SO(n)
SI(n)
SLAVE MODE 5 PIN
36
35
30, 38
SPI_CLK
34
33
SPI_SOMI
SPI_SIMO
SO(0)
SI(0)
SO(1)
SI(1)
SO(n-1)
SI(n-1)
SO(n)
SI(n)
29
DESEL(A)
37, 39
DESEL(A)
SPI_EN
SPI_CS[n]
A. Deselected is programmable either high or 3-state (requires external pullup)
Figure 6-87. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.24 Universal Asynchronouse Receiver/Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and
parallel-to-serial conversion on data received from the CPU.
6.24.1 UART Device-Specific Information
VCE6467T provides up to 3 UART peripheral interfaces depending on the selected pin multiplexing.
Each UART has the following features:
•
•
•
Selectable UART/IrDA (SIR/MIR)/CIR modes
Dual 64 entry FIFOs for received and transmitted data payload
Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt
generation
•
•
Frequency prescaler values from 0 to 16 383 it generate the appropriate baud rates
Two DMA requests and one interrupt request to the system
UART functions include:
•
•
Baud-rate up to 1.8432 Mbit/s
Software/Hardware flow control
–
–
Programmable Xon/Xoff characters
Programmable Auto-RTS and Auto-CTS
•
Programmable serial interfaces characteristics
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, mark, space, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
Additional Modem control functions (UDTR0, UDSR0, UDCD0, and URIN0) [UART0 only]
IR-IrDA functions include:
•
Both slow infrared (SIR, baud-rate up to 115.2 Kbit/s) and medium infrared (MIR, baud-rate up to 0.576
Mbits/s) supported
•
•
Supports framing error, cyclic redundancy check (CRC) error, and abort pattern (SIR, MIR) detection
8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors
IR-CIR functions include:
Consumer Infrared (CIR) remote control mode with programmable data encoding
•
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6.24.2 UART Peripheral Register Description(s)
Table 6-124 shows the UART register name summary. Table 6-125, Table 6-126, and Table 6-127 show
the UART0/1/2 registers, respectively along with their configuration requirements.
Table 6-124. UART Register Summary
ACRONYM
RHR
REGISTER NAME
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
ACRONYM
RXFLH
BLR
REGISTER NAME
Receive Frame Length High Register
BOF Control Register
THR
IER
ACREG
SCR
Auxilliary Control Register
IIR
Supplementary Control Register
Supplementary Status Register
BOF Length Register
FCR
SSR
LCR
Line Control Register
EBLR
MVR
MCR
Modem Control Register
Line Status Register
Module Version Register
LSR
SYSC
SYSS
WER
System Configuration Register
System Status Register
MSR
Modem Status Register
SPR
Scratchpad Register
Wake-up Enable Register
TCR
Transmission Control Register
Trigger Level Register
CFPS
DLL
Carrier Frequency Prescaler Register
Divisor Latch Low Register
Divisor Latch High Register
UART Autobauding Status Register
Enhanced Feature Register
UART XON1 Character Register
UART XON2 Character Register
UART XOFF1 Character Register
UART XOFF2 Character Register
IrDA Address 1 Register
TLR
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
TXFLL
TXFLH
RXFLL
Mode Definition Register 1
Mode Definition Register 2
Status FIFO Line Status Register
Resume Register
DLH
UASR
EFR
XON1
XON2
XOFF1
XOFF2
ADDR1
ADDR2
Status FIFO Register Low
Status FIFO Register High
Transmit Frame Length Low Register
Transmit Frame Length High Register
Receive Frame Length Low Register
IrDA Address 2 Register
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Table 6-125. UART0 – UART/IrDA/CIR Register Program Map
HEX ADDRESS
RANGE
REGISTER
LCR[7] = 0
LCR[7] = 1 & LCR[7:0] ≠ 0xBF
LCR[7:0] = 0xBF
READ
RHR
IER(1)
IIR
WRITE
THR
IER(1)
FCR(2)
LCR
READ
DLL
WRITE
DLL
READ
WRITE
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 002C
0x01C2 0030
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0048
0x01C2 004C
0x01C2 0050
0x01C2 0054
0x01C2 0058
0x01C2 005C
0x01C2 0060
DLL
DLH
DLL
DLH
DLH
FCR(2)
LCR
MCR(2)
–
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
DLH
IIR
EFR
EFR
LCR
MCR(2)
LCR
MCR(2)
LCR
LCR
MCR(2)
XON1/ADDR1
XON2/ADR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
XON1/ADDR1
LSR
–
LSR
XON2/ADDR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
BLR
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
BLR
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
ACREG
SCR
ACREG
SCR
–
–
SCR
SCR
–
SCR
SCR
–
SSR
–
SSR
SSR
EBLR
EBLR
–
–
–
–
–
–
–
–
–
–
MVR
–
MVR
–
MVR
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSC
–
SYSS
WER
CFPS
–
WER
CFPS
–
WER
WER
CFPS
–
CFPS
–
CFPS
–
CFPS
0x01C2 0064 -
0x01C2 007F
–
(1) In UART modes, IER.[7:4] can only be written when ENHANCED_EN in EFR = 1. In IrDA/CIR modes, ENHANCED_EN in EFR has no
impact on the access to IER.[7:4].
(2) MCR.[7:5] and the TX_FIFO_TRIG bits in FCR can only be written to when the ENHANCED_EN bit in EFR = 1.
(3) Transmission control register (TCR) and trigger level register (TLR) are accessible only when the ENHANCED_EN bit in the EFR =1
and the TCR_TLR bit in the MCR = 1.
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Table 6-126. UART1 – UART/IrDA/CIR Register Program Map
HEX ADDRESS
RANGE
REGISTER
LCR[7] = 0
LCR[7] = 1 & LCR[7:0] ≠ 0xBF
LCR[7:0] = 0xBF
READ
RHR
IER(1)
IIR
WRITE
THR
IER(1)
FCR(2)
LCR
READ
DLL
WRITE
DLL
READ
DLL
WRITE
0x01C2 0400
0x01C2 0404
0x01C2 0408
0x01C2 040C
0x01C2 0410
0x01C2 0414
0x01C2 0418
0x01C2 041C
0x01C2 0420
0x01C2 0424
0x01C2 0428
0x01C2 042C
0x01C2 0430
0x01C2 0434
0x01C2 0438
0x01C2 043C
0x01C2 0440
0x01C2 0444
0x01C2 0448
0x01C2 044C
0x01C2 0450
0x01C2 0454
0x01C2 0458
0x01C2 045C
0x01C2 0460
DLL
DLH
DLH
FCR(2)
LCR
MCR(2)
–
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
DLH
DLH
IIR
EFR
EFR
LCR
MCR(2)
LCR
MCR(2)
LCR
LCR
MCR(2)
XON1/ADDR1
XON2/ADR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
XON1/ADDR1
LSR
–
LSR
XON2/ADDR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
BLR
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
BLR
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
ACREG
SCR
ACREG
SCR
–
–
SCR
SCR
–
SCR
SCR
–
SSR
–
SSR
SSR
EBLR
EBLR
–
–
–
–
–
–
–
–
–
–
MVR
–
MVR
–
MVR
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSS
SYSC
–
WER
CFPS
–
WER
CFPS
–
WER
WER
CFPS
–
CFPS
–
CFPS
–
CFPS
0x01C2 0464 -
0x01C2 047F
–
(1) In UART modes, IER.[7:4] can only be written when ENHANCED_EN in EFR = 1. In IrDA/CIR modes, ENHANCED_EN in EFR has no
impact on the access to IER.[7:4].
(2) MCR.[7:5] and the TX_FIFO_TRIG bits in FCR can only be written to when the ENHANCED_EN bit in EFR = 1.
(3) Transmission control register (TCR) and trigger level register (TLR) are accessible only when the ENHANCED_EN bit in the EFR =1
and the TCR_TLR bit in the MCR = 1.
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Table 6-127. UART2 – UART/IrDA/CIR Register Program Map
HEX ADDRESS
RANGE
REGISTER
LCR[7] = 0
LCR[7] = 1 & LCR[7:0] ≠ 0xBF
LCR[7:0] = 0xBF
READ
RHR
IER(1)
IIR
WRITE
THR
IER(1)
FCR(2)
LCR
READ
DLL
WRITE
DLL
READ
WRITE
0x01C2 0800
0x01C2 0804
0x01C2 0808
0x01C2 080C
0x01C2 0810
0x01C2 0814
0x01C2 0818
0x01C2 081C
0x01C2 0820
0x01C2 0824
0x01C2 0828
0x01C2 082C
0x01C2 0830
0x01C2 0834
0x01C2 0838
0x01C2 083C
0x01C2 0840
0x01C2 0844
0x01C2 0848
0x01C2 084C
0x01C2 0850
0x01C2 0854
0x01C2 0858
0x01C2 085C
0x01C2 0860
DLL
DLH
DLL
DLH
DLH
FCR(2)
LCR
MCR(2)
–
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
DLH
IIR
EFR
EFR
LCR
MCR(2)
LCR
MCR(2)
LCR
LCR
MCR(2)
XON1/ADDR1
XON2/ADR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
XON1/ADDR1
LSR
–
LSR
XON2/ADDR2
XOFF1/TCR(3)
XOFF2/TLR(3)
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
BLR
TCR(3)
SPR/TLR(3)
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
BLR
MSR/TCR(3)
SPR/TLR(3)
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
UASR
–
MDR1
MDR2
TXFLL
TXFLH
RXFLL
RXFLH
–
ACREG
SCR
ACREG
SCR
–
–
SCR
SCR
–
SCR
SCR
–
SSR
–
SSR
SSR
EBLR
EBLR
–
–
–
–
–
–
–
–
–
–
MVR
–
MVR
–
MVR
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSS
WER
SYSC
–
SYSC
SYSC
–
SYSS
WER
CFPS
–
WER
CFPS
–
WER
WER
CFPS
–
CFPS
–
CFPS
–
CFPS
0x01C2 0864 -
0x01C2 087F
–
(1) In UART modes, IER.[7:4] can only be written when ENHANCED_EN in EFR = 1. In IrDA/CIR modes, ENHANCED_EN in EFR has no
impact on the access to IER.[7:4].
(2) MCR.[7:5] and the TX_FIFO_TRIG bits in FCR can only be written to when the ENHANCED_EN bit in EFR = 1.
(3) Transmission control register (TCR) and trigger level register (TLR) are accessible only when the ENHANCED_EN bit in the EFR =1
and the TCR_TLR bit in the MCR = 1.
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6.24.3 UART Electrical Data/Timing [Receive/Transmit]
Table 6-128. Timing Requirements for UARTx Receive(1) (see Figure 6-88)
-1G
MIN
NO.
UNIT
MAX
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (URXDx) [15/30/100 pF]
Pulse duration, receive start bit [15/30/100 pF]
0.96U
0.96U
1.05U
1.05U
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-129. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-88)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
128
1
2
3
f(baud)
Maximum programmable baud rate
kHz
ns
tw(UTXDB)
tw(UTXSB)
Pulse duration, transmit data bit (UTXDx) [15/30/100 pF]
Pulse duration, transmit start bit [15/30/100 pF]
U - 2
U - 2
U + 2
U + 2
ns
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UTXDx
Data Bits
5
4
Start
Bit
URXDx
Data Bits
Figure 6-88. UART Transmit/Receive Timing
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6.24.4 IrDA Interface Receive/Transmit Timings
Table 6-130. Signaling Rate and Pulse Duration Specification in Receive Mode
ELECTRICAL PULSE DURATION
NOM
SIGNALING RATE
UNIT
MAX
MIN
SIR MODE
2.4 Kbit/s (Kbps)
9.6 Kbps
1.41
1.41
1.41
1.41
1.41
1.41
78.1
19.5
9.75
4.87
3.25
1.62
88.55
22.13
11.07
5.96
μs
μs
μs
μs
μs
μs
19.2 Kbps
38.4 Kbps
57.6 Kbps
4.34
115.2 Kbps
2.23
MIR MODE
0.576 Mbit/s (Mbps)
297.2
416
518.8
ns
Table 6-131. Timing Requirements for IrDA Receive
-1G
MIN
NO.
UNIT
MAX
200
1
2
tr(URXD)
tf(URXD)
Rise time, receive data bit URXDx
Fall time, receive data bit URXDx
ns
ns
200
Table 6-132. Signaling Rate and Pulse Duration Specification in Transmit Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MAX
NOM
MIN
SIR MODE
2.4 Kbit/s (Kbps)
9.6 Kbps
78.10
19.50
9.75
4.87
3.25
1.62
78.1
19.5
9.75
4.87
3.25
1.62
78.10
19.50
9.75
4.87
3.25
1.62
μs
μs
μs
μs
μs
μs
19.2 Kbps
38.4 Kbps
57.6 Kbps
115.2 Kbps
MIR MODE
0.576 Mbit/s (Mbps)
414.0
416.0
419.0
ns
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6.25 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between VCE6467T and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 2 to 8-bit data to/from the DMSoC
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Standard and Fast Modes from 10 – 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
For more detailed information on the I2C peripheral, see the TMS320DM646x DMSoC Inter-Integrated
Circuit (I2C) Module User's Guide (literature number SPRUER0).
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6.25.1 I2C Peripheral Register Description(s)
Table 6-133. I2C Registers
HEX ADDRESS RANGE
0x1C2 1000
0x1C2 1004
0x1C2 1008
0x1C2 100C
0x1C2 1010
0x1C2 1014
0x1C2 1018
0x1C2 101C
0x1C2 1020
0x1C2 1024
0x1C2 1028
0x1C2 102C
0x1C2 1030
0x1C2 1034
0x1C2 1038
ACRONYM
ICOAR
ICIMR
REGISTER NAME
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Clock Divider Low Register
I2C Clock Divider High Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICPID1
ICPID2
I2C Peripheral Identification Register 1
I2C Peripheral Identification Register 2
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6.25.2 I2C Electrical Data/Timing
Table 6-134. Timing Requirements for I2C Timings(1) (see Figure 6-89)
-1G
STANDARD
MODE
NO.
FAST MODE
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
0(3) 0.9(4)
µs
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
20 + 0.1Cb
9
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
ns
ns
ns
ns
(5)
20 + 0.1Cb
10
11
12
(5)
20 + 0.1Cb
(5)
20 + 0.1Cb
300
(5)
13
14
15
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
µs
ns
pF
50
(5)
Cb
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-89. I2C Receive Timings
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Table 6-135. Switching Characteristics for I2C Timings(1) (see Figure 6-90)
-1G
STANDARD
MODE
NO.
PARAMETER
FAST MODE
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
td(SCLH-SDAL)
td(SDAL-SCLL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a repeated START
condition)
4.7
4
0.6
0.6
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
µs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SCLH)
tv(SCLL-SDAV)
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
250
0
0.9
Pulse duration, SDA high between STOP and START
conditions
23
24
25
26
27
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
ns
ns
ns
ns
20 + 0.1Cb
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
(2)
20 + 0.1Cb
(2)
20 + 0.1Cb
(2)
20 + 0.1Cb
300
(2)
28
29
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
µs
pF
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-90. I2C Transmit Timings
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6.26 Pulse Width Modulator (PWM)
The PWM provides a way to generate a pulse periodic waveform for motor control or can act as a
digital-to-analog converter with some external components.
6.26.1 PWM Device-Specific Information
The 2 VCE6467T Pulse Width Modulator (PWM) peripherals support the following features:
•
•
•
32-bit period counter
32-bit first-phase duration counter
32-bit repeat count for one-shot operation. One-shot operation generates N+1 periods of waveform, N
being the repeat count register value.
•
•
•
Configurable to operate in either one-shot or continuous mode
Programmable buffered period and first-phase duration registers
One-shot operation triggerable by VPIF or GPIO with programmable edge transitions. (low-to-high or
high-to-low).
•
•
•
•
One-shot operation generates N+1 periods of waveform, N being the repeat count register value
Configurable PWM output pin inactive state
Interrupt and EDMA synchronization events
Emulation support for stop or free-run operation
6.26.2 PWM Peripheral Register Description(s)
Table 6-136 and Table 6-137 show the register memory maps for PWM0/1.
Table 6-136. PWM0 Register
HEX ADDRESS RANGE
0x01C2 2000
ACRONYM
PID
REGISTER NAME
PWM0 Peripheral Identification Register
PWM0 Peripheral Control Register
PWM0 Configuration Register
PWM0 Start Register
0x01C2 2004
PCR
0x01C2 2008
CFG
0x01C2 200C
START
RPT
0x01C2 2010
PWM0 Repeat Count Register
PWM0 Period Register
0x01C2 2014
PER
0x01C2 2018
PH1D
-
PWM0 First-Phase Duration Register
Reserved
0x01C2 201C - 0x01C2 23FF
Table 6-137. PWM1 Register Memory Map
HEX ADDRESS RANGE
0x01C2 2400
ACRONYM
REGISTER NAME
PID
PCR
CFG
START
RPT
PER
PH1D
-
PWM1 Peripheral Identification Register
PWM1 Peripheral Control Register
PWM1 Configuration Register
PWM1 Start Register
0x01C2 2404
0x01C2 2408
0x01C2 240C
0x01C2 2410
PWM1 Repeat Count Register
PWM1 Period Register
0x01C2 2414
0x01C2 2418
PWM1 First-Phase Duration Register
Reserved
0x01C2 241C -0x01C2 27FF
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6.26.3 PWM0/1 Electrical Data/Timing
Table 6-138. Switching Characteristics Over Recommended Operating Conditions for PWM0/1 Outputs(1)
(see Figure 6-91 and Figure 6-92)
-1G
NO.
PARAMETER
UNIT
MIN
37
MAX
1
2
3
4
tw(PWMH)
tw(PWML)
tt(PWM)
Pulse duration, PWMx high
ns
ns
ns
ns
Pulse duration, PWMx low
37
Transition time, PWMx
5
td(VPIF-PWMV)
Delay time, VPIF (VSYNC) or GPIO trigger event to PWMx valid
4P 6P + 20
(1) P = SYSCLK3 period in ns.
1
2
PWM0/1
3
3
Figure 6-91. PWM Output Timing
VPIF(VSYNC)
4
INVALID
VALID
PWM0
PWM1
4
INVALID
VALID
Figure 6-92. PWM Output Delay Timing
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6.27 Timers
The timers support four modes of operation: a 64-bit general-purpose (GP) timer, dual-unchained 32-bit
GP timers, dual-chained 32-bit timers, or a watchdog timer. The GP timer mode can be used to generate
periodic interrupts or EDMA synchronization events. The watchdog timer mode is used to provide a
recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop.
6.27.1 Timers Device-Specific Information
The VCE6467T device has 3 64-bit general-purpose timers which have the following features:
•
•
64-bit count-up counter
Timer modes:
–
–
–
64-bit general-purpose timer mode (Timer 0 and 1)
Dual 32-bit general-purpose timer mode (Timer 0 and 1)
Watchdog timer mode (Timer 2) [mainly controlled by the ARM]
•
•
2 possible clock sources:
–
–
Internal clock
External clock input via timer input pin TINP0U, TINP0L, and TINP1L, (Timer 0 and 1 only)
2 operation modes:
–
–
One-time operation (timer runs for one period then stops)
Continuous operation (timer automatically resets after each period)
•
•
•
Generates interrupts to the DSP and the ARM CPUs
Generates sync event to EDMA
Causes device global reset upon watchdog timer timeout (Timer 2 only)
For more detailed information, see the TMS320DM646x DMSoC 64-Bit Timer User's Guide (literature
number SPRUER5).
6.27.2 Timer Peripheral Register Description(s)
Table 6-139, Table 6-140, and Table 6-141 show the registers for Timer 0, Timer 1, and Timer 2
(Watchdog).
Table 6-139. Timer 0 Registers
HEX ADDRESS RANGE
0x01C2 1400
ACRONYM
PID12
EMUMGT
TIM12
TIM34
PRD12
PRD34
TCR
DESCRIPTION
Timer 0 Peripheral Identification Register 12
Timer 0 Emulation Management
Timer 0 Counter Register 12
Timer 0 Counter Register 34
Timer 0 Period Register 12
Timer 0 Period Register 34
Timer 0 Control Register
0x01C2 1404
0x01C2 1410
0x01C2 1414
0x01C2 1418
0x01C2 141C
0x01C2 1420
0x01C2 1424
TGCR
-
Timer 0 Global Control Register
Reserved
0x01C2 1428 - 0x01C2 17FF
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Table 6-140. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
0x01C2 1800
0x01C2 1804
PID12
EMUMGT
TIM12
TIM34
PRD12
PRD34
TCR
Timer 1 Peripheral Identification Register 12
Timer 1 Emulation Management
Timer 1 Counter Register 12
Timer 1 Counter Register 34
Timer 1 Period Register 12
Timer 1 Period Register 34
Timer 1 Control Register
0x01C2 1810
0x01C2 1814
0x01C2 1818
0x01C2 181C
0x01C2 1820
0x01C2 1824
TGCR
-
Timer 1 Global Control Register
Reserved
0x01C2 1828 - 0x01C2 1BFF
Table 6-141. Timer 2 (Watchdog) Registers
HEX ADDRESS RANGE
0x01C2 1C00
ACRONYM
DESCRIPTION
PID12
EMUMGT
TIM12
TIM34
PRD12
PRD34
TCR
Timer 2 Peripheral Identification Register 12
Timer 2 Emulation Management
Timer 2 Counter Register 12
Timer 2 Counter Register 34
Timer 2 Period Register 12
Timer 2 Period Register 34
Timer 2 Control Register
0x01C2 1C04
0x01C2 1C10
0x01C2 1C14
0x01C2 1C18
0x01C2 1C1C
0x01C2 1C20
0x01C2 1C24
TGCR
WDTCR
-
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
0x01C2 1C28
0x01C2 1C2C - 0x01C2 1FFF
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6.27.3 Timer Electrical Data/Timing
Table 6-142. Timing Requirements for Timer Input(1) (see Figure 6-93)
-1G
MIN
NO.
UNIT
MAX
1
2
tw(TINPH)
tw(TINPL)
Pulse duration, TINPxL/TINP0U high
Pulse duration, TINPxL/TINP0U low
2P
2P
ns
ns
(1) P = DEV_MXI/DEV_CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN frequency is 27 MHz, use P = 37.037 ns.
Table 6-143. Switching Characteristics Over Recommended Operating Conditions for Timer Output(1) (see
Figure 6-93)
-1G
NO.
UNIT
MIN
P
MAX
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, TOUTxL/TOUTxU/TOUT2 high
Pulse duration, TOUTxL/TOUTxU/TOUT2 low
ns
ns
P
(1) P = DEV_MXI/DEV_CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN frequency is 27 MHz, use P = 37.037 ns.
1
2
TINPxL/TINPxU
3
4
TOUTxL/TOUTxU
Figure 6-93. Timer Timing
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6.28 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GP[0:15]).
6.28.1 GPIO Device-Specific Information
The VCE6467T GPIO peripheral supports the following:
•
•
Up to 33 3.3-V GPIO pins, GP[0:47; not all pinned out]
Interrupts:
–
–
–
Up to 8 unique GP[0:7] interrupts from Bank 0
3 GPIO bank (aggregated) interrupt signals from each of the 3 banks of GPIOs
Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
•
•
DMA events:
–
–
Up to 8 unique GPIO DMA events from Bank 0
3 GPIO bank (aggregated) DMA event signals from each of the 3 banks of GPIOs
Set/clear functionality: Software writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple software processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
Although, the VCE6467T device implements three GPIO banks, not all GPIOs from all banks are available
externally (pinned out). The following GPIOs are not pinned out on the VCE6467T device:
•
BANK 0
–
–
–
GP[9]
GP[14]
GP[15]
•
BANK 1
–
GP[27:31]
•
•
•
•
BANK 2
GP[34]
GP[35]
GP[43:47]
For more detailed information on GPIOs, see the TMS320DM646x DMSoC General-Purpose Input/Output
(GPIO) User's Guide (literature number SPRUEQ8).
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6.28.2 GPIO Peripheral Register Description(s)
Table 6-144 shows the GPIO peripheral registers.
Table 6-144. GPIO Registers
HEX ADDRESS RANGE
0x01C6 7000
ACRONYM
REGISTER NAME
PID
-
Peripheral Identification Register
Reserved
0x01C6 7004
0x01C6 7008
BINTEN
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
0x01C6 700C
0x01C6 7010
0x01C6 7014
0x01C6 7018
0x01C6 701C
0x01C6 7020
0x01C6 7024
0x01C6 7028
0x01C6 702C
0x01C6 7030
0x01C6 7034
-
Reserved
DIR01
GPIO Banks 0 and 1 Direction Register (GP[0:31])
GPIO Banks 0 and 1 Output Data Register (GP[0:31])
GPIO Banks 0 and 1 Set Data Register (GP[0:31])
GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GP[0:31])
GPIO Banks 0 and 1 Input Data Register (GP[0:31])
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GP[0:31])
CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GP[0:31])
SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GP[0:31])
CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GP[0:31])
INSTAT01
GPIO Banks 0 and 1 Interrupt Status Register (GP[0:31])
GPIO Bank 2
0x01C6 7038
0x01C6 703C
DIR2
GPIO Bank 2 Direction Register (GP[32:47])
GPIO Bank 2 Output Data Register (GP[32:47])
GPIO Bank 2 Set Data Register (GP[32:47])
GPIO Bank 2 Clear Data Register (GP[32:47])
GPIO Bank 2 Input Data Register (GP[32:47])
GPIO Bank 2 Set Rising Edge Interrupt Register (GP[32:47])
GPIO Bank 2 Clear Rising Edge Interrupt Register (GP[32:47])
GPIO Bank 2 Set Falling Edge Interrupt Register (GP[32:47])
OUT_DATA2
SET_DATA2
0x01C6 7040
0x01C6 7044
CLR_DATA2
IN_DATA2
0x01C6 7048
0x01C6 704C
SET_RIS_TRIG2
CLR_RIS_TRIG2
SET_FAL_TRIG2
0x01C6 7050
0x01C6 7054
0x01C6 7058
CLR_FAL_TRIG2 GPIO Bank 2 Clear Falling Edge Interrupt Register (GP[32:47])
0x01C6 705C
INSTAT2
-
GPIO Bank 2 Interrupt Status Register (GP[32:47])
Reserved
0x01C6 7060 - 0x01C6 77FF
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6.28.3 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-145. Timing Requirements for GPIO Inputs(1) (see Figure 6-94)
-1G
MIN
NO.
UNIT
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GP[x] input high
Pulse duration, GP[x] input low
2C(2)
2C(2)
ns
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have VCE6467T
recognize the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow
VCE6467T enough time to access the GPIO register through the internal bus.
(2) C = SYSCLK3 period in ns. For example, when running parts at 1 GHz, use C = 4 ns.
Table 6-146. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-94)
-1G
NO.
PARAMETER
UNIT
MIN
C(1) (2)
C(1) (2)
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GP[x] output high
Pulse duration, GP[x] output low
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C = SYSCLK3 period in ns. For example, when running parts at 1 GHz, use C = 4 ns.
2
1
GP[x]
Input
4
3
GP[x]
Output
Figure 6-94. GPIO Port Timing
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6.29 IEEE 1149.1 JTAG
The JTAG(3) interface is used for BSDL testing and emulation of the VCE6467T device.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
VCE6467T includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be
asserted upon power up and the device's internal emulation logic will always be properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
6.29.1 JTAG ID (JTAGID) Register Description(s)
Table 6-147. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
0x01C4 0028
JTAGID
(3) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
VCE6467T device, the JTAG ID register resides at address location 0x01C4 0028. The register hex value
for VCE6467T is: 0x1B77 002F. For the actual register bit names and their associated bit field
descriptions, see Figure 6-95 and Table 6-148.
31-28
VARIANT (4-Bit)
R-0001
27-12
11-1
0
PART NUMBER (16-Bit)
R-1011 0111 0111 0000
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-95. JTAG ID Register Description - VCE6467T Register Value - 0x1B77 002F
346
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SPRS690–MARCH 2011
Table 6-148. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value. VCE6467T value: 0001 [Silicon Revision 3.0 and later].
Part Number (16-Bit) value. VCE6467T value: 1011 0111 0111 0000.
PART NUMBER
MANUFACTURER Manufacturer (11-Bit) value. VCE6467T value: 0000 0010 111.
LSB LSB. This bit is read as a "1" for VCE6467T.
6.29.2 JTAG Test-Port Electrical Data/Timing
Table 6-149. Timing Requirements for JTAG Test Port(1) (2) (see Figure 6-96)
-1G
MIN
NO.
UNIT
MAX
1
2
tc(TCK)
Cycle time, TCK
20
0.4T
0.4T
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(TCKH)
Pulse duration, TCK high
3
tw(TCKL)
Pulse duration, TCK low
4
tc(RTCK)
Cycle time, RTCK
5
tw(RTCKH)
Pulse duration, RTCK high
0.4R
0.4R
12
6
tw(RTCKL)
Pulse duration, RTCK low
7
tsu(TDIV-RTCKH)
th(RTCKH-TDIV)
tsu(EMUV-TCKH)
th(TCKH-EMUV)
Setup time, TDI/TMS/TRST valid before RTCK high
Hold time, TDI/TMS/TRST valid after RTCK high
Setup time, EMU[1:0] valid before TCK high
Hold time, EMU[1:0] valid after TCK high
8
0
9
1.5
4
10
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
(2) R = RTCLK cycle time in ns. For example, when RTCK frequency is 20 MHz, use T = 50 ns.
Table 6-150. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port(1)
(see Figure 6-96)
-1G
NO.
PARAMETER
UNIT
MIN
MAX
11
12
td(RTCKL-TDOV)
td(TCKH-EMUV)
Delay time, RTCK low to TDO valid
Delay time, TCK high to EMU[1:0] valid
-1
8
ns
ns
2.5 T - 2.5
(1) T = TCK cycle time in ns. For example, when TCK frequency is 20 MHz, use T = 50 ns.
Copyright © 2011, Texas Instruments Incorporated
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1
2
3
TCK
4
5
6
RTCK
11
TDO
8
7
TDI/TMS/TRST
10
9
EMU[1:0](Input)
12
EMU[1:0](Output)
Figure 6-96. JTAG Test-Port Timing
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SPRS690–MARCH 2011
7 Mechanical Packaging and Orderable Information
The following table(s) show the thermal resistance characteristics for the PBGA–ZUT mechanical
package.
7.1 Thermal Data for ZUT
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZUT]
NO.
1
°C/W(1)
1.5
AIR FLOW (m/s)(2)
RΘJC
RΘJB
RΘJA
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N/A
2
9.9
3
19.2
14.8
13.8
12.7
11.9
0.3
0.00
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
4
5
RΘJMA
Junction-to-moving air
6
7
8
9
0.4
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.4
0.4
0.5
9.0
8.0
PsiJB
Junction-to-board
7.7
7.3
7.0
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages.
(2) m/s = meters per second
7.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Copyright © 2011, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
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16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
AVCE6467TZUTL1
VCE6467TZUTL1
OBSOLETE
OBSOLETE
FCBGA
FCBGA
ZUT
ZUT
529
529
Pb-Free (RoHS
Exempt)
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
Pb-Free (RoHS
Exempt)
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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