AWR1443FQIGABLRQ1 [TI]

集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 | ABL | 161 | -40 to 125;


型号：	AWR1443FQIGABLRQ1
厂家：	TEXAS INSTRUMENTS
描述：	集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 \| ABL \| 161 \| -40 to 125 雷达传感器
文件：	总76页 (文件大小：2554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AWR1443

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

AWR1443 单芯片 77GHz 和 79GHz FMCW 雷达传感器

•

高速数据接口，可支持分布式应用（即中间数据）

主机接口

1 特性

•

FMCW 收发器

– 通过 SPI 与外部处理器进行控制连接

– 用于故障报告的中断

符合 AECQ-100 标准

– 集成 PLL、发送器、接收器、基带和 ADC

– 76GHz 至 81GHz 的覆盖范围，具有 4GHz 的可

用带宽

•

器件高级特性

– 四个接收通道

– 嵌入式自监控，无需使用主机处理器

– 三个发送通道（可以同时使用两个通道）

– 基于分数 N PLL 的超精确线性调频脉冲引擎

– TX 功率：12dBm

– 复基带架构

– 嵌入式干扰检测功能

电源管理

•

– RX 噪声系数：

– 内置 LDO 网络，可增强 PSRR

– I/O 支持双电压 3.3V/1.8V

时钟源

•

14dB（76 至 77GHz）

15dB（77 至 81GHz）

– 1MHz 时的相位噪声：

– 支持外部驱动、频率为 40MHz 的时钟（方波/正

•

–95dBc/Hz（76 至 77GHz）

弦波）

–93dBc/Hz（77 至 81GHz）

– 支持 40MHz 晶体与负载电容器相连接

轻松的硬件设计

•

内置校准和自检

•

–

基于 Arm^®Cortex^®-R4F 的无线电控制系统

– 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆

晶 BGA 封装，可实现轻松组装和低成本 PCB

设计

– 小尺寸解决方案

运行条件

– 内置固件 (ROM)

– 针对工艺和温度进行自校准的系统

适用于嵌入式用户应用的片上可编程内核

– 时钟频率为 200MHz 的集成 Cortex®-R4F 微控

制器

– 结温范围：–40°C 至 125°C

– 片上引导加载程序支持自主模式（从 QSPI 闪存

加载用户应用）

– 集成外设

•

具有 ECC 的内部存储器

雷达硬件加速器（FFT、对数幅度计算等）

集成计时器（看门狗以及多达四个 32 位计时

器或两个 64 位计时器）

•

I2C（支持控制器模式和目标模式）

两个 SPI 端口

CAN 端口

多达六个通用 ADC 端口

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

•

手势识别

车门开启器应用

2 应用

•

接近传感

泊车辅助

占位检测

Crystal

Power Management

RX1

RX2

Antenna

Structure

SPI/I2C

RX3

RX4

External

MCU

Interface to

External

Peripherals

mmWave Sensor

CSI2 (4 Lane Data + 1 Clock lane)

TX1

TX2

Reset

Error

TX3

MCU Clock

图 2-1. 适用于汽车应用的自主雷达传感器

3 说明

AWR1443 器件是一款能够在 76 至 81GHz 频带中运行的集成式单芯片 FMCW 雷达传感器。该器件采用 TI 的低

功耗 45nm RFCMOS 工艺构建，具有一个集成式 ARM R4F 处理器和一个硬件加速器，用于进行雷达数据处理，

该解决方案在极小的封装中实现了出色的集成度。AWR1443 是适用于汽车领域中的低功耗、自监控、超精确雷达

系统的理想解决方案。

AWR1443 器件是一种自包含 FMCW 雷达传感器单芯片解决方案，能够简化 76 至 81GHz 频带中的汽车雷达传感

器实施。它实现了一个具有内置 PLL 和 ADC 转换器的单片实施 3TX、4RX 系统。简单编程模型更改可支持各种

传感器实施（近距离、中距离和远距离），并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件

作为完整的平台解决方案进行提供，其中包括 TI 参考设计、软件驱动程序、示例配置、API 指南以及用户文档。

不同的应用在雷达数据立方体存储器、处理能力和功能安全监控方面，对雷达器件的要求各不相同。因此，可以

将 AWR1443 视为适用于入门级雷达应用的 77GHz 片上雷达解决方案

器件信息

器件型号⁽²⁾

AWR1443FQIGABLQ1

AWR1443FQIGABLRQ1

封装⁽¹⁾

封装尺寸

托盘/卷带包装

托盘

FCBGA (161)

10.4mm × 10.4mm

卷带包装

(1) 如需更多信息，请参阅节 12 机械、封装和可订购信息。

(2) 如需更多信息，请参阅节 11.1，器件命名规则。

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

4 功能方框图

图 4-1 展示了器件的功能方框图

Cortex R4F

@ 200 MHz

RX1

RX2

RX3

RX4

LNA

ADC

(User programmable)

Digital Front

End

Boot

ROM

Prog RAM* Data RAM*

(Decimation

filter chain)

Serial Flash

interface

QSPI

SPI

Radar Data

Memory*

Optional External

MCU interface

ADC

Buffer

TX1

TX2

TX3

Radar

Hardware

Accelerator

(FFT, Log-

Mag, and

others.)

PMIC control

SPI / I2C

DCAN

Synth

(20 GHz)

Ramp

Generator

Primary communication

interface (automotive)

Debug

UARTs

DMA

For debug

RF Control/

BIST

Mailbox

Test/

Debug

JTAG for debug/

development

Osc.

VMON

Temp

GPADC

Main subsystem

(Customer programmed)

RF/Analog subsystem

* Total RAM available in Main subsystem is 576KB (for Cortex-R4F Program RAM, Data RAM, and Radar Data Memory)

图 4-1. 功能方框图

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

Table of Contents

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................6

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagram................................................................ 8

7.2 Signal Descriptions................................................... 13

7.3 Pin Multiplexing.........................................................17

8 Specifications................................................................ 22

8.1 Absolute Maximum Ratings...................................... 22

8.2 ESD Ratings............................................................. 22

8.3 Power-On Hours (POH)............................................23

8.4 Recommended Operating Conditions.......................23

8.5 Power Supply Specifications.....................................24

8.6 Power Consumption Summary................................. 25

8.7 RF Specification........................................................26

8.8 Thermal Resistance Characteristics for FCBGA

9.1 Overview...................................................................49

9.2 Functional Block Diagram.........................................49

9.3 External Interfaces....................................................50

9.4 Subsystems.............................................................. 51

9.5 Accelerators and Coprocessors................................57

9.6 Other Subsystems.................................................... 57

9.7 Boot Modes...............................................................58

10 Applications, Implementation, and Layout............... 62

10.1 Application Information........................................... 62

10.2 Short-Range Radar ................................................62

10.3 Blind Spot Detector and Ultrasonic Upgrades........ 63

10.4 Reference Schematic..............................................64

11 Device and Documentation Support..........................65

11.1 Device Nomenclature..............................................65

11.2 Tools and Software..................................................66

11.3 Documentation Support.......................................... 66

11.4 支持资源..................................................................66

11.5 Trademarks............................................................. 67

11.6 静电放电警告...........................................................67

11.7 术语表..................................................................... 67

12 Mechanical, Packaging, and Orderable

Package [ABL0161].....................................................27

8.9 Timing and Switching Characteristics....................... 27

9 Detailed Description......................................................49

Information.................................................................... 68

12.1 Packaging Information............................................ 68

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

5 Revision History

Changes from April 30, 2020 to January 10, 2022 (from Revision B (April 2020) to Revision C

(January 2022))

Page

•

通篇：将“A2D”替换为“ADC”；将“主子系统”和“主 R4F”更改为“主要子系统”和“主要 R4F”；在主/从术语方面改

用了更具包容性的措辞 .......................................................................................................................................1

（特性）：提及了毫米波传感器的额定工作温度范围；..................................................................................... 1

（特性）：将 1MHz 时的相位噪声从“–94dBc/Hz（76GHz 至 77GHz）”更新/更改为“-95dBc/Hz”，并从“–

91dBc/Hz（77GHz 至 81GHz）”更新/更改为“–93dBc/Hz”.................................................................................1

（应用）：添加了图示........................................................................................................................................2

更新/更改了“功能方框图”以改用包容性术语....................................................................................................... 3

(Device Comparison): Removed a row on Functional-Safety compliance; Added a table-note for LVDS

Interface; Additional information on Device security updated.............................................................................6

(Signal Descriptions): Updated descriptions for CLKP and CLKM pins for Reference Oscillator.....................13

(Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and

a table-note for the signal level applied on TX..................................................................................................22

(Average Power Consumption at Power Terminals): Added measurement conditions for the specified power

numbers............................................................................................................................................................25

(Maximum Current Rating at Power Terminals): Updated footnotes section to add estimation assumption for

VIOIN rail.......................................................................................................................................................... 25

(Synchronized Frame Triggering): Updated the maximum pulse width to 4000ns........................................... 28

(Clock Specifications): Updated/Changed 表 8-6 to reflect correct device operating temperature range........ 30

(Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppm..30

(Reference Schematics) : Added weblinks to device EVM documentation collateral ......................................64

•

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

6 Device Comparison

FUNCTION

AWR1243

AWR1443

AWR1642

AWR1843

Number of receivers

Number of transmitters

On-chip memory

—

576KB

1.5MB

2MB

Max I/F (Intermediate Frequency) (MHz)

Max real/complex 2x sampling rate (Msps)

Max complex 1x sampling rate (Msps)

Device Security⁽¹⁾

37.5

18.75

—

12.5

6.25

—

12.5

6.25

Yes

12.5

Yes

Processor

MCU (R4F)

—

Yes

—

Yes

DSP (C674x)

Peripherals

Serial Peripheral Interface (SPI) ports

Quad Serial Peripheral Interface (QSPI)

Inter-Integrated Circuit (I²C) interface

Controller Area Network (DCAN) interface

CAN-FD

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Trace

—

PWM

—

Hardware In Loop (HIL/DMM)

—

GPADC

Yes

—

LVDS/Debug⁽²⁾

CSI2

Hardware accelerator

1-V bypass mode

Yes

—

Yes

—

Yes

—

Cascade (20-GHz sync)

JTAG

Yes

3⁽³⁾

Yes

Number of Tx that can be simultaneously used

Per chirp configurable Tx phase shifter

—

PRODUCT PREVIEW (PP),

Product

ADVANCE INFORMATION (AI),

status⁽⁴⁾

or PRODUCTION DATA (PD)

(1) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part

variants as indicated by the Device Type identifier in Section 3, Device Information table.

(2) The LVDS interface is not a production interface and is only used for debug.

(3) 3 Tx Simultaneous operation is supported only in AWR1843 with 1V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin. Rest of the other devices only support simultaneous operation of 2 Transmitters.

(4) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

mmWave sensors

TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with

less power using the smallest footprint mmWave sensor portfolio for automotive

applications.

Automotive mmWave TI’s automotive mmWave sensor portfolio offers high-performance radar front end to

sensors

ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable

sensor portfolio enables design and development of ADAS system solution for every

performance, application and sensor configuration ranging from comfort functions to

safety functions in all vehicles.

Companion products Review products that are frequently purchased or used in conjunction with this product.

for AWR1443

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

7 Terminal Configuration and Functions

7.1 Pin Diagram

图 7-1 shows the pin locations for the 161-pin FCBGA package. 图 7-2, 图 7-3, 图 7-4, and 图 7-5 show the

same pins, but split into four quadrants.

VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT

VSSA

VOUT_PA

VSSA

VIN

_18CLK

VIN

_18VCO

RESERVED

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VSSA

VBGAP

VSSA

VIN

_13RF2

ANAMUX/

GPADC5

VSENSE/

GPADC6

VSSA

VIN

_13RF2

VIOIN

_18DIFF

RESERVED

VSSA

RX4

VSSA

VSS

VSSA

VDDIN

Reserved

TDI

CLKP

CLKM

VSSA

VIN_18BB

VSS

LVDS_

TXP[0]

LVDS_

TXM[0]

VIN

_13RF1

VSSA

RX3

VSS

VIN

_13RF1

LVDS

_TXM[1]

LVDS

_TXP[1]

VSS

VIN

_13RF1

VSSA

RX2

VSS

TDO

LVDS_CLKM LVDS_CLKP

HS_

RESERVED

_TXM[2]

HS_

RESERVED

_TXP[2]

VIN_18BB

VSS

VIOIN_18

HS_

RESERVED

_TXP[3]

RESERVED

_TXM[3]

VSSA

RX1

VSS

TMS

LVDS_

FRCLKP

LVDS_

FRCLKM

TCK

HS_

HS_P_

Debug2_M

WARM

_RESET

VSSA

GPIO[0]

Reserved

RS232_RX

RS232_TX

GPIO[1]

NERROR_OUTMCU_CLK_OUT

Sync_in

QSPI[3]

VDDIN

Sync_out

QSPI[0]

GPIO[2]

Debug2_M

Analog Test 1/ Analog Test 2/ Analog Test 3/

GPADC3

MISO_1 SPI_HOST_INTR_1NERROR_IN

QSPI_CS

MOSI_1

QSPI[1]

NRESET PMIC_CLK_OUT

VNWA

VDDIN

GPADC1

GPADC2

Analog Test 4/

GPADC4

VSSA

Reserved

VDDIN

SPI_CS_1

SPI_CLK_1

QSPI_CLK

QSPI[2]

VIOIN

VIN_SRAM

VSS

Not to scale

图 7-1. Pin Diagram

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

VSSA

VOUT_PA

VSSA

RESERVED

VOUT_PA

VSSA

TX1

VSSA

TX2

VSSA

TX3

VIN

VSSA

_13RF2

VIN

RESERVED

_13RF2

VSSA

VSS

RX4

VIN_18BB

VIN

VSS

VSSA

VSS

_13RF1

Not to scale

图 7-2. Top Left Quadrant

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

VOUT

_14APLL

VOUT

_14SYNTH

OSC

_CLKOUT

VSSA

VIN

_18CLK

VIN

_18VCO

RESERVED

VBGAP

VSSA

ANAMUX/

GPADC5

VSENSE/

GPADC6

VSSA

VIOIN

_18DIFF

RESERVED

VSS

VSSA

VDDIN

CLKP

CLKM

VSSA

VSS

LVDS_

TXM[0]

LVDS

_TXP[0]

VSS

Reserved

Not to scale

图 7-3. Top Right Quadrant

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

VIN

_13RF1

RX3

VSSA

VSS

VIN

_13RF1

VSSA

RX2

VSSA

VSS

VIN_18BB

VSSA

RX1

VSS

VSSA

GPIO[0]

Reserved

RS232_RX

MISO_1

RS232_TX

GPIO[1]

NERROR_IN

SPI_CS_1

NERROR_OUT

Analog Test 1/ Analog Test 2/ Analog Test 3/

GPADC3

SPI_HOST

_INTR_1

QSPI_CS

GPADC1

GPADC2

Analog Test 4/

GPADC4

VSSA

Reserved

VDDIN

MOSI_1

Not to scale

图 7-4. Bottom Left Quadrant

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

LVDS

VSS

TDI

_TXM[1]

_TXP[1]

VSS

TDO

VIOIN_18

TMS

LVDS_CLKM

LVDS_CLKP

HS_RESERVED HS_RESERVED

_TXM[2] TXP[2]

VSS

HS_RESERVED HS_RESERVED

_TXM[3]

_TXP[3]

LVDS_

TCK

FRCLKM

FRCLKP

WARM

HS_

MCU_CLK_OUT

Sync_in

QSPI[3]

VDDIN

Sync_out

QSPI[0]

GPIO[2]

PMIC_CLK_OUT

VIOIN

_RESET

_Debug2_M

_Debug2_P

QSPI[1]

NRESET

VNWA

VDDIN

SPI_CLK_1

QSPI_CLK

QSPI[2]

VIN_SRAM

VSS

Not to scale

图 7-5. Bottom Right Quadrant

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

7.2 Signal Descriptions

备注

All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are

non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply

being present to the device.

备注

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the

application where the state of the GPIO is critical, even when NRESET is low, a tri-state buffer should

be used to isolate the GPIO output from the radar device and a pull resister used to define the

required state in the application. The NRESET signal to the radar device could be used to control the

output enable (OE) of the tri-state buffer.

7.2.1 Signal Descriptions

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

DESCRIPTION

NUMBER TYPE

TX1

—

Single-ended transmitter1 o/p

Single-ended transmitter2 o/p

Single-ended transmitter3 o/p

Single-ended receiver1 i/p

Single-ended receiver2 i/p

Single-ended receiver3 i/p

Single-ended receiver4 i/p

Transmitters

TX2

TX3

RX1

RX2

Receivers

RX3

RX4

LVDS_TXP[0]

LVDS_TXM[0]

LVDS_CLKP

LVDS_CLKM

LVDS_TXP[1]

LVDS_TXM[1]

G15

G14

J15

J14

H15

H14

Differential data Out – Lane 0

Differential clock Out

Differential data Out – Lane 1

HS_RESERVED_TX

P[2]

K15

K14

L15

L14

—

Differential data Out – Lane 2

Differential data Out – Lane 3

HS_RESERVED_TX

M[2]

LVDS TX

HS_RESERVED_TX

P[3]

HS_RESERVED_TX

M[3]

LVDS_FRCLKP

LVDS_FRCLKM

HS_DEBUG2_P

HS_DEBUG2_M

M15

M14

N15

N14

—

Differential debug port 1

Differential debug port 2

B1, B15, D1,

D15

RESERVED

—

Reference clock output from clocking subsystem

after cleanup PLL. Can be used by peripheral chip

in multichip cascading

Reference clock OSC_CLKOUT

A14

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

DESCRIPTION

NUMBER TYPE

Low-frequency frame synchronization signal output.

Can be used by peripheral chip in multichip

cascading

SYNC_OUT

P11

N10

Pull Down

System

synchronization

Low-frequency frame synchronization signal input.

This signal could also be used as a hardware trigger

for frame start

SYNC_IN

SPI_CS_1

Pull Up

Pull Down

Pull Up

SPI chip select

SPI clock

SPI control

interface from

external MCU

(default

peripheral

mode)

SPI_CLK_1

MOSI_1

SPI data input

SPI data output

SPI interrupt to host

MISO_1

Pull Up

SPI_HOST_INTR_1

Pull Down

R3, R4, R5,

RESERVED

NRESET

—

P12

Power on reset for chip. Active low

Open-drain fail-safe warm reset signal. Can be

driven from PMIC for diagnostic or can be used as

status signal that the device is going through reset.

Reset

Safety

WARM_RESET

NERROR_OUT

N12

Open Drain

Open-drain fail-safe output signal. Connected to

PMIC/Processor/MCU to indicate that some severe

criticality fault has happened. Recovery would be

through reset.

Fail-safe input to the device. Error output from

any other device can be concentrated in the error

signaling monitor module inside the device and

appropriate action can be taken by firmware

NERROR_IN

Open Drain

TMS

TCK

TDI

L13

M13

H13

J13

Pull Up

Pull Down

Pull Up

—

JTAG

JTAG port for standard boundary scan

TDO

In XTAL mode: Input for the reference crystal

In External clock mode: Single ended input

reference clock port

CLKP

E14

—

Reference

oscillator

In XTAL mode: Feedback drive for the reference

crystal

In External clock mode: Connect this port to ground

CLKM

F14

B10

—

Band-gap

voltage

VBGAP

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

FUNCTION

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

DEFAULT PULL

STATUS⁽¹⁾

SIGNAL NAME

DESCRIPTION

NUMBER TYPE

F13,N11,P15

POW

VDDIN

—

1.2-V digital power supply

,R6

VIN_SRAM

VNWA

R14

P14

POW

—

1.2-V power rail for internal SRAM

1.2-V power rail for SRAM array back bias

I/O supply (3.3-V or 1.8-V): All CMOS I/Os would

operate on this supply.

VIOIN

R13

POW

—

VIOIN_18

K13

B11

POW

—

1.8-V supply for CMOS IO

1.8-V supply for clock module

1.8-V supply for high speed interface port

No connect

VIN_18CLK

VIOIN_18DIFF

Reserved

D13

G13

VIN_13RF1

VIN_13RF2

VIN_18BB

G5,J5,H5

C2,D2

K5,F5

B12

1.3-V Analog and RF supply,VIN_13RF1 and

VIN_13RF2 could be shorted on the board

1.8-V Analog baseband power supply

1.8-V RF VCO supply

VIN_18VCO

E5,E6,E8,E1

0,E11,F9,F1

1,G6,G7,G8,

G10,H7,H9,

Power supply

VSS

H11,J6,J7,J8 GND

,J10,K7,K8,K

9,K10,K11,L

5,L6,L8,L10,

R15

—

Digital ground

A1,A3,A5,A7

,A9,A15,B3,

B5,B7,B9,B1

3,B14,C1,C3

,C4,C5,C6,C

7,C8,C9,C15

,E1,E2,E3,E GND

13,E15,F3,G

1,G2,G3,H3,

J1,J2,J3,K3,

L1,L2,L3,

VSSA

—

Analog ground

M3,N1,N2,N

3,R1

VOUT_14APLL

VOUT_14SYNTH

VOUT_PA

A10

A13

—

Internal LDO

output/inputs

A2,B2

P13

PMIC_CLK_OUT

Dithered clock input to PMIC

External clock

out

Programmable clock given out to external MCU or

the processor

MCU_CLK_OUT

—

GPIO[0]

GPIO[1]

GPIO[2]

Pull Down

General-purpose IO

General-

purpose I/Os

N13

Chip-select output from the device. Device is a

controller connected to serial flash peripheral.

QSPI_CS

Pull Up

Clock output from the device. Device is a controller

connected to serial flash peripheral.

QSPI_CLK

R10

Pull Down

QSPI for Serial

Flash⁽²⁾

QSPI[0]

QSPI[1]

QSPI[2]

QSPI[3]

R11

Pull Down

Pull Up

Data IN/OUT

R12

P10

Pull Up

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

DEFAULT PULL

STATUS⁽¹⁾

FUNCTION

SIGNAL NAME

DESCRIPTION

NUMBER TYPE

Flash

RS232_TX

Pull Down

programming

and RS232

UART⁽²⁾

UART pins for programming external flash in

preproduction/debug hardware.

RS232_RX

Pull Up

Analog Test1 /

GPADC1

—

GP ADC channel 1

GP ADC channel 2

GP ADC channel 3

Test and Debug

output for

preproduction

phase. Can be

pinned out on

production

Analog Test2 /

GPADC2

Analog Test3 /

GPADC3

Analog Test4

—

GP ADC channel 4

GP ADC channel 5

GP ADC channel 6

hardware for

field debug

ANAMUX / GPADC5

VSENSE / GPADC6

C13

C14

(1) Status of PULL structures associated with the IO after device POWER UP.

(2) This option is for development/debug in preproduction phase. Can be disabled by firmware pin mux setting.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

7.3 Pin Multiplexing

表 7-1. Pin Multiplexing

PAD STATE

nReset = 0 [ASSERTED]

FUNCTION

SIGNAL DESCRIPTION

General Purpose IO

DIGITAL PIN

MUX CONFIG

VALUE [Bits3:0]

PIN NAME

ADDRESS⁽¹⁾

INTERNAL WEAK

PULL STATE

SIGNAL NAME

GPIO_12

SIGNAL TYPE

STATE

Hi-Z

Weak Pull Down

EA00h

GPIO_12

GPIO_0

SPI_HOST1_INTR

GPIO_13

General Purpose IO [AWR14xx]

General Purpose IO

Hi-Z

Weak Pull Down

EA04h

EA08h

GPIO_0

General Purpose IO

PMIC_CLKOUT

GPIO_16

Dithered Clock Output for PMIC

General Purpose IO

GPIO_1

General Purpose IO

GPIO_1

Low Frequency Synchronization

Signal output

SYNC_OUT

GPIO_19

MOSI_1

General Purpose IO

SPI Channel#1 Data Input

CAN Interface

Hi-Z

Weak Pull Up

EA0Ch

EA10h

EA14h

EA18h

EA1Ch

EA20h

MOSI_1

MISO_1

CAN_RX

GPIO_20

MISO_1

General Purpose IO

SPI Channel#1 Data Output

CAN Interface

CAN_TX

GPIO_3

General Purpose IO

SPI Channel#1 Clock

SPI_CLK_1

SPI_CS_1

MOSI_2

SPI_CLK_1

RCOSC_CLK

GPIO_30

SPI_CS_1

RCOSC_CLK

GPIO_21

MOSI_2

General Purpose IO

SPI Channel#1 Chip Select

General Purpose IO

SPI Channel#2 Data Input

I2C Data

I2C_SDA

GPIO_22

MISO_2

General Purpose IO

SPI Channel#2 Data Output

I2C Clock

MISO_2

I2C_SCL

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 7-1. Pin Multiplexing (continued)

PAD STATE

nReset = 0 [ASSERTED]

FUNCTION

DIGITAL PIN

MUX CONFIG

VALUE [Bits3:0]

PIN NAME

ADDRESS⁽¹⁾

INTERNAL WEAK

PULL STATE

SIGNAL NAME

GPIO_5

SIGNAL DESCRIPTION

SIGNAL TYPE

STATE

General Purpose IO

SPI Channel#2 Clock

Hi-Z

SPI_CLK_2

MSS_UARTA_RX

MSS_UARTB_TX

BSS_UART_TX

GPIO_4

EA24h

SPI_CLK_2

Debug: Firmware Trace

General Purpose IO

Hi-Z

SPI_CS_2

MSS_UARTA_TX

MSS_UARTB_TX

BSS_UART_TX

GPIO_8

SPI Channel#2 Chip Select

EA28h

SPI_CS_2

Debug: Firmware Trace

General Purpose IO

QSPI Data IN/OUT

Hi-Z

Weak Pull Down

EA2Ch

EA30h

QSPI[0]

QSPI[1]

R11

QSPI[0]

MISO_2

SPI Channel#1 Data Output

General Purpose IO

QSPI Data IN/OUT

GPIO_9

QSPI[1]

MOSI_2

SPI Channel#2 Data Input

General Purpose IO

QSPI Data IN/OUT

GPIO_10

Hi-Z

Weak Pull Down

EA34h

EA38h

QSPI[2]

QSPI[3]

R12

P10

QSPI[2]

GPIO_11

General Purpose IO

QSPI Data IN/OUT

QSPI[3]

GPIO_7

General Purpose IO

QSPI Clock output from the device.

Device operates as a master with

the serial flash being a slave

EA3Ch

EA40h

QSPI_CLK

QSPI_CS

R10

QSPI_CLK

SPI_CLK_2

GPIO_6

SPI Channel#2 Clock

General Purpose IO

Hi-Z

Weak Pull Up

QSPI Chip Select output from the

device.

Device operates as a master with

the serial flash being a slave

QSPI_CS

SPI_CS_2

SPI Channel#2 Chip Select

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 7-1. Pin Multiplexing (continued)

PAD STATE

nReset = 0 [ASSERTED]

FUNCTION

DIGITAL PIN

MUX CONFIG

VALUE [Bits3:0]

PIN NAME

ADDRESS⁽¹⁾

INTERNAL WEAK

PULL STATE

SIGNAL NAME

SIGNAL DESCRIPTION

SIGNAL TYPE

STATE

Failsafe input to the device. Nerror

output from any other device can be

concentrated in the error signaling

monitor module inside the device

and appropriate action can be taken

by Firmware

NERROR_IN

Hi-Z

Open drain fail safe warm reset

signal. Can be driven from PMIC

for diagnostic or can be used as

status signal that the device is going

through reset.

WARM_RESET

NERROR_OUT

N12

WARM_RESET

NERROR_OUT

Hi-Z Input Open Drain

Open drain fail safe output signal.

Connected to PMIC/Processor/MCU

to indicate that some severe

criticality fault has happened.

Recovery would be through reset.

Hi-Z

Open Drain

GPIO_17

General Purpose IO

JTAG Clock

Weak Pull Down

TCK

EA50h

TCK

M13

MSS_UARTB_TX

BSS_UART_RX

GPIO_18

Debug: Firmware Trace

General Purpose IO

JTAG Test Mode Select

Debug: Firmware Trace

General Purpose IO

JTAG Test Data In

Hi-Z

Weak Pull Up

EA54h

EA58h

TMS

TDI

L13

H13

TMS

BSS_UART_TX

GPIO_23

TDI

MSS_UARTA_RX

GPIO_24

General Purpose IO

JTAG Test Data Out

TDO

MSS_UARTA_TX

MSS_UARTB_TX

BSS_UART_TX

EA5Ch

TDO

J13

Debug: Firmware Trace

Sense On Power [Reset] Line

Impacts boot mode

SOP0

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 7-1. Pin Multiplexing (continued)

PAD STATE

nReset = 0 [ASSERTED]

FUNCTION

DIGITAL PIN

MUX CONFIG

VALUE [Bits3:0]

PIN NAME

ADDRESS⁽¹⁾

INTERNAL WEAK

PULL STATE

SIGNAL NAME

GPIO_25

SIGNAL DESCRIPTION

SIGNAL TYPE

STATE

General Purpose IO

Hi-Z

Weak Pull Down

Programmable clock given out to

external MCU or the processor

EA60h

MCU_CLKOUT

BSS_UART_RX

GPIO_26

Debug: Firmware Trace

General Purpose IO

Hi-Z

Weak Pull Down

GPIO_2

General Purpose IO

MSS_UARTB_TX

BSS_UART_TX

Debug: Firmware Trace

EA64h

GPIO_2

N13

Low frequency Synchronization

signal output

SYNC_OUT

PMIC_CLKOUT

GPIO_27

Dithered clock input to PMIC

General Purpose IO

Hi-Z

Weak Pull Down

PMIC_CLKOUT

Dithered Clock Output for PMIC

EA68h

EA6Ch

PMIC_CLKOUT

SYNC_IN

P13

N10

Sense On Power [Reset] Line

Impacts boot mode

SOP2

GPIO_28

SYNC_IN

General Purpose IO

Low frequency Synchronization

signal input

MSS_UARTB_RX

GPIO_29

Debug: Firmware Trace

General Purpose IO

Low frequency Synchronization

signal output

SYNC_OUT

RCOSC_CLK

SOP1

EA70h

EA74h

SYNC_OUT

P11

Sense On Power [Reset] Line

Impacts boot mode

GPIO_15

General Purpose IO

Hi-Z

Weak Pull Up

RS232_RX

Debug: Firmware load to RAM

FLASH Programming

Bootloader Controlled

RS232_RX

MSS_UARTA_RX

BSS_UART_TX

Debug: Firmware Trace

MSS_UARTB_RX

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 7-1. Pin Multiplexing (continued)

PAD STATE

nReset = 0 [ASSERTED]

FUNCTION

DIGITAL PIN

MUX CONFIG

VALUE [Bits3:0]

PIN NAME

ADDRESS⁽¹⁾

INTERNAL WEAK

PULL STATE

SIGNAL NAME

GPIO_14

SIGNAL DESCRIPTION

SIGNAL TYPE

STATE

General Purpose IO

RS232_TX

Debug: Firmware load to RAM

FLASH Programming

Bootloader Controlled

EA78h

RS232_TX

MSS_UARTA_TX

MSS_UARTB_TX

BSS_UART_TX

Debug: Firmware Trace

(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

PARAMETERS^{(1) (2)}

MIN

–0.5

MAX

UNIT

VDDIN

1.2 V digital power supply

1.4

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this

supply.

VIOIN

–0.5

3.8

VIOIN_18

1.8 V supply for CMOS IO

–0.5

VIN_18CLK

VIN_13RF1

VIN_13RF2

VIN_13RF1

1.8 V supply for clock module

1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could

be shorted on the board.

–0.5

1.45

1-V Internal LDO bypass mode. Device supports mode

where external Power Management block can supply 1 V on

VIN_13RF1 and VIN_13RF2 rails. In this configuration, the

internal LDO of the device would be kept bypassed.

–0.5

1.4

VIN_13RF2

VIN_18BB

VIN_18VCO supply

RX1-4

1.8-V Analog baseband power supply

1.8-V RF VCO supply

–0.5

Externally applied power on RF inputs

Externally applied power on RF outputs⁽³⁾

Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)

dBm

TX1-3

–0.3V

VIOIN + 0.3

Input and output

voltage range

Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V

(Transient Overshoot/Undershoot) or external oscillator input

VIOIN + 20% up to

20% of signal period

CLKP, CLKM

Clamp current

Input ports for reference crystal

–0.5

Input or Output Voltages 0.3 V above or below their respective

power rails. Limit clamp current that flows through the internal

diode protection cells of the I/O.

–20

T_J

Operating junction temperature range

–40

–55

125

150

°C

T_STG

Storage temperature range after soldered onto PC board

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) This value is for an externally applied signal level on the TX. Additionally, a reflection coefficient up to Gamma = 1 can be applied on

the TX output.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC

V_(ESD)

Electrostatic discharge

Q100-011

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.3 Power-On Hours (POH)

JUNCTION

OPERATING

TEMPERATURE (T_j)

NOMINAL CVDD VOLTAGE (V)

POWER-ON HOURS [POH] (HOURS)

CONDITION

(1) (2)

–40°C

600 (6%)

2000 (20%)

6500 (65%)

900 (9%)

75°C

100% duty cycle

95°C

1.2

125°C

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard

terms and conditions for TI semiconductor products.

(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would

not be applicable, if the Tx gain table is overwritten using an API.

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.14

3.135

1.71

NOM

1.2

3.3

1.8

MAX

1.32

3.465

1.89

1.9

UNIT

VDDIN

1.2 V digital power supply

VIN_SRAM

VNWA

1.2 V power rail for internal SRAM

1.2 V power rail for SRAM array back bias

I/O supply (3.3 V or 1.8 V):

All CMOS I/Os would operate on this supply.

VIOIN

VIOIN_18

1.8 V supply for CMOS IO

VIN_18CLK

VIN_13RF1

VIN_13RF2

1.8 V supply for clock module

1.9

1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2

could be shorted on the board

1.23

1.3

1.36

VIN_13RF1

(1-V Internal LDO

bypass mode)

0.95

1.05

VIN_13RF2

(1-V Internal LDO

bypass mode)

VIN18BB

1.8-V Analog baseband power supply

1.8V RF VCO supply

1.71

1.17

2.25

1.8

1.9

VIN_18VCO

Voltage Input High (1.8 V mode)

Voltage Input High (3.3 V mode)

Voltage Input Low (1.8 V mode)

Voltage Input Low (3.3 V mode)

High-level output threshold (I_OH= 6 mA)

Low-level output threshold (I_OL= 6 mA)

V_IL(1.8V Mode)

V_IH

V_IL

0.3*VIOIN

0.62

V_OH

V_OL

VIOIN – 450

450

0.2

V_IH(1.8V Mode)

0.96

1.57

NRESET

SOP[2:0]

V_IL(3.3V Mode)

0.3

V_IH(3.3V Mode)

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.5 Power Supply Specifications

表 8-1 describes the four rails from an external power supply block of the AWR1443 device.

表 8-1. Power Supply Rails Characteristics

SUPPLY

DEVICE BLOCKS POWERED FROM THE SUPPLY

RELEVANT IOS IN THE DEVICE

Input: VIN_18VCO, VIN18CLK, VIN_18BB,

VIOIN_18DIFF, VIOIN_18

LDO Output: VOUT_14SYNTH, VOUT_14APLL

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC, LVDS

1.8 V

1.3 V (or 1 V in internal

LDO bypass mode)⁽¹⁾

Power Amplifier, Low Noise Amplifier, Mixers and LO

Distribution

Input: VIN_13RF2, VIN_13RF1

LDO Output: VOUT_PA

3.3 V (or 1.8 V for 1.8 V

I/O mode)

Digital I/Os

Input VIOIN

1.2 V

Core Digital and SRAMs

Input: VDDIN, VIN_SRAM

(1) Three simultaneous transmitter operation is supported only in 1-V LDO bypass and PA LDO disable mode. In this mode 1V supply

needs to be fed on the VOUT PA pin.

The 1.3-V (1.0 V) and 1.8-V power supply ripple specifications mentioned in are defined to meet a target spur

level of –105 dBc (RF Pin = –15 dBm) at the RX. The spur and ripple levels have a dB-to-dB relationship, for

example, a 1-dB increase in supply ripple leads to a ~1 dB increase in spur level. Values quoted are rms levels

for a sinusoidal input applied at the specified frequency.

表 8-2. Ripple Specifications

RF RAIL

VCO/IF RAIL

FREQUENCY (kHz)

1.0 V (INTERNAL LDO BYPASS)

1.3 V (µV_RMS

)

1.8 V (µV_RMS)

(µV_RMS

)

137.5

275

648

550

1100

2200

4400

6600

117

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.6 Power Consumption Summary

表 8-3 and 表 8-4 summarize the power consumption at the power terminals.

表 8-3. Maximum Current Ratings at Power Terminals

PARAMETER

SUPPLY NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Total current drawn by all

nodes driven by 1.2V rail

VDDIN, VIN_SRAM, VNWA

500

Total current drawn by all

nodes driven by 1.3V rail

VIN_13RF1, VIN_13RF2

2000

850

Current consumption⁽¹⁾

VIOIN_18, VIN_18CLK,

VIOIN_18DIFF, VIN_18BB,

VIN_18VCO

Total current drawn by all

nodes driven by 1.8V rail

Total current drawn by

all nodes driven by 3.3V

rail⁽²⁾

VIOIN

(1) The specified current values are at typical supply voltage level.

(2) The exact VIOIN current depends on the peripherals used and their frequency of operation.

表 8-4. Average Power Consumption at Power Terminals

PARAMETER

CONDITION

DESCRIPTION

MIN

TYP

MAX UNIT

1.0-V internal

LDO bypass

mode

1TX, 4RX

2TX, 4RX

1TX, 4RX

2TX, 4RX

1.72

1.89

1.90

2.10

Sampling: 16.66 MSps complex

Transceiver, 40-ms frame time, 512

chirps, 512 samples/chirp, 8.5-μs

interchirp time (50% duty cycle)

Data Port: MIPI-CSI-2

Average power

consumption

1.3-V internal

LDO enabled

mode

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.7 RF Specification

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

–8

MAX UNIT

76 to 77 GHz

Noise figure

77 to 81 GHz

1-dB compression point (Out Of Band)⁽¹⁾

Maximum gain

dBm

Gain range

Gain step size

Image Rejection Ratio (IMRR)

IF bandwidth⁽²⁾

MHz

ADC sampling rate (real/complex 2x)

ADC sampling rate (complex 1x)

ADC resolution

12.5 Msps

6.25 Msps

Receiver

<–10

±0.5

±3

Bits

Return loss (S11)

Gain mismatch variation (over temperature)

Phase mismatch variation (over temperature)

RX gain = 30dB

IF = 1.5, 2 MHz at

–12 dBFS

In-band IIP2

dBm

RX gain = 24dB

IF = 10 kHz at -10dBm,

1.9 MHz at -30 dBm

Out-of-band IIP2

Idle Channel Spurs

Output power

–90

dBFS

dBm

Transmitter

Amplitude noise

Frequency range

Ramp rate

–145

dBc/Hz

81 GHz

100 MHz/µs

Clock

subsystem

76 to 77 GHz

77 to 81 GHz

–95

–93

Phase noise at 1-MHz offset

dBc/Hz

(1) 1-dB Compression Point (Out Of Band) is measured by feed a Continuous wave Tone (10 kHz) well below the lowest HPF cut-off

frequency.

(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set

of available HPF corners is summarized as follows:

Available HPF Corner Frequencies (kHz)

HPF1

HPF2

175, 235, 350, 700

350, 700, 1400, 2800

The filtering performed by the digital baseband chain is targeted to provide:

•

Less than ±0.5 dB pass-band ripple/droop, and

Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.

图 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

-18

NF (dB)

In-band P1DB (dBm)

-24

-30

-36

-42

-48

38 40

RX Gain (dB)

图 8-1. Noise Figure, In-band P1dB vs Receiver Gain

8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

RΘ_JC

RΘ_JB

RΘ_JA

RΘ_JMA

Psi_JT

Psi_JB

Junction-to-case

Junction-to-board

5.9

Junction-to-free air

Junction-to-moving air

Junction-to-package top

Junction-to-board

21.6

15.3 ⁽⁴⁾

0.69

5.8

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on

a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(4) Air flow = 1 m/s

8.9 Timing and Switching Characteristics

8.9.1 Power Supply Sequencing and Reset Timing

The AWR1443 device expects all external voltage rails to be stable before reset is deasserted. 图 8-2 describes

the device wake-up sequence.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

SOP

Setup

Time

SOP

Hold time to

nRESET

DC power

MSS

BOOT

START

nRESET

ASSERT

tPGDEL

Power

notOK

Stable before

nRESET

release

Power

QSPI

READ

VDDIN,

VIN_SRAM

VNWA

VIOIN_18

VIN18_CLK

VIOIN_18DIFF

VIN18_BB

VIN_13RF1

VIN_13RF2

VIOIN

SOP[2.1.0]

nRESET

Warm reset

delay for crystal

or ext osc

WARMRESET

OUTPUT

VBGAP

OUTPUT

CLKP, CLKM

Using Crystal

MCUCLK

OUTPUT (1)

QSPI_CS

OUTPUT

7ms (XTAL Mode)

500 µs (REFCLK Mode)

A. MCU_CLK_OUT in autonomous mode, where AWR1443 application is booted from the serial flash, MCU_CLK_OUT is not enabled by

default by the device bootloader.

图 8-2. Device Wake-up Sequence

8.9.2 Synchronized Frame Triggering

The AWR1443 device supports a hardware based mechanism to trigger radar frames. An external host can

pulse the SYNC_IN signal to start radar frames. The typical time difference between the rising edge of

the external pulse and the frame transmission on air (Tlag) is about 160 ns. There is also an additional

programmable delay that the user can set to control the frame start time.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

T_{active_frame}

SYNC_IN

(Hardware

Trigger)

Radar

Frames

T_pulse

T_lag

Frame-2

Frame-1

图 8-3. Sync In Hardware Trigger

表 8-5. Frame Trigger Timing

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

T_{active_frame}

T_pulse

Active frame duration

User defined

4000

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.3 Input Clocks and Oscillators

8.9.3.1 Clock Specifications

An external crystal is connected to the device pins. 图 8-4 shows the crystal implementation.

C_f1

CLKP

C_p

40 MHz

CLKM

C_f2

图 8-4. Crystal Implementation

备注

The load capacitors, C_f1and C_f2in 图 8-4, should be chosen such that 方程式 1 is satisfied. C_Lin the

equation is the load specified by the crystal manufacturer. All discrete components used to implement

the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and

CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

C _f2

C_L= C _f1

+C_P

_f1+C _f2

(1)

表 8-6 lists the electrical characteristics of the clock crystal.

表 8-6. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

f_P

Parallel resonance crystal frequency

C_L

Crystal load capacitance

Crystal ESR

ESR

Temperature range Expected temperature range of operation

–40

125

°C

Frequency

Crystal frequency tolerance^{(1) (2)}

tolerance

–200

200

ppm

µW

Drive level

(1) The crystal manufacturer's specification must satisfy this requirement.

(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. 表 8-7 lists

the electrical characteristics of the external clock signal.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 8-7. External Clock Mode Specifications

SPECIFICATION

PARAMETER

UNIT

MIN

TYP

MAX

Frequency

MHz

mV (pp)

AC-Amplitude

700

1200

DC-t_rise/fall

Input Clock:

External AC-coupled sine wave or DC-

coupled square wave

Phase Noise at 1 kHz

Phase Noise at 10 kHz

Phase Noise at 100 kHz

Phase Noise at 1 MHz

Duty Cycle

–132

–143

–152

–153

dBc/Hz

Phase Noise referred to 40 MHz

Freq Tolerance

–100

100

ppm

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)

8.9.4.1 Peripheral Description

The SPI uses a MibSPI Protocol by TI.

The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.

The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals or

another microcontroller.

Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

8-bit baud clock generator

SPICLK can be internally-generated (controller mode) or received from an external clock source

(peripheral mode)

•

Each word transferred can have a unique format.

SPI I/Os not used in the communication can be used as digital input/output signals

8.9.4.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a 16-bit

transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer RAM can be

partitioned into multiple transfer group with variable number of buffers each.

节 8.9.4.2.2 and 节 8.9.4.2.3 assume the operating conditions stated in 节 8.9.4.2.1.

8.9.4.2.1 SPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOADOutput load capacitance

8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

TYP

MAX UNIT

t_c(SPC)M

256_tc(VCLK)

0.5t_c(SPC)M+ 4

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M– 3

2⁽⁴⁾

3⁽⁴⁾

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock

polarity = 0)

SIMO)M

4⁽⁴⁾

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M– 3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

5⁽⁴⁾

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

NO.

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

PARAMETER

MIN

TYP

MAX UNIT

(C2TDELAY+2)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

(C2TDELAY+2)*

t_c(VCLK)– 7.5

Setup time CS active until SPICLK

high

(clock polarity = 0)

* t_c(VCLK)+ 7

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

6⁽⁵⁾

t_C2TDELAY

(C2TDELAY+2)*

t_c(VCLK)– 7.5

(C2TDELAY+2)

* t_c(VCLK)+ 7

Setup time CS active until SPICLK low

(clock polarity = 1)

(C2TDELAY +3)

* t_c(VCLK)– 7.5

(C2TDELAY+3)

* t_c(VCLK)+ 7

Hold time, SPICLK low until CS inactive (clock polarity = 0)

0.5*t_c(SPC)M

(T2CDELAY +

1) *t_c(VCLK)– 7

0.5*t_c(SPC)M

(T2CDELAY +

1) * t_c(VCLK)

7.5

7⁽⁵⁾

t_T2CDELAY

Hold time, SPICLK high until CS inactive (clock polarity = 1)

0.5*t_c(SPC)M

(T2CDELAY +

1) *t_c(VCLK)– 7

(T2CDELAY +

1) * t_c(VCLK)

7.5

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

SPCL)M

8⁽⁴⁾

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1

Master Out Data Is Valid

SPISIMO

Master In Data

Must Be Valid

SPISOMI

图 8-5. SPI Controller Mode External Timing (CLOCK PHASE = 0)

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

Master Out Data Is Valid

SPICSn

图 8-6. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)

8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^{(1) (2) (3)}

NO.

PARAMETER

Cycle time, SPICLK⁽⁴⁾

MIN

TYP

MAX UNIT

t_c(SPC)M

256t_c(VCLK)

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 4

0.5t_c(SPC)M+ 4

2⁽⁴⁾

3⁽⁴⁾

t_d(SPCH-

Delay time, SPISIMO valid before SPICLK low, (clock polarity 0.5t_c(SPC)M– 3

= 0)

SIMO)M

4⁽⁴⁾

t_d(SPCL-

Delay time, SPISIMO valid before SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M– 3

SIMO)M

t_v(SPCL-

Valid time, SPISIMO data valid after SPICLK low, (clock

polarity = 0)

0.5t_c(SPC)M

–

10.5

SIMO)M

5⁽⁴⁾

t_v(SPCH-

Valid time, SPISIMO data valid after SPICLK high, (clock

polarity = 1)

0.5t_c(SPC)M

–

10.5

SIMO)M

t_C2TDELAY

Setup time CS active until SPICLK

high

(clock polarity = 0)

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

0.5*t_c(SPC)M

(C2TDELAY +

2)*t_c(VCLK)– 7

0.5*t_c(SPC)M

(C2TDELAY+2

) * t_c(VCLK)

7.5

0.5*t_c(SPC)M

(C2TDELAY +

2)*t_c(VCLK)– 7

0.5*t_c(SPC)M

(C2TDELAY+2

) * t_c(VCLK)

7.5

6⁽⁵⁾

0.5*t_c(SPC)M

(C2TDELAY+2

)*t_c(VCLK)– 7

0.5*t_c(SPC)M

(C2TDELAY+2

) * t_c(VCLK)

Setup time CS active until SPICLK

low

(clock polarity = 1)

7.5

0.5*t_c(SPC)M

(C2TDELAY+3

)*t_c(VCLK)– 7

0.5*t_c(SPC)M

(C2TDELAY+3

) * t_c(VCLK)

7.5

Hold time, SPICLK low until CS inactive (clock polarity = 0)

Hold time, SPICLK high until CS inactive (clock polarity = 1)

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

7⁽⁵⁾

t_T2CDELAY

(T2CDELAY +

1) *t_c(VCLK)+ 7

1) *t_c(VCLK)

–

7.5

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

NO.

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

PARAMETER

MIN

TYP

MAX UNIT

t_su(SOMI-

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

SPCL)M

8⁽⁴⁾

t_su(SOMI-

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

SPCH)M

t_h(SPCL-

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

SOMI)M

9⁽⁴⁾

t_h(SPCH-

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

SOMI)M

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).

(2) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M= 2t_{c(MSS_VCLK)}≥ 25 ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

Master Out Data Is Valid

Data Valid

SPISIMO

Master In Data

Must Be Valid

SPISOMI

图 8-7. SPI Controller Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

图 8-8. SPI Controller Mode Chip Select Timing (CLOCK PHASE = 1)

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.4.3 SPI Peripheral Mode I/O Timings

8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input,

and SPISOMI = output)^{(1) (2) (3)}

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_c(SPC)S

Cycle time, SPICLK⁽⁴⁾

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

t_{d(SPCH-SOMI)S}

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

2⁽⁵⁾

3⁽⁵⁾

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0)

4⁽⁵⁾

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

5⁽⁵⁾

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

Setup time, SPISIMO before SPICLK low (clock

polarity = 0; clock phase = 0) OR (clock polarity =

1; clock phase = 1)

t_{su(SIMO-SPCL)S}

Setup time, SPISIMO before SPICLK high (clock

t_{su(SIMO-SPCH)S}polarity = 1; clock phase = 0) OR (clock polarity =

0; clock phase = 1)

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0; clock phase = 0) OR (clock

polarity = 1; clock phase = 1)

t_{h(SPCL-SIMO)S}

Hold time, SPISIMO data valid after SPICLK high

(clock polarity = 1; clock phase = 0) OR (clock

polarity = 0; clock phase = 1)

t_{h(SPCL-SIMO)S}

(1) The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).

(2) The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.

(3) t_{c(MSS_VCLK)}= main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(4) When the SPI is in peripheral mode, the following must be true: For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_{c(MSS_VCLK)}≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: t_c(SPC)S= 2t_{c(MSS_VCLK)}≥ 25 ns.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

SPISIMO

图 8-9. SPI peripheral Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity = 0)

SPICLK

(clock polarity = 1)

SPISOMI

SPISOMI Data Is Valid

SPISIMO Data

Must Be Valid

SPISIMO

图 8-10. SPI peripheral Mode External Timing (CLOCK PHASE = 1)

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)

1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.

2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.

图 8-11 shows the SPI communication timing of the typical interface protocol.

2 SPI clocks

CLK

0x4321

0x1234

CRC

0x5678

0x8765

MOSI

MISO

IRQ

0xDCBA

0xABCD

CRC

16 bytes

图 8-11. SPI Communication

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.5 LVDS Interface Configuration

The AWR1443 supports seven differential LVDS IOs/Lanes. The lane configuration supported is four Data lanes

(LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M), and one

HS_DEBUG LVDS pair. The LVDS interface is used for debugging. The LVDS interface supports the following

data rates:

•

900 Mbps (450 MHz DDR Clock)

600 Mbps (300 MHz DDR Clock)

450 Mbps (225 MHz DDR Clock)

400 Mbps (200 MHz DDR Clock)

300 Mbps (150 MHz DDR Clock)

225 Mbps (112.5 MHz DDR Clock)

150 Mbps (75 MHz DDR Clock)

Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.

LVDS_TXP/M

LVDS_FRCLKP/M

Data bitwidth

LVDS_CLKP/M

图 8-12. LVDS Interface Lane Configuration And Relative Timings

8.9.5.1 LVDS Interface Timings

表 8-8. LVDS Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty Cycle Requirements

max 1 pF lumped capacitive load on

LVDS lanes

48%

52%

Output Differential Voltage

peak-to-peak single-ended with 100 Ω

resistive load between differential pairs

250

450

Output Offset Voltage

Trise and Tfall

1125

1275

20%-80%, 900 Mbps

900 Mbps

330

Jitter (pk-pk)

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

Trise

LVDS_CLK

Clock Jitter = 6sigma

LVDS_TXP/M

LVDS_FRCLKP/M

1100 ps

图 8-13. Timing Parameters

8.9.6 General-Purpose Input/Output

节 8.9.6.1 lists the switching characteristics of output timing relative to load capacitance.

8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (C_L)

PARAMETER^{(1) (2)}

TEST CONDITIONS

C_L= 20 pF

VIOIN = 1.8V

VIOIN = 3.3V

UNIT

2.8

6.4

9.4

2.8

6.4

9.4

3.3

6.7

9.6

3.1

6.6

9.6

3.0

6.9

10.2

2.8

6.6

9.8

3.3

7.2

10.5

3.1

6.6

9.6

t_r

t_f

t_r

t_f

Max rise time

C_L= 50 pF

C_L= 75 pF

Slew control = 0

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

C_L= 20 pF

C_L= 50 pF

C_L= 75 pF

Max fall time

Max rise time

Max fall time

Slew control = 1

(1) Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).

(2) The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.7 Controller Area Network Interface (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multi-commander communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps.

The DCAN is ideal for applications operating in noisy and harsh environments that require reliable serial

communication or multiplexed wiring.

The DCAN has the following features:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 Mbps

Configurable Message objects

Individual identifier masks for each message object

Programmable FIFO mode for message objects

Suspend mode for debug support

Programmable loop-back modes for self-test operation

Direct access to Message RAM in test mode

Supports two interrupt lines - Level 0 and Level 1

Automatic Message RAM initialization

8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER

MIN

TYP

MAX

UNIT

t_{d(CAN_tx)}

t_{d(CAN_rx)}

Delay time, transmit shift register to CAN_tx pin⁽¹⁾

Delay time, CAN_rx pin to receive shift register⁽¹⁾

(1) These values do not include rise/fall times of the output buffer.

8.9.8 Serial Communication Interface (SCI)

The SCI has the following features:

•

Standard universal asynchronous receiver-transmitter (UART) communication

Standard non-return to zero (NRZ) format

Double-buffered receive and transmit functions

Asynchronous or iso-synchronous communication modes with no CLK pin

Capability to use Direct Memory Access (DMA) for transmit and receive data

Two external pins: RS232_RX and RS232_TX

8.9.8.1 SCI Timing Requirements

MIN

TYP

MAX

UNIT

kHz

f(baud)

Supported baud rate at 20 pF

921.6

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.9 Inter-Integrated Circuit Interface (I2C)

The inter-integrated circuit (I2C) module is a multicontroller communication module providing an interface

between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an

I²C-bus™. This module will support any target or controller I2C compatible device.

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398

393 40011)

– Bit/Byte format transfer

– 7-bit and 10-bit device addressing modes

– General call

– START byte

– Multi-controller transmitter/ target receiver mode

– Multi-controller receiver/ target transmitter mode

– Combined controller transmit/receive and receive/transmit mode

– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

•

备注

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C sends the target address second byte every

time it sends the target address first byte)

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

UNIT

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.9.1 I2C Timing Requirements⁽¹⁾

STANDARD MODE

FAST MODE

MIN

MAX

MIN

2.5

MAX

t_c(SCL)

Cycle time, SCL

μs

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low

(for a repeated START condition)

4.7

0.6

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low

0.6

μs

(for a START and a repeated START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

1.3

0.6

100

μs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SCLL-SDA)

t_w(SDAH)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

3.45⁽¹⁾

0.9

Pulse duration, SDA high between STOP and START

conditions

4.7

1.3

t_{su(SCLH-SDAH)}

t_w(SP)

Setup time, SCL high before SDA high

(for STOP condition)

0.6

μs

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

(2) (3)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the

SCL signal.

(3) C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

图 8-14. I2C Timing Diagram

备注

•

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW

period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-

mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such

a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA

line tr max + t_su(SDA-SCLH)

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.10 Quad Serial Peripheral Interface (QSPI)

The quad serial peripheral interface (QSPI) module is a kind of SPI module that allows single, dual, or quad read

access to external SPI devices. This module has a memory mapped register interface, which provides a direct

interface for accessing data from external SPI devices and thus simplifying software requirements. The QSPI

works as a controller only. The QSPI in the device is primarily intended for fast booting from quad-SPI flash

memories.

The QSPI supports the following features:

•

Programmable clock divider

Six-pin interface

Programmable length (from 1 to 128 bits) of the words transferred

Programmable number (from 1 to 4096) of the words transferred

Support for 3-, 4-, or 6-pin SPI interface

Optional interrupt generation on word or frame (number of words) completion

Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles

节 8.9.10.2 and 节 8.9.10.3 assume the operating conditions stated in 节 8.9.10.1.

8.9.10.1 QSPI Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOAD

Output load capacitance

8.9.10.2 Timing Requirements for QSPI Input (Read) Timings^{(1) (2)}

MIN

7.3

TYP

MAX

UNIT

t_su(D-SCLK)

t_h(SCLK-D)

t_su(D-SCLK)

t_h(SCLK-D)

Setup time, d[3:0] valid before falling sclk edge (Q12)

Hold time, d[3:0] valid after falling sclk edge (Q13)

Setup time, final d[3:0] bit valid before final falling sclk edge

Hold time, final d[3:0] bit valid after final falling sclk edge

1.5

7.3 – P⁽³⁾

1.5 + P⁽³⁾

(1) Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.

(2) The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although

non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Mode 0.

(3) P = SCLK period in ns.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.10.3 QSPI Switching Characteristics

NO.

PARAMETER

Cycle time, sclk

MIN

TYP

MAX

UNIT

t_c(SCLK)

t_w(SCLKL)

Pulse duration, sclk low

0.5*P – 3⁽¹⁾

0.5*P – 3

–M*P – 1⁽²⁾

N*P – 1⁽²⁾

–3.5

t_w(SCLKH)

Pulse duration, sclk high

t_d(CS-SCLK)

t_d(SCLK-CS)

t_d(SCLK-D1)

t_ena(CS-D1LZ)

t_dis(CS-D1Z)

t_d(SCLK-D1)

Delay time, sclk falling edge to cs active edge

Delay time, sclk falling edge to cs inactive edge

Delay time, sclk falling edge to d[0] transition

Enable time, cs active edge to d[0] driven (lo-z)

Disable time, cs active edge to d[0] tri-stated (hi-z)

–M*P + 2.5⁽²⁾

N*P + 2.5⁽²⁾

–P – 4⁽²⁾

–P +1⁽²⁾

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

–3.5 – P⁽²⁾

7 – P⁽²⁾

(1) P = SCLK period in ns.

(2) M = QSPI_SPI_DC_REG.DDx + 1, N = 2

图 8-15. QSPI Read (Clock Mode 0)

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

PHA=0

POL=0

sclk

Command

Bit n-1

Command

Bit n-2

Write Data

Bit 1

Write Data

Bit 0

d[0]

d[3:1]

SPRS85v_TIMING_OSPI1_04

图 8-16. QSPI Write (Clock Mode 0)

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

8.9.11 JTAG Interface

节 8.9.11.2 and 节 8.9.11.3 assume the operating conditions stated in 节 8.9.11.1.

8.9.11.1 JTAG Timing Conditions

MIN

TYP

MAX

UNIT

Input Conditions

t_R

t_F

Input rise time

Input fall time

Output Conditions

C_LOAD

Output load capacitance

8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG

NO.

MIN

TYP

MAX

UNIT

t_c(TCK)

Cycle time TCK

66.66

26.67

2.5

t_w(TCKH)

Pulse duration TCK high (40% of tc)

Pulse duration TCK low(40% of tc)

Input setup time TDI valid to TCK high

Input setup time TMS valid to TCK high

Input hold time TDI valid from TCK high

Input hold time TMS valid from TCK high

t_w(TCKL)

t_su(TDI-TCK)

t_su(TMS-TCK)

t_h(TCK-TDI)

t_h(TCK-TMS)

2.5

8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG

NO.

PARAMETER

MIN

TYP

MAX

UNIT

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

TCK

TDO

TDI/TMS

SPRS91v_JTAG_01

图 8-17. JTAG Timing

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9 Detailed Description

9.1 Overview

The AWR1443 device includes the entire millimeter wave blocks and analog baseband signal chain for three

transmitters (two usable at the same instance) and four receivers, as well as a customer-programmable MCU

with a hardware accelerator for radar signal processing. This device is applicable as a radar-on-a-chip in

use-cases with modest requirements for memory, processing capacity and application code size. These could

be cost-sensitive automotive applications that are evolving from 24 GHz narrowband implementation and some

emerging simple ultra-short-range radar applications. Typical application examples for this device include basic

Blind Spot Detect, Parking Assist, and so forth.

In terms of scalability, the AWR1443 device could be paired with a low-end external MCU, to address more

complex applications that might require additional memory for larger application software footprint and faster

interfaces. Because the AWR1443 device also provides high speed data interfaces, it is suitable for interfacing

with more capable external processing blocks. Here system designers can choose the AWR1443 to provide raw

ADC data or use the on-chip Hardware Accelerator for partial processing viz. first stage Fast Fourier Transform.

9.2 Functional Block Diagram

Cortex R4F

@ 200 MHz

RX1

RX2

RX3

RX4

LNA

ADC

(User programmable)

Digital Front

End

Boot

ROM

Prog RAM* Data RAM*

(Decimation

filter chain)

Serial Flash

interface

QSPI

Radar Data

Memory*

Optional External

MCU interface

SPI

ADC

Buffer

TX1

TX2

TX3

Radar

PMIC control

SPI / I2C

DCAN

Hardware

Accelerator

(FFT, Log-

Mag, and

others.)

Synth

(20 GHz)

Ramp

Generator

Primary communication

interface (automotive)

Debug

UARTs

DMA

For debug

RF Control/

BIST

Mailbox

Test/

Debug

JTAG for debug/

development

Osc.

VMON

Temp

GPADC

Main subsystem

(Customer programmed)

RF/Analog subsystem

* Total RAM available in Main subsystem is 576KB (for Cortex-R4F Program RAM, Data RAM, and Radar Data Memory)

图 9-1. Functional Block Diagram

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.3 External Interfaces

The AWR1443 device provides the following external interfaces:

•

Reference Clock – Reference clock available for Host Processor after device wakeup.

Low speed control information

– Up to two 4-line standard SPI interface

– One I²C interface (Pin multiplexed with one of the SPI ports)

One Controller Area Network (CAN) Port for Automotive Interfacing

Reset – Active Low reset for device wakeup from host General Purpose IOs

Error Signaling – Used for notifying the host in case the Radio Controller detects a fault

•

The AWR1443 device comprises of three main blocks – Radar (or the Millimeter Wave) System, Main (or the

Control) System and Processing System.

RADAR System

Radar Processing Inter-connect [128 Bit @ 200MHz]

RF/Analog/Monitoring

FFT

ADC

ACCELERATOR

EDMA

LVDS

BUFFERS

RAM

MAILBOX

(384KB)

2x16KB

Main (Control) System Inter-connect [64 Bit @ 200MHz]

CRC

JTAG

ROM

DMA

Integrated MCU

ARM^®Cortex^®R4F

Program

RAM

Data

RAM

Peripheral Inter-connect

SPI

Timer

UART

QSPI

CAN

I2C

PWM

SPI

图 9-2. System Interconnect

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.4 Subsystems

9.4.1 RF and Analog Subsystem

The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA, mixer,

IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The three transmit

channels can be operated up to a maximum of two at a time (simultaneously) for transmit beamforming purpose

as required; whereas the four receive channels can all be operated simultaneously.

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.4.1.1 Clock Subsystem

The AWR1443 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has

a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF

synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum.

The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective

sensor operation.

The clean-up PLL also provides a reference clock for the host processor after system wakeup.

The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the

quality of the generated clock.

图 9-3 describes the clock subsystem.

Self Test

Timing

Engine

RF SYNTH

1 GHz

(fixed clockdomain)

Lock Detect

SoC Clock

Clean-

Up PLL

MULT

XO/

Slicer

CLK Detect

40 MHz

图 9-3. Clock Subsystem

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.4.1.2 Transmit Subsystem

The AWR1443 transmit subsystem consists of three parallel transmit chains, each with independent phase and

amplitude control. A maximum of 2 transmit chains can be operational at the same time. However all 3 chains

can be operated together in a time multiplexed fashion. The device supports binary phase modulation for MIMO

radar and interference mitigation.

Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit chains also

support programmable backoff for system optimization.

图 9-4 describes the transmit subsystem.

Loopback Path

Fine Phase Shifter Control

PCB

6 bits

12dBm

@ 50 Ω

û-

0/180°

(from Timing Engine)

Self Test

图 9-4. Transmit Subsystem (Per Channel)

9.4.1.3 Receive Subsystem

The AWR1443 receive subsystem consists of four parallel channels. A single receive channel consists of an

LNA, mixer, IF filtering, ADC conversion, and decimation. All four receive channels can be operational at the

same time an individual power-down option is also available for system optimization.

Unlike conventional real-only receivers, the AWR1443 device supports a complex baseband architecture, which

uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each receiver

channel. The AWR1443 is targeted for fast chirp systems. The band-pass IF chain has configurable lower cutoff

frequencies above 175 kHz and can support bandwidths up to 5 MHz.

图 9-5 describes the receive subsystem.

Self Test

DAC

Loopback

Path

DSM

PCB

RSSI

50 W

GSG

DSM

DAC

图 9-5. Receive Subsystem (Per Channel)

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.4.1.4 Radio Processor Subsystem

The Radio Processor subsystem (also referred to as BIST Subsystem in this document) includes the digital

front-end, the ramp generator and an internal processor for control / configuration of the low-level RF/analog

and ramp generator registers. The Radar Processor also schedules periodic monitoring tasks. User applications,

running on

Master (Control) System, do not have direct access to Radar System; access is based on well-defined API

messages (over a hardware channel) from the master subsystem.

备注

This radio processor is programmed by TI and takes care of RF calibration and self-test/monitoring

functions (BIST). This processor is not available directly for customer use/application.

The digital front-end takes care of filtering and decimating the raw sigma-delta ADC output and provides the final

ADC data samples at a programmable sampling rate.

9.4.2 Main (Control) System

The Main (Control) System includes ARM’s automotive grade Cortex-R4F processor clocked at 200 MHz, which

is user programmable. User applications executing on this processor control the overall operation of the device,

including Radar Control via well-defined API messages, radar signal processing (assisted by the radar hardware

accelerator) and peripherals for external interface.

The Main (Control) System plays a big role in enabling autonomous operation of AWR1443 as a radar-on-a-chip

sensor. The device includes a quad serial peripheral interface (QSPI) which can be used to download customer

code directly from a serial flash. A (classic) CAN interface is included that can be used to communicate directly

from the device to a CAN bus. An SPI/I2C interface is available for power management IC (PMIC) control when

the AWR1443 is used as an autonomous sensor.

For more complex applications, the device can operate under the control of an external MCU, which can

communicate with AWR1443 device over an SPI interface. In this case, it is possible to use the AWR14xx as a

radar sensor, providing raw detected objects to the external MCU. External MCU could reduce the application

code complexity residing in the device and makes more memory available for radar data cube inside the

AWR1443. This configuration also eliminates the need for a separate serial flash to be connected to the

AWR1443.

Furthermore, the external MCU can provide faster interfaces, such as CAN-FD or Ethernet, for the radar sensor

to connect to a central processing unit (CPU). In such a distributed configuration, multiple AWR1443 devices

mounted around the vehicle can connect to the CPU, providing a surround view. The external MCU itself

is low-cost, because the low-level radar signal processing is accomplished inside the AWR1443, using the

hardware accelerator, while the higher-layer intelligence and complex algorithms reside in the common CPU,

making the overall solution cost-effective.

Note that although four interfaces – one CAN, one I2C and two SPI interfaces – are present in the AWR1443

device for external communication and PMIC control, only two of these interfaces are usable at any point in time.

The total memory (RAM) available in the Main subsystem is 576 KB. This is partitioned between the R4F

program RAM, R4F data RAM and radar data memory. The maximum usable size for R4F is 448 KB and this

is partitioned between the R4F’s tightly coupled interfaces TCMA (320 KB) and TCMB (128 KB). Although the

complete 448 KB is unified memory and can be used for program or data, typical applications use TCMA as

program and TCMB as data memory.

The remaining memory, starting at a minimum of 128 KB, is available to be used as radar data memory for

storing the ‘radar data cube’. It is possible to increase the radar data memory size in 64 KB increments, at the

cost of corresponding reduction in R4F program or data RAM size. The maximum size of radar data memory

possible is 384 KB. A few example configurations supported are listed in 表 9-1.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 9-1. R4F RAM⁽¹⁾

R4F

R4F DATA

PROGRAM

RAM

RADAR DATA

MEMORY

OPTION

RAM

320KB

256KB

128KB

64KB

128KB

192KB

256KB

384KB

64KB

(1) For AWR1443 ES version 1.0, available RAM is 448 KB instead

of 576KB.

The Main Subsystem, Cortex-R4F memory map is shown in 表 9-2.

表 9-2. Main System Memory Map

Frame Address (Hex)

Name

Size

Description

Start

End

CPU Tightly Coupled Memories

TCMA ROM

TCM RAM-A

TCM RAM-B

0x0000_0000

0x0020_0000

0x0800_0000

0x0001_FFFF

0x0024_FFFF

0x0802_FFFF

96KiB

Program ROM

128–320KiB

64–128KiB

Memory size is dependant on the

allocation done in 表 9-1, R4F RAM

System Peripherals

0xF060_1000

0xF060_2000

0xF060_17FF

0xF060_27FF

2KiB

RADARSS to MSS mailbox memory space

MSS to RADARSS mailbox memory space

Mail Box

MSS<->RADARSS

MSS to RADARSS mailbox Configuration

Registers

0xF060_8000

0xF060_8060

0xFFFF_E100

0xF060_80FF

0xF060_86FF

0xFFFF_E2FF

188B

756B

RADARSS to MSS mailbox Configuration

Registers

TOP Level Reset, Clock management

registers

0xFFFF_FF00

0xFFFF_EA00

0xFFFF_F800

0xFFFF_FFFF

0xFFFF_EBFF

0xFFFF_FBFF

256B

512KiB

352B

MSS Reset, Clock management registers

IO Mux module registers

PRCM & Control Module

General-purpose control registers

TPCC,TPTC,ADC buffer configuration,

status registers

0x5000_0400

584B

GIO

DMA

VIM

0xFFF7_BC00

0xFFFF_F000

0xFFFF_FD00

0xFFFF_FC00

0xFFFF_EE00

0xFFF7_BDFF

0xFFFF_F3FF

0xFFFF_FEFF

0xFFFF_FCFF

0xFFFF_EEFF

180B

1KiB

512B

192B

GIO module configuration registers

DMA-1 module configuration registers

VIM module configuration registers

RTI-A module

RTI-A

RTI-B

RTI-B module register space

Serial Interfaces and Connectivity

QSPI

0xC000_0000

0xC080_0000

0xFFF7_F400

0xFFF7_F600

0xFFF7_E500

0xFFF7_E700

0xFFF7_DC00

0xFFF7_D400

0x5200_0000

0x5202_0000

0xC07F_FFFF

0xC0FF_FFFF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_E5FF

0xFFF7_E7FF

0xFFF7_DDFF

0xFFF7_D4FF

8MB

116B

512B

148B

512B

112B

16KiB

QSPI –Flash Memory space

QSPI module configuration registers

MIBSPI-A module configuration registers

SPI module configuration registers

SCI-A module configuration registers

SCI-B module configuration registers

CAN module configuration registers

I2C module configuration registers

ADC ping pong buffer memory space

Common buffer memory space

MIBSPI

SPI

SCI-A/UART

SCI-B/UART

CAN

I2C

ADC Buffer

CBUF_FIFO

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 9-2. Main System Memory Map (continued)

Frame Address (Hex)

Name

Size

Description

Start

End

0x5008_0000

0x5008_0800

0x5008_1000

0x5203_0000

0x5203_8000

0x5008_07FF

0x5008_0FFF

512B

264B

4KiB

FFT Accelerator PARAM memory

FFT accelerator Configuration registors

FFT accelerator Window registers

FFT accelerator Memory -1 space

FFT accelerator Memory -2 space

Hardware FFT accelerator

0x5203_7FFF

32KiB

L3 Memory

L3 Shared Memory

0x5100_0000

384KiB

L3 Shared memory space

Interconnects

0xFFF7_87FF

0xFCFF_17FF

PCR

PCR-2

0xFFF7_8000

0xFCFF_1000

0x5207_0000

1KiB

128B

PCR-1 interconnect configuration port

PCR-2 interconnect configuration port

128 bit SCR configuration port

128 bit SCR

Safety Modules

CRC

PBIST

STC

0xFE00_0000

0xFFFF_E400

0xFFFF_E600

0xFFFF_EC00

0xFFFF_F400

0xFFFF_F500

0xFFFF_F600

0xFEFF_FFFF

0xFFFF_E5FF

0xFFFF_E7FF

0xFFFF_ECFF

0xFFFF_F4FF

0xFFFF_F5FF

0xFFFF_F6FF

16KiB

464B

284B

44B

CRC module configuration registers

PBIST module configuration registers

STC module configuration registers

DCC-A module configuration registers

DCC-B module configuration registers

ESM module configuration registers

CCMR4 module configuration registers

DCC-A

DCC-B

ESM

44B

156B

136B

CCMR4

Peripheral Memories (System & Non System)

CAN RAM

DMA RAM

0xFF1E_0000

0xFFF8_0000

0xFFF8_2000

0xFF0E_0000

0xFF0E_0200

0xFF1F_FFFF

0xFFF8_0FFF

0xFFF8_2FFF

0xFF0E_01FF

0xFF0E_03FF

128KB

4KB

CAN RAM memory space

DMA RAM memory space

VIM RAM

2KB

VIM RAM memory space

MIBSPIA-TX RAM

MIBSPIA- RX RAM

0.5KB

MIBSPIA-TX RAM memory space

MIBSPIA- RX RAM memory space

Debug Modules

0xFFAF_FFFF

Debug subsystem memory space and

registers

Debug Sub System

0xFFA0_0000

244KiB

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.4.3 Host Interface

The AWR1443 device communicates with the host radar processor over the following main interfaces:

•

Reference Clock – Reference clock available for host processor after device wakeup

Control – 4-port standard SPI (peripheral) for host control . All radio control commands (and response) flow

through this interface.

•

Reset – Active-low reset for device wakeup from host

Out-of-band interrupt

Error – Used for notifying the host in case the radio controller detects a fault

9.5 Accelerators and Coprocessors

The Processing System in the AWR1443 device is an accelerator for FFT operations. The Radar Hardware

Accelerator is an IP that enables off-loading the burden of certain frequently used computations in FMCW radar

signal processing from the main processor. It is well-known that FMCW radar signal processing involves the use

of FFT and Log-Magnitude computations in order to obtain a radar image across the range, velocity and angle

dimensions. Some of the frequently used functions in FMCW radar signal processing can be done within the

Radar Hardware Accelerator, while still retaining the flexibility of implementing other proprietary algorithms in the

Master System processor.

Key features of the Radar Processing Accelerator are:

•

FFT computation, with programmable FFT sizes (powers of 2) up to 1024-pt complex FFT

Internal FFT bit-width of 24 bits (each for I and Q) for good SQNR performance, with fully programmable

butterfly scaling at every radix-2 stage for user flexibility

•

Built-in capabilities for simple pre-FFT processing – specifically, programmable windowing, basic interference

zeroing-out and basic BPM removal

•

Magnitude (absolute value) and Log-Magnitude computation capability

Flexible data flow and data sample arrangement to support efficient multi-dimensional FFT operations and

transpose accesses as required

•

Chaining and Looping mechanism to sequence a set of accelerator operations one-after-another with minimal

intervention from the main processor

•

CFAR-CA detector support (linear and logarithmic)

Miscellaneous other capabilities of the accelerator

– Stitching two or four 1024-point FFTs to get the equivalent of 2048-point or 4096-point FFT for industrial

level sensing applications where large FFT sizes are required

– Slow DFT mode, with resolution equivalent to 16K size FFT, for FFT peak interpolation (eg. range

interpolation) purpose

– Complex Vector Multiplication and Dot product capability for vectors of size up to 512

9.6 Other Subsystems

9.6.1 ADC Channels (Service) for User Application

The AWR1443 device includes provision for an ADC service for user application, where the

GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1, ADC2,

ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.

•

ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for customer’s

external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST subsystem. This API

could be linked with the user application running on MSS R4F.

•

BIST subsystem firmware will internally schedule these measurements along with other RF and Analog

monitoring operations. The API allows configuring the settling time (number of ADC samples to skip) and

number of consecutive samples to take. At the end of a frame, the minimum, maximum and average of the

readings will be reported for each of the monitored voltages.

GPADC Specifications:

625 Ksps SAR ADC

•

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

•

0 to 1.8V input range

10-bit resolution

For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a switched

capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic capacitance (GPADC

channel 6, the internal buffer is not available).

ANALOG TEST 1-4,

GPADC

ANAMUX

VSENSE

A. GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±7°C.

图 9-6. ADC Path

9.6.1.1 GP-ADC Parameter

PARAMETER

TYP

1.8

UNIT

ADC supply

ADC unbuffered input voltage range

ADC buffered input voltage range⁽¹⁾

ADC resolution

0 – 1.8

0.4 – 1.3

bits

LSB

Ksps

ADC offset error

±5

ADC gain error

±5

ADC DNL

–1/+2.5

±2.5

625

400

ADC INL

ADC sample rate⁽²⁾

ADC sampling time⁽²⁾

ADC internal cap

ADC buffer input capacitance

ADC input leakage current

(1) Outside of given range, the buffer output will become nonlinear.

(2) ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.

9.7 Boot Modes

As soon as device reset is de-asserted, the R4F processor of the Main (Control) system starts executing its

bootloader from an on-chip ROM memory.

The bootloader of the Main system operates in two basic modes and these are specified on the user hardware

(Printed Circuit Board) by configuring what are termed as “Sense on Power” (SOP) pins. These pins on the

device boundary are scanned by the bootloader firmware and choice of mode for bootloader operation is made.

表 9-3 enumerates the relevant SOP combinations and how these map to bootloader operation.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

表 9-3. SOP Combinations

SOP2 (P13)

SOP1 (P11)

SOP0 (J13)

BOOTLOADER MODE AND OPERATION

Functional Mode

Device Bootloader loads user application from QSPI Serial Flash to

internal RAM and switches the control to it

Flashing Mode

Device Bootloader spins in loop to allow flashing of user application

(or device firmware patch – Supplied by TI) to the serial flash

Debug Mode

Bootloader is bypassed and R4F processor is halted. This allows

user to connect emulator at a known point

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.7.1 Flashing Mode

In Flashing Mode, the Main System’s bootloader enables the UART driver and expects a data stream comprising

of User Application (Binary Image) and Device Firmware (referred to as Device Firmware Patch or Service Pack)

from an external flashing utility. 图 9-7 shows the flashing utility executing on a PC platform, but the protocol can

be accomplished on an embedded platform as well.

Serial

FLASH

User Application

And device firmware

Flashing

ROM

UART

FLASHING

UTILITY

Program

RAM

Integrated MCU

ARM Cortex-R4F

Radar

Section

RAM

Data

RAM

图 9-7. Figure 5. Bootloader Flashing Mode

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

9.7.2 Functional Mode

In Functional Mode, the Main System’s bootloader looks for a valid image in the serial flash memory, interfaced

over the QSPI port. If a valid image is found, the bootloader transfers the same to Main System’s memory

subsystem. If the device firmware image is found, it gets transferred to the Radar section’s memory subsystem.

If a valid image (or the QSPI Serial Flash is not found), the bootloader initializes the SPI port and awaits for the

image transfer. This operation comes handy for configurations where the AWR1443 is interfaced to an external

processor which has its own nonvolatile storage hence can store the user application and the AWR1443 device’s

firmware image.

User Application is Loaded

Serial

From FLASH to R4F RAM and

Flash

Device Patch to Radar Section

ROM

UART

Data

RAM

Integrated MCU

ARM Cortex-R4F

Radar

Section

RAM

Histogram

RAM

External

Processor

SPI

User Application is Loaded

From FLASH to R4F RAM and

Device Patch to Radar Section

图 9-8. Bootloader’s Functional Mode

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

10 Applications, Implementation, and Layout

备注

Information in the following Applications section is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI's customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

10.1 Application Information

Key device features driving the following applications are:

•

Integration of Radar Front End and Programmable MCU

On-chip Hardware Accelerator for Radar Data Processing

Flexible boot modes: Autonomous Application boot using a serial flash or external boot over SPI.

10.2 Short-Range Radar

40-MHz

Crystal

Power

Management

Antenna

Structure

RX1

Integrated MCU

AcceARM Cortex-R4F

and

Hardware

Accelerator for

Radar Processing

RX2

RX3

Radar

Front End

External

MCU

RX4

SPI

TX1

TX2

Control

TX3

Detected

Objects

AWR1443

图 10-1. Short-Range Radar

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

10.3 Blind Spot Detector and Ultrasonic Upgrades

40-MHZ

Crystal

Serial

Flash

Power

Management

Antenna

Structure

RX1

RX2

RX3

RX4

Integrated MCU

ARM Cortex-R4F

and

Hardware

Accelerator for

Radar Processing

Radar

Front End

Automotive

Network

CAN

PHY

CAN

TX1

TX2

TX3

AWR1443

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

10.4 Reference Schematic

The reference schematic and power supply information can be found in the AWR1443 EVM Documentation.

Listed for convenience are: Design Files, Schematics, Layouts, and Stack up for PCB.

•

Altium AWR1443 EVM Design Files

AWR1443 EVM Schematic Drawing, Assembly Drawing, and Bill of Materials

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions follow.

11.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for

example, AWR1443). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices and tools (TMDS).

Device development evolutionary flow:

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

Production devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package

type (for example, ABL0161 ALB0161), the temperature range (for example, blank is the default commercial

temperature range). 图 11-1 provides a legend for reading the complete device name for any AWR1443 device.

For orderable part numbers of AWR1443 devices in the ABL0161 package types, see the Package Option

Addendum of this document , the TI website (www.ti.com), or contact your TI sales representative.

For additional description of the device nomenclature markings on the die, see the AWR1443 Device Errata .

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

AWR

ABL

Qualification

Q1 = AEC-Q100

Blank = no special Qual

Prefix

AWR = Production

Tray or Tape & Reel

Generation

1 = 76 œ 81 GHz

R = Big Reel

Blank = Tray

Variant

2 = FE

4 = FE + FFT + MCU

6 = FE + MCU + DSP + 1.5 MB

Package

ABL = BGA

Security

Num RX/TX Channels

G = General

S = Secure

D = Development Secure

RX = 1,2,3,4

TX = 1,2,3

Silicon PG Revision

Blank = Rev 1.0

E = Rev 2.0

Temperature (Tj)

C = 0°C to 70°C

K = œ40°C to 85°C

A = œ40°C to 105°C

I = œ40°C to 125°C

F = Rev 3.0

Features

Blank = Baseline

P = High Performance

Safety

Q = Non-Functional Safety

图 11-1. Device Nomenclature

11.2 Tools and Software

Models

AWR1443 BSDL model

AWR1x43 IBIS model

Boundary scan database of testable input and output pins for IEEE 1149.1 of the

specific device.

IO buffer information model for the IO buffers of the device. For simulation on a

circuit board, see IBIS Open Forum.

AWR1443 checklist for

schematic review, layout

review, bringup/wakeup

A set of steps in spreadsheet form to select system functions and pinmux options.

Specific EVM schematic and layout notes to apply to customer engineering. A

bringup checklist is suggested for customers.

11.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

The current documentation that describes the DSP, related peripherals, and other technical collateral follows.

Errata

AWR1443 device errata Describes known advisories, limitations, and cautions on silicon and provides

workarounds.

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI

的《使用条款》。

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

^®, Arm^®, and Cortex^®are registered trademarks of ARM Limited.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

12 Mechanical, Packaging, and Orderable Information

12.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

PACKAGE OUTLINE

ABL0161B

FCBGA - 1.17 mm max height

SCALE 1.400

PLASTIC BALL GRID ARRAY

10.5

10.3

BALL A1 CORNER

10.5

10.3

1.17 MAX

SEATING PLANE

0.1 C

BALL TYP

0.37

0.27

TYP

9.1 TYP

PKG

(0.65) TYP

PKG

9.1

TYP

0.45

161X

0.35

0.15

0.08

C A B

0.65 TYP

BALL A1 CORNER

9 10 11

12 13 14 15

0.65 TYP

4223365/A 10/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

EXAMPLE BOARD LAYOUT

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

10 11 12 13 14 15

(0.65) TYP

PKG

LAND PATTERN EXAMPLE

SCALE:10X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

( 0.32)

METAL

(

0.32)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223365/A 10/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

English Data Sheet: SWRS202

Submit Document Feedback

Product Folder Links: AWR1443

AWR1443

www.ti.com.cn

ZHCSHS2C – MAY 2017 – REVISED JANUARY 2022

EXAMPLE STENCIL DESIGN

ABL0161B

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

(0.65) TYP

161X ( 0.32)

10 11 12 13 14 15

(0.65) TYP

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4223365/A 10/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

Submit Document Feedback

Product Folder Links: AWR1443

English Data Sheet: SWRS202

PACKAGE OPTION ADDENDUM

www.ti.com

2-Jun-2023

PACKAGING INFORMATION

Orderable Device

AWR1443FQIGABLQ1

AWR1443FQIGABLRQ1

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ACTIVE

FCCSP

ABL

161

176

RoHS & Green

Call TI

Level-3-260C-168 HR

AWR1443

Samples

964FC

ACTIVE

ABL

1000 RoHS & Green

Call TI

-40 to 125

AWR1443

964FC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Jun-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

AWR1443FQIGABLQ1

ABL

FCCSP

161

176

8 x 22

150

315 135.9 7620 13.4

16.8

17.2

Pack Materials-Page 1

GENERIC PACKAGE VIEW

ABL 161

10.4 x 10.4, 0.65 mm pitch

FCBGA - 1.17 mm max height

PLASTIC BALL GRID ARRAY

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225978/A

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

AWR1443FQIGABLRQ1 [TI]

相关型号：

AWR1642

AWR1642ABIGABLQ1

AWR1642ABIGABLRQ1

AWR1642ABISABLQ1

AWR1642ABISABLRQ1

AWR1843

AWR1843ABGABLQ1

AWR1843ABGABLRQ1

AWR1843ABSABLQ1

AWR1843ABSABLRQ1

AWR1843AOP

AWR1843AOP_V01