BQ2004E [TI]
Fast-Charge ICs; 快速充电芯片
| 型号： | BQ2004E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fast-Charge ICs |
| 文件： | 总16页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq2004E/H
Fast-Charge ICs
ture and voltage are within config-
ured limits.
Features
General Description
➤ Fast charge and conditioning of
nickel cadmium or nickel-metal
hydride batteries
The bq2004E and bq2004H Fast
Charge ICs provide comprehensive
fast charge control functions together
with high-speed switching power con-
trol circuitry on a monolithic CMOS
device.
Temperature, voltage, and time are
monitored throughout fast charge.
Fast charge is terminated by any of
the following:
➤ Hysteretic PWM switch-mode
current regulation or gated con-
trol of an external regulator
n
Rate of temperature rise
(∆T/∆t)
Integration of closed-loop current
control circuitry allows the bq2004
to be the basis of a cost-effective so-
lution for stand-alone and system-
integrated chargers for batteries of
one or more cells.
➤ Easily integrated into systems or
n
n
n
n
n
Peak voltage detection (PVD)
Negative delta voltage (-∆V)
Maximum voltage
used as a stand-alone charger
➤ Pre-charge qualification of tem-
perature and voltage
Maximum temperature
Maximum time
➤ Configurable, direct LED outputs
Switch-activated discharge-before-
charge allows bq2004E/H-based charg-
ers to support battery conditioning
and capacity determination.
display battery and charge status
➤ Fast-charge termination by ∆ tem-
perature/∆ time, peak volume de-
tection, -∆V, maximum voltage,
maximum temperature, and maxi-
mum time
After fast charge, optional top-off
and pulsed current maintenance
phases with appropriate display
mode selections are available.
High-efficiency power conversion is
accomplished using the bq2004E/H as
a hysteretic PWM controller for
switch-mode regulation of the charg-
ing current. The bq2004E/H may al-
ternatively be used to gate an exter-
nally regulated charging current.
The bq2004H differs from the
bq2004E only in that fast charge,
hold-off, and top-off time units have
been scaled up by a factor of two,
and the bq2004H provides different
display selections. Timing differ-
ences between the two ICs are illus-
trated in Table 1. Display differ-
ences are shown in Table 2.
➤ Optional top-off charge and
pulsed current maintenance
charging
➤ Logic-level controlled low-power
mode (< 5µA standby current)
Fast charge may begin on application
of the charging supply, replacement
of the battery, or switch depression.
For safety, fast charge is inhibited
unless/until the battery tempera-
Pin Connections
Pin Names
SNS
LED1
LED2
VSS
Sense resistor input
Charge status output 1
Charge status output 2
System ground
DCMD
DSEL
VSEL
Discharge command
Display select
DCMD
DSEL
VSEL
1
2
3
4
5
6
16
15
14
13
12
11
INH
Voltage termination
select
DIS
MOD
TM1
TM2
TCO
TS
Timer mode select 1
Timer mode select 2
Temperature cutoff
Temperature sense
Battery voltage
TM
TM
V
1
CC
SS
VCC
5.0V 10% power
V
2
MOD
DIS
Charge current control
TCO
LED
LED
2
TS
7
8
10
9
Discharge control
output
1
BAT
SNS
INH
Charge inhibit input
BAT
16-Pin Narrow DIP
or Narrow SOIC
PN2004E01.eps
6/99 E
1
bq2004E/H
Charging current sense input
SNS
Pin Descriptions
SNS controls the switching of MOD based on
an external sense resistor in the current
path of the battery. SNS is the reference po-
tential for both the TS and BAT pins. If
SNS is connected to VSS, then MOD switches
high at the beginning of charge and low at
the end of charge.
Discharge-before-charge control input
DCMD
The DCMD input controls the conditions
that enable discharge-before-charge. DCMD
is pulled up internally. A negative-going
pulse on DCMD initiates a discharge to end-
of-discharge voltage (EDV) on the BAT pin,
followed by a new charge cycle start. Tying
DCMD to ground enables automatic
discharge-before-charge on every new charge
cycle start.
Charge status outputs
LED1–
LED2
Push-pull outputs indicating charging
status. See Table 2.
Display select input
DSEL
VSEL
Ground
Vss
VCC
This three-state input configures the charge
status display mode of the LED1 and LED2 out-
puts and can be used to disable top-off and
pulsed-trickle. See Table 2.
VCC supply input
5.0V, 10% power input.
Charge current control output
MOD
Voltage termination select input
MOD is a push-pull output that is used to
control the charging current to the battery.
MOD switches high to enable charging cur-
rent to flow and low to inhibit charging
current flow.
This three-state input controls the voltage-
termination technique used by the
bq2004E/H. When high, PVD is active.
When floating, -∆V is used. When pulled low,
both PVD and -∆V are disabled.
Discharge control output
DIS
Timer mode inputs
TM1–
TM2
Push-pull output used to control an external
transistor to discharge the battery before
charging.
TM1 and TM2 are three-state inputs that
configure the fast charge safety timer, voltage
termination hold-off time, “top-off”, and
trickle charge control. See Table 1.
Charge inhibit input
INH
When low, the bq2004E/H suspends all
charge actions, drives all outputs to high im-
pedance, and assumes a low-power opera-
tional state. When transitioning from low to
high, a new charge cycle is started.
Temperature cut-off threshold input
TCO
Input to set maximum allowable battery
temperature. If the potential between TS
and SNS is less than the voltage at the TCO
input, then fast charge or top-off charge is ter-
minated.
Temperature sense input
TS
Input, referenced to SNS, for an external
thermister monitoring battery temperature.
Battery voltage input
BAT
BAT is the battery voltage sense input, refer-
enced to SNS. This is created by a high-
impedance resistor-divider network con-
nected between the positive and the negative
terminals of the battery.
2
bq2004E/H
Functional Description
Discharge-Before-Charge
Figure 2 shows a block diagram and Figure 3 shows a
state diagram of the bq2004E/H.
The DCMD input is used to command discharge-before-
charge via the DIS output. Once activated, DIS becomes
active (high) until VCELL falls below VEDV, at which time
DIS goes low and a new fast charge cycle begins.
Battery Voltage and Temperature
Measurements
The DCMD input is internally pulled up to VCC (its inac-
tive state). Leaving the input unconnected, therefore,
results in disabling discharge-before-charge. A negative
going pulse on DCMD initiates discharge-before-charge
at any time regardless of the current state of the
bq2004. If DCMD is tied to VSS, discharge-before-charge
will be the first step in all newly started charge cycles.
Battery voltage and temperature are monitored for
maximum allowable values. The voltage presented on
the battery sense input, BAT, should represent a
two-cell potential for the battery under charge.
resistor-divider ratio of:
A
RB1
RB2
N
2
=
- 1
Starting A Charge Cycle
is recommended to maintain the battery voltage within
the valid range, where N is the number of cells, RB1 is
the resistor connected to the positive battery terminal,
and RB2 is the resistor connected to the negative bat-
tery terminal. See Figure 1.
A new charge cycle is started by:
1. Application of VCC power.
2. VCELL falling through the maximum cell voltage,
V
MCV where:
Note: This resistor-divider network input impedance to
end-to-end should be at least 200kΩ and less than 1MΩ.
VMCV = 0.8 ∗ VCC 30mV
3. A transition on the INH input from low to high.
A ground-referenced negative temperature coefficient ther-
mistor placed in proximity to the battery may be used as a
low-cost temperature-to-voltage transducer. The tempera-
ture sense voltage input at TS is developed using a
If DCMD is tied low, a discharge-before-charge will be
executed as the first step of the new charge cycle. Oth-
erwise, pre-charge qualification testing will be the first
step.
resistor-thermistor network between VCC and VSS
. See
Figure 1. Both the BAT and TS inputs are referenced to
SNS, so the signals used inside the IC are:
The battery must be within the configured temperature
and voltage limits before fast charging begins.
V
BAT - VSNS = VCELL
and
The valid battery voltage range is VEDV < VBAT < VMCV
where:
VTS - VSNS = VTEMP
VEDV = 0.4 ∗ VCC 30mV
Negative Temperature
Coefficient Thermister
V
CC
PACK +
RT1
PACK+
PACK-
T
S
RB1
bq2004E/H
N
T
C
bq2004E/H
RT2
BAT
RB2
SNS
PACK -
SNS
Fg2004a.eps
Figure 1. Voltage and Temperature Monitoring
3
bq2004E/H
TM1 TM2
TCO
Timing
Control
TCO
Check
TS
OSC
LED1
LED2
DSEL
LTF
Check
Display
Control
V
- V
TS SNS
A/D
SNS
BAT
V
- V
BAT SNS
DCMD
DVEN
Charge Control
State Machine
EDV
Check
MOD
Control
PWR
Control
MCV
Check
Discharge
Control
DIS
MOD
INH
V
V
CC SS
BD200401.eps
Figure 2. Block Diagram
Fast charge continues until termination by one or more
of the six possible termination conditions:
The valid temperature range is VHTF < VTEMP < VLTF
,
where:
n
n
n
n
n
n
Delta temperature/delta time (∆T/∆t)
Peak voltage detection (PVD)
Negative delta voltage (-∆V)
Maximum voltage
VLTF = 0.4 ∗ VCC 30mV
VHTF = [(1/3 ∗ VLTF) + (2/3 ∗ VTCO)] 30mV
V
TCO is the voltage presented at the TCO input pin, and is
configured by the user with a resistor divider between VCC
and ground. The allowed range is 0.2 to 0.4 ∗ VCC
.
Maximum temperature
Maximum time
If the temperature of the battery is out of range, or the
voltage is too low, the chip enters the charge pending
state and waits for both conditions to fall within their al-
lowed limits. During the charge-pending mode, the IC
first applies a top-off charge to the battery.
PVD and -∆V Termination
The bq2004E/H samples the voltage at the BAT pin once
every 34s. When -∆V termination is selected, if VCELL is
lower than any previously measured value by 12mV
4mV (6mV/cell), fast charge is terminated. When PVD
termination is selected, if VCELL is lower than any previ-
ously measured value by 6mV 2mV (3mV/cell), fast
charge is terminated. The PVD and -∆V tests are valid
The top-off charge, at the rate of 1 8 of the fast charge,
continues until the fast-charge conditions are met or the
top-off time-out period is exceeded. The IC then trickle
charges until the fast-charge conditions are met. There
is no time limit on the charge pending state; the charger
remains in this state as long as the voltage or tempera-
ture conditons are outside of the allowed limits. If the
voltage is too high, the chip goes to the battery absent
state and waits until a new charge cycle is started.
in the range 0.4 ∗ VCC < VCELL < 0.8 ∗ VCC
.
4
bq2004E/H
VSEL Input
Low
Voltage Termination
∆T/∆t Termination
Disabled
-∆V
PVD
The bq2004E/H samples at the voltage at the TS pin
every 34s, and compares it to the value measured two
samples earlier. If VTEMP has fallen 16mV 4mV or
more, fast charge is terminated. The ∆T/∆t termination
Float
High
test is valid only when VTCO < VTEMP < VLTF
.
Voltage Sampling
Temperature Sampling
Each sample is an average of voltage measurements.
The IC takes 32 measurements in PVD mode and 16
measurements in -∆V mode. The resulting sample peri-
ods (9.17ms and 18.18ms, respectively) filter out har-
monics centered around 55Hz and 109Hz. This tech-
nique minimizes the effect of any AC line ripple that
may feed through the power supply from either 50Hz or
60Hz AC sources. Tolerance on all timing is 16%.
Each sample is an average of 16 voltage measurements.
The resulting sample period (18.18ms) filters out har-
monics around 55Hz. This technique minimizes the ef-
fect of any AC line ripple that may feed through the
power supply from either 50Hz or 60Hz AC sources. Tol-
erance on all timing is 16%.
Maximum Voltage, Temperature, and Time
Temperature and Voltage Termination
Hold-off
Anytime VCELL rises above VMCV, the LEDs go off and cur-
rent flow into the battery ceases immediately. If VCELL
A hold-off period occurs at the start of fast charging. then falls back below VMCV before tMCV = 1.5s 0.5s, the
chip transitions to the Charge Complete state (maximum
voltage termination). If VCELL remains above VMCV at the
expiration of tMCV, the bq2004E/H transitions to the Bat-
tery Absent state (battery removal). See Figure 3.
During the hold-off period, -∆V and ∆T/∆t termination
are disabled. The MOD pin is enabled at a duty cycle of
260µs active for every 1820µs inactive. This modulation
results in an average rate 1/8th that of the fast charge
rate. This avoids premature termination on the voltage
spikes sometimes produced by older batteries when
fast-charge current is first applied. Maximum voltage
and maximum temperature terminations are not af-
fected by the hold-off period.
Maximum temperature termination occurs anytime
VTEMP falls below the temperature cutoff threshold
V
TCO. Charge will also be terminated if VTEMP rises
above the low temperature fault threshold, VLTF, after
fast charge begins.
Table 1. Fast Charge Safety Time/Hold-Off/Top-Off Table
Typical
Fast-Charge
Safety
Typical
Corresponding
Fast-Charge
Rate
PVD, -∆V
Hold-Off
Time (s)
Pulse-
Trickle
Top-Off
Rate
Pulse-
Trickle
Rate
Time (min)
Period (Hz)
2004E 2004H
2004E 2004H 2004E 2004H 2004E 2004H
2004E 2004H
TM1 TM2
Low Low
C/4
C/2
1C
2C
4C
C/2
1C
2C
4C
C/8
C/4
C/2
1C
325
154
77
650
325
154
77
137
546
273
137
68
273
546
546
273
137
546
546
273
137
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
C/512
C/512
C/512
C/512
C/512
C/512
C/512
C/512
Disabled
Float Low
High Low
Low Float
Float Float
High Float
Low High
Float High
High High
15
7.5
30
15
39
3.75
1.88
15
7.5
3.75
30
2C
19
39
C/4
C/2
1C
154
77
325
154
77
546
273
137
68
C/16
C/32
C/16
C/18
C/4
C/8
C/4
C/2
7.5
15
39
3.75
1.88
7.5
3.75
2C
19
39
Note: Typical conditions = 25°C, VCC = 5.0V.
5
bq2004E/H
Table 2. bq2004E/H LED Output Summary
Mode 1
bq2004E
Charge Action State
LED1
Low
LED2
Low
Battery absent
Fast charge pending or a discharge-before-charge in progress
Fast charging
High
Low
High
High
Low
DSEL = VSS
Fast charge complete, top-off, and/or trickle
High
Mode 1
bq2004H
Charge Action State
Battery absent
LED1
Low
LED2
Low
Discharge-before-charge in progress
High
High
1
8 second high
DSEL = VSS
Fast charge pending
Low
1
8 second low
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
Mode 2
bq2004E
Charge Action State (See note)
Battery absent
LED1
Low
LED2
Low
Fast charge pending or discharge-before-charge in progress
Fast charging
High
Low
High
High
Low
DSEL = Floating
Fast charge complete, top-off, and/or trickle
High
Mode 2
bq2004H
Charge Action State (See note)
Battery absent
LED1
Low
LED2
Low
Discharge-before-charge in progress
High
High
1
8 second high
DSEL = Floating Fast charge pending
Fast charging
Low
1
8 second low
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
Mode 3
bq2004E/H
Charge Action State
LED1
LED2
Low
Battery absent
Low
1
8 second high
Fast charge pending or discharge-before-charge in progress
Low
1
8 second low
DSEL = VCC
Fast charging
Low
High
Fast charge complete, top-off, and/or trickle
High
Low
Note:
Pulse trickle is inhibited in Mode 2.
6
bq2004E/H
Maximum charge time is configured using the TM pin.
Time settings are available for corresponding charge
rates of C/4, C/2, 1C, and 2C. Maximum time-out termi-
nation is enforced on the fast-charge phase, then reset,
and enforced again on the top-off phase, if selected.
There is no time limit on the trickle-charge phase.
Charge Current Control
The bq2004E/H controls charge current through the MOD
output pin. The current control circuitry is designed to sup-
port implementation of a constant-current switching regulator
or to gate an externally regulated current source.
When used in switch mode configuration, the nominal
regulated current is:
Top-off Charge
An optional top-off charge phase may be selected to
follow fast charge termination for the C/2 through 4C
rates. This phase may be necessary on NiMH or other
battery chemistries that have a tendency to terminate
charge prior to reaching full capacity. With top-off en-
abled, charging continues at a reduced rate after
fast-charge termination for a period of time equal to
0.235∗ the fast-charge safety time (See Table 1.) Dur-
ing top-off, the MOD pin is enabled at a duty cycle of
260µs active for every 1820µs inactive. This modula-
tion results in an average rate 1/8th that of the fast
charge rate. Maximum voltage, time, and temperature
are the only termination methods enabled during top-
off.
I
REG = 0.225V/RSNS
Charge current is monitored at the SNS input by the
voltage drop across a sense resistor, RSNS, between the
low side of the battery pack and ground. RSNS is sized to
provide the desired fast charge current.
If the voltage at the SNS pin is less than VSNSLO, the
MOD output is switched high to pass charge current to
the battery.
When the SNS voltage is greater than VSNSHI, the MOD
output is switched low—shutting off charging current to
the battery.
VSNSLO = 0.04 ∗ VCC 25mV
VSNSHI = 0.05 ∗ VCC 25mV
Pulse-Trickle Charge
Pulse-trickle charging may be configured to follow the
fast charge and optional top-off charge phases to com-
pensate for self-discharge of the battery while it is idle
in the charger.
When used to gate an externally regulated current
source, the SNS pin is connected to VSS, and no sense re-
sisitor is required.
In the pulse-trickle mode, MOD is active for 260µs of a
period specified by the settings of TM1 and TM2. See
Table 1. The resulting trickle-charge rate is C/512.
Both pulse trickle and top-off may be disabled by tying
TM1 and TM2 to VSS or by selecting Mode 2 in the dis-
play.
Charge Status Indication
Charge status is indicated by the LED1 and LED2 out-
puts. The state of these outputs in the various charge cy-
cle phases is given in Table 2 and illustrated in Figure 3.
In all cases, if VCELL exceeds the voltage at the MCV
pin, both LED1 and LED2 outputs are held low regard-
less of other conditions. Both can be used to directly
drive an LED.
7
bq2004E/H
New Charge Cycle Started by
Any One of:
Falling Edge
on DCMD
V
Rising to Valid Level
CC
Yes
V
Battery Replacement
DCMD Tied to Ground?
No
(V
Falling through V
)
CELL
MCV
Inhibit (INH) Released
< V
Discharge-
Before-Charge
CELL
EDV
V
< V
< V
CELL MCV
EDV
Battery Voltage?
Charge
Pending
V
< V
V
> V
CELL
EDV
CELL
MCV
V
> V
CELL
MCV
V
V
> V
or
LTF
TEMP
< V
HTF
TEMP
V
>
CELL
Top-Off and
Pulse-Trickle
Charge
V
MCV
Battery Temperature?
V
< V
< V
TEMP LTF
HTF
Battery
Absent
V
< V
< V
EDV
CELL
MCV
and
V
< V
TEMP
< V
HTF
LTF
t > tMCV
Pulse
Trickle
Charge
Pulse
Trickle
Charge
Fast
Charge
V
V
MCV
>
CELL
-
V or
V
V
<
CELL
MCV
T/ t or
V
or
<
V
TCO
Charge
TEMP
Complete
V
V
V
V
>
>
CELL
MCV
CELL
MCV
Maximum Time Out
Pulse
Trickle
Charge
Top-Off
Selected?
Top-Off
Charge
Yes
V
< V
TCO
TEMP
No
or 0.235 Maximum
Time Out
SD2004EH.eps
Figure 3. Charge Algorithm State Diagram
8
bq2004E/H
Absolute Maximum Ratings
Symbol
VCC
Parameter
VCC relative to VSS
Minimum
Maximum
Unit
Notes
-0.3
+7.0
V
DC voltage applied on any pin ex-
cluding VCC relative to VSS
VT
-0.3
+7.0
V
TOPR
Operating ambient temperature
Storage temperature
-20
-55
-
+70
+125
+260
+85
°C
°C
°C
°C
Commercial
TSTG
TSOLDER
TBIAS
Soldering temperature
10 sec max.
Temperature under bias
-40
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Thresholds (T = T
; V 10%)
OPR CC
A
Symbol
Parameter
Rating
Tolerance
Unit
Notes
High threshold at SNS result-
ing in MOD = Low
0.05 VCC
*
VSNSHI
V
0.025
Low threshold at SNS result-
ing in MOD = High
VSNSLO
VLTF
0.04 * VCC
V
V
0.010
0.030
0.030
0.030
0.030
4
VTEMP ≥ VLTF inhib-
its/terminates charge
0.4 VCC
*
Low-temperature fault
High-temperature fault
End-of-discharge voltage
Maximum cell voltage
VTEMP ≤ VHTF inhibits
charge
VCELL < VEDV inhibits
fast charge
VCELL > VMCV inhibits/
terminates charge
(1/3 VLTF) + (2/3 VTCO
)
VHTF
VEDV
VMCV
VTHERM
-∆V
V
*
*
0.4 VCC
*
V
0.8 VCC
*
V
TS input change for∆T/∆t
detection
V
CC = 5V, TA = 25°C
CC = 5V, TA = 25°C
-16
-12
-6
mV
mV
mV
BAT input change for -∆V
detection
BAT input change for PVD
detection
V
4
VCC = 5V, TA = 25°C
PVD
2
9
bq2004E/H
Recommended DC Operating Conditions (T = T
A
OPR)
Symbol
VCC
Condition
Supply voltage
Minimum
Typical Maximum
Unit
V
Notes
4.5
0
5.0
5.5
VBAT
VCELL
VTS
Battery input
-
-
-
-
-
-
-
-
-
VCC
VCC
VCC
VCC
V
BAT voltage potential
Thermistor input
TS voltage potential
Temperature cutoff
Logic input high
Logic input high
Logic input low
0
V
VBAT - VSNS
0
V
VTEMP
VTCO
0
V
VTS - VSNS
0.2 VCC
*
0.4 VCC
*
V
Valid ∆T/∆t range
DCMD, INH
2.0
-
V
VIH
VCC - 0.3
-
V
TM1, TM2, DSEL, VSEL
DCMD, INH
-
-
0.8
0.3
V
VIL
Logic input low
V
TM1, TM2, DSEL, VSEL
DIS, MOD, LED1, LED2,
VOH
VCC - 0.8
Logic output high
Logic output low
-
-
-
V
V
IOH ≤ -10mA
DIS, MOD, LED1, LED2,
IOL ≤ 10mA
VOL
-
0.8
ICC
ISB
IOH
IOL
Supply current
-
-
1
-
3
1
mA Outputs unloaded
µA
INH = VIL
Standby current
DIS, LED1, LED2, MOD source
DIS, LED1, LED2, MOD sink
Input leakage
-10
10
-
-
-
mA @VOH = VCC - 0.8V
mA @VOL = VSS + 0.8V
-
-
-
1
µA
µA
INH, BAT, V = VSS to VCC
IL
Input leakage
50
-
400
DCMD, V = VSS to VCC
TM1, TM2, DSEL, VSEL,
V = VSS to VSS + 0.3V
µA
µA
IIL
Logic input low source
Logic input high source
-
-
-
70
-
TM1, TM2, DSEL, VSEL,
V = VCC - 0.3V to VCC
IIH
-70
TM1, TM2, DSEL, and VSEL
should be left disconnected
(floating) for Z logic input state
µA
IIZ
Tri-state
-2
-
2
Note:
All voltages relative to VSS except as noted.
10
bq2004E/H
Impedance
Symbol
Parameter
Minimum
Typical
Maximum
Unit
MΩ
MΩ
MΩ
MΩ
RBAT
RTS
Battery input impedance
TS input impedance
50
50
50
50
-
-
-
-
-
-
-
-
RTCO
RSNS
TCO input impedance
SNS input impedance
Timing (T = 0 to +70°C; V
10%)
CC
A
Symbol
Parameter
Minimum Typical Maximum
Unit
Notes
Pulse width for DCMD
and INH pulse command
Pulse start for charge or discharge
before charge
µs
tPW
dFCV
fREG
1
-16
-
-
-
-
-
Time base variation
16
%
VCC = 4.75V to 5.25V
MOD output regulation
frequency
300
kHz
Maximum voltage termi-
nation time limit
Time limit to distinguish battery re-
moved from charge complete.
tMCV
1
-
2
s
Note:
Typical is at TA = 25°C, VCC = 5.0V.
11
bq2004E/H
16-Pin DIP Narrow (PN)
(
)
16-Pin PN 0.300" DIP
Inches
Millimeters
Min.
Dimension
Min.
Max.
0.180
0.040
0.022
0.065
0.013
0.770
0.325
0.280
0.370
0.110
0.150
0.040
Max.
4.57
1.02
0.56
1.65
0.33
19.56
8.26
7.11
9.40
2.79
3.81
1.02
A
A1
B
0.160
0.015
0.015
0.055
0.008
0.740
0.300
0.230
0.300
0.090
0.115
0.020
4.06
0.38
0.38
1.40
0.20
18.80
7.62
5.84
7.62
2.29
2.92
0.51
B1
C
D
E
E1
e
G
L
S
12
bq2004E/H
16-Pin SOIC Narrow (SN)
(
)
16-Pin SN 0.150" SOIC
Inches
Millimeters
Dimension
Min.
Max.
Min.
1.52
0.10
0.33
0.18
9.78
3.81
1.14
5.72
0.38
Max.
1.78
0.25
0.51
0.25
10.16
4.06
1.40
6.22
0.89
D
B
e
A
A1
B
0.060
0.004
0.013
0.007
0.385
0.150
0.045
0.225
0.015
0.070
0.010
0.020
0.010
0.400
0.160
0.055
0.245
0.035
E
C
D
E
H
e
A
C
H
L
A1
.004
L
13
bq2004E/H
Data Sheet Revision History
Change No.
Page No.
Description
Nature of Change
Clarification
1
All
Combined bq2004E and bq2004H, revised and
expanded format of this data sheet
2
7
5
Separated bq2004E and bq2004H in Table 2, LED
Output Summary
Clarification
Clarification
3
4
Description of charge-pending state
Note:
Change 1 = Oct. 1997 B changes from Sept. 1996 (bq2004E), Feb. 1997 (bq2004H).
Change 2 = Feb. 1998 C changes from Oct. 1997 B.
Change 3 = Dec. 1998 D changes from Feb. 1998 C.
Change 4 = June 1999 E changes from Dec. 1998 D.
14
bq2004E/H
Ordering Information
bq2004
Package Option:
PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC
Device:
E = bq2004E Fast-Charge IC
H= bq2004H Fast-Charge IC
15
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
BQ2004ESNG4
Switch-mode NiCd/NiMH Battery Charger w/Negative dV, Peak Voltage Detection, dT/dt Termination 16-SOIC -20 to 70
TI
BQ2004ESNTR
NiCd/NiMH buck charger w/negative dV, PVD, dT/dt termination and timing setup2 16-SOIC -20 to 70
TI
BQ2004HSNG4
Switch-mode NiCd/NiMH Battery Charger w/Negative dV, Peak Voltage Detection, dT/dt Termination 16-SOIC -20 to 70
TI
BQ2004HSNTR
NiCd/NiMH buck charger w/negative dV, PVD, dT/dt termination and timing setup3 16-SOIC -20 to 70
TI
BQ2004HSNTRG4
Switch-mode NiCd/NiMH Battery Charger w/Negative dV, Peak Voltage Detection, dT/dt Termination 16-SOIC -20 to 70
TI
©2020 ICPDF网 联系我们和版权申明