BQ2011SN中文资料_数据手册_规格书

bq2011

Gas Gauge IC for

High Discharge Rates

Nominal available charge may be di-

Features

➤ Conservative and repeatable

measurement of available charge

in rechargeable batteries

General Description

rectly indicated using a five-seg-

ment LED display. These segments

are used to indicate graphically the

nominal available charge.

The bq2011 Gas Gauge IC is intended

for battery-pack installation to main-

tain an accurate record of available

battery charge. The IC monitors a

voltage drop across a sense resistor

connected in series between the nega-

tive battery terminal and ground to

determine charge and discharge ac-

tivity of the battery. The bq2011 is

designed for systems such as power

tools with very high discharge rates.

➤ Designed for portable equipment

such as power tools with high dis-

charge rates

The bq2011 supports a simple single-

line bidirectional serial link to an exter-

nal processor (common ground). The

bq2011 outputs battery information in

response to external commands over the

serial link. To support subassembly

testing, the outputs may also be con-

trolled by command. The external proc-

essor may also overwrite some of the

bq2011 gas gauge data registers.

➤ Designed for battery pack inte-

gration

- ¹²⁰µA typical standby current

(self-discharge estimation mode)

Battery self-discharge is estimated

based on an internal timer and tem-

perature sensor. Compensations for

battery temperature and rate of

charge or discharge are applied to

the charge, discharge, and

selfdischarge calculations to provide

available charge information across

a wide range of operating conditions.

Initial battery capacity is set using

the PFC and MODE pins. Actual

battery capacity is automatically

“learned” in the course of a dis-

charge cycle from full to empty and

may be displayed depending on the

display mode.

- ^{Small size enables imple-}

1

The bq2011 may operate directly

from four cells. With the REF output

and an external transistor, a simple,

inexpensive regulator can be built to

provide V_CCfrom a greater number

of cells.

mentations in as little as

square inch of PCB

2

➤ Direct drive of LEDs for capacity

display

➤ Self-discharge compensation us-

ing internal temperature sensor

Internal registers include available

charge, temperature, capacity, battery

ID, and battery status.

➤ Simple single-wire serial commu-

nications port for subassembly

testing

➤ 16-pin narrow SOIC

Pin Connections

Pin Names

MODE

SEG₁

SEG₂

SEG₃

SEG₄

SEG₅

PFC

Display mode output

LED segment 1

LED segment 2

LED segment 3

LED segment 4

LED segment 5

NC

DQ

No connect

MODE

1

2

3

4

5

6

16

15

14

13

12

11

V

CC

Serial communications

input/output

SEG

REF

NC

DQ

RBI

SB

1

2

3

4

5

RBI

SB

Register backup input

Battery sense input

Display control input

Sense resistor input

3.0–6.5V

DISP

SR

Programmed full count

selection input

PFC

7

8

10

9

DISP

SR

V_CC

V_SS

V

SS

REF

Voltage reference output

Negative battery terminal

16-Pin Narrow SOIC

PN201101.eps

2/96 E

1

bq2011

Display control input

DISP

Pin Descriptions

DISP floating allows the LED display to

be active during charge and discharge if

V_SRO< -1mV (charge) or V_SRO> 2mV (dis-

charge). Transitioning DISP low activates

the display for 4 0.5 seconds.

Display mode output

MODE

When left floating, this output selects rela-

tive mode for capacity display. If connected

to the anode of the LEDs to source current,

absolute mode is selected for capacity dis-

play. See Table 1.

Secondary battery input

SB

This input monitors the single-cell voltage

potential through a high-impedance resis-

tive divider network for the end-of-discharge

voltage (EDV) threshold and maximum cell

voltage (MCV).

LED display segment outputs

SEG₁–

SEG₅

Each output may activate an LED to sink

the current sourced from MODE, the bat-

tery, or V_CC

.

Register backup input

RBI

Programmed full count selection input

PFC

SR

This input is used to provide backup potential

to the bq2011 registers during periods when

V_CC≤ 3V. A storage capacitor should be con-

nected to RBI.

This three-level input pin defines the pro-

grammed full count (PFC) thresholds and

scale selections described in Table 1. The

state of the PFC pin is only read immediate-

ly after a reset condition.

Serial I/O pin

DQ

Sense resistor input

This is an open-drain bidirectional pin.

Voltage reference output for regulator

The voltage drop (V_SR) across the sense re-

sistor R_Sis monitored and integrated over

time to interpret charge and discharge activ-

ity. The SR input is tied to the low side of

the sense resistor. V_SR> V_SSindicates dis-

charge, and V_SR< V_SSindicates charge. The

effective voltage drop, V_SRO, as seen by the

bq2011 is V_SR+ V_OS(see Table 3).

REF

REF provides a voltage reference output for

an optional micro-regulator.

Supply voltage input

Ground

V_CC

V_SS

No connect

NC

2

bq2011

Figure 1 shows a typical battery pack application of the

bq2011 using the LED display with absolute mode as a

charge-state indicator. The bq2011 can be configured to

display capacity in either a relative or an absolute dis-

play mode. The relative display mode uses the last

measured discharge capacity of the battery as the bat-

tery “full” reference. The absolute display mode uses the

programmed full count (PFC) as the full reference, forc-

ing each segment of the display to represent a fixed

amount of charge. A push-button display feature is

available for momentarily enabling the LED display.

Functional Description

General Operation

The bq2011 determines battery capacity by monitoring

the amount of charge input to or removed from a re-

chargeable battery. The bq2011 measures discharge and

charge currents, estimates self-discharge, monitors the

battery for low-battery voltage thresholds, and compen-

sates for temperature and charge/discharge rates. The

charge measurement is made by monitoring the voltage

across a small-value series sense resistor between the

negative battery terminal and ground. The available

battery charge is determined by monitoring this voltage

over time and correcting the measurement for the envi-

ronmental and operating conditions.

The bq2011 monitors the charge and discharge currents

as a voltage across a sense resistor (see R_Sin Figure 1).

A filter between the negative battery terminal and the

SR pin may be required if the rate of change of the bat-

tery current is too great.

R

1

bq2011

Q1

Gas Gauge IC

ZVNL110A

REF

C1

0.1 F

RB

1

V

MODE

CC

V

CC

SEG

PFC

SB

1

2

3

4

5

2

DISP

V

SS

R

S

SR

RBI

DQ

Charger

Load

Indicates optional.

Directly connect to V

CC

across 4 cells (4.8V nominal and should not

exceed 6.5V) with a resistor and a Zener diode to limit voltage during charge.

Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells.

Programming resistors and ESD-protection diodes are not shown.

R-C on SR may be required, (application-specific), where the maximum

R should not exceed 20K.

FG201101.eps

Figure 1. Battery Pack Application Diagram—LED Display,

Absolute Mode

3

bq2011

charge display translation. The temperature range is

available over the serial port in 10°C increments as

shown below:

Register Backup

The bq2011 RBI input pin is intended to be used with a

storage capacitor to provide backup potential to the inter-

nal bq2011 registers when V_CCmomentarily drops below

3.0V. V_CCis output on RBI when V_CCis above 3.0V.

TMPGG (hex)

Temperature Range

< -30°C

0x

1x

2x

3x

4x

5x

6x

7x

8x

9x

Ax

Bx

Cx

After V_CCrises above 3.0V, the bq2011 checks the inter-

nal registers for data loss or corruption. If data has

changed, then the NAC and FULCNT registers are

cleared, and the LMD register is loaded with the initial

PFC.

-30°C to -20°C

-20°C to -10°C

-10°C to 0°C

0°C to 10°C

10°C to 20°C

20°C to 30°C

30°C to 40°C

40°C to 50°C

50°C to 60°C

60°C to 70°C

70°C to 80°C

> 80°C

Voltage Thresholds

In conjunction with monitoring V_SRfor charge/discharge

currents, the bq2011 monitors the single-cell battery po-

tential through the SB pin. The single-cell voltage po-

tential is determined through a resistor-divider network

per the following equation:

RB₁

RB₂

= N − 1

where N is the number of cells, RB₁is connected to the

positive battery terminal, and RB₂is connected to the

negative battery terminal. The single-cell battery volt-

age is monitored for the end-of-discharge voltage (EDV)

and for maximum cell voltage (MCV). The EDV thresh-

old level is used to determine when the battery has

reached an “empty” state, and the MCV threshold is used

for fault detection during charging. The EDV and MCV

thresholds for the bq2011 are fixed at:

V

_EDV= 0.90V

Layout Considerations

V

_MCV= 2.00V

The bq2011 measures the voltage differential between

the SR and V_SSpins. V_OS(the offset voltage at the SR

pin) is greatly affected by PC board layout. For optimal

results, the PC board layout should follow the strict rule

of a single-point ground return. Sharing high-current

ground with small signal ground causes undesirable

noise on the small signal nodes. Additionally:

During discharge and charge, the bq2011 monitors V_SR

for various thresholds, V_SR1–V_SR4. These thresholds are

used to compensate the charge and discharge rates. Ref-

er to the discharge compensation section for details.

EDV monitoring is disabled if V_SR> V_SR1(50mV typical)

and resumes 1 second after V_SRdrops back below V_SR1

.

Reset

n

The capacitors (SB and V_CC) should be placed as close

as possible to the SB and V_CCpins, respectively, and

their paths to V_SSshould be as short as possible. A

high-quality ceramic capacitor of 0.1µf is recommended

The bq2011 recognizes a valid battery whenever V_SBis

greater than 0.1V typical. V_SBrising from below 0.25V

resets the device. Reset can also be accomplished with a

command over the serial port as described in the Reset

Register section.

for V_CC

.

n

The sense resistor (R_S) should be as close as possible

to the bq2011.

Temperature

The R-C on the SR pin should be located as close as

possible to the SR pin. The maximum R should not

exceed 20K.

The bq2011 internally determines the temperature in

10°C steps centered from -35°C to +85°C. The tempera-

ture steps are used to adapt charge and discharge rate

compensations, self-discharge counting, and available

4

bq2011

1. Last Measured Discharge (LMD) or

learned battery capacity:

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates

the operation of the bq2011. The bq2011 accumulates a

measure of charge and discharge currents, as well as an

estimation of self-discharge. Charge and discharge cur-

rents are temperature and rate compensated, whereas

self-discharge is only temperature compensated.

LMD is the last measured discharge capacity of the

battery. On initialization (application of V_CCor bat-

tery replacement), LMD = PFC. During subsequent

discharges, the LMD is updated with the latest

measured capacity in the Discharge Count Register

(DCR) representing a discharge from full to below

EDV. A qualified discharge is necessary for a ca-

pacity transfer from the DCR to the LMD register.

The LMD also serves as the 100% reference thresh-

old used by the relative display mode.

The main counter, Nominal Available Charge (NAC),

represents the available battery capacity at any given

time. Battery charging increments the NAC register,

while battery discharging and self-discharge decrement

the NAC register and increment the DCR (Discharge

Count Register).

2. Programmed Full Count (PFC) or initial

battery capacity:

The Discharge Count Register (DCR) is used to update

the Last Measured Discharge (LMD) register only if a

complete battery discharge from full to empty occurs

without any partial battery charges. Therefore, the

bq2011 adapts its capacity determination based on the

actual conditions of discharge.

The initial LMD and gas gauge rate values are pro-

grammed by using PFC. The PFC also provides the

100% reference for the absolute display mode. The

bq2011 is configured for a given application by se-

lecting a PFC value from Table 1. The correct PFC

may be determined by multiplying the rated bat-

tery capacity in mAh by the sense resistor value:

The battery's initial capacity is equal to the Pro-

grammed Full Count (PFC) shown in Table 1. Until

LMD is updated, NAC counts up to but not beyond this

threshold during subsequent charges. This approach al-

lows the gas gauge to be charger-independent and com-

patible with any type of charge regime.

Battery capacity (mAh) sense resistor (Ω) =

*

PFC (mVh)

Selecting a PFC slightly less than the rated capac-

ity for absolute mode provides capacity above the

full reference for much of the battery's life.

Charge

Inputs

Discharge

Current

Self-Discharge

Timer

Current

Rate and

Temperature

Compensation

Rate and

Temperature

Compensation

Temperature

Compensation

+

-

Nominal

Available

Charge

(NAC)

Last

Measured

Discharged Qualified Register

(LMD) (DCR)

Transfer

Discharge

Count

+

<

Main Counters

and Capacity

Reference (LMD)

Temperature Step,

Other Data

Temperature

Translation

Chip-Controlled

Available Charge

LED Display

Serial

Port

Outputs

FG201104.eps

Figure 2. Operational Overview

5

bq2011

Select:

Example: Selecting a PFC Value

PFC = 34304 counts or 6.5mVh

Given:

PFC = Z (float)

Sense resistor = 0.005Ω

Number of cells = 6

MODE = not connected

The initial full battery capacity is 6.5mVh

(1300mAh) until the bq2011 “learns” a new capac-

ity with a qualified discharge from full to EDV.

Capacity = 1300mAh, NiCd cells

Current range = 1A to 80A

Relative display mode

Voltage drop over⁶s⁴ense resistor = 5mV to 400mV

C

Self-discharge =

Therefore:

1300mAh 0.005Ω = 6.5mVh

*

Table 1. bq2011 Programmed Full Count mVh Selections

Programmed

Full Count (PFC)

PFC

mVh

Scale

MODE Pin

Display Mode

1

H

27648

34304

44800

42240

31744

23808

10.5

2640

1

Z

L

H

Z

6.5

8.5

8.0

6.0

4.5

Floating

Relative

5280

1

5280

1

5280

1

Connected to LEDs

Absolute

5280

1

L

5280

6

bq2011

3. Nominal Available Charge (NAC):

Discharge Counting

NAC counts up during charge to a maximum value

of LMD and down during discharge and self dis-

charge to 0. NAC is reset to 0 on initialization and

on the first valid charge following discharge to EDV.

To prevent overstatement of charge during periods

of overcharge, NAC stops incrementing when NAC

= LMD.

All discharge counts where V_SRO> 500µV cause the

NAC register to decrement and the DCR to increment.

Exceeding the fast discharge threshold (FDQ) if the rate

is equivalent to V_SRO> 2mV activates the display, if en-

abled. The display becomes inactive after V_SROfalls be-

low 2mV.

Self-Discharge Estimation

Note: NAC is set to the value in LMD when SEG₅

is pulled low during a reset.

The bq2011 continuously decrements NAC and incre-

ments DCR for self-discharge based on time and tempera-

4. Discharge Count Register (DCR):

ture. The self-discharge count rate is programmed to be a

1

The DCR counts up during discharge independent

of NAC and could continue increasing after NAC

has decremented to 0. Prior to NAC = 0 (empty

battery), both discharge and self-discharge incre-

ment the DCR. After NAC = 0, only discharge in-

crements the DCR. The DCR resets to 0 when NAC

= LMD. The DCR does not roll over but stops

counting when it reaches FFFFh.

nominal

NAC rate per day. This is the rate for a bat-

80

*

tery whose temperature is between 20°–30°C. The NAC

register cannot be decremented below 0.

Count Compensations

The bq2011 determines fast charge when the NAC up-

dates at a rate of ≥2 counts/sec. Charge and discharge

activity is compensated for temperature and charge/dis-

charge rate before updating the NAC and/or DCR. Self-

discharge estimation is compensated for temperature

before updating the NAC or DCR.

The DCR value becomes the new LMD value on the

first charge after a valid discharge to V_EDVif:

n

No valid charge initiations (charges greater than

256 NAC counts; or 0.006 – 0.01C) occurred dur-

ing the period between NAC = LMD and EDV

detected.

Charge Compensation

Two charge efficiency factors are used for trickle charge

and fast charge. Fast charge is defined as a rate of

charge resulting in ≥ 2 NAC counts/sec (≥ 0.15C to 0.32C

depending on PFC selections; see Table 2). The compen-

sation defaults to the fast charge factor until the actual

charge rate is determined.

n

The self-discharge count is not more than 4096

counts (8% to 18% of PFC, specific percentage

threshold determined by PFC).

The temperature is ≥ 0°C when the EDV level is

reached during discharge.

Temperature adapts the charge rate compensation fac-

tors over three ranges between nominal, warm, and hot

temperatures. The compensation factors are shown below.

The valid discharge flag (VDQ) indicates whether

the present discharge is valid for LMD update.

Charge Counting

Charge

Trickle Charge

Compensation

Fast Charge

Charge activity is detected based on a negative voltage

on the V_SRinput. If charge activity is detected, the

bq2011 increments NAC at a rate proportional to V_SRO

(V_SR+ V_OS) and, if enabled, activates an LED display

if V_SRO< -1mV. Charge actions increment the NAC af-

ter compensation for charge rate and temperature.

Temperature

Compensation

<40°C

0.80

0.75

0.95

0.90

≥ 40°C

The bq2011 determines a valid charge activity sustained

at a continuous rate equivalent to V_SRO< -400µV.

A

valid charge equates to a sustained charge activity

greater than 256 NAC counts. Once a valid charge is de-

tected, charge counting continues until V_SROrises

above -400µV.

7

bq2011

Discharge Compensation

Table 2. Self-Discharge Compensation

Corrections for the rate of discharge are made by adjust-

ing an internal discharge compensation factor. The dis-

charge factor is based on the dynamically measured V_SR

The compensation factors during discharge are:

Temperature

Range

Self-Discharge Compensation

.

Typical Rate/Day

NAC

320

< 10°C

10–20°C

20–30°C

30–40°C

40–50°C

50–60°C

60–70°C

> 70°C

Discharge

Compensation

Factor

NAC

160

Approximate

_SRThreshold

V

Efficiency

100%

95%

NAC

80

V

_SR< 50 mV

1.00

1.05

1.15

1.25

NAC

40

V

_SR1> 50 mV

NAC

20

V

_SR2> 100 mV

V_SR3> 150 mV

_SR4> 253 mV

85%

NAC

10

75%

NAC

5

V

75%

NAC

2.5

Temperature compensation during discharge also takes place.

At lower temperatures, the compensation factor increases by

0.05 for each 10°C temperature step below 10°C.

Error Summary

Comp. factor = 1.00 + (0.05 N)

*

Capacity Inaccurate

Where N = number of 10°C steps below 10°C and

The LMD is susceptible to error on initialization or if no up-

dates occur. On initialization, the LMD value includes the

error between the programmed full capacity and the actual

capacity. This error is present until a valid discharge oc-

curs and LMD is updated (see the DCR description on page

7). The other cause of LMD error is battery wear-out. As

the battery ages, the measured capacity must be adjusted

to account for changes in actual battery capacity.

V

_SR< 50mV.

For example:

T > 10°C: Nominal compensation, N = 0

0°C < T < 10°C: N = 1 (i.e., 1.00 becomes 1.05)

-10°C < T < 0°C: N = 2 (i.e., 1.00 becomes 1.10)

-20°C < T < -10°C: N = 3 (i.e., 1.00 becomes 1.15)

-20°C < T < -30°C: N = 4 (i.e., 1.00 becomes 1.20)

A Capacity Inaccurate counter (CPI) is maintained and

incremented each time a valid charge occurs and is reset

whenever LMD is updated from the DCR. The counter

does not wrap around but stops counting at 255. The ca-

pacity inaccurate flag (CI) is set if LMD has not been

updated following 64 valid charges.

Self-Discharge Compensation

The self-discharge compensation is programmed for a

nominal rate of ¹

NAC per day. This is the rate for a

*

Current-Sensing Error

battery within th⁸e⁰20–30°C temperature range (TMPGG

= 6x). This rate varies across 8 ranges from <10°C to

>70°C, doubling with each higher temperature step

(10°C). See Table 2

Table 3 illustrates the current-sensing error as a func-

tion of V_SR. A digital filter eliminates charge and

discharge counts to the NAC register when V_SRO(V_SR

_OS) is between -400µV and 500µV.

+

V

Table 3. bq2011 Current-Sensing Errors

Symbol

INL

Parameter

Typical

Maximum

Units

Notes

Integrated non-linearity

error

Add 0.1% per °C above or below 25°C

and 1% per volt above or below 4.25V.

2

4

%

Integrated non-

repeatability error

Measurement repeatability given

similar operating conditions.

INR

1

2

%

8

bq2011

logic-low state for a period, t_STRH,B. The next section is the

actual data transmission, where the data should be valid by

a period, t_DSU, after the negative edge used to start commu-

nication. The data should be held for a period, t_DV, to allow

the host or bq2011 to sample the data bit.

Communicating with the bq2011

The bq2011 includes a simple single-pin (DQ plus re-

turn) serial data interface. A host processor uses the in-

terface to access various bq2011 registers. Battery char-

acteristics may be easily monitored by adding a single

contact to the battery pack. The open-drain DQ pin on

the bq2011 should be pulled up by the host system, or may

be left floating if the serial interface is not used.

The final section is used to stop the transmission by return-

ing the DQ pin to a logic-high state by at least a period,

t

_SSU, after the negative edge used to start communication.

The final logic-high state should be held until a period, t_SV

to allow time to ensure that the bit transmission was

,

The interface uses a command-based protocol, where the

host processor sends a command byte to the bq2011. stopped properly. The timings for data and break commu-

The command directs the bq2011 to either store the next

eight bits of data received to a register specified by the

command byte or output the eight bits of data specified

by the command byte.

nication are given in the serial communication timing

specification and illustration sections.

Communication with the bq2011 is always performed

with the least-significant bit being transmitted first.

Figure 3 shows an example of a communication se-

quence to read the bq2011 NAC register.

The communication protocol is asynchronous return-to-

one. Command and data bytes consist of a stream of eight

bits that have a maximum transmission rate of 333

bits/sec. The least-significant bit of a command or data

byte is transmitted first. The protocol is simple enough

that it can be implemented by most host processors using

either polled or interrupt processing. Data input from the

bq2011 may be sampled using the pulse-width capture

timers available on some microcontrollers.

bq2011 Registers

The bq2011 command and status registers are listed in

Table 4 and described below.

Command Register (CMDR)

Communication is normally initiated by the host proces-

The write-only CMDR register is accessed when eight

valid command bits have been received by the bq2011.

The CMDR register contains two fields:

sor sending a BREAK command to the bq2011.

A

BREAK is detected when the DQ pin is driven to a

logic-low state for a time, t_Bor greater. The DQ pin

should then be returned to its normal ready-high logic

state for a time, t_BR. The bq2011 is now ready to receive

a command from the host processor.

n

W/R bit

n

Command address

The W/R bit of the command register is used to select

whether the received command is for a read or a write

function.

The return-to-one data bit frame consists of three distinct

sections. The first section is used to start the transmission

by either the host or the bq2011 taking the DQ pin to a

Written by Host to bq2011

CMDR = 03h

Received by Host to bq2011

NAC = 65h

LSB

MSB

LSB

MSB

Break 1 1 0 0 0 0 0 0

1 0 1 0 0 1 1 0

DQ

TD201101.eps

Figure 3. Typical Communication with the bq2011

9

bq2011

Table 4. bq2011 Command and Status Registers

Control Field

Loc. Read/

Register

Name

Symbol

(hex) Write

7(MSB)

6

5

4

3

2

1

0(LSB)

Command

register

CMDR

00h

01h

Write

Read

W/R

AD6

AD5

AD4

AD3

AD2

AD1

EDV

AD0

n/u

Primary

FLGS1 status flags

register

CHGS

BRP

MCV

CI

VDQ

GG3

n/u

Temperature

TMPGG and gas gauge 02h

register

Read

TMP3 TMP2

TMP1

TMP0

GG2

GG1

GG0

Nominal

available

charge high

byte register

NACH

NACL

03h

17h

R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

Nominal

available

charge low

byte register

Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

Battery

BATID identification 04h

register

Last meas-

ured dis-

charge regis-

ter

LMD

05h

R/W

LMD7 LMD6

LMD5

DR1

LMD4 LMD3 LMD2 LMD1 LMD0

Secondary

FLGS2 status flags

register

06h

09h

Read

CR

DR2

DR0

n/u

OVLD

Capacity

CPI

inaccurate

Read

CPI7

1

CPI6

OC5

CPI5

OC4

CPI4

OC3

CPI3

OC2

CPI2

OC1

CPI1

n/u

CPI0

OCE

count register

Output con-

trol register

OCTL

0ah

0bh

Write

Full count

register

FULCNT

Read

FUL7

RST

FUL6

0

FUL5

0

FUL4

0

FUL3

0

FUL2

0

FUL1

0

FUL0

0

RST

Reset register 39h

n/u = not used

Write

Note:

10

bq2011

The W/R values are:

The BRP values are:

CMDR Bits

FLGS1 Bits

7

6

-

5

4

3

2

1

0

7

6

5

4

3

2

1

0

W/R

-

BRP

-

Where W/R is:

Where BRP is:

0

The bq2011 outputs the requested register

contents specified by the address portion of

CMDR.

0

bq2011 is charged until NAC = LMD or dis-

charged until the EDV flag is asserted

1

SB rising from below 0.1V, or a serial port

initiated reset has occurred

1

The following eight bits should be written

to the register specified by the address por-

tion of CMDR.

The maximum cell voltage flag (MCV) is asserted

whenever the potential on the SB pin (relative to V_SS) is

above 2.0V. The MCV flag is asserted until the condi-

tion causing MCV is removed.

The lower seven-bit field of CMDR contains the address

portion of the register to be accessed. Attempts to write

to invalid addresses are ignored.

The MCV values are:

CMDR Bits

FLGS1 Bits

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

AD0

(LSB)

-

AD6 AD5 AD4 AD3 AD2 AD1

-

MCV

-

Where MCV is:

Primary Status Flags Register (FLGS1)

0

1

V

_SB< 2.0V

_SB> 2.0V

The read-only FLGS1 register (address=01h) contains

the primary bq2011 flags.

V

The capacity inaccurate flag (CI) is used to warn the

user that the battery has been charged a substantial

number of times since LMD has been updated. The CI

flag is asserted on the 64th charge after the last LMD

update or when the bq2011 is reset. The flag is cleared

after an LMD update.

The charge status flag (CHGS) is asserted when a

valid charge rate is detected. Charge rate is deemed

valid when V_SRO< -400µV. A V_SROof greater than-

400µV or discharge activity clears CHGS.

The CHGS values are:

FLGS1 Bits

The CI values are:

7

6

-

5

4

3

2

1

0

FLGS1 Bits

CHGS

-

7

6

5

4

3

2

1

0

-

CI

-

Where CHGS is:

0

Either discharge activity detected or V_SRO>

-400µV

Where CI is:

0

When LMD is updated with a valid full dis-

charge or the bq2011 is reset

1

V_SRO< -400µV

The battery replaced flag (BRP) is asserted whenever

the potential on the SB pin (relative to V_SS), V_SB, rises

above 0.1V and determines the internal registers have

been corrupted. The BRP flag is also set when the

bq2011 is reset (see the RST register description). BRP

is latched until either the bq2011 is charged until NAC

= LMD or discharged until EDV is reached. BRP = 1

signifies that the device has been reset.

1

After the 64th valid charge action with no

LMD updates

11

bq2011

The valid discharge flag (VDQ) is asserted when the

bq2011 is discharged from NAC=LMD. The flag remains

set until either LMD is updated or one of three actions

that can clear VDQ occurs:

TMPGG Temperature Bits

7

6

5

4

3

2

1

0

TMP3 TMP2 TMP1 TMP0

-

n

The self-discharge count register (SDCR) has

exceeded the maximum acceptable value (4096

counts) for an LMD update.

The bq2011 contains an internal temperature sensor.

The temperature is used to set charge and discharge ef-

ficiency factors as well as to adjust the self-discharge co-

efficient. The temperature register contents may be

translated as shown below.

n

A valid charge action equal to 256 NAC counts with

V

_SRO< -400µV.

The EDV flag was set at a temperature below 0°C

The VDQ values are:

n

TMP3

TMP2

TMP1

TMP0

Temperature

T < -30°C

FLGS1 Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

7

6

5

4

3

2

1

0

-30°C < T < -20°C

-20°C < T < -10°C

-10°C < T < 0°C

0°C < T < 10°C

10°C < T < 20°C

20°C < T < 30°C

30°C < T < 40°C

40°C < T < 50°C

50°C < T < 60°C

60°C < T < 70°C

70°C < T < 80°C

T > 80°C

-

VDQ

-

Where VDQ is:

0

SDCR ≥ 4096, subsequent valid charge ac-

tion detected, or EDV is asserted with the

temperature less than 0°C

1

On first discharge after NAC = LMD

The end-of-discharge warning flag (EDV) warns the

user that the battery is empty. SEG1 blinks at a 4Hz

rate. EDV detection is disabled if V_SR> V_SR1. The EDV

flag is latched until a valid charge has been detected.

The EDV values are:

FLGS1 Bits

7

6

5

4

3

2

1

0

-

EDV

-

Where EDV is:

The bq2011 calculates the available charge as a function

of NAC, temperature, and a full reference, either LMD

or PFC. The results of the calculation are available via

the display port or the gas gauge field of the TMPGG

register. The register is used to give available capacity

0

Valid charge action detected and V_SB

0.90V

≥

1

V

_SB< 0.90V providing that V_SR< V_SR1

Temperature and Gas Gauge Register

(TMPGG)

in ¹₁₆increments from 0 to¹⁵

.

16

TMPGG Gas Gauge Bits

The read-only TMPGG register (address=02h) contains

two data fields. The first field contains the battery tem-

perature. The second field contains the available charge

from the battery.

7

6

5

4

3

2

1

0

-

GG3 GG2

GG1 GG0

12

bq2011

The gas gauge display and the gas gauge portion of the

TMPGG register are adjusted for cold temperature de-

pendencies. A piece-wise correction is performed as fol-

lows:

The CR values are:

FLGS2 Bits

7

6

5

4

3

2

1

0

CR

-

Temperature

> 0°C

Available Capacity Calculation

NAC / “Full Reference”

Where CR is:

-20°C < T < 0°C

< -20°C

0.75 NAC / “Full Reference”

*

0

1

When charge rate falls below 2 counts/sec

When charge rate is above 2 counts/sec

0.5 NAC / “Full Reference”

*

The fast charge regime efficiency factors are used when

CR = 1. When CR = 0, the trickle charge efficiency fac-

tors are used. The time to change CR varies due to the

user-selectable count rates.

The adjustment between > 0°C and -20°C < T < 0°C has a

4°C hysteresis.

Nominal Available Charge Register (NAC)

The discharge rate flags, DR2–0, are bits 6–4.

The read/write NACH register (address=03h) and the

read-only NACL register (address=17h) are the main

gas gauging registers for the bq2011. The NAC registers

are incremented during charge actions and decremented

during discharge and self-discharge actions. The correc-

tion factors for charge/discharge efficiency are applied

automatically to NAC.

FLGS2 Bits

7

6

5

4

3

2

1

0

-

DR2

DR1

DR0

-

They are used to determine the present discharge re-

gime as follows:

On reset, the NACH and NACL registers are cleared to

zero. NACL stops counting when NACH reaches zero.

When the bq2011 detects a valid charge, NACL resets to

zero; writing to the NAC register affects the available

charge counts and, therefore, affects the bq2011 gas

gauge operation.

DR2

DR1

DR0

V_SR(V)

0

V

_SR< 50mV

50mV < V_SR< 100mV

(overload, OVLD=1)

0

1

Battery Identification Register (BATID)

0

1

0

1

0

100mV < V_SR< 150mV

150mV < V_SR< 253mV

The read/write BATID register (address=04h) is avail-

able for use by the system to determine the type of bat-

tery pack. The BATID contents are retained as long as

V_CCis greater than 2V. The contents of BATID have no

effect on the operation of the bq2011. There is no de-

fault setting for this register.

V_SRD> 253mV

The overload flag (OVLD) is asserted when a discharge

overload is detected, V_SRD> 50mV. OVLD remains as-

serted as long as the condition persists and is cleared

when V_SRD< 50mV.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the

bq2011 uses as a measured full reference. The bq2011

adjusts LMD based on the measured discharge capacity

of the battery from full to empty. In this way the bq2011

updates the capacity of the battery. LMD is set to PFC

during a bq2011 reset.

FLGS2 Bits

7

6

5

4

3

2

1

0

-

OVLD

DR2–0 and OVLD are set based on the measurement of the

voltage at the SR pin relative to V_SS. The rate at which

this measurement is made varies with device activity.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains

the secondary bq2011 flags.

The charge rate flag (CR) is used to denote the fast

charge regime. Fast charge is assumed whenever a

charge action is initiated. The CR flag remains asserted

if the charge rate does not fall below 2 counts/sec.

13

bq2011

Resetting the bq2011 sets the following:

Full Count Register (FULCNT)

n

LMD = PFC

The read-only FULCNT register (address=0bh) provides

the system with a diagnostic of the number of times the

battery has been fully charged (NAC = LMD). The

number of full occurrences can be determined by multiply-

ing the value in the FULCNT register by 16. Any dis-

charge action other than self-discharge allows detection of

another full occurrence during the next valid charge ac-

tion.

n

CPI, VDQ, NAC, and OCE = 0 or

NAC = LMD when SEG5 = L

n

CI and BRP = 1

Display

The bq2011 can directly display capacity information

using low-power LEDs. If LEDs are used, the segment

pins should be tied to V_CC, the battery, or the MODE pin

for programming the bq2011.

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in-

dicate the number of times a battery has been charged

without an LMD update. Because the capacity of a re-

chargeable battery varies with age and operating condi-

tions, the bq2011 adapts to the changing capacity over

time. A complete discharge from full (NAC=LMD) to

empty (EDV=1) is required to perform an LMD update

assuming there have been no intervening valid charges,

the temperature is greater than or equal to 0°C, and the

self-discharge counter is less than 4096 counts.

The bq2011 displays the battery charge state in either

absolute or relative mode. In relative mode, the battery

charge is represented as a percentage of the LMD. Each

LED segment represents 20% of the LMD.

In absolute mode, each segment represents a fixed

amount of charge, based on the initial PFC. In absolute

mode, each segment represents 20% of the PFC. As the

battery wears out over time, it is possible for the LMD

to be below the initial PFC. In this case, all of the LEDs

may not turn on, representing the reduction in the ac-

tual battery capacity.

The CPI register is incremented every time a valid

charge is detected. The register increments to 255 with-

out rolling over. When the contents of CPI are incre-

mented to 64, the capacity inaccurate flag, CI, is as-

serted in the FLGS1 register. CPI is reset whenever an

update of the LMD register is performed, and the CI flag

is also cleared.

The capacity display is also adjusted for the present bat-

tery temperature. The temperature adjustment reflects

the available capacity at a given temperature but does

not affect the NAC register. The temperature adjust-

ments are detailed in the TMPGG register description.

Output Control Register (OCTL)

When DISP is tied to V_CC, the SEG_1–5outputs are inac-

tive. When DISP is left floating, the display becomes ac-

tive during charge if the NAC registers are counting at a

rate equivalent to V_SRO< -1mV or fast discharge if the

NAC registers are counting at a rate equivalent to V_SRO

> 2mV. When pulled low, the segment output becomes

active for 4 seconds, 0.5 seconds.

The write-only OCTL register (address=0ah) provides

the system with a means to check the display connec-

tions for the bq2011. The segment drivers may be over-

written by data from OCTL when the least-significant

bit of OCTL, OCE, is set. The data in bits OC_5–1of the

OCTL register (see Table 4 on page 10 for details) is out-

put onto the segment pins, SEG_5–1, respectively if

OCE=1. Whenever OCE is written to 1, the MSB of

OCTL should be set to a 1. The OCE register location

must be cleared to return the bq2011 to normal opera-

tion. OCE may be cleared by either writing the bit to a

logic zero via the serial port or by resetting the bq2011

as explained below. Note: Whenever the OCTL register is

written, the MSB of OCTL should be written to a logic one.

The segment outputs are modulated as two banks, with

segments 1, 3, and 5 alternating with segments 2 and 4.

The segment outputs are modulated at approximately

320Hz, with each bank active for 30% of the period.

SEG₁blinks at a 4Hz rate whenever V_SBhas been de-

tected to be below V_EDVto indicate a low-battery condi-

tion or NAC is less than 10% of the LMD or PFC, de-

pending on the display mode.

Reset Register (RST)

The reset register (address=39h) provides the means to

perform a software-controlled reset of the device. A full

device reset may be accomplished by first writing LMD

(address = 05h) to 00h and then writing the RST regis-

ter contents from 00h to 80h. Setting any bit other than

the most-significant bit of the RST register is not al-

lowed, and results in improper operation of the bq2011.

Microregulator

The bq2011 can operate directly from 4 cells. To facilitate

the power supply requirements of the bq2011, an REF out-

put is provided to regulate an external low-threshold n-

FET. A micropower source for the bq2011 can be inexpen-

sively built using the FET and an external resistor.

14

bq2011

Absolute Maximum Ratings

Symbol

V_CC

Parameter

Relative to V_SS

Minimum

-0.3

Maximum

+7.0

Unit

V

Notes

All other pins

-0.3

+7.0

V

Minimum 100Ω series resistor

should be used to protect SR in case

of a shorted battery (see the bq2011

application note for details).

V_SR

Relative to V_SS

-0.3

0

+7.0

+70

V

°C

Commercial

T_OPR

Operating temperature

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-

sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T = T

; V = 3.0 to 6.5V)

OPR

A

Symbol

V_EDV

V_SR1

Parameter

Minimum

Typical

Maximum

0.93

75

Unit

V

Notes

End-of-discharge warning

0.87

20

0.90

50

SB

Discharge compensation threshold

Valid charge

mV

µV

V

SR (see note)

V_SR+ V_OS

SB

V_SR2

70

100

150

253

-

125

V_SR3

120

220

-

175

V_SR4

275

V_SRQ

V_SRD

V_MCV

V_BR

-400

-

Valid discharge

500

1.95

-

Maximum single-cell voltage

Battery removed/replaced

2.0

0.1

2.05

0.25

V

SB

Note:

For proper operation of the threshold detection circuit, V_CCmust be at least 1.5V greater than the volt-

age being measured.

15

bq2011

DC Electrical Characteristics (T = T

)

A

OPR

Symbol

V_CC

Parameter

Supply voltage

Minimum Typical Maximum

Unit

Notes

V_CCexcursion from < 2.0V to ≥

3.0V initializes the unit.

3.0

4.25

6.5

V

V_OS

Offset referred to V_SR

Reference at 25°C

DISP = V_CC

I_REF= 5µA

-

5.7

4.5

2.0

-

50

150

6.3

7.5

-

µV

V

6.0

V_REF

R_REF

Reference at -40°C to +85°C

Reference input impedance

-

V

5.0

MΩ V_REF= 3V

µA V_CC= 3.0V, DQ = 0

µA V_CC= 4.25V, DQ = 0

µA V_CC= 6.5V, DQ = 0

V

90

135

180

250

V_CC

-

I_CC

Normal operation

-

120

-

170

V_SB

Battery input

0

-

R_SBmax

I_DISP

I_MODE

I_RBI

SB input impedance

DISP input leakage

MODE input leakage

RBI data-retention current

Internal pulldown

10

-

MΩ 0 < V_SB< V_CC

µA V_DISP= V_SS

µA DISP = V_CC

nA V_RBI> V_CC< 3V

KΩ

5

-0.2

-

0.2

100

-

R_DQ

500

V_SR> V_SS= discharge;

V_SR

Sense resistor input

-0.3

-

2.0

V

_SR< V_SS= charge

R_SR

SR input impedance

PFC logic input high

PFC logic input low

PFC logic input Z

10

-

MΩ -200mV < V_SR< V_CC

V_IHPFC

V_ILPFC

V_IZPFC

I_IHPFC

I_ILPFC

V_CC- 0.2

-

V

PFC

-

V_SS+ 0.2

float

-

float

PFC input high current

PFC input low current

-

1.2

-

µA V_PFC= V_CC/2

V_CC= 3V, I_OLS≤ 1.75mA

V_OLSL

SEG_Xoutput low, low V_CC

SEG_Xoutput low, high V_CC

-

0.1

0.4

-

V

SEG₁–SEG₅

V_CC= 6.5V, I_OLS≤ 11.0mA

SEG₁–SEG₅

V_OLSH

V_OHML

V_OHMH

MODE output high, low V_CC

MODE output high, high V_CC

V_CC- 0.3

-

V

V_CC= 3V, I_OHMODE= -5.25mA

V_CC= 6.5V, I_OHMODE= -33.0mA

V_CC- 0.6

-

I_OHMODEMODE source current

-33

11.0

5.0

-

mA At V_OHMODE= V_CC- 0.6V

mA At V_OLSH= 0.4V, V_CC= 6.5V

mA At V_OL= V_SS+ 0.3V, DQ

I_OLS

SEG_Xsink current

-

I_OL

Open-drain sink current

Open-drain output low

DQ input high

-

V_OL

-

0.5

-

V

I_OL≤ 5mA, DQ

V_IHDQ

V_ILDQ

R_FLOAT

2.5

-

DQ

DQ input low

-

0.8

-

Float state external impedance

-

5

MΩ PFC

Note:

All voltages relative to V_SS.

16

bq2011

Serial Communication Timing Specification (T = T

)

A

OPR

Symbol

t_CYCH

t_CYCB

t_STRH

t_STRB

t_DSU

t_DH

Parameter

Cycle time, host to bq2011

Cycle time, bq2011 to host

Start hold, host to bq2011

Start hold, bq2011 to host

Data setup

Minimum

Typical

Maximum

Unit

ms

ns

Notes

See note

3

-

6

5

-

500

-

µs

750

µs

Data hold

750

1.50

-

µs

t_DV

Data valid

-

ms

µs

t_SSU

t_SH

Stop setup

2.25

Stop hold

700

2.95

3

-

t_SV

Stop valid

ms

t_B

Break

t_BR

Break recovery

1

Note:

The open-drain DQ pin should be pulled to at least V_CCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

Serial Communication Timing Illustration

DQ

(R/W "1")

t

STRH

DQ

t

STRB

(R/W "0")

t

DH

DSU

t

DV

t

SH

SSU

DQ

t

SV

(BREAK)

t

BR

CYCH, CYCB, B

17

bq2011

16-Pin SOIC Narrow (SN)

(

)

16-Pin SN SOIC Narrow

Dimension

Minimum

0.060

0.004

0.013

0.007

0.385

0.150

0.045

0.225

0.015

Maximum

0.070

0.010

0.020

0.010

0.400

0.160

0.055

0.245

0.035

A

A1

B

D

B

e

C

D

E

e

H

L

H

All dimensions are in inches.

A

C

A1

.004

L

18

bq2011

Data Sheet Revision History

Change No. Page No.

Description

Self-discharge count rate

Nature of Change

* NAC rate per day

1

3

7

Was:

Is:

64

80

* NAC rate per day

Compensation factor 30–40°C Was:

Is:

0.90

0.95

Compensation factor >40°C

Was:

Is:

0.80

0.90

4

7

8

Charge compensation

Changed compensation factor variation with temperature

Self-discharge compensation

Changed self-discharge compensation rate variation with

temperature

Notes:

Changes 1 and 2 = See the 1995 Data Book.

Change 3 = Jan. 1996 D changes from July 1994 C.

Change 4 = Feb. 1996 E changes from Jan. 1996 D.

Ordering Information

bq2011

Temperature Range:

blank = Commercial (0 to +70°C)

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2011 Gas Gauge IC

19

PACKAGE OPTION ADDENDUM

www.ti.com

8-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SOIC

Drawing

BQ2011SN-D118

BQ2011SN-D118G4

BQ2011SN-D118TR

ACTIVE

PREVIEW

ACTIVE

D

16

48

None

CU NIPDAU Level-1-220C-UNLIM

Call TI Call TI

CU NIPDAU Level-1-220C-UNLIM

2500

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	0.150 INCH, SOIC-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G16	长度：	9.9 mm
信道数量：	1	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3/6.5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Power Management Circuits	最大供电电流 (Isup)：	0.25 mA
最大供电电压 (Vsup)：	6.5 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	4.25 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	Base Number Matches：	1

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