Communicating with the bq2011
The bq2011 includes a simple single-pin (DQ plus re-
turn) serial data interface. A host processor uses the in-
terface to access various bq2011 registers. Battery char-
acteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2011 should be pulled up by the host system, or may
be left floating if the serial interface is not used.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2011.
The command directs the bq2011 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.
The communication protocol is asynchronous return-to-
one. Command and data bytes consist of a stream of eight
bits that have a maximum transmission rate of 333
bits/sec. The least-significant bit of a command or data
byte is transmitted first. The protocol is simple enough
that it can be implemented by most host processors using
either polled or interrupt processing. Data input from the
bq2011 may be sampled using the pulse-width capture
timers available on some microcontrollers.
Communication is normally initiated by the host proces-
sor sending a BREAK command to the bq2011. A
BREAK is detected when the DQ pin is driven to a
logic-low state for a time, t
or greater. The DQ pin
should then be returned to its normal ready-high logic
state for a time, t
. The bq2011 is now ready to receive
a command from the host processor.
The return-to-one data bit frame consists of three distinct
sections. The first section is used to start the transmission
by either the host or the bq2011 taking the DQ pin to a
logic-low state for a period, t
. The next section is the
actual data transmission, where the data should be valid by
a period, t
, after the negative edge used to start commu-
nication. The data should be held for a period, t
, to allow
the host or bq2011 to sample the data bit.
The final section is used to stop the transmission by return-
ing the DQ pin to a logic-high state by at least a period,
, after the negative edge used to start communication.
The final logic-high state should be held until a period, t
to allow time to ensure that the bit transmission was
stopped properly. The timings for data and break commu-
nication are given in the serial communication timing
specification and illustration sections.
Communication with the bq2011 is always performed
with the least-significant bit being transmitted first.
Figure 3 shows an example of a communication se-
quence to read the bq2011 NAC register.
The bq2011 command and status registers are listed in
Table 4 and described below.
Command Register (CMDR)
The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2011.
The CMDR register contains two fields:
The W/R bit of the command register is used to select
whether the received command is for a read or a write
Written by Host to bq2011
CMDR = 03h
Received by Host to bq2011
NAC = 65h
Break 1 1 0 0 0 0 0 0
1 0 1 0 011 0
Figure 3. Typical Communication with the bq2011
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