BQ2052SN-A515_技术文档

Preliminary bq2052

Gas Gauge IC

for Lithium Primary Cells

communications link to an external

Features

General Description

micro-controller. The link allows

the micro-controller to read and

write the internal registers of the

bq2052. The internal registers in-

clude available battery capacity,

voltage, temperature, current, and

battery status. The controller may

also overwrite some of the bq2052

gas gauge data registers.

➤ Accurate measurement of avail-

able capacity in Lithium primary

batteries such as Lithium Sul-

phur Dioxide and Lithium Man-

ganese Dioxide

The bq2052 Lithium Primary Gas

Gauge IC is intended for bat-

tery-pack or in-system installation

to maintain an accurate record of

available battery capacity. The IC

monitors a voltage drop across a

sense resistor connected in series

with the cells to determine dis-

charge activity of the battery. The

bq2052 applies compensations for

battery temperature and discharge

rate to the available charge counter

to provide available capacity infor-

mation across a wide range of oper-

ating conditions.

➤ Provides a low-cost battery moni-

tor solution for pack integration

- ^{Complete circuit can fit less}

than 1 square inch of PCB

space

The bq2052 can operate from the

batteries in the pack. The REF out-

put and an external FET provide a

simple, inexpensive voltage regula-

tor to supply power to the circuit

from the cells.

- ^{Low operating current}

- ^{Less than 100nA of data}

retention current

➤ Single-wire communication inter-

face (HDQ bus) for critical battery

parameters

Compensated available capacity

may be directly indicated using an

LED display. The LED display is

programmable and can be config-

ured as two, four, or five segments.

These segments are used to depict

available battery capacity. The

bq2052 supports a single-wire serial

➤ Communicates remaining capac-

ity with direct drive of LEDs in 3

selectable modes

➤ Measurements automatically

compensated for discharge rate

and temperature

➤ 16-pin narrow SOIC

Pin Connections

Pin Names

LCOM

LED common output

V_SS

System ground

SEG₁/PROG₁LED segment 1/

program 1 input

LCOM

SEG /PROG

1

2

3

4

5

6

16

15

14

13

12

11

V

CC

SR

Sense resistor input

Display control input

Battery sense input

Register backup input

REF

CP

1

DISP

SB

SEG₁/PROG₂LED segment 2/

program 2 input

SEG /PROG

2

SEG /PROG

HDQ

RBI

SB

3

SEG₁/PROG₃LED segment 3/

program 3 input

RBI

HDQ

SEG /PROG

4

Serial communications

input/output

SEG /PROG

5

SEG₁/PROG₄LED segment 4/

program 4 input

PROG

6

7

8

10

9

DISP

SR

PROG₆

REF

Program 6 input

V

SS

SEG₁/PROG₅LED segment 5/

program 5 input

Voltage reference output

Supply voltage

16-Pin Narrow SOIC

CP

Control port

V_CC

PN2052H1.eps

SLUS019–MAY 1999

1

bq2052 Preliminary

Sense resistor input

SR

Pin Descriptions

The voltage drop (V ) across the sense resis-

SR

tor R is monitored and integrated over time

LED common output

LCOM

S

to interpret discharge activity. V

> V in-

SS

SR

dicates discharge. The effective voltage drop,

, as seen by the bq2052 is V + V

This open-drain output switches V

to

CC

source current for the LEDs. The switch is

off during initialization to allow reading of

the soft pull-up or pull-down program resis-

tors. LCOM is also high impedance when the

display is off.

V

SRO

.

OS

SR

Display control input

DISP

DISP high disables the LED display. DISP

tied to V (no display LEDs in the circuit)

CC

LED display segment outputs (dual func-

tion with PROG –PROG )

SEG –

1

SEG

5

allows PROG to connect directly to V

or

CC

X

1

5

V

instead of through a pull-up or

SS

pull-down resistor. DISP low activates the

display.

Each output may activate an LED to sink

the current sourced from LCOM.

Secondary battery input

SB

Programmed full count selections

PROG –

1

PROG

2

This input monitors the battery cell voltage

potential through a high-impedance resis-

tive divider network for the end-of-discharge

voltage (EDV) thresholds.

These three-level input pins define the pro-

grammed full count.

Power gauge scale selection inputs (dual

PROG

3

function with SEG –SEG )

3

4

Register backup input

RBI

This three-level input pin defines the scale

factor.

This pin is used to provide backup potential to

the bq2052 registers during periods when V

CC

≤ 3V. A storage capacitor or a battery can be

Programmed compensation factors

PROG

4

5

6

connected to RBI.

This three-level input pin defines the bat-

tery discharge compensation factors.

Serial communication input/output

HDQ

CP

This is the open-drain bidirectional commu-

nications port.

Programmed display mode

This three-level input pin defines the capac-

ity indication display mode.

Control port

This open drain output may be controlled by

serial port commands and its state is re-

flected in the CPIN bit in FLGS1.

Programmed initial capacity state

This input defines the initial battery capac-

ity indication state. When tied to V , the

CC

Voltage reference output for regulator

REF

bq2052 sets the available capacity to full on

reset. When tied to V , the bq2052 sets the

SS

REF provides a voltage reference output for

an optional micro-regulator.

available capacity to zero on reset.

Ground

V

SS

Supply voltage input

V

CC

2

Preliminary bq2052

Measurements

Functional Description

The bq2052 uses a voltage-to-frequency converter (VFC)

for discharge measurement and an analog-to-digital con-

verter (ADC) for battery voltage measurement.

General Operation

The bq2052 determines battery capacity by monitoring

the amount of charge removed from a primary battery.

The bq2052 measures discharge currents and battery

voltage, monitors the battery for the low battery-voltage

thresholds, and compensates available capacity for tem-

perature and discharge rate. The bq2052 measures ca-

pacity by monitoring the voltage across a small-value se-

ries sense resistor between the negative battery termi-

nal and ground.

Discharge Counting

The VFC measures the discharge flow of the battery by

monitoring a small value sense resistor between the SR

pin and V

as shown in Figure 1. The bq2052 detects

SS

“discharge” activity when the potential at the SR input,

, is positive. The bq2052 integrates the signal over

V

SRO

time using an internal counter. The fundamental rate of

the counter is 3.125µVh. The VFC measures signals up

to 0.5V in magnitude.

Figure 1 shows a typical battery pack application of the

bq2052 using the LED display capability as a

charge-state indicator. The bq2052 displays capacity

with two, four, or five LEDs using the programmed full

count (PFC) as the battery’s “full” reference. The bq2052

has a push-button input for momentarily enabling the

LED display.

Digital Magnitude Filter

The bq2052 has a digital filter to eliminate discharge

counting below a set threshold. The minimum discharge

threshold, V

, for the bq2052 is 250µV.

SRD

R

1

bq2052

Gas Gauge IC

Q1

ZVNL110A

REF

C

1

RB

1

V

LCOM

CC

SEG

SB

1

2

3

4

5

2

DISP

V

SS

R

S

100K

0.1µF

SR

H or L

PROG6

CP

RBI

To µC

HDQ

Notes:

Load

1.

Indicates optional.

2. V_CCcan connect directly to two lithium primary cells

(6.0V nominal and should not exceed 6.5V).

Otherwise, R1, C1, and Q1 are needed for regulation of > 2 cells.

3. Programming resistors and ESD-protection diodes are not shown.

4. R-C on SR is required.

5. A series diode is required on RBI if the bottom series cell is used as the backup source.

If the cell is used, the backup capacitor is not required, and the anode is connected to the

positive terminal of the cell.

FG205201.eps

Figure 1. Application Diagram—5-Segment LED Display

3

bq2052 Preliminary

Table 1. bq2052 Current-Sensing Errors

Symbol

Parameter

Typical

Maximum

Units

Notes

Integrated non-linearity

error

Add 0.1% per °C above or below 25°C

and 1% per volt above or below 4.25V.

INL

2

4

%

Integrated non-

repeatability error

Measurement repeatability given

similar operating conditions.

INR

1

2

%

Voltage Monitoring and Thresholds

Temperature

In conjunction with monitoring the SR input for dis-

charge currents, the bq2052 monitors the battery poten-

The bq2052 has an internal temperature sensor to mea-

sure temperature. The bq2052 determines the tempera-

ture and stores it in the TEMP register (address = 02h).

The bq2052 uses temperature to adapt remaining capac-

ity for the battery’s discharge efficiency.

tial through the SB pin. The voltage at the SB pin, V

,

SB

is developed through a high impedance resistor network

connect across the battery. The bq2052 monitors the

voltage at the SB pin and reports the voltage in the VSB

register (address = 0bh).

Gas Gauge Operation

The bq2052 compares the V

reading to two

SB

end-of-discharge voltage (EDV) thresholds. The EDV

threshold levels are used to determine when the battery

has reached an “empty” state. The EDV thresholds for

the bq2052 are programmable with the default values

fixed at:

General

The operational overview diagram in Figure 2 illus-

trates the operation of the bq2052. The bq2052 accumu-

lates a measure of discharge currents and calculates

available capacity. The bq2052 compensates available

capacity for discharge rate and temperature and pro-

vides the information in the Compensated Available Ca-

pacity (CAC) registers (address = 0eh–0fh). The main

counter, Discharge Count Register (DCR) (address =

2eh), represents the cumulative amount of charge re-

moved from the battery. Battery discharging increments

the DCR register.

EDV1 (first) = 0.76V

EDVF (final) = EDV1 - 0.10V = 0.66V

If V

is below either of the two EDV thresholds for 8

SB

consecutive samples over a 4 second period, the bq2052

sets the associated flag in the FLGS1 register (address =

01h). Once set, the EDV flags remain set, independent

of V

.

SB

Discharge

Current

Rate and

Temperature

Inputs

Efficiency

Factor

Full Nominal

Available Charge

(FNAC)

+

–

Discharge

Count

Register

(DCR)

Compensated

Available

Capacity

(CAC)

Complete

Data Set

Main Counters

Chip-Controlled

Available Charge

LED Display

Serial Port

Outputs

FG2052.eps

Figure 2. Operational Overview

4

Preliminary bq2052

Table 2. bq2052 Programmed Full Count mVh

PROG

Programmed

Full Count

(PFC)

PROG

x

3

1

2

H

Z

L

Units

SCALE =

1/40

SCALE =

1/80

SCALE =

1/160

mVh/

count

-

H

Z

H

Z

48128

46080

43264

39936

38400

36096

31744

28928

26112

1203

1152

1082

998

602

576

541

499

480

451

397

362

327

301

288

271

250

240

226

199

181

164

mVh

L

H

Z

960

Z

L

H

Z

902

L

794

723

L

653

The bq2052 applies the compensation according to the

formula:

Main Gas-Gauge Registers

Programmed Full Count

CAC = [F

∗ FNAC] - DCR

CE

The PFC register stores the user-specified battery full

capacity. The 8-bit PFC registers stores the full capacity

in mVh scaled as shown in Table 2.

Where F

is the calculated efficiency compensation

CE

factor, FNAC = Full Nominal Available Capacity and

DCR = Discharge Count Register.

Full Nominal Available Capacity

The bq2052 calculates an F

based on the battery dis-

CE

charge rate and temperature. The discharge rate por-

tion of the F compensation is a “peak hold” function;

The FNAC register stores the full capacity reference of

the battery. It can be programmed to initialize to PFC

or zero. The 8-bit FNAC register stores data scaled to

the same units as PFC. The bq2052 does not update

FNAC during the course of operation; therefore, if it is

programmed to 0 on initialization, it must be written to

full using the serial port.

CE

therefore, the bq2052 latches the highest discharge rate

it has measured and uses the highest rate to calculate

F

throughout the complete discharge cycle. The

CE

highest discharge rate measured by the bq2052 is stored

in MRATE (address = 12h).

The bq2052 does not latch the temperature portion of an

CE

Discharge Count Register

F

calculation. Therefore, CAC may increase or de-

The DCR is the main gas gauging register and contains

the cumulative amount of discharge counted by the

bq2052. The 16-bit register stores data scaled to the

same units as PFC.

crease during the course of a complete discharge cycle if

a temperature shift causes a change in the calculated

CE

F

value.

Programming the bq2052

Compensated Available Capacity

The CAC registers contain the current available capac-

ity of the battery. The data stored in CAC represents

the amount of remaining capacity of the battery compen-

sated for rate and temperature use conditions. Tables 3,

4, and, 5 outline the options for typical efficiency com-

pensation factors for lithium primary batteries. The

bq2052 applies the efficiency factors to FNAC to derive

CAC.

The bq2052 is programmed with the PROG

pins.

1–6

During power-up or initialization, the bq2052 reads the

state of these six three-level inputs and latches in the

programmable configuration settings.

7

5

bq2052 Preliminary

Programmable Configuration Settings

Design Capacity

Table 5. Discharge Efficiency Factor Table

PROG4 = H

The battery’s rated design capacity or Programmed Full

Discharge Rage

Count (PFC) is programmed with the PROG –PROG

1

3

TEMP

-20

-10

0

21

55

0

C/80

93

98

100

104

106

107

C/25

92

C/10

88

C/5

83

89

91

95

97

98

C/3

75

81

84

88

90

91

pins as shown in Table 2, and represents the battery’s

full reference.

92

98

100

104

106

107

97

93

The correct PFC may be determined by multiplying the

rated battery capacity in mAh by the sense resistor

value:

99

96

102

105

99

100

101

Battery capacity (mAh)

(mVh)

sense resistor (Ω) = PFC

*

70

Selecting a PFC slightly less than the rated capacity

provides a conservative capacity reference. The bq2052

stores the selected PFC in the PFC register (address =

10h).

Display Mode

The display mode is selected using the PROG pin. The

5

three options include a two, four, or five segment display

mode as described in Tables 7, 8, and 9.

Discharge Rate and Temperature Compensation

The discharge rate and temperature compensations are se-

Initial Capacity Setting

lected using the PROG pin. The level of PROG on

4

The PFC value is copied to the FNAC register if PROG

power-up or initialization determines which compensation

table the bq2052 uses for the discharge cycle. The following

tables illustrate the calculated efficiency compensation fac-

tors at selected discharge rates and temperatures.

6

is programmed high, otherwise FNAC defaults to 0.

FNAC may be written to the desired full capacity to ini-

tialize the pack manually.

Programming Example

Table 3. Discharge Efficiency Factor Table

PROG4 = Z

Given:

Sense resistor = 0.05mΩ

Number of cells = 5 in series

Capacity = 7000mAh,

Discharge Rage

TEMP

-20

-10

0

21

55

0

C/80

99

98

99

C/25

96

C/10

92

C/5

85

89

90

92

93

C/3

81

85

87

89

90

Chemistry = LiSO

2

97

98

99

Discharge current range = 250mA to 2A

97

94

Voltage drop over sense resistor = 12.5mV to 100mV

Display mode = 5 segment bar graph display

97

94

98

96

Therefore:

99

98

96

7000mAh 0.05 = 350mVh

*

70

98

96

Select:

Table 4. Discharge Efficiency Factor Table

PROG4 = L

PFC = 26112 counts or 327mVh

PROG = low

1

PROG = low

2

PROG = float

3

Discharge Rage

PROG = float, high, or low depending on desired com-

4

TEMP

-20

-10

0

21

55

0

C/80

85

91

94

97

C/25

80

88

91

95

C/10

70

80

85

89

C/5

53

68

74

81

85

86

C/3

50

51

60

68

74

76

pensation factors

PROG = float selects five segment display

87

93

96

99

100

101

5

PROG = high sets FNAC to PFC

6

With these selections, the full battery capacity is

327mVh (6540mAh).

99

100

97

98

92

93

70

6

Preliminary bq2052

Table 6. bq2052 Command and Status Registers

Loc. Read/

(hex) Write

Control Field

Symbol

Register Name

7

6

5

4

3

2

1

0

CMDWD Command word

00h

W

R

CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0

INIT RSVD RSVD CPIN RSVD RSVD EDV1 EDVF

TEMP7 TEMP6 TEMP5 TEMP4 TEMP3 TEMP2 TEMP1 TEMP0

FLGS1

TEMP

Primary status flags 01h

02h

R

Temperature (°C)

Nominal available

capacity

NAC

03h R/W NAC7

NAC6 NAC5 NAC4 NAC3 NAC2 NAC1 NAC0

BATID

VSRL

VSRH

Battery identification

Current scale (Low)

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

05h

R

VSRL7 VSRL6 VSRL5 VSRL4 VSRL3 VSRL2 VSRL1 VSRL0

VSRH7 VSRH6 VSRH5 VSRH4 VSRH3 VSRH2 VSRH1 VSRH0

Current scale (High) 06h

Program pin pull-

PPD

PPU

VSB

07h

R

RSVD RSVD PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

RSVD RSVD PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

down

Program pin pull-up 08h

Battery voltage

0bh

VSB7

VSB6

VTS6

VSB5

VTS5

VSB4 VSB3 VSB2 VSB1

VSB0

VTS0

register

End-of-discharge

threshold select

register

VTS

0ch R/W VTS7

VTS4

VTS3 VTS2 VTS1

Relative compensated

capacity

RCAC

CACL

0dh

0eh

0fh

R

RSVD RCAC6 RCAC5 RCAC4 RCAC3 RCAC2 RCAC1 RCAC0

CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0

CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0

Compensated avail-

able capacity low byte

Compensated available

capacity high byte

CACH

PFC

R

Program pin full count 10h

Full nominal

PFC7

PFC6

PFC5

PFC4 PFC3 PFC2 PFC1

PFC0

FNAC

11h R/W FNAC7 FNAC6 FNAC5 FNAC4 FNAC3 FNAC2 FNAC1 FNAC0

available capacity

MAX

Maximum discharge

rate

12h

13h

R

MAX7 MAX6 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0

RATE7 RATE6 RATE5 RATE4 RATE3 RATE2 RATE1 RATE0

RATE

DCRL

Discharge rate

Discharge count

register (low byte)

2eh R/W DCRL7 DCRL6 DCRL5 DCRL4 DCRL3 DCRL2 DCRL1 DCRL0

2fh R/W DCRH7 DCRH6 DCRH5 DCRH4 DCRH3 DCRH2 DCRH1 DCRH0

Discharge count

register (high byte)

DCRH

Notes:

RSVD = reserved.

All other registers not documented are reserved.

7

bq2052 Preliminary

Send Host to bq-HDQ

CDMR

Send Host to bq-HDQ or

Receive from bq-HDQ

Data

t

RR

Address

R/W

MSB

Bit7

LSB

Bit0

Break

t

RSPS

Address-Bit/

Data-Bit

Start-bit

Stop-Bit

TD201807.eps

Figure 4. bq2052 Communication Example

Written by Host to bq2052

CMDR = 03h

Received by Host to bq2052

NAC = 65h

LSB

MSB

LSB

MSB

Break 1 1 0 0 0 0 0 0

1 0 1 0 0 1 1 0

HDQ

t

RSPS

TD2052TC.eps

Figure 5. Typical Communication with the bq2052

8

Preliminary bq2052

Communicating With the bq2052

bq2052 Command Code and

Registers

The bq2052 includes a simple single-pin (HDQ plus re-

turn) serial data interface. A host processor uses the in-

terface to access various bq2052 registers. Battery char-

acteristics may be easily monitored by adding a single

contact to the battery pack. The open-drain HDQ pin on

the bq2052 should be pulled up by the host system, or

may be left floating if the serial interface is not used.

The bq2052 status registers are listed in Table 6 and de-

scribed below.

Command Code

The bq2052 latches the command code when eight valid

command bits have been received by the bq2052. The

command code contains two fields:

The interface uses a command-based protocol, where the

host processor sends a command byte to the bq2052.

The command directs the bq2052 to either store the next

eight bits of data received to a register specified by the

command byte or output the eight bits of data specified

by the command byte.

I

W/R bit

I

Command address

The W/R bit of the command code is used to select whether

the received command is for a read or a write function.

The communication protocol is asynchronous re-

turn-to-one. Command and data bytes consist of a

stream of eight bits that have a maximum transmission

rate of 5K bits/sec. The least-significant bit of a com-

mand or data byte is transmitted first. The protocol is

simple enough that it can be implemented by most host

processors using either polled or interrupt processing.

Data input from the bq2052 may be sampled using the

pulse-width capture timers available on some

microcontrollers.

The W/R values are:

Command Code Bits

7

6

-

5

4

3

2

1

0

W/R

-

Where W/R is:

If a communication error occurs, e.g., t

> 250µs, the

CYCB

0

The bq2052 outputs the requested register con-

tents specified by the address portion of com-

mand code.

bq2052 should be sent a BREAK to reinitiate the serial

interface. A BREAK is detected when the HDQ pin is

driven to a logic-low state for a time, t or greater. The

B

HDQ pin should then be returned to its normal

1

The following eight bits should be written to the

register specified by the address portion of com-

mand code.

ready-high logic state for a time, t . The bq2052 is now

BR

ready to receive a command from the host processor.

The return-to-one data bit frame consists of three dis-

tinct sections. The first section is used to start the

transmission by either the host or the bq2052 taking the

The lower seven-bit field of the command code contains

the address portion of the register to be accessed. At-

tempts to write to invalid addresses are ignored.

HDQ pin to a logic-low state for a period, t

. The

STRH;B

next section is the actual data transmission, where the

data should be valid by a period, t , after the nega-

DSU;B

tive edge used to start communication. The data should

Command Code Bits

7

6

5

4

3

2

1

0

be held for a period, t , to allow the host or bq2052

DH;DV

to sample the data bit.

AD0

(LSB)

-

AD6 AD5 AD4 AD3

AD2 AD1

The final section is used to stop the transmission by re-

turning the HDQ pin to a logic-high state by at least a pe-

Command Word (CMDWD)

riod, t , after the negative edge used to start commu-

SSU;B

nication. The final logic-high state should be until a pe-

riod t , to allow time to ensure that the bit trans-

mission was stopped properly. The timings for data and

break communication are given in the serial communica-

tion timing specification and illustration sections.

The CMDWD register (address = 00h) is used by the ex-

ternal host to control the CP pin and to reset the

bq2052.

CYCH;B

CMDWD

0x55

Action

Communication with the bq2052 is always performed

with the least-significant bit being transmitted first.

Figure 5 shows an example of a communication se-

quence to read the bq2052 NAC register.

CP high impedence, CPIN bit in FLGS1 set

CP driven low, CPIN bit in FLGS1 cleared

bq2052 reset

0x66

0x78

9

bq2052 Preliminary

Primary Status Flags Register (FLGS1)

1

V < V

SB TS

The FLGS1 register (address = 01h) contains the pri-

mary bq2052 flags.

The bq2052 sets the final end-of-discharge warning

flag (EDVF) when VSB is less than the EDVF threshold.

The EDVF threshold is set 100mV below the EDV1

threshold. The EDVF flag is used to warn the system or

user that battery power is at a failure condition. The

bq2052 turns all segment drivers off upon EDVF detec-

tion.

The initialized flag (INIT) is asserted to a 1 or 0 when-

ever the bq2052 is initialized either by the application of

Vcc or by a serial port command. INIT = 1 signifies that

the device has been reset with FNAC set to PFC. INIT = 0

signifies that the battery has been reset with FNAC = 0.

The EDVF location is:

The INIT location is:

FLGS1 Bits

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

-

EDVF

INIT

-

Where EDVF is:

where INIT is:

0

1

V

≥ (V - 100mV)

SB TS

0

1

The bq2052 initialized with FNAC = 0.

The bq2052 initialized with FNAC = PFC.

V

SB

< (V -100mV)

TS

The CPIN but reflects the state of the CP output. If set,

the CP output is high impedance. If cleared, the CP out-

put is asserted low. The CP output is an open drain out-

put and requires an external pull-up register.

Temperature Register (TEMP)

The 8-bit TEMP register (address=02h) contains the

battery temperature in degrees C. The bq2052 contains

an internal temperature sensor. The temperature is

used to set discharge efficiency factors. The temperature

register contents are store in 2’s complement form and

represent the temperature 5°C.

The CPIN location is

FLGS1 Bits

7

6

5

4

3

2

1

0

Nominal Available Capacity Register (NAC)

-

CPIN

-

The NAC register contains the uncompensated remaining

capacity of the battery. The bq2052 determines NAC as

Where CPIN is:

NAC = FNAC - DCR

0

1

CP is low

CP is high impedance

Battery Identification Register (BATID)

The 8-bit BATID register (address=04h) is a general

purpose memory register that can be used to uniquely

identify a battery pack. The bq2052 maintains the

BATID contents as long as VRBI is greater than 2V. The

contents of this register have no effect on the operation

of the bq2052.

The bq2052 sets the first end-of-discharge warning

flag (EDV1) when the battery voltage VSB is less than

the EDV1 threshold VTS. The flag warns the user that

the battery is almost empty. The bq2052 modulates the

first segment pin, SEG1, at a 4Hz rate if the 4 or 5 seg-

ment display mode is enabled and EDV1 is asserted.

The EDV1 threshold has a default value of 0.76V but

can be adjusted by writing the VTS register .

Current Scale Registers (VSRL/VSRH)

The VSRH high-byte register and the VSRL low-byte

register are used to calculate the average signal across

the SR and VSS pins. This register pair is updated ev-

ery 5.625 seconds. VSRH and VSRL form a 16-bit value

representing the average current over this time. The

battery pack current can be calculated by:

The EDV1 location is

FLGS1 Bits

7

6

5

4

3

2

1

0

-

EDV1

-

(VSRH ∗ 256 + VSRL)

|I(mA)| =

Where EDV1 is:

≥ V

(RS)

0

V

SB

TS

10

Preliminary bq2052

where

temperature. The CAC value is also used in calculating

the LED display pattern relative to PFC.

R = sense resistor value in Ω.

S

Program Full Count (PFC)

VSRH = high-byte value of current scale

VSRL = low-byte value of current scale

The PFC register (address = 10h) contains the user se-

lected programmed full count (PFC) setting.

Program Pin Pull-Down Register (PPD)

Full Nominal Available Capacity (FNAC)

The PPD register (address = 07h) contains the pull-down

programming pin information for the bq2052. The pro-

gram pins, PROG , have a corresponding PPD register

1–6

The FNAC (address = 11h) contains the full capacity

reference of the battery.

location, PPD

.

A given location is set if the bq2052

1–6

Maximum Discharge Rate (MAXRATE)

detects a pull-down resistor on its corresponding seg-

ment driver. For example, if PROG and PROG have

pull-down resistors, the contents of PPD are xx001001.

1

4

The MAXRATE register (address = 12h) stores the high-

est discharge rate detected by the bq2052. The bq2052

uses the MAXRATE value to calculate the efficiency

compensation factors.

Program Pin Pull-Up Register (PPU)

The PPU register (address = 08h) contains the pull-up

programming pin information for the bq2052. The seg-

Discharge Rate (RATE)

ment drivers, PROG , have a corresponding PPU reg-

1–6

The RATE register (address = 13h) provides the current

discharge rate of the battery.

ister location, PPU

.

A given location is set if a

pull-up resistor has been detected on its corresponding

segment driver. For example, if PROG and PROG

1–6

3

5

Discharge Count Registers (DCRH/DCRL)

have pull-up resistors, the contents of PPU are

xx010100.

The DCRH high-byte register and the DCRL low-byte

register are the main gas gauging registers for the

bq2052. The DCR registers are incremented during dis-

charge.

Battery Voltage (VSB)

The battery voltage register (address = 0bh) stored the

voltage detected on the SB pin. The bq2052 updates the

VSB register approximately once per second with the

present value of the battery voltage.

Writing to the DCR registers affects the available charge

counts and, therefore, affects the bq2052 gas gauge oper-

ation.

VSB

256













V

SB

= 1.2V ∗

Display

The bq2052 can directly display remaining capacity in-

formation using low-power LEDs. The bq2052 uses the

CAC value in relation to FNAC as the basis for the dis-

play activity. The bq2052 displays the battery’s remain-

ing capacity in either of three modes selected with pro-

Voltage Threshold Register (VTS)

The end-of-discharge threshold voltages (EDV1 and

EDVF) can be set using the VTS register. The VTS reg-

ister sets the EDV1 trip point. EDVF is set 100mV below

EDV1. The default value in the VTS register is A2h,

representing EDV1 = 0.76V and EDVF = 0.66V.

gram pin PROG . The display is activated using the

5

DISP input. When DISP is connected to V , the SEG

CC

outputs are OFF. When pulled low, the segment outputs

turn ON for a period of 4 0.5s, depending on the se-

lected mode.

VTS

256













EDV1 = 1.2V

*

.

The segment outputs are modulated as two banks, with

segments 1, 3, and 5 alternating with segments 2 and 4.

The segment outputs are modulated at approximately

100Hz with each segment bank active for 30% of the pe-

riod. In incremental and bar graph modes, SEG1 blinks

at a 4Hz rate whenever VSB is below VEDV1 (EDV1

flag bit set in FLGS1), indicating a low-battery condi-

tion. When VSB is below VEDVF (EDVF flag bit set in

FLGS1) the display outputs are disabled in all modes.

Relative CAC Register (RCAC)

The RCAC register (address = 0dh) provides the relative

battery state-of-charge by dividing CAC by FNAC.

RCAC varies from 0 to 7dh representing relative

state-of-charge from 0 to 125%.

Compensated Available Capacity (CAC)

The CAC registers (address = 0eh–0fh) contain the

available capacity compensated for discharge rate and

11

bq2052 Preliminary

In incremental mode (PROG = L), the battery charge

5

Microregulator

state is displayed on pins SEG1–SEG4. The charge state

condition indicated by each segment is shown in Table 7.

Only the segment pin representing the present remain-

ing capacity is ON (low); all other segments are OFF

(high impedance). When DISP is pulled low, the display

is active for 10s.

A micro-power source for the bq2052 can be inexpen-

sively built using a FET and an external resistor as

shown in Figure 1.

RBI Input

Table 7. Incremental Display Mode

PROG₅= L

The RBI input pin should be used with a storage capaci-

tor or external supply to provide backup potential to the

internal bq2052 registers when V

drops below 3.0V.

CC

SEG Pin ON

Remaining Capacity

90 -100%

V

is output on RBI when V

is above 3.0V. If using

CC

SEG4

SEG3

SEG2

SEG1

an external supply (such as the bottom series cell) as the

backup source, an external diode is required for isola-

tion.

50 - < 90%

20 - < 50%

< 20%

Initialization

SEG1—BLINK

V

< V

SB EDV1

The bq2052 can be initialized by removing V

and

CC

In binary mode (PROG5 = H), the battery charge state is

displayed using only pins SEG1 and SEG2, with the re-

maining capacity indication defined as in Table 8. When

DISP is pulled low, the display is active for 4s.

grounding the RBI pin for 5s or by a command over the

serial port. The serial port reset command requires

writing 78h to register CMDWD (address = 00h).

On initialization with PROG6 = H, the bq2052 sets the

registers as

Table 8. Binary Display Mode

PROG₅= H

FNAC = PFC

CACH = PFC

CACL = 0x00

RCAC = 0x64

FLGS1 = 0x90

SEG 1

ON

SEG 2

ON

Remaining Capacity

70 -100%

OFF

ON

40 - < 70%

10 - < 40%

OFF

< 10% or V < V

SB EDVF

In bar graph mode (PROG = Z), the battery charge

5

state is displayed using pins SEG1 through SEG 5 ac-

cording to Table 9. When DISP is pulled low, the display

is active for 4s.

Table 9. Bar Graph Display Mode

PROG₅= Z

SEG1

ON

SEG2

ON

SEG3

ON

SEG4

ON

SEG5

ON

Remaining Capacity

80 - 100%

ON

OFF

ON

OFF

ON

OFF

60 - < 80%

40 - < 60%

20 - < 40%

< 20%

OFF

BLINK

VSB < VEDV1

12

Preliminary bq2052

Layout Considerations

On initialization with PROG6=L, the bq2052 sets the

registers as

The bq2052 measures the voltage differential between

the SR and V pins. V (the offset voltage at the SR

FNAC = 0x00

CACH = 0x00

CACL = 0x00

RCAC = 0x00

FLGS1 = 0x10

SS

OS

pin) is greatly affected by PC board layout. For optimal

results, the PC board layout should follow the strict rule

of a single-point ground return. Sharing high-current

ground with small signal ground causes undesirable

noise on the small signal nodes.

Absolute Maximum Ratings

Symbol

Parameter

Minimum Maximum

Unit

V

Notes

V

Relative to V

-0.3

+7.0

+8.5

CC

SS

All other pins

REF

Relative to V

V

SS

Relative to V

V

Current limited by R1 (see Figure 1)

Recommended 100KΩ series resistor

should be used to protect SR in case

of a shorted battery.

V

Relative to V

-0.3

-20

Vcc+0.7

+70

V

SR

SS

T

OPR

Operating temperature

°C

Commercial

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional

operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet.

Exposure to conditions beyond the operational limits for extended periods of time may affect device reli-

ability.

DC Voltage Thresholds (T = T

; V = 3.0 to 6.5V)

OPR

A

Symbol

Parameter

First empty warning

Final empty warning

SR sense range

Minimum

Typical

Maximum

0.79

Unit

V

Notes

SB, default

SR, V + V

V

0.73

0.76

EDV1

EDVF

SRO

V

-

-300

-

V

- 0.10

-

V

EDV1

-

+500

-250

mV

µV

SR

OS

Valid discharge

V

+ V

(see note)

OS

SRD

SR

Note:

V

is affected by PC board layout. Proper layout guidelines should be followed for optimal performance.

OS

See “Layout Considerations.”

13

bq2052 Preliminary

DC Electrical Characteristics (T = T

)

A

OPR

Symbol

Parameter

Supply voltage

Minimum Typical Maximum

Unit

Notes

V

excursion from < 2.0V to

≥ 3.0V initializes the unit.

CC

V

CC

3.0

4.25

6.5

V

R

Offset referred to V

Reference at 25°C

DISP = V

CC

-

5.7

4.5

2.0

-

50

150

6.3

7.5

-

µV

V

OS

SR

6.0

I

= 5µA

= 3V

REF

Reference at -40°C to +85°C

Reference input impedance

-

V

5.0

MΩ

µA

V

REF

= 3.0V, HDQ = 0

= 4.25V, HDQ = 0

= 6.5V, HDQ = 0

90

135

180

250

CC

I

CC

Normal operation

-

120

CC

-

170

V

SB

Battery input

0

-

V

CC

-

R

I

SB input impedance

DISP input leakage

LCOM input leakage

RBI data retention current

Internal pulldown

10

-

MΩ

µA

nA

KΩ

MΩ

V

0 < V < V

SB CC

SBmax

V

= V

SS

5

DISP

LCOM

RBI

DISP

I

DISP = V

-0.2

-

0.2

CC

100

V

> V

< 3V

RBI

R

V

500

10

-

HDQ

SR input impedance

PROG logic input high

PROG logic input low

PROG logic input Z

V

< V

CC

SR

V

- 0.2

PROG

IHPFC

ILPFC

IZPFC

CC

1-6

-

V

+ 0.2

V

SS

1-6

float

V

= 3V, I

1 5

≤ 1.75mA

OLS

CC

V

SEG output low, low V

CC

-

0.1

0.4

-

V

OLSL

SEG – , CP

V

CC

= 6.5V, I

1 5

≤ 11.0mA

OLS

SEG output low, high V

CC

-

OLSH

OHML

OHMH

SEG – , CP

V

= 3V, I

=

OHLCOM

CC

LCOM output high, low V

V

- 0.3

CC

-5.25mA

V

CC

> 3.5V, I

=

OHLCOM

LCOM output high, high V

- 0.6

-

CC

-33.0mA

I

SEG sink current

Open-drain sink current

Open-drain output low

HDQ input high

11.0

-

mA

V

At V

= 0.4V, V

= 6.5V

CC

OLS

OLSH

5.0

-

= V + 0.3V, HDQ

SS

OL

V

0.3

-

I

≤ 5mA, HDQ

OL

2.5

-

V

HDQ

IHDQ

ILDQ

HDQ input low

0.8

V

Soft pull-up or pull-down resis-

tor value (for programming)

R

PROG –PROG

1

-

200

-

KΩ

PROG

6

R

Float state external impedance

5

MΩ

PROG

1–6

FLOAT

Note:

All voltages relative to V

.

SS

14

Preliminary bq2052

Serial Communication Timing Specification (T = T

)

A

OPR

Symbol

CYCH

CYCB

STRH

STRB

DSU

DSUB

DH

Parameter

Cycle time, host to bq2052 (write)

Cycle time, bq2052 to host (read)

Start hold, host to bq2052 (write)

Start hold, bq2052 to host (read)

Data setup

Minimum Typical Maximum

Unit

µs

ns

µs

Notes

See note

t

190

5

-

250

-

205

-

32

-

50

-

Data setup

-

Data hold

90

-

µs

Data valid

80

145

320

-

DV

Stop setup

-

SSU

Stop setup

-

SSUB

RSPS

B

Response time, bq2052 to host

Break

190

40

µs

Break recovery

-

BR

Note:

The open-drain HDQ pin should be pulled to at least V

by the host system for proper HDQ operation.

CC

HDQ may be left floating if the serial interface is not used.

15

bq2052 Preliminary

Break Timing

t

BR

B

TD201803.eps

Host to bq2052

Write "1"

Write "0"

t

STRH

DSU

t

DH

t

SSU

t

CYCH

bq2052 to Host

Read "1"

Read "0"

t

STRB

DSUB

t

DV

t

SSUB

t

CYCB

16

Preliminary bq2052

16-Pin SOIC Narrow (SN)

(

)

16-Pin SN SOIC Narrow

Dimension

Minimum

0.060

0.004

0.013

0.007

0.385

0.150

0.045

0.225

0.015

Maximum

0.070

0.010

0.020

0.010

0.400

0.160

0.055

0.245

0.035

A

A1

B

D

B

e

C

D

E

e

H

L

H

All dimensions are in inches.

A

C

A1

.004

L

Ordering Information

bq2052

Temperature Range:

blank = Commercial (-20 to +70°C)

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2052 Gas Gauge IC

17

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any

product or service without notice, and advise customers to obtain the latest version of relevant information to verify,

before placing orders, that information being relied on is current and complete. All products are sold subject to the

terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty,

patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accor-

dance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems

necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, ex-

cept those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,

PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI

SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR

USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI

PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards

must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that

any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellec-

tual property right of TI covering or relating to any combination, machine, or process in which such semiconductor

products or services might be or are used. TI’s publication of information regarding any third party’s products or ser-

vices does not constitute TI’s approval, warranty or endorsement thereof.

18


型号：	BQ2052SN-A515
厂家：	TEXAS INSTRUMENTS
描述：	具有高速单总线 (HDQ) 接口、3 种可编程 LED 模式的锂原电池电量监测计 \| D \| 16 \| -20 to 70 电池光电二极管
文件：	总18页 (文件大小：162K)
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下载：	下载PDF数据表文档文件

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