BQ2205L [TI]
POWER MONITORING AND SWITCHING CONTROLLER FOR 3.3V SRAM; 电源监视和开关控制器的3.3V SRAM
| 型号： | BQ2205L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | POWER MONITORING AND SWITCHING CONTROLLER FOR 3.3V SRAM |
| 文件： | 总10页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS581 − FEBRUARY 2004
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FEATURES
DESCRIPTION
D
D
Power Monitoring and Switching for
Non-Volatile Control of SRAMs
The CMOS bq2205 SRAM non-volatile controller
with reset provides all the necessary functions for
converting one or two banks of standard CMOS
SRAM into non-volatile read/write memory.
Input Decoder Allows Control of 1 or 2 Banks
of SRAM
D
D
D
D
D
Write-Protect Control
A precision comparator monitors the 3.3-V VCC
input for an out-of-tolerance condition. When
out-of-tolerance is detected, the two conditioned
chip-enable outputs are forced inactive to
write-protect both banks of SRAM.
3-V Primary Cell Input
3.3-V Operation
Reset Output for System Power-On Reset
Less than 20-ns Chip Enable Propagation
Delay
Power for the external SRAMs, VOUT, is switched
from the VCC supply to the battery-backup supply
as VCC decays. On a subsequent power-up, the
VOUT supply is automatically switched from the
backup supply to the VCC supply. The external
SRAMs are write-protected until a power-valid
condition exists. The reset output provides
power-fail and power-on resets for the system.
During power-valid operation, the input decoder, A,
selects one of two banks of SRAM.
D
Small 16-Lead TSSOP Package
APPLICATIONS
D
D
D
D
D
D
NVSRAM Modules
Point-of-Sale Systems
Facsimile, Printers and Photocopiers
Internet Appliances
Servers
Medical Instrumentation and Industrial
Products
From Address
V
CC
bq2205LYPW
Selector
Main Supply
VDC
V
CC
12 VCC
BW 15
RST 16
To Microprocessor
GND
1
11
9
A
V
CC
CE
VOUT 13
Backup Supply
VDC
Pushbutton
Reset
(Optional)
BC
VCC
VCC
P
CE
CON1 10
CE
CE
GND
4
5
8
V
SS
V
SRAM Bank 1
SRAM Bank 2
SS
SS
V
CE
CON2 14
UDG−03129
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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SLUS581 − FEBRUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
OPERATION
PART NUMBER
SYMBOL
−20°C to 70°C
3.3 V
bq2205LYPW
bq2205LY
(1)
The PW package is available taped and reeled. Add an R suffix to the device type (i.e. bq2205LYPWR) to order quantities of 2,000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(2)
bq2205LY
−0.3 to 6.0
−0.3 to 4.5
−0.3 to VCC + 0.3
−20 to 70
UNIT
V
, (wrt V )
SS
CC
BC , (wrt V
)
Input voltage range
V
P
SS
all other pins, (wrt V
)
SS
Operating temperature range, T
A
Storage temperature, T
stg
−55 to 125
−40 to 85
°C
Temperature under bias, T
Jbias
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
3.0
MAX
UNIT
Supply voltage, V
CC
3.6
4.0
0.8
Supply voltage from backup cell, V
BC
2.0
−0.3
2.2
Low-level input voltage, V
IL
V
High-level input voltage, V
IH
V
V
+ 0.3
0.4
CC
RST low-level input voltage, V
IL
−0.3
2.2
RST high-level input voltage, V
IH
+ 0.3
70
CC
Operating temperature range, T
−20
°C
A
2
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SLUS581 − FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
(T = 25°C, V
A CC(min)
≤ V
CC
≤ V unless otherwise noted)
CC(max)
PARAMETER
TEST CONDITIONS
MIN
TYP
210
MAX
500
UNIT
V
> V
CC(MIN)
CC
CE = low
CE
VCC supply current, I
CC(vcc)
µA
= 0 mA
CONX
V
> V
, V
= 0 V
BC
BC(MIN) CC
CE = low
Backup Battery Supply Current, I
Output voltage (VOUT)
50
150
nA
CC(BC)
CE
= 0 mA
CONX
(VOUT) =
(VOUT)=
I
I
80 mA, V
100µ A, V
> V
< V
Vcc−0.3
CC
(SO)
V
BC
−0.3
2.85
CC
(SO)
Power fail detect voltage, V
PFD
2.9
2.95
V
V
> V
< V
V
PFD
V
BC
(PFD)
Supply switch-over voltage, V
SO
V
BC
BC
(PFD)
RST output voltage
BW output voltage
I(RST) = 1 mA
I(BW)= 1 mA
0.4
0.4
1
Input leakage current on A and CE pins
−1
µA
Voh CE
Ioh = 0.5 mA
2.4
0.4
con1,2
Vol CE
Iol = 2.0 mA
(1)
V
con1,2
Battery warning level V
0.677xV
CC
BW
Capacitance
Output capacitance
Input capacitance
VOUT = 0 V
VOUT = 0 V
7
5
pF
Power-Down and Power-Up Timing, Refer to Figure 1 through 3
VCC slew rate fall time, t 3.0 V to 0.0 V
to V
PFD(max)
300
100
F
µs
VCC slew rate rise time, t
V
SO
R
V
to RST active, t
RST
PFD
30
30
85
85
25
(reset active timeout period)
ms
(2)
Chip-enable recovery time, t
CER
Chip-enable propagation delay time to external
SRAM, t
See Figure 2
RST pin
15
1
ns
CED
Push-button low time, t
µs
PBL
(1)
(2)
Battery warning level is detected on power up and the BW pin is latched at t
time after V
CC
PFD
passes through V on power up.
PFD
CER
Time during which external SRAM is write protected after V
passes through V on power up.
CC
3
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SLUS581 − FEBRUARY 2004
AC TEST CONDITIONS, INPUT PULSE LEVELS 0 V ≤ V ≤ 3 V, t = t = 5 NS
IN
R
F
TTL
CE
CONX
CL
(including scope
and JIG)
Figure 1. Output Load
t
t
F
R
VCC
V
PFD(max)
V
V
PFD
PFD
VCC
V
V
SO
SO
t
t
CER
t
CED
CED
CE
CE
CONX
t
RST
RST
Figure 2. Power-Down/Power-Up Timing Diagram
t
t
RST
PBL
RST
V
PBRH
V
PBRL
Figure 3. Push-Button Reset Timing
4
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TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
bq2205LY
A
1
9
I
SRAM bank select input
BC
I
Backup supply input
P
BW
CE
15
O
I
Battery warning output (open-drain)
Chip enable input (active low)
Conditioned chip enable output 1
Conditioned chip enable output 2
No connect. These pins must be left floating.
11
CE
CE
10
O
O
−
O
I
CON1
14
CON2
N/C
2, 3, 6, 7
16
RST
Power-up reset to system CPU output (open-drain)
Main supply input
V
V
V
12
CC
13
O
−
SRAM supply output
OUT
SS
4, 5, 8
Ground input
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
N/C
N/C
RST
BW
CE
CON2
V
V
V
V
SS
SS
OUT
CC
N/C
N/C
CE
CE
BC
CON1
P
V
SS
N/C no connection
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FUNCTIONAL DESCRIPTION
Two banks of CMOS static RAM can be battery-backed using the VOUT and conditioned chip-enable output
pins from the bq2205. As the voltage input VCC slews down during a power failure, the two-conditioned chip
enable outputs, CE
and CE
, are forced inactive independent of the chip enable input, CE. This activity
CON1
CON2
unconditionally write-protects the external SRAM as VCC falls to an out-of-tolerance threshold V
supply continues to fall past V
. As the
PFD
, an internal switching device forces VOUT to the backup energy source.
PFD
CE
and CE
are held high by the VOUT energy source.
CON1
CON2
During power-up, VOUT is switched back to the 3.3-V supply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CE and CE are held inactive for time t after the power supply has reached
CON1
CON2
CER
V
, independent of the CE input, to allow for processor stabilization.
PFD
During power-valid operation, the CE input is passed through to one of the two CE
outputs with a
CONx
propagation delay of less than t
. The CE input is output on one of the two CE
output pins; depending
CED
CONx
on the level of bank select input A. See truth table below.
Table 1. Truth Table
INPUT
OUTPUT
CE
H
A
x
CE
CE
CON2
CON1
H
H
L
L
L
H
L
L
H
H
Bank select input A is usually tied to a high-order address pin so that a large nonvolatile memory can be
designed using lower-density memory devices. Non-volatility and decoding are achieved by hardware hookup
as shown in the application diagram.
The RST output can be used as the power-on reset for a microprocessor. Access to the external RAM may begin
when RST returns inactive.
BATTERY BACKUP INPUT
Backup energy source, BC input is provided on the bq2205 for use with an external primary cell. The primary
P,
cell input is designed to accept any 3-V primary battery (non-rechargeable), typically some type of lithium
chemistry.
Power-Down and Power-Up Cycle
The bq2205 continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below
V
, the bq2205 write-protects the external SRAM. The power source is switched to BC when V
is less
PFD
P
CC
than V
is above V
and BC is greater than V
, or when V
is less than BC and BC is less than V
. When VCC
PFD
P
PFD
CC
P
P
PFD
, the power source is V . Write-protection continues for t
time after VCC rises above V
.
PFD
CC
CER
PFD
An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq2205.
As the voltage input V slews down during a power failure, the chip enable output, CE , is forced inactive
CC
CONx
independent of the chip enable input CE.
As the supply continues to fall past V
, an internal switching device forces VOUT to the external backup
PFD
energy source. CE
is held high by the VOUT energy source.
CONx
6
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FUNCTIONAL DESCRIPTION
During power up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage
sourcing VOUT. If V < BC on the bq2205 the switch to the main supply occurs at V . CE is held
PFD
CER
processor stabilization.
P
PFD
CONx
inactive for time t
after the power supply has reached V
, independent of the CE input, to allow for
PFD
Power-On Reset
The bq2205 provides a power-on reset, which pulls the RST pin low on power down and remains low on power
up for t after V passes V . With valid battery voltage on BC , RST remains valid for V = V . The
RST
CC
PFD
P
CC
SS
pull-up resistor on this pin should not exceed 10 kΩ if a push button reset is used.
Battery Low Warning
The bq2205 checks the battery voltage on power-up. The threshold for the battery warning comparator is V
,
BW
and a low level is sensed after power valid on each power up and latched after t
is presented at BW pin where a low indicates a low battery.
time. The latched value
CER
APPLICATION INFORMATION
PCB LAYOUT INFORMATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
D
D
To obtain optimal performance, the decoupling capacitor from input terminals to V should be placed as
SS
close as possible to the bq2205, with short trace runs to both signal and V pins.
SS
All low-current V
connections should be kept separate from the high-current paths from the inputs
SS
supplies. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
7
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SLUS581 − FEBRUARY 2004
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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