BQ24074RGTT [TI]
1.5A USB-FRIENDLY Li-Ion BATTERY CHARGER AND POWER-PATH MANAGEMENT IC; 1.5A USB供能的锂离子电池充电器和电源路径管理IC型号: | BQ24074RGTT |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.5A USB-FRIENDLY Li-Ion BATTERY CHARGER AND POWER-PATH MANAGEMENT IC |
文件: | 总39页 (文件大小:2536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
bq24072, bq24073
bq24074, bq24075, bq24079
www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
1.5A USB-FRIENDLY Li-Ion BATTERY CHARGER AND POWER-PATH MANAGEMENT IC
1
FEATURES
DESCRIPTION
•
Fully Compliant USB Charger
–
–
–
Selectable 100mA and 500mA Maximum
Input Current
The bq2407x series of devices are integrated Li-ion
linear chargers and system power path management
devices
targeted
at
space-limited
portable
100mA Maximum Current Limit Ensures
Compliance to USB-IF Standard
applications. The devices operate from either a USB
port or AC adapter and support charge currents up to
1.5A. The input voltage range with input overvoltage
protection supports unregulated adapters. The USB
input current limit accuracy and start up sequence
allow the bq2407x to meet USB-IF inrush current
specification. Additionally, the input dynamic power
management (VIN-DPM) prevents the charger from
crashing incorrectly configured USB sources.
Input based Dynamic Power Management
(VIN-DPM) for Protection Against Poor USB
Sources
•
•
28V Input Rating with Overvoltage Protection
Integrated Dynamic Power Path Management
(DPPM) Function Simultaneously and
Independently Powers the System and
Charges the Battery
The bq2407x features dynamic power path
management (DPPM) that powers the system while
simultaneously and independently charging the
battery. The DPPM circuit reduces the charge current
when the input current limit causes the system output
to fall to the DPPM threshold; thus, supplying the
system load at all times while monitoring the charge
current separately. This feature reduces the number
of charge and discharge cycles on the battery, allows
for proper charge termination and enables the system
to run with a defective or absent battery pack.
•
•
•
Supports up to 1.5A Charge Current with
Current Monitoring Output (ISET)
Programmable Input Current Limit up to 1.5A
for Wall Adapters
System Output Tracks Battery Voltage
(bq24072)
•
•
Programmable Termination Current (bq24074)
Battery Disconnect Function with SYSOFF
Input (bq24075, bq24079)
Typical Application Circuit
•
•
Programmable Pre-Charge and Fast-Charge
Safety Timers
1kW
1kW
Reverse Current, Short-Circuit and Thermal
Protection
•
•
NTC Thermistor Input
Proprietary Start Up Sequence Limits Inrush
Current
IN
SYSTEM
IN
OUT
10
11
13
1mF
4.7mF
•
•
Status Indication – Charging/Done, Power
Good
bq24075
bq24079
5
8
EN2
BAT
VSS
2
3
Small 3 mm × 3 mm 16 Lead QFN Package
System
ON/OFF
Control
15
SYSOFF
4.7mF
PACK+
TEMP
1
TS
APPLICATIONS
•
•
•
•
Smart Phones
PACK-
Portable Media Players
Portable Navigation Devices
Low-Power Handheld Devices
1.18kW
1.13kW
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
bq24072, bq24073
bq24074, bq24075, bq24079
SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Additionally, the regulated system input enables instant system turn-on when plugged in even with a totally
discharged battery. The power-path management architecture also permits the battery to supplement the system
current requirements when the adapter cannot deliver the peak system currents, enabling the use of a smaller
adapter.
The battery is charged in three phases: conditioning, constant current, and constant voltage. In all charge
phases, an internal control loop monitors the IC junction temperature and reduces the charge current if the
internal temperature threshold is exceeded. The charger power stage and charge current sense functions are
fully integrated. The charger function has high accuracy current and voltage regulation loops, charge status
display, and charge termination. The input current limit and charge current are programmable using external
resistors.
ORDERING INFORMATION
PART NUMBER
OPTIONAL
FUNCTION
VOVP
VBAT(REG)
VOUT(REG)
VDPPM
MARKING
(1)(2)
bq24072RGTR
bq24072RGTT
bq24073RGTR
bq24073RGTT
bq24074RGTR
bq24074RGTT
bq24075RGTR
bq24075RGTT
bq24079RGTR
bq24079RGTT
6.6 V
6.6 V
6.6 V
6.6 V
10.5 V
10.5 V
6.6 V
6.6 V
6.6 V
6.6 V
4.2V
4.2V
4.2V
4.2V
4.2V
4.2V
4.2V
4.2V
4.1V
4.1V
VBAT + 225 mV
VBAT + 225 mV
4.4 V
VO(REG) – 100 mV
VO(REG) – 100 mV
VO(REG) – 100 mV
VO(REG) – 100 mV
VO(REG) – 100 mV
VO(REG) – 100 mV
4.3 V
TD
TD
CKP
CKP
CKQ
CKQ
BZF
BZF
CDU
CDU
ODI
TD
4.4 V
TD
4.4 V
ITERM
ITERM
SYSOFF
SYSOFF
SYSOFF
SYSOFF
4.4 V
5.5 V
5.5 V
4.3 V
5.5 V
4.3 V
5.5 V
4.3 V
ODI
(1) The RGT package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
(2) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
2
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24072 bq24073 bq24074 bq24075, bq24079
bq24072, bq24073
bq24074, bq24075, bq24079
www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
ABSOLUTE MAXIMUM RATINGS(1)
over the 0°C to 125°C operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 28
–0.3 to 5
UNIT
V
IN (with respect to VSS)
BAT (with respect to VSS)
V
VI
Input Voltage
Input Current
OUT, EN1, EN2, CE, TS, ISET, PGOOD, CHG, ILIM, TMR, ITERM,
SYSOFF, TD (with respect to VSS)
–0.3 to 7
V
II
IN
1.6
A
A
OUT
5
5
Output Current
(Continuous)
IO
BAT (Discharge mode)
BAT (Charging mode)
CHG, PGOOD
A
1.5(2)
A
Output Sink Current
Junction temperature
Storage temperature
15
mA
°C
°C
TJ
–40 to 150
–65 to 150
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
DISSIPATION RATINGS
POWER RATING
PACKAGE(1)
RθJA
RθJC
TA ≤ 25°C
TA = 85°C
(2)
RGT
39.47 °C/W
2.4 °C/W
2.3 W
225mW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. The pad is
connected to the ground plane by a 2x3 via matrix.
RECOMMENDED OPERATING CONDITIONS
MIN
4.35
4.35
4.35
MAX
26
UNIT
IN voltage range
V
VI
’72, ’73, ‘75, '79
‘74
6.4
IN operating voltage range
V
10.2
1.5
IIN
Input current, IN pin
A
A
IOUT
IBAT
ICHG
TJ
Current, OUT pin
4.5
Current, BAT pin (Discharging)
Current, BAT pin (Charging)
Junction Temperature
4.5
A
1.5(1)
125
8000
3000
15
A
–40
1100
590
0
°C
Ω
RILIM
RISET
RITERM
RTMR
Maximum input current programming resistor
(2)
Fast-charge current programming resistor
Ω
Termination current programming resistor
Timer programming resistor
kΩ
kΩ
18
72
(1) The IC operational charging life is reduced to 20,000 hours, when charging at 1.5A and 125°C. The thermal regulation feature reduces
charge current if the IC’s junction temperature reaches 125°C; thus without a good thermal design the maximum programmed charge
current may not be reached.
(2) Use a 1% tolerance resistor for RISET to avoid issues with the RISET short test when using the maximum charge current setting.
Copyright © 2008–2009, Texas Instruments Incorporated
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SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
UVLO
Vhys
Undervoltage lock-out
VIN: 0 V → 4 V
VIN: 4 V → 0 V
3.2
3.3
3.4
V
Hysteresis on UVLO
200
300
mV
Input power detected when VIN > VBAT + VIN(DT)
VBAT = 3.6 V, VIN: 3.5 V → 4 V
VIN(DT)
Input power detection threshold
Hysteresis on VIN(DT)
55
20
80
130
mV
mV
ms
Vhys
VBAT = 3.6 V, VIN: 4 V → 3.5 V
Time measured from VIN: 0 V → 5 V 1 µs
rise-time to PGOOD = LO
tDGL(PGOOD)
Deglitch time, input power detected status
1.2
VIN: 5 V → 7 V
VIN: 5 V → 11 V
VIN: 7 V → 5V
VIN: 11 V → 5 V
(’72, ’73, ’75, '79)
(’74)
6.4
6.6
10.5
110
175
50
6.8
VOVP
Vhys
Input overvoltage protection threshold
Hysteresis on OVP
V
10.2
10.8
(’72, ’73, ’75, '79)
(’74)
mV
tDGL(OVP)
tREC
Input overvoltage blanking time (OVP fault deglitch)
Input overvoltage recovery time
µs
Time measured from VIN: 11 V → 5 V with 1 µs
fall-time to PGOOD = LO
1.2
ms
ILIM, ISET SHORT CIRCUIT DETECTION (CHECKED DURING STARTUP)
ISC
Current source
VIN > UVLO and VIN > VBAT + VIN(DT)
VIN > UVLO and VIN > VBAT + VIN(DT)
1.3
mA
mV
VSC
520
QUIESCENT CURRENT
CE = LO or HI, input power not detected,
No load on OUT pin, TJ = 85°C
IBAT(PDWN)
Sleep current into BAT pin
6.5
µA
µA
EN1= HI, EN2=HI, VIN = 6 V, TJ= 85°C
EN1= HI, EN2=HI, VIN = 10 V, TJ= 85°C
50
IIN
Standby current into IN pin
Active supply current, IN pin
200
CE = LO, VIN = 6 V, no load on OUT pin,
VBAT > VBAT(REG), (EN1, EN2) ≠ (HI, HI)
ICC
1.5
mA
POWER PATH
VDO(IN-OUT)
VIN – VOUT
VIN = 4.3 V, IIN = 1A, VBAT = 4.2V
IOUT = 1 A, VIN = 0 V, VBAT > 3 V
VIN > VOUT + VDO(IN-OUT), VBAT < 3.2 V
300
50
475
100
3.5
mV
mV
VDO(BAT-OUT)
VBAT – VOUT
3.3
3.4
OUT pin voltage regulation (bq24072)
VBAT
150mV
+
VBAT
225mV
+
VBAT
270mV
+
VIN > VOUT + VDO(IN-OUT), VBAT ≥ 3.2 V
VO(REG)
V
OUT pin voltage regulation (bq24073, bq24074)
OUT pin voltage regulation (bq24075, bq24079)
VIN > VOUT + VDO(IN-OUT)
VIN > VOUT + VDO(IN-OUT)
EN1 = LO, EN2 = LO
4.3
5.4
90
4.4
5.5
4.5
5.6
95
100
500
mA
IINmax
Maximum input current
EN1 = HI, EN2 = LO
450
475
EN2 = HI, EN1 = LO
KILIM/RILIM
1610
1525
A
ILIM = 500mA to 1.5A
1500
1330
200
1720
1720
1500
AΩ
KILIM
Maximum input current factor
ILIM = 200mA to 500mA
EN2 = HI, EN1 = LO, RILIM = 8 kΩ to 1.1 kΩ
IINmax
VIN-DPM
Programmable input current limit range
mA
V
Input voltage threshold when input current is
reduced
EN2 = LO, EN1 = X
4.35
4.5
4.63
VO(REG)
180mV
–
VO(REG)
100mV
–
VO(REG) –
30mV
(’72, ’73, ’74)
V
V
V
Output voltage threshold when charging current is
reduced
VDPPM
(’75, '79)
4.2
4.3
4.4
VBAT = 3.6V, RILIM = 1.5kΩ, RLOAD = 10Ω → 2Ω
V
OUT ≤ VBAT
–40mV
VBSUP1
Enter battery supplement mode
VBAT = 3.6V, RILIM = 1.5kΩ, RLOAD = 2Ω → 10Ω
VOUT ≥
VBAT–20mV
VBSUP2
VO(SC1)
VO(SC2)
Exit battery supplement mode
V
V
Output short-circuit detection threshold, power-on
VIN > VUVLO and VIN > VBAT + VIN(DT)
VIN > VUVLO and VIN > VBAT + VIN(DT)
0.8
0.9
1
Output short-circuit detection threshold, supplement
mode VBAT – VOUT > VO(SC2) indicates short-circuit
200
250
300
mV
tDGL(SC2)
tREC(SC2)
Deglitch time, supplement mode short circuit
Recovery time, supplement mode short circuit
250
60
µs
ms
4
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Product Folder Link(s): bq24072 bq24073 bq24074 bq24075, bq24079
bq24072, bq24073
bq24074, bq24075, bq24079
www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY CHARGER
IBAT
Source current for BAT pin short-circuit detection
BAT pin short-circuit detection threshold
VBAT = 1.5V
VBAT rising
4
1.6
7.5
1.8
11
2
mA
V
VBAT(SC)
('72, '73, '74, '75)
('79)
4.16
4.059
2.9
4.20
4.100
3
4.23
4.141
3.1
V
VBAT(REG)
Battery charge voltage
VLOWV
Pre-charge to fast-charge transition threshold
Deglitch time on pre-charge to fast-charge transition
Deglitch time on fast-charge to pre-charge transition
VIN > VUVLO and VIN > VBAT + VIN(DT)
V
tDGL1(LOWV)
tDGL2(LOWV)
25
ms
ms
25
VBAT(REG) > VBAT > VLOWV, VIN = 5 V CE = LO,
EN1 = LO, EN2 = HI
Battery fast charge current range
Battery fast charge current
300
1500
mA
A
ICHG
CE = LO, EN1= LO, EN2 = HI,
VBAT > VLOWV, VIN = 5 V, IINmax > ICHG, no load on OUT pin,
thermal loop and DPPM loop not active
KISET/RISET
KISET
Fast charge current factor
Pre-charge current
797
890
KPRECHG/RISET
88
975
AΩ
A
IPRECHG
KPRECHG
Pre-charge current factor
70
106
AΩ
A
CE = LO, (EN1, EN2) ≠ (LO, LO),
0.09×ICHG
0.1×ICHG
0.11×ICHG
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and thermal
loop not active
Termination comparator detection threshold
(internally set)
ITERM
CE = LO, (EN1, EN2) = (LO, LO),
0.027×ICHG
72
0.033×ICHG 0.040×ICHG
VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and thermal
loop not active
IBIAS(ITERM)
ITERM
Current for external termination-setting resistor
VIN > VUVLO and VIN > VBAT + VIN(DT)
75
78
µA
Termination current threshold (externally set)
(bq24074)
A
KITERM × RITERM / RISET
USB500 or ISET mode(EN1, EN2) ≠ (LO, LO)
A
0.0225
0.0300
0.0375
0.012
CE = LO, VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and
thermal loop not active
K Factor for termination detection threshold
(externally set) (bq24074)
KITERM
USB100 mode (EN1, EN2) = (LO, LO),
CE = LO, VBAT > VRCH, t < tMAXCH, VIN = 5 V, DPPM loop and
thermal loop not active
0.008
0.0100
25
tDGL(TERM)
VRCH
tDGL(RCH)
tDGL(NO-IN)
Deglitch time, termination detected
ms
V
VBAT(REG)
–140mV
VBAT(REG)
–100mV
VBAT(REG)
–60mV
Recharge detection threshold
VIN > VUVLO and VIN > VBAT + VIN(DT)
Deglitch time, recharge threshold detected
Delay time, input power loss to OUT LDO turn-off
62.5
20
ms
ms
VBAT = 3.6 V. Time measured from
VIN: 5 V → 3 V 1 µs fall-time
IBAT(DET)
tDET
Sink current for battery detection
Battery detection timer
VBAT = 2.5V
5
7.5
10
mA
ms
BAT high or low
250
BATTERY CHARGING TIMERS
tPRECHG
tMAXCHG
tPRECHG
tMAXCHG
KTMR
Pre-charge safety timer value
TMR = floating
1440
1800
18000
2160
s
s
Charge safety timer value
Pre-charge safety timer value
Charge safety timer value
Timer factor
TMR = floating
14400
21600
18 kΩ < RTMR < 72 kΩ
18 kΩ < RTMR < 72 kΩ
RTMR × KTMR
10×RTMR ×KTMR
48
s
s
36
60
s/kΩ
BATTERY-PACK NTC MONITOR(1)
INTC
NTC bias current
VIN > UVLO and VIN > VBAT + VIN(DT)
Battery charging, VTS Falling
72
75
78
µA
mV
mV
mV
mV
ms
V
VHOT
High temperature trip point
270
300
330
VHYS(HOT)
VCOLD
Hysteresis on high trip point
Battery charging, VTS Rising from VHOT
Battery charging, VTS Rising
30
2100
Low temperature trip point
2000
2200
VHYS(COLD)
tDGL(TS)
VDIS(TS)
Hysteresis on low trip point
Battery charging, VTS Falling from VCOLD
TS fault detected to charger disable
TS unconnected
300
Deglitch time, pack temperature fault detection
TS function disable threshold (bq24072, bq24073)
50
VIN - 200mV
THERMAL REGULATION
TJ(REG)
Temperature regulation limit
125
155
20
°C
°C
°C
TJ(OFF)
Thermal shutdown temperature
Thermal shutdown hysteresis
TJ Rising
TJ(OFF-HYS)
(1) These numbers set trip points of 0°C and 50°C while charging, with 3°C hysteresis on the trip points, with a Vishay Type 2 curve NTC
with an R25 of 10 kΩ.
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SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over junction temperature range (0° ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC LEVELS ON EN1, EN2, CE, SYSOFF, TD
VIL
VIH
IIL
Logic LOW input voltage
Logic HIGH input voltage
Input sink current
0
0.4
6
V
V
1.4
VIL= 0V
1
µA
µA
IIH
Input source current
VIH= 1.4V
10
LOGIC LEVELS ON PGOOD, CHG
VOL
Output LOW voltage
ISINK = 5 mA
0.4
V
RGT PACKAGE
(Top View)
16 15 14 13
16 15 14 13
16 15 14 13
1
2
3
4
1
12
11
12
1
2
3
4
12
ILIM
OUT
OUT
CHG
ILIM
OUT
OUT
CHG
TS
BAT
BAT
CE
TS
ILIM
OUT
OUT
CHG
TS
BAT
BAT
CE
2
bq24072
bq24073
11
10
9
11
10
9
BAT
bq24075
bq24074
3
bq24079 10
BAT
4
9
CE
5
6
7
8
5
6
7
8
5
6
7
8
PIN FUNCTIONS
PIN
NO.
I/O
DESCRIPTION
NAME
'72, '73
'74
'75, '79
External NTC Thermistor Input. Connect the TS input to the NTC thermistor in the battery pack. TS monitors
a 10kΩ NTC thermistor. For applications that do not utilize the TS function, connect a 10kΩ fixed resistor
from TS to VSS to maintain a valid voltage level on TS.
TS
1
1
1
I
Charger Power Stage Output and Battery Voltage Sense Input. Connect BAT to the positive terminal of the
battery. Bypass BAT to VSS with a 4.7 µF to 47 µF ceramic capacitor.
BAT
2, 3
4
2, 3
4
2, 3
4
I/O
Charge Enable Active-Low Input. Connect CE to a high logic level to place the battery charger in standby
mode. In standby mode, OUT is active and battery supplement mode is still available. Connect CE to a low
logic level to enable the battery charger. CE is internally pulled down with ~285 kΩ. Do not leave CE
unconnected to ensure proper operation.
CE
I
EN2
EN1
5
6
5
6
5
6
I
I
Input Current Limit Configuration Inputs. Use EN1 and EN2 control the maximum input current and enable
USB compliance. See Table 2 for the description of the operation states. EN1 and EN2 are internally pulled
down with ≈285 kΩ. Do not leave EN1 or EN2 unconnected to ensure proper operation.
Open-drain Power Good Status Indication Output. PGOOD pulls to VSS when a valid input source is
detected. PGOOD is high-impedance when the input power is not within specified limits. Connect PGOOD to
the desired logic voltage rail using a 1kΩ-100kΩ resistor, or use with an LED for visual indication.
PGOOD
VSS
7
8
9
7
8
9
7
8
9
O
–
Ground. Connect to the thermal pad and to the ground rail of the circuit.
Open-Drain Charging Status Indication Output. CHG pulls to VSS when the battery is charging. CHG is high
impedance when charging is complete and when charger is disabled. Connect CHG to the desired logic
voltage rail using a 1kΩ-100kΩ resistor, or use with an LED for visual indication.
CHG
O
System Supply Output. OUT provides a regulated output when the input is below the OVP threshold and
above the regulation voltage. When the input is out of the operation range, OUT is connected to VBAT except
when SYSOFF is high (bq24075 and bq24079 only). Connect OUT to the system load. Bypass OUT to VSS
with a 4.7 µF to 47 µF ceramic capacitor.
OUT
ILIM
IN
10, 11
12
10, 11
12
10, 11
12
O
I
Adjustable Current Limit Programming Input. Connect a 1100 Ω to 8 kΩ resistor from ILIM to VSS to program
the maximum input current (EN2=1, EN1=0). The input current includes the system load and the battery
charge current. Leaving ILIM unconnected disables all charging.
Input Power Connection. Connect IN to the external DC supply (AC adapter or USB port). The input operating
range is 4.35V to 6.6V (bq24072, bq24073, bq24075, and bq24079) or 4.35V to 10.5V (bq23074). The input
can accept voltages up to 26V without damage but operation is suspended. Connect bypass capacitor 1 µF
to 10 µF to VSS.
13
13
13
I
6
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PIN FUNCTIONS (continued)
PIN
NO.
'74
I/O
DESCRIPTION
NAME
'72, '73
'75, '79
Timer Programming Input. TMR controls the pre-charge and fast-charge safety timers. Connect TMR to VSS
to disable all safety timers. Connect a 18 kΩ to 72 kΩ resistor between TMR and VSS to program the timers
a desired length. Leave TMR unconnected to set the timers to the default values.
TMR
14
14
–
14
I
I
I
I
Termination Disable Input. Connect TD high to disable charger termination. Connect TD to VSS to enable
charger termination. TD is checked during startup only and cannot be changed during operation. See the TD
section in this datasheet for a description of the behavior when termination is disabled. TD is internally pulled
down to VSS with ~285 kΩ. Do not leave TD unconnected to ensure proper operation.
TD
15
–
–
–
Termination Current Programming Input. Connect a 0 Ω to 15 kΩ resistor from ITERM to VSS to program the
termination current. Leave ITERM unconnected to set the termination current to the default 10% termination
threshold.
ITERM
SYSOFF
15
–
System Enable Input. Connect SYSOFF high to turn off the FET connecting the battery to the system output.
When an adapter is connected, charging is also disabled. Connect SYSOFF low for normal operation.
SYSOFF is internally pulled up to VBAT through a large resistor (~5 MΩ). Do not leave SYSOFF unconnected
to ensure proper operation.
–
15
Fast Charge Current Programming Input. Connect a 590 Ω to 3 kΩ resistor from ISET to VSS to program the
fast charge current level. Charging is disabled if ISET is left unconnected. While charging, the voltage at ISET
reflects the actual charging current and can be used to monitor charge current. See the SubSec2 1.1 section
for more details.
ISET
16
16
16
I/O
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device.
The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not
use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all
times.
Thermal
Pad
Table 1. EN1/EN2 Settings
EN2
EN1
Maximum input current into IN pin
100 mA. USB100 mode
0
0
1
1
0
1
0
1
500 mA. USB500 mode
Set by an external resistor from ILIM to VSS
Standby (USB suspend mode)
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SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
SIMPLIFIED BLOCK DIAGRAM
250mV
VBAT
VO(SC1)
OUT-SC1
OUT-SC2
tDGL(SC2)
Q1
IN
OUT
ISET
EN2
Short Detect
225mV
Precharge
VIN-LOW
2.25V
Fastcharge
USB100
USB500
TJ
ILIM
VREF- ILIM
TJ(REG)
USB-susp
Short Detect
VDPPM
VO(REG)
VOUT
Q2
EN2
EN1
VBAT(REG)
BAT
VBAT
VOUT
CHARGEPUMP
SYSOFF
bq24075
bq24079
IBIAS- ITERM
40mV
Supplement
VLOWV
225mV
(’72, ’73, ’75)
ITERM
bq24074
VRCH
VBAT(SC)
~3V
I TERM-floating
VIN
INTC
BAT-SC
VBAT + V
IN-DT
tDGL(NO-IN)
VHOT
TS
tDGL(TS)
tDGL(PGOOD)
Charge Control
VUVLO
VOVP
VCOLD
tBLK(OVP)
VDIS(TS)
EN1
EN2
USB Suspend
TD
(bq24072,
bq24073)
CE
CHG
Halt timers
Reset timers
VIPRECHG
VICHG
Dynamically
Controlled
Oscillator
PGOOD
VISET
Fast-Charge
Timer
Timer fault
TMR
Pre-Charge
Timer
~100mV
Timers disabled
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www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
TYPICAL CHARACTERISTICS
VIN = 6V, EN1=1, EN2=0, bq24073 application circuit, TA = 25°C, unless otherwise noted.
ADAPTER PLUG-IN
BATTERY CONNECTED
BATTERY DETECTION
BATTERY INSERTED
BATTERY DETECTION
BATTERY REMOVED
RLOAD = 10Ω
VIN
VCHG
5 V/div
VCHG
5 V/div
1 A/div
5 V/div
1 A/div
Charging Initiated
VOUT
4.4 V
500 mV/div
5 V/div
VBAT
3.6 V
IBAT
IBAT
VPGOOD
2 V/div
2 V/div
Battery
Removed
VBAT
VBAT
500 mA/div
IBAT
Battery Inserted
Battery Detection Mode
400 ms/div
Battery Detection Mode
400 ms/div
4 ms/div
Figure 1.
Figure 2.
Figure 3.
ENTERING AND EXITING BATTERY
SUPPLEMENT MODE
RLOAD = 25ΩTO 4.5Ω
bq24074
ENTERING AND EXITING BATTERY
SUPPLEMENT MODE
RLOAD = 20ΩTO 4.5Ω
bq24072
ENTERING AND EXITING DPPM
MODE
RLOAD = 20Ω to 9Ω
1 A/div
IOUT
IOUT
500 mA/div
IOUT
1 A/div
500 mA/div
IBAT
IBAT
Supplement Mode
500 mA/div
Supplement Mode
IBAT
500 mA/div
200 mV/div
VOUT
3.825 V
200 mV/div
VOUT
4.4 V
VBAT
VOUT
4.4 V
VBAT
3.8 V
3.6 V
500 mV/div
Tracking to VBAT +225 mV
1 ms/div
400 ms/div
1 ms/div
Figure 4.
Figure 5.
Figure 6.
SYSTEM ON/OFF WITH INPUT
CONNECTED
OVP FAULT
VIN = 6V to 15V
RLOAD = 10Ω
VIN = 6V
CHARGER ON/OF USING CE
bq24075, bq24079
VCE
5 V/div
VSYSOFF
5 V/div
10 V/div
VIN
VCHG
5 V/div
1 V/div
VOUT
VOUT
5.5 V
4.4 V
VBAT
2 V/div
VBAT
VBAT
4 V
500 mV/div
3.6 V
4.2 V
Mandatory Precharge
500 mA/div
500 mA/div
IBAT
IBAT
1 A/div
IBAT
400 ms/div
10 ms/div
40 ms/div
Figure 7.
Figure 8.
Figure 9.
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SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
VIN = 6V, EN1=1, EN2=0, bq24073 application circuit, TA = 25°C, unless otherwise noted.
SYSTEM ON/OFF WITH INPUT NOT
CONNECTED
VIN = 0V
DROPOUT VOLTAGE
vs
bq24075, bq24079
THERMAL REGULATION
TEMPERATURE
600
500
400
0.7
0.6
IL = 1 A
VSYSOFF
5 V/div
0.5
0.4
0.3
VBAT
4 V
2 V/div
300
200
VOUT
Battery Powering
System
0.2
0.1
0
System Power Off
IBAT
500 mA/div
100
0
4 ms/div
120
125
130
135
140
145
125
0
25
100
50
75
Temperature - o
C
TJ - Junction Temperature - °C
Figure 10.
Figure 11.
bq24072
Figure 12.
DROPOUT VOLTAGE
vs
TEMPERATURE
NO INPUT SUPPLY
bq24072
OUTPUT REGULATION VOLTAGE
OUTPUT REGULATION VOLTAGE
vs
vs
BATTERY VOLTAGE
TEMPERATURE
4.6
4.4
120
3.80
3.78
3.76
3.74
3.72
3.70
3.68
3.66
3.64
3.62
3.60
VIN = 5 V
VIN = 5 V,
VBAT = 3.5 V,
IL = 1 A
IL = 1 A
100
80
4.2
4
VBAT = 3 V
3.8
3.6
3.4
3.2
3
60
40
VBAT = 3.9 V
20
0
125
2
0
50
75
100
3
4.5
25
2.5
3.5
4
0
25
50
75
100
125
TJ - Junction Temperature - °C
VBAT - Battery Voltage - V
TJ - Junction Temperature - °C
Figure 13.
Figure 14.
Figure 15.
bq24073/ 74
bq24075, bq24079
OUTPUT REGULATION VOLTAGE
OUTPUT REGULATION VOLTAGE
BAT REGULATION VOLTAGE
vs
vs
vs
TEMPERATURE
TEMPERATURE
TEMPERATURE
4.45
4.43
4.40
4.38
4.35
5.75
5.70
5.65
5.60
4.210
4.205
4.200
4.195
VIN = 6 V,
IL = 1 A
VIN = 5 V,
IL = 1 A
5.55
5.50
5.45
5.40
4.190
4.185
4.180
5.35
4.33
4.30
5.30
5.25
0
50
75
100
125
25
0
25
50
75
100
125
30
25
10
15
20
0
5
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 16.
Figure 17.
Figure 18.
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www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
VIN = 6V, EN1=1, EN2=0, bq24073 application circuit, TA = 25°C, unless otherwise noted.
bq24072/ 73/ 75/ 79
OVERVOLTAGE PROTECTION
THRESHOLD
bq24074
OVERVOLTAGE PROTECTION
THRESHOLD
bq24074
INPUT CURRENT LIMIT
vs
vs
vs
TEMPERATURE
TEMPERATURE
INPUT VOLTAGE
6.70
6.65
6.60
6.55
10.70
10.65
10.60
10.55
10.50
10.45
800
700
600
500
10.5 V
RILIM
6.6 V
VI Rising
VI Rising
USB500
400
300
VI Falling
10.40
10.35
10.30
10.25
10.20
VI Falling
200
6.50
6.45
USB100
100
0
5
6
7
8
9
10
0
25
75
125
0
25
50
75
100
125
50
100
VI - Input Voltage - V
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 19.
Figure 20.
Figure 21.
FASTCHARGE CURRENT
vs
BATTERY VOLTAGE
FASTCHARGE CURRENT
vs
BATTERY VOLTAGE
PRECHARGE CURRENT
vs
BATTERY VOLTAGE
310
305
300
295
290
105
104
1.05
1.03
RISET = 900 W
RISET = 900 W
RISET = 3 kW
103
102
101
100
99
1.01
0.99
98
0.97
0.95
97
285
280
96
95
3.6
3
3.8
2
2.2
2.4
2.6
2.8
3
3.4
4
4.2
3
3.2
3.4
3.6
3.8
4
4.2
3.2
VBAT - Battery Voltage - V
VBAT - Battery Voltage - V
VBAT - Battery Voltage - V
Figure 22.
Figure 23.
Figure 24.
PRECHARGE CURRENT
vs
BATTERY VOLTAGE
31.5
RISET = 3 kW
31
30.5
30
29.5
29
28.5
2
2.2
2.4
2.6
2.8
3
VBAT - Battery Voltage - V
Figure 25.
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APPLICATION CIRCUITS
VIN = UVLO to VOVP, IFASTCHG = 800mA, IIN(MAX) = 1.3A, Battery Temperature Charge Range = 0°C to 50°C, 6.25
hour Fastcharge Safety Timer
R4
1.5 kW
R5
1.5 kW
SYSTEM
Adaptor
DC+
IN
OUT
C2
4.7 mF
C1
1 mF
GND
VSS
bq24072
bq24073
HOST
EN2
EN1
TS
TD
CE
BAT
C3
4.7 mF
PACK+
TEMP
R1
46.4 kW
R2
1.18 kW
R3
1.13 kW
PACK-
Figure 26. Using bq24072/ bq24073 in a Host Controlled Charger Application
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VIN = UVLO to VOVP, IFASTCHG = 800mA, IIN(MAX) = 1.3A, ITERM = 110mA, Battery Temperature Charge
Range = 0°C to 50°C, Safety Timers disabled
R4
R5
1.5 kW
1.5 kW
SYSTEM
Adaptor
DC+
IN
OUT
C2
4.7 mF
C1
1 mF
GND
VSS
bq24074
EN2
EN1
TS
TMR
CE
BAT
C3
4.7mF
PACK+
TEMP
R1
4.12 kW
R2
1.18 kW
R3
1.13 kW
PACK-
Figure 27. Using bq24074 in a Stand Alone Charger Application
VIN = UVLO to VOVP, IFASTCHG = 800mA, IIN(MAX) = 1.3A, Battery Temperature Charge Range = 0°C to 50°C,
6.25 hour Fastcharge Safety Timer
R4
1.5 kW
R5
1.5 kW
SYSTEM
Adaptor
DC+
IN
OUT
C2
4.7 mF
C1
1 mF
GND
VSS
bq24075
bq24079
HOST
EN2
EN1
TS
SYSOFF
CE
BAT
C3
4.7 mF
PACK+
TEMP
R1
46.4 kW
R2
1.18 kW
R3
1.13 kW
PACK-
Figure 28. Using bq24075 or bq24079 to Disconnect the Battery from the System
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EXPLANATION OF DEGLITCH TIMES AND COMPARATOR HYSTERESIS
Figures not to scale
V
OVP
V
- V
hys(OVP)
OVP
V
IN
Typical Input Voltage
Operating Range
t < t
DGL(OVP)
V
+ V
IN(DT)
BAT
V
+ V
- V
IN(DT) hys(INDT)
BAT
UVLO
UVLO - V
hys(UVLO)
PGOOD
t
DGL(PGOOD)
t
t
DGL(OVP)
DGL(NO-IN)
t
DGL(PGOOD)
Figure 29. Power-Up, Power-Down, Power Good Indication
t
V
DGL1(LOWV)
BAT
V
LOWV
t < t
DGL1(LOWV)
t
DGL2(LOWV)
t
t < t
DGL2(LOWV)
DGL1(LOWV)
I
CHG
Fast-Charge
Fast-Charge
Pre-Charge
I
PRE-CHG
Pre-Charge
Figure 30. Pre- to Fast-Charge, Fast- to Pre-Charge Transition – tDGL1(LOWV), tDGL2(LOWV)
V
BAT
V
RCH
Re-Charge
t < t
DGL(RCH)
t
DGL(RCH)
Figure 31. Recharge – tDGL(RCH)
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Turn
Q2 OFF
Force
Q2 ON
Force
Q2 ON
Turn
Q2 OFF
t
t
REC(SC2)
REC(SC2)
V
- V
OUT
BAT
Recover
V
O(SC2)
t
t
t < t
t < t
DGL(SC2)
DGL(SC2)
DGL(SC2)
DGL(SC2)
Figure 32. OUT Short-Circuit – Supplement Mode
V
COLD
V
- V
hys(COLD)
COLD
Suspend
Charging
Resume
Charging
t < t
t
DGL(TS)
DGL(TS)
V
TS
V
- V
hys(HOT)
HOT
V
HOT
Figure 33. Battery Pack Temperature Sensing – TS Pin. Battery Temperature Increasing
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DETAILED FUNCTIONAL DESCRIPTION
The bq2407x devices are integrated Li-Ion linear chargers and system power path management devices targeted
at space-limited portable applications. The device powers the system while simultaneously and independently
charging the battery. This feature reduces the number of charge and discharge cycles on the battery, allows for
proper charge termination and enables the system to run with a defective or absent battery pack. It also allows
instant system turn-on even with a totally discharged battery. The input power source for charging the battery
and running the system can be an AC adapter or a USB port. The devices feature Dynamic Power Path
Management (DPPM), which shares the source current between the system and battery charging, and
automatically reduces the charging current if the system load increases. When charging from a USB port, the
input dynamic power management (VIN-DPM) circuit reduces the input current if the input voltage falls below a
threshold, preventing the USB port from crashing. The power-path architecture also permits the battery to
supplement the system current requirements when the adapter cannot deliver the peak system currents.
UNDERVOLTAGE LOCKOUT (UVLO)
The bq2407X family remains in power down mode when the input voltage at the IN pin is below the undervoltage
threshold (UVLO).
During the power down mode the host commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1
FET connected between IN and OUT pins is off, and the status outputs CHG and PGOOD are high impedance.
The Q2 FET that connects BAT to OUT is ON. (If SYSOFF is high, Q2 is off). During power down mode, the
VOUT(SC2) circuitry is active and monitors for overload conditions on OUT.
POWER ON
When VIN exceeds the UVLO threshold, the bq2407x powers up. While VIN is below VBAT + VIN(DT), the host
commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT
pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to
OUT is ON. (If SYSOFF is high, Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for
overload conditions on OUT.
Once VIN rises above VBAT + VIN(DT), PGOOD is driven low to indicate the valid power status and the CE, EN1,
and EN2 inputs are read. The device enters standby mode if (EN1 = EN2 = HI) or if an input overvoltage
condition occurs. In standby mode, Q1 is OFF and Q2 is ON so OUT is connected to the battery input. (If
SYSOFF is high, FET Q2 is off). During this mode, the VOUT(SC2) circuitry is active and monitors for overload
conditions on OUT.
When the input voltage at IN is within the valid range: VIN > UVLO AND VIN > VBAT + VIN(DT) AND VIN < VOVP, and
the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) ≠ (HI, HI)] all internal
timers and other circuit blocks are activated. The device then checks for short-circuits at the ISET and ILIM pins.
If no short conditions exists, the device switches on the input FET Q1 with a 100mA current limit to checks for a
short circuit at OUT. When VOUT is above VSC, the FET Q1 switches to the current limit threshold set by EN1,
EN2 and RILIM and the device enters into the normal operation. During normal operation, the system is powered
by the input source (Q1 is regulating), and the device continuously monitors the status of CE, EN1 and EN2 as
well as the input voltage conditions.
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PGOOD = Hi-Z
CHG = Hi-Z
BATTFET ON
UVLO<VIN<VOVP
and
VIN>VBAT+VIN(DT)
No
Yes
PGOOD = Low
Yes
Yes
EN1=EN2=1
No
ILIM or ISET short?
No
Begin Startup
IIN(MAX) 100mA
Yes
VOUT short?
No
Input Current
Limit set by EN1
and EN2
No
CE = Low
Yes
Begin Charging
Figure 34. Startup Flow Diagram
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SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
OVERVOLTAGE PROTECTION (OVP)
The bq2407x accepts inputs up to 28V without damage. Additionally, an overvoltage protection (OVP) circuit is
implemented that shuts off the internal LDO and discontinues charging when VIN > VOVP for a period long than
tDGL(OVP). When in OVP, the system output (OUT) is connected to the battery and PGOOD is high impedance.
Once the OVP condition is removed, a new power on sequence starts (See the SubSec2 0.1 section). The safety
timers are reset and a new charge cycle will be indicated by the CHG output.
DYNAMIC POWER-PATH MANAGEMENT
The bq2407x features an OUT output that powers the external load connected to the battery. This output is
active whenever a source is connected to IN or BAT. The following sections discuss the behavior of OUT with a
source connected to IN to charge the battery and a battery source only.
INPUT SOURCE CONNECTED (ADAPTER or USB)
With a source connected, the dynamic power-path management (DPPM) circuitry of the bq2407x monitors the
input current continuously. The OUT output for the bq24073/ 74/ 75/ 79 is regulated to a fixed voltage (VO(REG)).
For the bq24072, OUT is regulated to 200mV above the voltage at BAT. When the BAT voltage falls below 3.2V,
OUT is clamped to 3.4V. This allows for proper startup of the system load even with a discharged battery. The
current into IN is shared between charging the battery and powering the system load at OUT. The bq2407x has
internal selectable current limits of 100mA (USB100) and 500mA (USB500) for charging from USB ports, as well
as a resistor-programmable input current limit.
The bq2407x is USB IF compliant for the inrush current testing. The USB spec allows up to 10µF to be hard
started, which establishes 50µC as the maximum inrush charge value when exceeding 100mA. The input current
limit for the bq2407x prevents the input current from exceeding this limit, even with system capacitances greater
than 10µF. Note that the input capacitance to the device must be selected small enough to prevent a violation
(<10µF), as this current is not limited. Figure 35 demonstrates the startup of the bq2407x and compares it to the
USB-IF specification.
10μC
50μC
100 μs/div
Figure 35. USB-IF Inrush Current Test
The input current limit selection is controlled by the state of the EN1 and EN2 pins as shown in Table 1. When
using the resistor-programmable current limit, the input current limit is set by the value of the resistor connected
from the ILIM pin to VSS, and is given by the equation:
IIN-MAX = KILIM/RILIM
The input current limit is adjustable up to 1.5A. The valid resistor range is 1.1 kΩ to 8 kΩ.
When the IN source is connected, priority is given to the system load. The DPPM and Battery Supplement
modes are used to maintain the system load. Figure 37 and Figure 38 illustrate examples of the DPPM and
supplement modes. These modes are explained in detail in the following sections.
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Input DPM Mode (VIN-DPM)
The bq2407x utilizes the VIN-DPM mode for operation from current-limited USB ports. When EN1 and EN2 are
configured for USB100 (EN2=0, EN1=0) or USB500 (EN2=0, EN2=1) modes, the input voltage is monitored. If
VIN falls to VIN-DPM, the input current limit is reduced to prevent the input voltage from falling further. This prevents
the bq2407x from crashing poorly designed or incorrectly configured USB sources. Figure 36 shows the VIN-DPM
behavior to a current limited source. In this figure, the input source has a 400mA current limit and the device is in
USB500 mode (EN1=1, EN2=0).
I
OUT
200mA/div
Input collapses
V
IN
(5V)
500mV/div
Input regulated to V
IN_DPM
USB500 Current Limit
200mA/div
200mA/div
I
Input current limit is
reduced to prevent
crashing the supply
IN
I
BAT
4 ms/div
Figure 36. VIN-DPM Waveform
DPPM Mode
When the sum of the charging and system load currents exceeds the maximum input current (programmed with
EN1, EN2 and ILIM pins), the voltage at OUT decreases. Once the voltage on the OUT pin falls to VDPPM, the
bq2407x enters DPPM mode. In this mode, the charging current is reduced as the OUT current increases in
order to maintain the system output. Battery termination is disabled while in DPPM mode.
Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at OUT reduces further. When the OUT voltage drops below the
VBSUP1 threshold, the battery supplements the system load. The battery stops supplementing the system load
when the voltage at OUT rises above the VBSUP2 threshold.
During supplement mode, the battery supplement current is not regulated (BAT-FET is fully on), however there is
a short circuit protection circuit built in. Figure 5 demonstrates supplement mode. If during battery supplement
mode, the voltage at OUT drops VO(SC2) below the BAT voltage, the OUT output is turned off if the overload
exists after tDGL(SC2). The short circuit recovery timer then starts counting. After tREC(SC2), OUT turns on and
attempts to restart. If the short circuit remains, OUT is turned off and the counter restarts. Battery termination is
disabled while in supplement mode.
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1200 mA
900 mA
A
400 mA
0 mA
900 mA
500 mA
0 mA
500 mA
0 mA
-300 mA
3.8 V
3.7 V
~3.6 V
DPPM Loop Active
Supplement Mode
Figure 37. bq24072 DPPM and Battery Supplement Modes (VOREG = VBAT + 225mV, VBAT = 3.6V)
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1200 mA
900 mA
A
400 mA
0 mA
900 mA
500 mA
0 mA
500 mA
0 mA
-300 mA
4.4 V
4.3 V
DPPM Loop Active
Supplement Mode
~3.6 V
Figure 38. bq24073 DPPM and Battery Supplement Modes (VOREG = 4.4V, VBAT = 3.6V)
INPUT SOURCE NOT CONNECTED
When no source is connected to the IN input, OUT is powered strictly from the battery. During this mode the
current into OUT is not regulated, similar to Battery Supplement Mode, however the short circuit circuitry is
active. If the OUT voltage falls below the BAT voltage by 250mV for longer than tDGL(SC2), OUT is turned off. The
short circuit recovery timer then starts counting. After tREC(SC2), OUT turns on and attempts to restart. If the short
circuit remains, OUT is turned off and the counter restarts. This ON/OFF cycle continues until the overload
condition is removed.
BATTERY CHARGING
Set CE low to initiate battery charging. First, the device checks for a short-circuit on the BAT pin by sourcing
IBAT(SC) to the battery and monitoring the voltage. When the BAT voltage exceeds VBAT(SC), the battery charging
continues. The battery is charged in three phases: conditioning pre-charge, constant current fast charge (current
regulation) and a constant voltage tapering (voltage regulation). In all charge phases, an internal control loop
monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is
exceeded.
Figure 39 illustrates a normal Li-Ion charge cycle using the bq2407x:
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PRECHARGE
CC FAST CHARGE
CV TAPER
DONE
V
BAT(REG)
I
O(CHG)
Battery Current
Battery Voltage
V
LOWV
CHG = Hi-z
I
(PRECHG)
I
(TERM)
Figure 39. Typical Charge Cycle
In the pre-charge phase, the battery is charged at with the pre-charge current (IPRECHG). Once the battery voltage
crosses the VLOWV threshold, the battery is charged with the fast-charge current (ICHG). As the battery voltage
reaches VBAT(REG), the battery is held at a constant voltage of VBAT(REG) and the charge current tapers off as the
battery approaches full charge. When the battery current reaches ITERM, the CHG pin indicates charging done by
going high-impedance.
Note that termination detection is disabled whenever the charge rate is reduced because of the actions of the
thermal loop, the DPPM loop or the VIN(LOW) loop.
The value of the fast-charge current is set by the resistor connected from the ISET pin to VSS, and is given by
the equation
ICHG = KISET/RISET
The charge current limit is adjustable up to 1.5A. The valid resistor range is 590Ω to 3 kΩ. Note that if ICHG is
programmed as greater than the input current limit, the battery will not charge at the rate of ICHG, but at the
slower rate of IIN(MAX) (minus the load current on the OUT pin, if any). In this case, the charger timers will be
proportionately slowed down.
CHARGE CURRENT TRANSLATOR
When the charger is enabled, internal circuits generate a current proportional to the charge current at the ISET
input. The current out of ISET is 1/400 (±10%) of the charge current. This current, when applied to the external
charge current programming resistor, RISET, generates an analog voltage that can be monitored by an external
host to calculate the current sourced from BAT.
VISET = ICHARGE / 400 × RISET
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Begin Charging
Yes
Battery short detected?
No
Start Precharge
CHG = Low
No
No
tPRECHARGE
Elapsed?
VBAT > VLOWV
Yes
End Charge
Flash CHG
Start Fastcharge
CHARGE set by ISET
I
No
No
tFASTCHARGE
Elapsed?
IBAT < ITERM
Yes
End Charge
Flash CHG
Charge Done
CHG = Hi-Z
TD = Low
(’72, ’73 Only)
No
(’74, ’75 = YES)
Yes
Termination Reached
BATTFET Off
Wait for VBAT < VRCH
No
VBAT < VRCH
Yes
Run Battery Detection
No
Battery Detected?
Yes
Figure 40. Battery Charging Flow Diagram
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ADJUSTABLE TERMINATION THRESHOLD (ITERM Input, bq24074)
The termination current threshold in the bq24074 is user-programmable. Set the termination current by
connecting a resistor from ITERM to VSS. For USB100 mode (EN1 = EN2 = Low), the termination current value
is calculated as:
ITERM = 0.01 × RITERM/ RISET
In the other input current limit modes (EN1 ≠ EN2), the termination current value is calculated as:
ITERM = 0.03 × RITERM/ RISET
The termination current is programmable up to 50% of the fastcharge current. The RITERM resistor must be less
than 15 kΩ. Leave ITERM unconnected to select the default internally set termination current.
TERMINATION DISABLE (TD Input, bq24072, bq24073)
The bq24072 and bq24073 contain a TD input that allows termination to be enabled/ disabled. Connect TD to a
logic high to disable charge termination. When termination is disabled, the device goes through the pre-charge,
fast-charge and CV phases, then remains in the CV phase. During the CV phase, the charger maintains the
output voltage at BAT equal to VBAT(REG), and charging current does not terminate. The charge current is set by
ICHG or IINmax, whichever is less. Battery detection is not performed. The CHG output is high impedance once
the current falls below ITERM and does not go low until the input power or CE are toggled. When termination is
disabled, the pre-charge and fast-charge safety timers are also disabled. Battery pack temperature sensing (TS
pin functionality) is disabled if the TD pin is high and the TS pin is unconnected or pulled up to VIN.
BATTERY DETECTION AND RECHARGE
The bq2407x automatically detects if a battery is connected or removed. Once a charge cycle is complete, the
battery voltage is monitored. When the battery voltage falls below VRCH, the battery detection routine is run.
During battery detection, current (IBAT(DET)) is pulled from the battery for a duration tDET to see if the voltage on
BAT falls below VLOWV. If not, charging begins. If it does, then it indicates that the battery is missing or the
protector is open. Next, the precharge current is applied for tDET to close the protector if possible. If VBAT < VRCH
,
then the protector closed and charging is initiated. If VBAT > VRCH, then the battery is determined to be missing
and the detection routine continues.
BATTERY DISCONNECT (SYSOFF Input, bq24075, bq24079)
The bq24075 and bq24079 feature a SYSOFF input that allows the user to turn the FET Q2 off and disconnect
the battery from the OUT pin. This is useful for disconnecting the system load from the battery, factory
programming where the battery is not installed or for host side impedance track fuel gauging, such as bq27500,
where the battery open circuit voltage level must be detected before the battery charges or discharges. The
/CHG output remains low when SYSOFF is high. Connect SYSOFF to VSS, to turn Q2 on for normal operation.
SYSOFF is internally pulled to VBAT through ~5 MΩ resistor.
DYNAMIC CHARGE TIMERS (TMR Input)
The bq2407x devices contain internal safety timers for the pre-charge and fast-charge phases to prevent
potential damage to the battery and the system. The timers begin at the start of the respective charge cycles.
The timer values are programmed by connecting a resistor from TMR to VSS. The resistor value is calculated
using the following equation:
tPRECHG = KTMR × RTMR
tMAXCHG = 10 × KTMR × RTMR
Leave TMR unconnected to select the internal default timers. Disable the timers by connecting TMR to VSS.
Note that timers are suspended when the device is in thermal shutdown, and the timers are slowed proportionally
to the charge current when the device enters thermal regulation. For the bq24072 and bq24073, the timers are
disabled when TD is connected to a high logic level.
During the fast charge phase, several events increase the timer durations.
1. The system load current activates the DPPM loop which reduces the available charging current
2. The input current is reduced because the input voltage has fallen to VIN(LOW)
3. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG)
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During each of these events, the internal timers are slowed down proportionately to the reduction in charging
current. For example, if the charging current is reduced by half for two minutes, the timer clock is reduced to half
the frequency and the counter counts half as fast resulting in only one minute of "counting" time.
If the pre charge timer expires before the battery voltage reaches VLOWV, the bq2407x indicates a fault condition.
Additionally, if the battery current does not fall to ITERM before the fast charge timer expires, a fault is indicated.
The CHG output flashes at approximately 2 Hz to indicate a fault condition. The fault condition is cleared by
toggling CE or the input power, entering/ exiting USB suspend mode, or an OVP event.
STATUS INDICATORS (PGOOD, CHG)
The bq2407x contains two open-drain outputs that signal its status. The PGOOD output signals when a valid
input source is connected. PGOOD is low when (VBAT + VIN(DT)) < VIN < VOVP. When the input voltage is outside
of this range, PGOOD is high impedance.
The charge cycle after power-up, CE going low, or exiting OVP is indicated with the CHG pin on (low - LED on),
whereas all refresh (subsequent) charges will result in the CHG pin off (open - LED off). In addition, the CHG
signals timer faults by flashing at approximately 2 Hz.
PGOOD STATUS INDICATOR
Input State
VIN < VUVLO
PGOOD Output
Hi impedance
Hi impedance
Low
VUVLO < VIN < VIN(DT)
VIN(DT) < VIN < VOVP
VIN > VOVP
Hi impedance
CHG STATUS INDICATOR
Charge State
Charging
CHG Output
Low (for first charge cycle)
Flashing at 2Hz
Charging suspended by thermal loop
Safety timers expired
Charging done
Recharging after termination
IC disabled or no valid input power
Battery absent
Hi impedance
THERMAL REGULATION AND THERMAL SHUTDOWN
The bq2407x contain a thermal regulation loop that monitors the die temperature. If the temperature exceeds
TJ(REG), the device automatically reduces the charging current to prevent the die temperature from increasing
further. In some cases, the die temperature continues to rise despite the operation of the thermal loop,
particularly under high VIN and heavy OUT system load conditions. Under these conditions, if the die
temperature increases to TJ(OFF), the input FET Q1 is turned OFF. FET Q2 is turned ON to ensure that the
battery still powers the load on OUT. Once the device die temperature cools by TJ(OFF-HYS), the input FET Q1 is
turned on and the device returns to thermal regulation. Continuous overtemperature conditions result in a
"hiccup" mode. During thermal regulation, the safety timers are slowed down proportionately to the reduction in
current limit.
Note that this feature monitors the die temperature of the bq2407x. This is not synonymous with ambient
temperature. Self heating exists due to the power dissipated in the IC because of the linear nature of the battery
charging algorithm and the LDO associated with OUT. A modified charge cycle with the thermal loop active is
shown in Figure 41. Battery termination is disabled during thermal regulation.
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PRECHARGE
THERMAL
CC FAST
CHARGE
CV TAPER
DONE
REGULATION
V
I
O(REG)
O(CHG)
Battery Voltage
Battery Current
V
(LOWV)
HI-z
I
(PRECHG)
I
(TERM)
T
J(REG)
IC Junction Temperature, T
J
Figure 41. Charge Cycle Modified by Thermal Loop
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BATTERY PACK TEMPERATURE MONITORING
The bq2407x features an external battery pack temperature monitoring input. The TS input connects to the NTC
thermistor in the battery pack to monitor battery temperature and prevent dangerous over-temperature
conditions. During charging, INTC is sourced to TS and the voltage at TS is continuously monitored. If, at any
time, the voltage at TS is outside of the operating range (VCOLD to VHOT), charging is suspended. The timers
maintain their values but suspend counting. When the voltage measured at TS returns to within the operation
window, charging is resumed and the timers continue counting. When charging is suspended due to a battery
pack temperature fault, the CHG pin remains low and continues to indicate charging.
For the bq24072 and bq24073, battery pack temperature sensing is disabled when termination is disabled (TD =
High) and the voltage at TS is greater than VDIS(TS). For applications that do not require the TS monitoring
function, connect a 10kΩ resistor from TS to VSS to set the TS voltage at a valid level and maintain charging.
The allowed temperature range for 103AT-2 type thermistor is 0°C to 50°C. However, the user may increase the
range by adding two external resistors. See Figure 42 for the circuit details. The values for RT1 and RT2 are
calculated using the following equations:
-1500μA ´(RHOT + RCOLD) ± 20 ´ 5625μA2 ´ (RCOLD-RHOT)2 + 105μW ´(RCOLD -RHOT)
RT1 =
3000μA
(2)
1 V ´ (R1 + RHOT)
RT2 =
250 μA ´ RT1 + 250 μA ´ RHOT - 1 V
(3)
RHOT and RCOLD are the thermistor resistance at the desired hot and cold temperatures, respectively. Note
that the temperature window cannot be tightened more than using only the thermistor connected to TS, it
can only be extended.
INTC
bq2407x
RT1
PACK+
TS
TEMP
+
VCOLD
RT2
PACK-
+
VHOT
Figure 42. Extended TS Pin Thresholds
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APPLICATIONS INFORMATION
bq2407x CHARGER DESIGN EXAMPLE
See Figure 26 to Figure 28 for Schematics of the Design Example.
Requirements
•
•
•
•
•
•
Supply voltage = 5V
Fast charge current of approximately 800 mA; ISET - pin 16
Input Current Limit =1.3A; ILIM - pin 12
Termination Current Threshold = 110mA; ITERM – pin 15 (bq24074 only)
Safety timer duration, Fast-Charge = 6.25 hours; TMR – pin 14
TS – Battery Temperature Sense = 10kΩ NTC (103AT-2)
Calculations
Program the Fast Charge Current (ISET):
RISET = KISET / ICHG
KISET = 890 AΩ from the electrical characteristics table.
RISET = 890AΩ/0.8A = 1.1125 kΩ
Select the closest standard value, which for this case is 1.13kΩ. Connect this resistor between ISET (pin 16) and
VSS
.
Program the Input Current Limit (ILIM)
RILIM = KILIM / II_MAX
KILIM = 1550 AΩ from the electrical characteristics table.
RISET = 1550AΩ / 1.3A = 1.192 kΩ
Select the closest standard value, which for this case is 1.18 kΩ. Connect this resistor between ILIM (pin 12) and
VSS
.
Program the Termination Current Threshold (ITERM) (bq24074 only)
RITERM = ITERM × RISET / 0.030
RISET = 1.13 kΩ from the above calculation.
RITERM = 110mA × 1.13 kΩ / 0.030 = 4.143 kΩ
Select the closest standard value, which for this case is 4.12kΩ. Connect this resistor between ITERM (pin 15)
and VSS. Note that when in USB100 mode (EN1 = EN2 = VSS), the termination threshold is 1/3 of the normal
threshold.
Program 6.25-hour Fast-Charge Safety Timer (TMR)
RTMR = tMAXCHG / (10 × KTMR
)
KTMR = 48 s/kΩ from the electrical characteristics table.
RTMR = (6.25 hr × 3600 s/hr) / (10 × 45 s/kΩ) = 46.8kΩ
Select the closest standard value, which for this case is 46.4 kΩ. Connect this resistor between TMR (pin 2) and
VSS
.
TS Function
Use a 10kΩ NTC thermistor in the battery pack (103AT-2). For applications that do not require the TS monitoring
function, connect a 10kΩ resistor from TS to VSS to set the TS voltage at a valid level and maintain charging.
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CHG and PGOOD
LED Status: connect a 1.5kΩ resistor in series with a LED between OUT and CHG to indicate charging status.
Connect a 1.5kΩ resistor in series with a LED between OUT and PGOOD to indicate when a valid input source is
connected.
Processor Monitoring Status: connect a pullup resistor (on the order of 100 kΩ) between the processor’s power
rail and CHG and PGOOD
Termination Disable (TD) (bq24072, bq24073 only)
Connect TD high to disable termination. Connect TD low to enable termination.
System ON/OFF (SYSOFF) (bq24075 or bq24079 only)
Connect SYSOFF high to disconnect the battery from the system load. Connect SYSOFF low for normal
operation
SELECTING IN, OUT AND BAT pin CAPACITORS
In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin,
input, output and battery pins. Using the values shown on the application diagram, is recommended. After
evaluation of these voltage signals with real system operational conditions, one can determine if capacitance
values can be adjusted toward the minimum recommended values (DC load application) or higher values for fast
high amplitude pulsed load applications. Note if designed high input voltage sources (bad adaptors or wrong
adaptors), the capacitor needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values
so a 16V capacitor may be adequate for a 30V transient (verify tested rating with capacitor manufacturer).
THERMAL PACKAGE
The bq24072/3/4/5 family is packaged in a thermally enhanced MLP package. The package includes a thermal
pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad
should be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in the
application note entitled: QFN/SON PCB Attachment Application Note (SLUA271). The most common measure
of package thermal performance is thermal impedance (θJA ) measured (or modeled) from the chip junction to the
air surrounding the package surface (ambient). The mathematical expression for θJA is:
θJA = (TJ - T) / P
Where:
TJ = chip junction temperature
T = ambient temperature
P = device power dissipation
Factors that can influence the measurement and calculation of θJA include:
1. Whether or not the device is board mounted
2. Trace size, composition, thickness, and geometry
3. Orientation of the device (horizontal or vertical)
4. Volume of the ambient air surrounding the device under test and airflow
5. Whether other surfaces are in close proximity to the device being tested
Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage
increases to ≈3.4V within the first 2 minutes. The thermal time constant of the assembly typically takes a few
minutes to heat up so when doing maximum power dissipation calculations, 3.4V is a good minimum voltage to
use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the
PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of
time. The fast charge current will start to taper off if the part goes into thermal regulation.
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The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from the following equation when a battery pack is being charged :
P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(BAT)] × I(BAT)
The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is
recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage
and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or
higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop
is always active.
Half-Wave Adaptors
Some adapters implement a half rectifier topology, which causes the adapter output voltage to fall below the
battery voltage during part of the cycle. To enable operation with adapters under those conditions, the bq2407x
family keeps the charger on for at least 20 msec (typical) after the input power puts the part in sleep mode. This
feature enables use of external adapters using 50 Hz networks. The input must not drop below the UVLO voltage
for the charger to work properly. Thus, the battery voltage should be above the UVLO to help prevent the input
from dropping out. Additional input capacitance may be needed.
Sleep Mode
When the input is between UVLO and VIN(DT), the device enters sleep mode. After entering sleep mode for
>20mS the internal FET connection between the IN and OUT pin is disabled and pulling the input to ground will
not discharge the battery, other than the leakage on the BAT pin. If one has a full 1000mAHr battery and the
leakage is 10µA, then it would take 1000mAHr/10µA = 100000 hours (11.4 years) to discharge the battery. The
battery’s self discharge is typically 5 times higher than this.
Layout Tips
•
To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter
capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2407x, with short
trace runs to both IN, OUT and GND (thermal pad).
•
All low-current GND connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
•
•
The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces
The bq2407x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is
also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. Full
PCB design guidelines for this package are provided in the application note entitled: QFN/SON PCB
Attachment Application Note (SLUA271).
30
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): bq24072 bq24073 bq24074 bq24075, bq24079
bq24072, bq24073
bq24074, bq24075, bq24079
www.ti.com................................................................................................................................................. SLUS810D–SEPTEMBER 2008–REVISED JUNE 2009
Revision History
Changes from Original (September 2008) to Revision A ............................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed device Features...................................................................................................................................................... 1
Changed Description. ............................................................................................................................................................ 1
Changed Typical Application Circuit ...................................................................................................................................... 1
Changed description of CHG pin........................................................................................................................................... 6
Changed SYSOFF Description.............................................................................................................................................. 7
Changed the Simplified Block Diagram ................................................................................................................................. 8
Added Figure 4 through Figure 11......................................................................................................................................... 9
Changed APPLICATION CIRCUITS section. ...................................................................................................................... 12
Added Using bq24075 to Disconnect the Battery from the System, Figure 28. .................................................................. 13
Changed DETAILED FUNCTIONAL DESCRIPTION section.............................................................................................. 16
Changed text in section - STATUS INDICATORS (PGOOD, CHG).................................................................................... 25
Changed Table - CHG STATUS INDICATOR..................................................................................................................... 25
Changed Equation 2 and Equation 3................................................................................................................................... 27
Changed section - Half-Wave Adaptors .............................................................................................................................. 30
Changes from Revision A (December 2008) to Revision B ........................................................................................... Page
Changed VBAT(REG) max value From 4.24 V To: 4.23 V ......................................................................................................... 5
•
Changes from Revision B (January 2009) to Revision C ............................................................................................... Page
Changed Maximum input current factor values. ................................................................................................................... 4
•
Changes from Revision C (March 2009) to Revision D .................................................................................................. Page
Added Device number bq24079. ........................................................................................................................................... 1
•
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): bq24072 bq24073 bq24074 bq24075, bq24079
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2009
PACKAGING INFORMATION
Orderable Device
BQ24072RGTR
BQ24072RGTRG4
BQ24072RGTT
BQ24072RGTTG4
BQ24073RGTR
BQ24073RGTRG4
BQ24073RGTT
BQ24073RGTTG4
BQ24074RGTR
BQ24074RGTRG4
BQ24074RGTT
BQ24074RGTTG4
BQ24075RGTR
BQ24075RGTRG4
BQ24075RGTT
BQ24075RGTTG4
BQ24079RGTR
BQ24079RGTT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGT
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2009
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
BQ24072RGTR
BQ24072RGTT
BQ24073RGTR
BQ24073RGTT
BQ24074RGTR
BQ24074RGTT
BQ24075RGTR
BQ24075RGTT
BQ24079RGTR
BQ24079RGTT
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
16
16
16
16
16
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24072RGTR
BQ24072RGTT
BQ24073RGTR
BQ24073RGTT
BQ24074RGTR
BQ24074RGTT
BQ24075RGTR
BQ24075RGTT
BQ24079RGTR
BQ24079RGTT
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
RGT
16
16
16
16
16
16
16
16
16
16
3000
250
346.0
190.5
346.0
190.5
346.0
190.5
346.0
190.5
346.0
190.5
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
346.0
212.7
29.0
31.8
29.0
31.8
29.0
31.8
29.0
31.8
29.0
31.8
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
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