BQ24083DRCR [TI]
1-A, SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC; 1 -A ，单芯片，锂离子和锂聚合物充电器IC
| 型号： | BQ24083DRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-A, SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC |
| 文件： | 总23页 (文件大小：1582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24083
www.ti.com ........................................................................................................................................................................................................ SLUS848–MAY 2008
1-A, SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC
1
FEATURES
DESCRIPTION
2
•
Integrated Power FET and Current Sensor for
Up to 1-A Charge Applications From AC
Adapter
The bq24083 is highly integrated and flexible Li-Ion
linear charge device targeted at space-limited charger
applications. It offers an integrated power FET and
current sensor, high-accuracy current and voltage
regulation, charge status, and charge termination, in
a single monolithic device. An external resistor sets
the magnitude of the charge current. The bq24083
has an option of two output battery charge voltages:
4.06 V and 4.2 V.
•
•
•
Precharge Conditioning With Safety Timer
Charge and Power-Good Status Output
Automatic Sleep Mode for Low Power
Consumption
•
•
•
Integrated Charge-Current Monitor
Fixed 7-Hour Fast Charge Safety Timer
The device charges the battery in three phases:
conditioning, constant current, and constant voltage.
Charge is terminated based on minimum current. An
internal charge timer provides a backup safety for
charge termination. The device automatically restarts
the charge if the battery voltage falls below an
internal threshold. The device automatically enters
sleep mode when the ac adapter is removed.
Ideal for Low-Dropout Charger Designs for
Single-Cell Li-Ion or Li-Pol Packs in
Space-Limited Portable Applications
•
•
Small 3-mm × 3-mm SON Package
Pin Select Battery Voltage (4.06V/4.2V)
APPLICATIONS
•
•
•
•
PDAs, MP3 Players
Digital Cameras
Internet Appliances
Smartphones
AC
Adapter
PACK+
C2
Battery Pack
+
VDC
bq24083
OUT 10
C1
0.1 mF
1
IN
0.1 µF
GND
System
PACK–
System
Interface
2
3
4
5
NC
9
8
7
6
CE
PG
STAT1
STAT2 VBSEL
VSS ISET
RSET
1.13 kW
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
bq24083
SLUS848–MAY 2008........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
CHARGE
REGULATION
VOLTAGE (V)
FAST-CHARGE
TIMER (HOURS)
PART
TJ
FUNCTIONS
MARKINGS
NUMBER(1)(2)
bq24083DRCT
bq24083DRCR
–40°C to 125°C
4.2/ 4.06
CE , PG, and VBSEL
7
CFZ
(1) The DRC package is available taped and reeled only in quantities of 3,000 devices per reel.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
DISSIPATION RATINGS
TA < 40°C
POWER RATING
DERATING FACTOR
ABOVE TA = 40°C
PACKAGE
RθJA
RθJC
DRC(1)
46.87 °C/W
4.95 °C/W
1.5 W
0.021 W/°C
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2- × 3-via matrix.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
VALUE
–0.3 to 7
15
UNIT
V
VI
Input voltage(2)
IN, CE, ISET, OUT, PG, STAT1, STAT2, VBSEL
Output sink/source current
Output current
STAT1, STAT2, PG
OUT
mA
A
1.5
TA
Operating free-air temperature range
Junction temperature range
Storage temperature
°C
–40 to 125
TJ
°C
Tstg
–65 to 150
300
°C
Lead temperature for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS
.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
0
MAX
6.5
UNIT
V
VCC
TJ
Supply voltage
Operating junction temperature range
125
°C
2
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bq24083
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ELECTRICAL CHARACTERISTICS
over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT
ICC(VCC) VCC current
VCC > VCC(min)
1.2
2
2
5
mA
Sum of currents into OUT pin,
VCC < V(SLP)
ICC(SLP)
Sleep current
µA
V
ICC(STBY)
IIB(OUT)
Standby current
CE = High, 0°C ≤ TJ ≤ 85°C
150
5
Input current on OUT pin
Charge DONE, VCC > VCC(MIN)
1
VOLTAGE REGULATION VO(REG) + V(DO−MAX) ≤ VCC, I(TERM) < IO(OUT) ≤ 1 A
VBSEL = HI
4.06
4.2
VO(REG)
Output voltage
VBSEL = LO
TA = 25°C
−0.35%
−1%
0.35%
1%
Voltage regulation accuracy
VO(OUT) = VO(REG), IO(OUT) = 1 A
VO(REG) + V(DO)) ≤ VCC
V(DO)
Dropout voltage (V(IN) − V(OUT)
)
350
500
mV
CURRENT REGULATION
Output current range(1)
VI(OUT) > V(LOWV)
,
IO(OUT)
50
1000
mA
V
VI(IN) − VI(OUT) > V(DO), VCC ≥ 4.5 V
Voltage on ISET pin, VCC ≥ 4.5 V,
VI ≥ 4.5 V, VI(OUT) > V(LOWV)
VI − VI(OUT) > V(DO)
V(SET)
Output current set voltage
Output current set factor
,
2.463
2.5
2.538
50 mA ≤ IO(OUT) ≤ 1 A
10 mA ≤ IO(OUT) < 50 mA
1 mA ≤ IO(OUT) < 10 mA
307
296
246
322
320
320
337
346
416
K(SET)
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
Precharge to fast-charge transition
threshold
V(LOWV)
Voltage on OUT pin
2.8
3
3.2
V
V
CC(MIN) ≥ 4.5 V, tFALL = 100 ns,
Deglitch time for fast-charge to precharge
transition
10-mV overdrive,
VI(OUT) decreasing below threshold
250
375
500
ms
IO(PRECHG) Precharge range(2)
V(PRECHG) Precharge set voltage
TERMINATION DETECTION
0 V < VI(OUT) < V(LOWV), t < t(PRECHG)
5
100
270
mA
mV
Voltage on ISET pin, VO(REG) = 4.2 V,
0 V < VI(OUT) > V(LOWV), t < t(PRECHG)
240
255
I(TERM)
Charge termination detection range(3)
VI(OUT) > V(RCH), t < t(TRMDET)
5
100
265
mA
mV
Voltage on ISET pin, VO(REG) = 4.2 V,
VI(OUT) > V(RCH), t < t(TRMDET)
V(TERM)
Charge termination detection set voltage
235
250
375
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
tTRMDET
Deglitch time for termination detection
charging current decreasing below
10-mV overdrive
250
500
ms
(1) See Equation 2 in the Function Description section.
(2) See Equation 1 in the Function Description section.
(3) See Equation 4 in the Function Description section.
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ELECTRICAL CHARACTERISTICS (continued)
over 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY RECHARGE THRESHOLD
VO(REG) VO(REG) VO(REG)
V(RCH)
Recharge threshold
V
– 0.115
− 0.10 − 0.085
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns
t(DEGL)
Deglitch time for recharge detect
decreasing below or increasing above
threshold, 10-mV overdrive
250
375
500
ms
STAT1, STAT2, and PG OUTPUTS
VOL
Low-level output saturation voltage
IO = 5 mA
0.25
0.4
V
VBSEL, CE and TE INPUTS
VIL
Low-level input voltage
0
1.4
–1
V
VIH
High-level input voltage
IIL
CE and TE low-level input current
CE and TE high-level input current
VBSEL low-level input current
VBSEL high-level input current
µA
µA
IIH
1
40
IIL
VBSEL = 0 (LOW)
VBSEL = VCC (HI)
–20
IIH
TIMERS
t(PRECHG)
t(CHG)
I(FAULT)
Precharge time
1,584
1,800
2,016
s
s
Charge time
22,176 25,200 28,224
200
Timer fault recovery current
µA
SLEEP COMPARATOR
V
CC ≤ VI(OUT)
V(SLP)
Sleep-mode entry threshold voltage
+ 80 mV
2.3 V ≤ VI(OUT) ≤ VO(REG)
V
V
+ 190
CC ≥ VI(OUT)
V(SLPEXIT) Sleep-mode exit threshold voltage
Sleep-mode entry deglitch time
V(IN) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
250
375
500
ms
THERMAL SHUTDOWN THRESHOLDS
T(SHTDWN) Thermal trip threshold
Thermal hysteresis
165
15
TJ increasing
°C
UNDERVOLTAGE LOCKOUT
UVLO
Undervoltage lockout
Hysteresis
Decreasing VCC
2.4
2.5
27
2.6
V
mV
TEMPERATURE SENSE COMPARATOR (bq24081)
V(TS1)
V(TS2)
I(TS)
High-voltage threshold
2.475
0.485
96
2.5
0.5
2.525
0.515
108
V
Low-voltage threshold
TS pin current source
102
375
µA
t(DEGL)
Deglitch time for temperature fault
250
500
mv
4
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bq24083
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PIN CONFIGURATION
DRC PACKAGE
(TOP VIEW)
VSS STAT2 STAT1 NC
IN
1
5
4
3
2
bq24083
6
7
VBSEL
8
9
10
ISET
OUT
CE
PG
TERMINAL FUNCTIONS
TERMINAL
NAME
I/O
DESCRIPTION
NO.
9
CE
N.C.
IN
I
–
I
Charge enable input (active-low)
No Connection. Leave this pin unconnected. Used for internal test purposes.
Adapter dc voltage. Connect minimum 0.1-µF capacitor to VSS
2
1
.
Charge current. External resistor to VSS sets precharge and fast-charge current, and also the termination
current value. Can be used to monitor the charge current.
ISET
6
I
OUT
10
8
O
O
O
O
I
Charge current output. Connect minimum 0.1-µF capacitor to VSS.
PG
Power-good status output (open-drain)
STAT1
STAT2
VBSEL
VSS
3
Charge status outputs (open-drain)
4
7
Voltage output selection. (HI = 4.06 V, LO = 4.2 V)
Ground
5
–
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device.
The exposed thermal pad must be connected to the same potential as the VSS pin on the printed-circuit
board. Do not use the thermal pad as the primary ground input for the device. The VSS pin must be
connected to ground at all times.
Thermal pad
–
–
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FUNCTIONAL BLOCK DIAGRAM
(3)
IN
OUT
ISET
V(PRECHG)
V(SET)
VO(REG)
V(RCH)
V(LOWV)
(3)
(3)
(3)
V(TERM)
VBSEL(4)
4.06 V
4.2 V
V(IN)
(3)
VI(OUT) + V(SLP)
ITS
UVLO
Charge
Control,
Timers,
and
V(TS1)
TS(2)
(3)
Status
V(TS2)
STAT1
CE(1)
STAT2
PG(1)
VSS
(1) Signal deglitched
6
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bq24083
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TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
450
I
= 1000 mA
O(OUT)
400
350
I
I
I
= 750 mA
= 500 mA
= 250 mA
O(OUT)
O(OUT)
O(OUT)
300
250
200
150
100
50
0
0
50
100
150
T
J
- Junction Temperature - oC
Figure 1.
Figure 2. VIN Hot-Plug Power-Up Sequence
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TYPICAL CHARACTERISTICS (continued)
Figure 3. Charge Enable Power-Up Sequence (CE = High-to-Low)
Figure 4. Battery Hot-Plug During Charging Phase
8
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TYPICAL CHARACTERISTICS (continued)
(1) No battery – In termination deglitch prior to STAT1 going high. VOUT (VBAT) cycling between charge and done prior to screen capture.
(2) Stat1 goes high – In done state
(3) 2-V battery is inserted during the charge done state.
(4) Charging is initiated – STAT1 goes low and charge current is applied.
(5) Battery is removed – VOUT goes into regulation, IOUT goes to zero, and termination deglitch timer starts running (same as state 1).
(6) Deglitch timer expires – charge done is declared.
Figure 5. Battery Hot-Plug and Removal Power Sequence
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bq24083
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FUNCTIONAL DESCRIPTION
The device supports a precision Li-Ion, Li-Pol charging system suitable for single cells. Figure 6 shows a typical
charge profile, and Figure 7 shows an operational flow chart.
Preconditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Current
Pre-
Conditioning
and Term
Detect
Safety Timer
M0066-01
Figure 6. Typical Charging Profile
10
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POR
SLEEP MODE
VCC > VI(OUT)
No
checked at all
times?
Indicate SLEEP
MODE
Yes
Regulate
IO(PRECHG)
Reset and Start
t(PRECHG) Timer
VI(OUT)<V(LOWV)
?
es
Y
and
Indicate Charge-
In-Progress
No
Reset All Timers,
Start t(CHG) Timer
Regulate Current
or Voltage
and
Indicate Charge-
In-Progress
No
VI(OUT)<V(LOWV)
?
Yes
Yes
t(PRECHG)
Expired?
t(CHG) Expired?
No
No
Yes
Yes
Fault Condition
Indicate Fault
Yes
VI(OUT)<V(LOWV)
?
No
Yes
VI(OUT) >V(RCH)
?
Iterm
No
Detection
?
No
Yes
Enable I(FAULT)
Current
Turn Off Charge
Indicate DONE
VI(OUT) >V(RCH)
?
No
Yes
VI(OUT) <V(RCH)
?
No
Disable I(FAULT)
Current
Yes
F0018-01
Figure 7. Operational Flow Chart
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Battery Preconditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold, the device applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. Resistor RSET, connected
between the ISET and VSS, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in
the Electrical Characteristics table.
K(SET) x V(PRECHG)
IO(PRECHG)
=
RSET
(1)
The device activates a safety timer, t(PRECHG), during the conditioning phase. If the V(LOWV) threshold is not
reached within the timer period, the device turns off the charger and enunciates FAULT on the STATx pins. See
the Timer Fault Recovery section for additional details.
Battery Fast-Charge Constant Current
The device offers on-chip current regulation with programmable set point. Resistor RSET, connected between the
ISET and VSS, determines the charge rate. The V(SET) and K(SET) parameters are specified in the specifications
table.
K(SET) x V(SET)
I
=
O(OUT)
RSET
(2)
Charge-Current Monitor
When the charge function is enabled internal circuits generate a current proportional to the charge current at the
ISET pin. This current, when applied to the external charge current programming resistor RISET generates an
analog voltage that can be monitored by an external host to calculate the current sourced from the OUT pin.
RISET
K(SET)
V(ISET) + I(OUT)
(3)
Battery Fast-Charge Voltage Regulation
The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the
battery pack. The device monitors the battery-pack voltage between the OUT and VSS pins. When the battery
voltage rises to the VO(REG) threshold, the voltage regulation phase begins and the charging current begins to
taper down.
As a safety backup, the device also monitors the charge time in the charge mode. If charge is not terminated
within this time period, t(CHG), the charger is turned off and FAULT is set on the STATx pins. See the Timer Fault
and Recovery section for additional details.
Charge Termination Detection and Recharge
The device monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, charge is terminated. The V(TERM) and K(SET) parameters are specified in the specifications
table.
K(SET) x V(TERM)
IO(TERM)
=
RSET
(4)
After charge termination, the device restarts the charge once the voltage on the OUT pin falls below the V(RCH)
threshold. This feature keeps the battery at full capacity at all times.
The device monitors the charging current during the voltage regulation phase. Once the termination threshold,
I(TERM), is detected, the charge is terminated immediately.
Resistor RSET, connected between the ISET and VSS, determines the current level at the termination threshold.
Sleep Mode
The device enters the low-power sleep mode if the input power (IN) is removed from the circuit. This feature
prevents draining the battery during the absence of input supply.
12
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Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table.
These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.
Table 1. Status Pin Summary
CHANGE STATE
Precharge in progress
Fast charge in progress
Charge done
STAT1
ON
STAT2
ON
ON
OFF
ON
OFF
Charge suspend (temperature)
Timer fault
OFF
OFF
Sleep mode
PG Output
The open-drain power-good (PG) output pulls low when a valid input voltage is present. This output is turned off
(high-impedance) in sleep mode. The PG pin can be used to drive an LED or communicate to the host
processor.
Charge-Enabled (CE) Input
The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge and a high-level signal disables the charge and places the device in a low-power mode. A high-to-low
transition on this pin also resets all timers and timer fault conditions.
Battery Voltage Selection, (VBSEL) Input
The VBSEL input is used to select the output voltage of bq24083. A low level signal on this pin selects the
charge voltage of 4.2 V. A high level voltage selects the charge voltage of 4.06 V. If VBSEL is left open, an
internal current source flowdown ensures the charge voltage is set to 4.2 V (typical).
Timer Fault and Recovery
As shown in Figure 7, the device provides a recovery method to deal with timer fault conditions. The following
summarizes this method:
Condition Number 1
OUT pin voltage is above the recharge threshold (V(RCH)), and a timeout fault occurs.
Recovery method: the device waits for the OUT pin voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the OUT pin voltage falls
below the recharge threshold, the device clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.
Condition Number 2
OUT pin voltage is below the recharge threshold (V(RCH)), and a timeout fault occurs
Recovery method: Under this scenario, the device applies the I(FAULT) current. This small current is used to detect
a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If
the OUT pin voltage goes above the recharge threshold, then the device disables the I(FAULT) current and
executes the recovery method described for condition number 1. Once the OUT pin voltage falls below the
recharge threshold, the bq24080/bq24083 clears the fault and starts a new charge cycle. A POR or CE toggle
also clears the fault.
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APPLICATION INFORMATION
bq24083 CHARGER DESIGN EXAMPLE
Requirements
•
•
•
Supply voltage = 5 V
Fast-charge current of approximately 750 mA
Battery-temperature sense (bq24081): default setting = –2°C to 44.5°C
Calculations
Program the charge current for 750 mA:
RISET = [V(SET) × K(SET) / I(OUT)
]
From electrical characteristics table, V(SET) = 2.5 V.
From electrical characteristics table, K(SET) = 322.
RISET = [2.5 V × 322 / 0.75 A] = 1.073 kΩ
Selecting the closest standard value, use a 1.07-kΩ resistor connected between ISET (pin 6) and ground.
STAT Pins and PG Pin
Status pins Monitored by Processor:
Select a pullup resistor that can source more than the input bias (leakage) current of both the processor and
status pins and still provide a logic high. RPULLUP ≤ [V(cc-pullup) – V(logic hi-min) / (I(P-monitor) + I(STAT-OpenDrain)) ] =
(3.3 V – 1.9 V) / (1 µA + 1 µA) ≤ 700 kΩ; Connect a 100-kΩ pullup between each status pin and the VCC of
the processor. Connect each status pin to a µP monitor pin.
Status viewed by LED:
Select an LED with a current rating less than 10 mA and select a resistor to place in series with the LED to
limit the current to the desired current value (brightness). RLED = [(V(IN) – V(LED-on)) / I(LED)] = (5 V – 2 V) / 1.5
mA = 2 kΩ. Place an LED and resistor in series between the input and each status pin.
Selecting Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on the input power pin. A 0.1-µF
ceramic capacitor, placed in close proximity to the IN pin and GND pad works well. In some applications, it may
be necessary to protect against a hot plug input voltage overshoot. This is done in three ways:
1. The best way is to add an input zener, 6.2 V, between the IN pin and VSS.
2. A low-power zener is adequate for the single event transient. Increasing the input capacitance lowers the
characteristic impedance which makes the input resistance move effective at damping the overshoot, but
risks damaging the input contacts by the high inrush current.
3. Placing a resistor in series with the input dampens the overshoot, but causes excess power dissipation.
The device only requires a small capacitor for loop stability. A 0.1-µF ceramic capacitor placed between the OUT
and GND pad is typically sufficient.
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1.5 kW
100 kW
SOURCE
INPUT
bq24083
OUT 10
PACK+
VDC
1
2
IN
C1
C2
+
0.1 mF
0.1 mF
1.5 kW
PACK–
GND
NC
9
CE
PG
1.5 kW
3
4
5
STAT1
8
7
6
HI, V
= 4.06
OUT
STAT2 VBSEL
VSS
LO, V
= 4.2
OUT
Charge Current
Translator Output
ISET
1.13 kW
RSET
Thermal Considerations
The bq24083 is in a thermally enhanced MLP package. The package includes a thermal pad to provide an
effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for
this package are provided in the application report entitled, QFN/SON PCB Attachment (TI Literature Number
SLUA271).
The most common measure of package thermal performance is thermal impedance (RθJA) measured (or
modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical
expression for RθJA is:
TJ - TA
=
RqJA
P
(5)
Where:
•
•
•
TJ = device junction temperature
TA = ambient temperature
P = device power dissipation
Factors that can greatly influence the measurement and calculation of RθJA include:
•
•
•
•
•
•
•
Orientation of the device (horizontal or vertical)
Volume of the ambient air surrounding the device under test and airflow
Whether other surfaces are in close proximity to the device being tested
Use multiple 10–13 mil vias in the PowerPAD™ to copper ground plane.
Avoid cutting the ground plane with a signal trace near the power IC.
The PCB must be sized to have adequate surface area for heat dissipation.
FR4 (figerglass) thickness should be minimized.
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power
FET. It can be calculated from the following equation:
P = (V(IN) - V(OUT)) x IO(OUT)
(6)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 6.
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PCB Layout Considerations
It is important to pay special attention to the PCB layout. The following provides some guidelines:
•
To obtain optimal performance, the decoupling capacitor from VCC to V(IN) and the output filter capacitors from
OUT to VSS should be placed as close as possible to the device, with short trace runs to both signal and VSS
pins. The VSS pin should have short trace runs to the GND pin.
•
All low-current VSS connections should be kept separate from the high-current charge or discharge paths from
the battery. Use a single-point ground technique incorporating both the small-signal ground path and the
power ground path.
•
•
The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
The device is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment
(TI Literature Number SLUA271).
16
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :bq24083
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2008
PACKAGING INFORMATION
Orderable Device
BQ24083DRCR
BQ24083DRCT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRC
10
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SON
DRC
10
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
BQ24083DRCR
BQ24083DRCT
SON
SON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24083DRCR
BQ24083DRCT
SON
SON
DRC
DRC
10
10
3000
250
346.0
190.5
346.0
212.7
29.0
31.8
Pack Materials-Page 2
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