BQ24150A [TI]
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support; 完全集成开关模式单节锂离子电池充电器与USB完全遵守和USB -OTG支持
| 型号： | BQ24150A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support |
| 文件： | 总41页 (文件大小：2603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
Fully Integrated Switch-Mode One-Cell Li-Ion Charger
With Full USB Compliance and USB-OTG Support
1
FEATURES
2
•
Charge Faster than Linear Chargers
–
Output for VBUS: 5.05 V/ 200 mA
•
High-Accuracy Voltage and Current Regulation
•
2 x 2 mm 20-Pin WCSP Package
–
–
–
Input Current Regulation Accuracy: ±5%
(100 mA and 500 mA)
APPLICATIONS
•
•
•
Mobile and Smart Phones
MP3 Players
Handheld Devices
Charge Voltage Regulation Accuracy:
±0.5% (25°C), ±1% (0°C to 125°C)
Charge Current Regulation Accuracy: ±5%
•
High-Efficiency Mini-USB/AC Battery Charger
for Single-Cell Li-Ion and Li-Polymer Battery
Packs
DESCRIPTION
The bq24150A/1A
is
a
compact,
flexible,
high-efficiency, USB-friendly switch-mode charge
management device for single-cell Li-ion and
Li-polymer batteries used in a wide range of portable
applications. The charge parameters can be
programmed through an I2C interface. The
•
•
•
•
20-V Absolute Maximum Input Voltage Rating
6-V Maximum Operating Input Voltage
Built-In Input Current Sensing and Limiting
Integrated Power FETs for Up To 1.25-A
Charge Rate
bq24150A/1A integrates
a
synchronous PWM
controller, power MOSFETs, input current sensing,
high-accuracy current and voltage regulation, and
charge termination, into a small WCSP package.
•
Programmable Charge Parameters through
I2C™ Interface (up to 3.4 Mbps):
–
–
–
–
–
Input Current
The bq24150A/1A charges the battery in three
phases: conditioning, constant current and constant
voltage. The input current is automatically limited to
the value set by the host. Charge is terminated based
on user-selectable minimum current level. A safety
timer with reset control provides a safety backup for
I2C interface. During normal operation, bq24150A/1A
automatically restarts the charge cycle if the battery
voltage falls below an internal threshold and
automatically enters sleep mode or high impedance
mode when the input supply is removed. The charge
status is reported to the host using the I2C interface.
Fast-Charge/Termination Current
Charge Voltage (3.5 V to 4.44 V)
Safety Timer with Reset Control
Termination Enable
•
•
Synchronous Fixed-Frequency PWM
Controller Operating at 3 MHz With 0% to
99.5% Duty Cycle
Robust Protection
–
Reverse Leakage Protection Prevents
Battery Drainage
TYPICAL APPLICATION CIRCUIT
–
–
Thermal Regulation and Protection
Input/Output Overvoltage Protection
L
1.0 mH
O
R
SNS
V
BUS
VBUS
SW
C
O
C
IN
C
U1
bq24150A/1A
BOOT
•
•
Status Output for Charging and Faults
10
mF
1 mF
10nF
PACK+
+
PMID
BOOT
PGND
Automatic High Impedance Mode for Low
Power Consumption
C
IN
0.1 mF
VAUX
4.7 mF
CSIN
CSOUT
AUXPWR
VREF
10 kW
10 kW
2
I
C BUS
PACK-
10 kW
SCL
SCL
SDA
STAT
•
•
•
•
USB Friendly Boot-Up Sequence
SDA
STAT
OTG
C
AUXPWR
Automatic Charging – bq24150A
OTG
C
1
mF
VREF
10 kW
1
mF
HOST
Automatic High Impedance Mode – bq24151A
Boost Mode Operation for USB OTG:
–
Input Voltage Range (from Battery): 2.5 V to
4.5 V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
During the charging process, the bq24150A/1A monitors its junction temperature (TJ) and reduces the charge
current once TJ increases to approximately 125°C. To support USB OTG device, bq24150A/1A provides VBUS
(approximately 5.05 V) by boosting the battery voltage. The bq24150A/1A is available in 20-pin WCSP package.
WCSP PACKAGE
(Top View)
A1
A2
A3
A4
VBUS
VBUS
BOOT
SCL
B1
B2
B3
B4
PMID
PMID
PMID
SDA
C1
SW
C2
SW
C3
SW
C4
STAT
D1
D2
D3
D4
PGND
PGND
PGND
OTG
E1
E2
AUX
PWR
E3
E4
CSOUT
CSIN
VREF
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
CSOUT
VBUS
PMID
SW
NO.
Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 µF) to
PGND if there are long inductive leads to battery.
E4
I
A1, A2
B1, B2, B3
C1, C2, C3
A3
I
Charger input voltage. Bypass it with a 1-µF ceramic capacitor from VBUS to PGND.
Connection point between reverse blocking MOSFET and high-side switching MOSFET. Bypass it
with a minimum of 3.3-µF capacitor from PMID to PGND.
O
O
O
Internal switch to output inductor connection.
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 10-nF ceramic capacitor
(voltage rating above 10 V) from BOOT pin to SW pin.
BOOT
PGND
CSIN
D1, D2, D3
E1
Power ground
Charge current-sense input. Battery current is sensed via the voltage drop across an external sense
resistor. A 0.1-µF ceramic capacitor to PGND is required.
I
I2C interface clock. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
I2C interface data. Open drain output, connect a 10-kΩ pullup resistor to 1.8V rail
SCL
SDA
A4
B4
I
I/O
Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a
128-µS pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can
be used to drive a LED or communicate with a host processor.
STAT
C4
O
Internal bias regulator voltage. Connect a 1-µF ceramic capacitor from this output to PGND. External
load on VREF is not allowed.
VREF
E3
E2
O
I
Auxiliary power supply, connected to the battery pack to provide power in high-impedance mode.
Bypass it with a 1-µF ceramic capacitor from this pin to PGND.
AUXPWR
Boost mode enable control or input current limiting selection pin. When OTG is in active status,
bq24150A/1A is forced to operate in boost mode. It has higher priority over I2C control and can be
disabled through control register. The logic voltage level at OTG active status can also be controlled.
At POR, the OTG pin is default to be used as the input current limiting selection pin. When OTG =
High, Iin – limit = 500mA and when OTG = Low, Iin – limit = 100mA, see the Control Register for
details.
OTG
D4
I
2
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
PACKAGE DIMENSIONS
PACKAGE DEVICES
bq24150A, bq24151A
D
E
1.976 ± 0.05mm
1.946 ± 0.05mm
ORDERING INFORMATION(1)
AUTOMATIC CHARGING
(VBUS Recycled, VBAT < VLOWV
32 Minutes Mode)
PART NUMBER BIT PN0,
CONTROL REGISTER 03H, BIT 3
PART NO.
MARKING
MEDIUM
QUANTITY
,
bq24150AYFFR
bq24150AYFFT
bq24151AYFFR
bq24151AYFFT
bq24150A Tape and Reel
bq24150A Tape and Reel
bq24151A Tape and Reel
bq24151A Tape and Reel
3000
250
Yes
Yes
No
1
1
0
0
3000
250
No
(1) For the most current package information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
DISSIPATION RATINGS(1)
T
A ≤ 25°C
DERATING FACTOR
TA > 25°C
PACKAGE
RθJA
RθJC
POWER RATING
(1)
WSCP-20
185°C/W(2)
1.57°C/W
0.54 W
0.0054 W/°C
(1) Maximum power dissipation is a function of TJ(max), RθJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / RθJA
.
(2) For PCB board with only top trace layer. For PCB board with four layers (top trace layer, buried ground layer, buried signal layer and
bottom layer), RθJA drops to 75.96°C/W
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 20
–0.3 to 7
–0.3 to 20
6.5
UNIT
V
VSS Supply voltage range (with respect to PGND)
VBUS
VI
Input voltage range (with respect to and PGND)
SCL, SDA, OTG, CSIN, CSOUT, AUXPWR
PMID, STAT
V
V
VO
Output voltage range (with respect to and PGND) VREF
SW, BOOT
Voltage difference between CSIN and CSOUT inputs (V(CSIN) – V(CSOUT)
V
–0.7 to 20
±7
V
)
V
Output sink
STAT
SW
10
mA
A
IO
Output Current (average)
Operating free-air temperature range
Junction temperature
Storage temperature
1.25
TA
TJ
–40 to 85
–40 to 150
–65 to 150
°C
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
4
NOM
MAX
6(1)
UNIT
V
VBUS
TJ
Supply voltage, VBUS
Operating junction temperature range
0
+125
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOST or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VBUS > VBUS(min), PWM switching
10
mA
VBUS > VBUS(min), PWM NOT switching
5
0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,
V(AUXPWR) > V(LOWV), SCL, SDA, OTG = 0 V or 1.8 V
20
µA
µA
I(VBUS)
VBUS supply current control
0°C < TJ < 85°C, VBUS = 5 V, HZ_MODE = 1,
V(AUXPWR) < V(LOWV), 32S mode, SCL, SDA, OTG = 0
V or 1.8 V
35
0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High Impedance
mode
Ilkg
Leakage current from battery to VBUS pin
5
µA
µA
Battery discharge current in High Impedance
mode, (CSIN, CSOUT, AUXPWR, SW pins)
0°C < TJ < 85°C, V(AUXPWR) = 4.2 V, High Impedance
mode, SCL, SDA, OTG = 0 V or 1.8 V
20
VOLTAGE REGULATION
V(OREG) Output charge voltage
Operating in voltage regulation, programmable
TA = 25°C
3.5
–0.5%
–1%
4.44
0.5%
1%
V
Voltage regulation accuracy
CURRENT REGULATION (FAST CHARGE)
IO(CHARGE) Output charge current
V
(LOWV) ≤ V(AUXPWR) < V(OREG)
,
550
1250
mA
VBUS > V(SLP), R(SNS) = 68 mΩ, Programmable
Regulation accuracy for charge current across 20 mV ≤ V(IREG) ≤ 40 mV
–5%
–3%
5%
3%
R(SNS)
40 mV < V(IREG)
V(IREG) = IO(CHARGE) × R(SNS)
WEAK BATTERY DETECTION
V(LOWV) Weak battery voltage threshold
Programmable
3.4
3.7
5%
V
Weak battery voltage accuracy
Hysteresis for V(LOWV)
–5%
Battery voltage falling
100
30
mV
ms
Deglitch time for weak battery threshold
Rising voltage, 2-mV over drive, tRISE = 100 ns
OTG PIN LOGIC LEVEL
VIL
VIH
Input low threshold level
Input high threshold level
0.4
V
V
1.3
50
CHARGE TERMINATION DETECTION
Termination charge current
I(TERM)
V(AUXPWR) > V(OREG) – V(RCH)
VBUS > V(SLP), R(SNS) = 68 mΩ, Programmable
,
mA
ms
400
Deglitch time for charge termination
Both rising and falling, 2-mV overdrive,
tRISE, tFALL = 100 ns
30
3 mV ≤ V(IREG_TERM) < 5 mV
5 mV ≤ V(IREG_TERM) < 20 mV
20 mV ≤ V(IREG_TERM) ≤ 40 mV
–25%
–10%
–5%
25%
10%
5%
Voltage regulation accuracy for termination
current across R(SNS)
V(IREG_TERM) = IO(TERM) × R(SNS)
INPUT POWER SOURCE DETECTION
Input voltage lower limit
Input power source detection, Input voltage falling
Rising voltage, 2-mV overdrive, tRISE = 100 ns
Input voltage rising
3.6
3.8
30
4
V
ms
mV
S
VIN(min)
tINT
Deglitch time for VBUS rising above VIN(min)
Hysteresis for VIN(min)
100
200
Detection Interval
Input power source detection
2
4
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
INPUT CURRENT LIMITING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIN = 100 mA
IIN = 500 mA
88
93
98
mA
USB charge
mode
IIN
VREF BIAS REGULATOR
VREF Internal bias regulator voltage
Input current limiting threshold
450
475
500
VBUS >VIN(min) or V(AUXPWR) > V(BAT)min,
I(VREF) = 1 mA, C(VREF) = 1 µF
V
2
6.5
VREF output short current limit
BATTERY RECHARGE THRESHOLD
30
mA
V(RCH)
Recharge threshold voltage
Deglitch time
Below V(OREG)
100
120
130
150
mV
ms
V(AUXPWR) decreasing below threshold,
tFALL = 100 ns, 10-mV overdrive
STAT OUTPUTS
Low-level output saturation voltage, STAT
High-level leakage current for STAT
IO = 10 mA, sink current
0.4
1
V
VOL(STAT)
Voltage on STAT pin is 5 V
µA
I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
VIL
Output low threshold level
Input low threshold level
Input high threshold level
Input bias current
IO = 10 mA, sink current
0.4
0.4
V
V
VIH
1.2
V
I(BIAS)
f(SCL)
V(pull-up) = 1.8 V, SDA and SCL
1
µA
MHz
SCL clock frequency
3.4
BATTERY DETECTION
Battery detection current before charge done
Begins after termination detected,
V(AUXPWR) ≤ V(OREG)
–0.45
262
mA
ms
(1)
(sink current)
Battery detection time
SLEEP COMPARATOR
I(DETECT)
Sleep-mode entry threshold,
VBUS - VAUXPWR
V(SLP)
2.3 V ≤ V(AUXPWR) ≤ V(OREG), VBUS falling
2.3 V ≤ V(AUXPWR) ≤ V(OREG)
0
40
100
30
100
160
mV
mV
ms
Sleep-mode exit hysteresis
40
V(SLP_EXIT)
Deglitch time for VBUS rising above V(SLP)
V(SLP_EXIT)
+
Rising voltage, 2-mV overdrive, tRISE = 100 ns
UNDERVOLTAGE LOCKOUT
UVLO
IC active threshold voltage
VBUS rising
3.05
120
3.3
3.55
V
UVLO(HYS)
PWM
IC active hysteresis
VBUS falling from above UVLO
150
mV
Voltage from BOOT pin to SW pin
During charge or boost operation
6.5
V
Internal top reverse blocking MOSFET
on-resistance
IIN(LIMIT) = 500 mA, Measured from VBUS to PMID
180
120
250
Internal top N-channel Switching MOSFET
on-resistance
Measured from PMID to SW, VBOOT - VSW= 4V
Measured from SW to PGND
250
200
mΩ
MHz
Internal bottom N-channel MOSFET
on-resistance
110
3
f(OSC)
Oscillator frequency
Frequency accuracy
Maximum duty cycle
Minimum duty cycle
–10%
0
10%
D(MAX)
D(MIN)
99.5%
100
Synchronous mode to non-synchronous mode
transition current threshold(2)
Low side MOSFET cycle by cycle current sensing
mA
(1) Negative charge current means the charge current flows from the battery to charger (discharging battery).
(2) Bottom N-channel MOSFET always turns on for ≈60 ns and then turns off if current is too low.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 1, VBUS = 5 V, HZ_MODE = 0, OPA_MODE = 0 (charger mode operation), TJ = 0°C to 125°C, TJ = 25°C for
typical values (unless otherwise noted)
PARAMETER
CHARGE MODE PROTECTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Threshold over VBUS to turn off converter during
charge
Input VBUS OVP threshold voltage
V(OVP_IN) hysteresis
6.3
6.5
140
117
6.7
V
V(OVP-IN)
VBUS falling from above V(OVP_IN)
mV
V(CSOUT) threshold over V(OREG) to turn off charger
during charge
Output OVP threshold voltage
110
121
V(OVP)
%V(OREG)
V(OVP) hysteresis
Lower limit for V(CSOUT) falling from above V(OVP)
Charge mode operation
11
2.3
2
I(LIMIT)
Cycle-by-cycle current limit for charge
Short-circuit voltage threshold
V(SHORT) hysteresis
1.5
1.9
3
A
V
V(AUXPWR) falling
2.1
V(SHORT)
I(SHORT)
V(AUXPWR) rising from below V(SHORT)
100
10
mV
mA
Short-circuit current
V(AUXPWR) ≤ V(SHORT)
5
15
BOOST MODE OPERATION FOR VBUS (OPA_MODE = 1, HZ_MODE = 0)
V(BUS_B)
Boost output voltage (to VBUS pin)
Boost output voltage accuracy
2.5V < V(AUXPWR) < 4.5 V, Open loop
Including line and load regulation
5.05
V
–3%
200
3%
I(BO)
Maximum output current for boost
Cycle by cycle current limit for boost
V(BUS_B) = 5.05 V, 2.5 V < V(AUXPWR) < 4.5 V
V(BUS_B) = 5.05 V, 2.5 V < V(AUXPWR) < 4.5 V
mA
A
I(BLIMIT)
1
6
Overvoltage protection threshold for boost
(VBUS pin)
Threshold over VBUS to turn off converter during
boost
5.8
6.2
V
mV
V
VBUS(OVP)
VBUS(OVP) hysteresis
VBUS falling from above VBUS(OVP)
V(CSOUT) rising edge during boost
125
4.9
Maximum battery voltage for boost (CSOUT
pin)
4.75
5.05
V(BAT)MAX
V(BAT)MIN
V(BAT)MAX hysteresis
V(CSOUT) falling from above VBATMAX
During boosting
200
2.5
2.9
mV
V
Minimum battery voltage for boost (AUXPWR
pin)
Before boost starts
3.05
V
Output resistance at high-impedance mode
(From VBUS to PGND)
HZ_MODE = 1
165
kΩ
PROTECTION
T(SHTDWN)
Thermal trip
165
10
Thermal hysteresis
°C
s
T(CF)
Thermal regulation threshold(3)
Charge current begins to reduce
32 Second mode
120
32
T(32S)
Time constant for the 32 second timer
12
(3) Verified by design
6
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
TYPICAL APPLICATION CIRCUITS
VBUS = 5 V, I(CHARGE) = 1250 mA, VBAT = 3.5 V to 4.44 V (adjustable), Safety Timer = 32 minutes or 32
seconds.
L
1.0 mH
R
SNS
O
V
BAT
V
BUS
VBUS
SW
C
C
O
IN
68 mW
C
U1
BOOT
10 mF
1 mF
bq24150A/1A
10 nF
PACK +
BOOT
PGND
PMID
4.7 mF
C
IN
2
C
CSIN
+
VAUX
10 kW
0.1 mF
CSIN
I C BUS
10 kW
PACK -
10 kW
10 kW
CSOUT
SCL
SCL
SDA
STAT
SDA
AUXPWR
VREF
C
AUXPWR
STAT
OTG
OTG
1 mF
C
VREF
10 kW
1 mF
HOST
Figure 1. I2C Controlled 1-Cell Charger Application Circuit
VBUS = 5 V, I(IN_LIMIT) = 500 mA, VOUT = 3.5 V to 4.44V (adjustable), Safety Timer = 32 minutes or 32 seconds.
LO 1.0 mH
R
SNS
V
OUT
V
BUS
Host-
Controlled
Switch
VBUS
SW
C
C
O
IN
68 mW
0.1 mF
C
U1
Bq24150A/1A
BOOT
10 mF
1 mF
10nF
Q
BOOT
PGND
PMID
C
IN
4.7 mF
C
CSIN
V
SYS
VAUX
10 kW
Host
Charge
Controller
CSIN
PACK +
2
I C BUS
10 kW
+
10 kW
10 kW
CSOUT
SCL
SCL
SDA
STAT
SDA
STAT
AUXPWR
VREF
C
AUXPWR
C
PACK-
CSOUT
0.1 mF
OTG
OTG
C
1 mF
VREF
10 kW
1 mF
HOST
Figure 2. I2C Controlled 1-Cell Pre-Regulator Application
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Using circuit shown in Figure 1, TA = 25°C, unless otherwise specified.
ADAPTER INSERTION
BATTERY INSERTION/REMOVAL
VBAT
2 V/div
VBUS
2 V/div
Vbus =5 V, Iin_limit = 500 mA,
32S Mode
VSW
VSW
5 V/div
5 V/div
Vbus = 0–5 V, Vbat = 3.5 V Charge mode
IBAT
IBAT
0.5 A/div
0.5 A/div
1S/div
500 mS/div
Figure 3.
Figure 4.
PWM CHARGING WAVEFORMS
POOR SOURCE DETECTION
VBUS
2 V/div
VSW
2 V/div
VSW
5 V/div
IL
0.5 A/div
Vbus = 5 V @ 10 mA, Iin_limit = 100 mA,
Vbat = 3.2 V, Ichg = 550 mA
IBUS
Vbus = 5 V, Vbat = 2.6 V, Voreg = 4.2 V, Ichg = 1250 mA
0.1 A/div
2 mS/div
100 nS/div
Figure 5.
Figure 6.
BATTERY DETECTION AT POWER UP
CYCLE BY CYCLE CURRENT LIMIT IN CHARGE MODE
VBUS
5 V/div
VIN = 0-5 V, No Battery,
COUT = 100 mF, RLOAD = 5 kW
VSW
2 V/div
VBAT
1 V/div
IL
OTG
0.5 A/div
5 V/div
Vbus = 5 V, Vbat = 3.6 V Charge mode
operation
IBAT
50 mA/div
2 mS/div
500 mS/div
Figure 7.
Figure 8.
8
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT CONTROL
CHARGER EFFICIENCY
92
90
88
86
Vbus = 5 V, Iin_limit = 100/500 mA,
(OTG Control, 32 Minute Mode),
2
Iin_limit = 100 mA (I C Control, 32 Second Mode)
VBUS = 5 V
Vbat = 4 V
Vbat = 3.6 V
OTG
5 V/div
32 Second
Mode
32 Minute
Mode
IBUS
84
0.2 A/div
Vbat = 3 V
82
80
0.5 S/div
0
100 200 300 400 500 600 700 800 900 10001100 12001300
Charge Current - mA
Figure 9.
Figure 10.
BOOST WAVEFORM (PWM MODE)
BOOST WAVEFORM (PFM MODE)
VBUS 100 mV/div, 5.06 V Offset
VBUS 10 mV/div, 5.08 V Offset
VBAT 10 mV/div, 3.52 V Offset
VBAT 100 mV/div, 3.5 V Offset
VSW
VSW
2 V/div
2 V/div
VBAT = 3.5 V, VBUS = 5.06 V, IBUS = 42 mA
IL
IL
0.2 A/div
0.2 A/div
VBAT = 3.5 V, VBUS = 5.07 V, IBUS = 215 mA
5 mS/div
100 nS/div
Figure 11.
Figure 12.
VBUS OVERLOAD WAVEFORMS (BOOST MODE)
LOAD STEP UP RESPONSE (BOOST MODE)
VBUS
100 mV/div,
5.06 V Offset
VBAT = 3.5 V, VBUS = 5.05 V, IBUS = 42 mA
VBUS
2 V/div
VBAT = 3.85 V, VBUS = 5.07 V, IBUS = 0-215 mA
VPMID
200 mV/div,
5.02 V Offset
VBAT
0.2 V/div,
3.8 V Offset
VSW
5 V/div
VSW
5 V/div
IBUS
0.2 A/div
IBAT
0.1 A/div
5 mS/div
100 mS/div
Figure 13.
Figure 14.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOAD STEP DOWN RESPONSE (BOOST MODE)
CYCLE BY CYCLE CURRENT LIMITING IN BOOST MODE
VBUS
100 mV/div,
5.06 V Offset
Vbat = 3.6 V, Vbus = 4.11 V, Boost mode
overload operation
VBAT = 3.85 V, VBUS = 5.07 V, IBUS = 215 mA-0
VSW
VBAT
2 V/div
0.2 A/div,
3.8 V Offset
VSW
5 V/div
IL
0.5 A/div
IBAT
0.1 A/div
100 mS/div
200 nS/div
Figure 15.
Figure 16.
BOOST TO CHARGE MODE TRANSITION (OTG CONTROL)
BOOST EFFICIENCY
95
VBUS
0.5 V/div,
4.5 V Offset
VBAT = 4 V
VBAT = 3.6 V
90
OTG
2 V/div
Vbus = 4.5 V, (Charge Mode)/5.1 V (Boost Mode),
Iin_limit = 500 mA, Vbat = 3.4 V, 32S Mode.
85
VSW
5 V/div
VBAT = 2.5 V
80
IL
0.5 A/div
75
70
0.5 mS/div
0
50
100
150
200
Load Current at VBUS - mA
Figure 17.
Figure 18.
LINE REGULATION FOR BOOST
LOAD REGULATION FOR BOOST
5.1
5.1
IBUS = 100 mA
5.09
5.09
IBUS = 200 mA
5.08
5.08
5.07
5.07
5.06
5.05
5.04
VBAT = 3.6 V
5.06
5.05
VBAT = 4 V
5.04
IBUS = 50 mA
5.03
5.03
5.02
5.02
5.01
5
VBAT = 2.5 V
5.01
5
4.99
0
50
100
150
200
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
Load Current at VBUS - mA
VBAT - V
Figure 19.
Figure 20.
10
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
FUNCTIONAL BLOCK DIAGRAM (Charge Mode)
PMID
bq24150A/1A
PMID
VPMID
PMID
NMOS
NMOS
VBUS
VBUS
SW
SW
SW
VBUS
Q2
CBC
Current
Limiting
Q3
Q1
ILIMIT
NMOS
VOUT
PWM
Controller
VREF1
OSC
Charge
Pump
-
+
-
+
CSOUT
CSIN
-
IIN_
VOREG
LIMIT
-
+
-
TCF
TJ
+
VCSIN
IOCHARGE
-
PWM_CHG
VREF
VBUS
VUVLO
VBUS
+
VBUS UVLO
VREF
BOOT
-
REFERNCES
& BIAS
+
Poor Input
VBUS OVP
V
IN(
MIN)
VPMID
VBUS
+
-
VOVP
_IN
VBAT
CHARGE CONTRO,L
TIMER and DISPLAY
LOGIC
VREF
ISHORT
TJ
+
Thermal
Shutdown
-
TSHTDWN
AUXPWR
STAT
VOUT
VOVP
+
Battery OVP
Sleep
*
LINEAR _CHG
-
VBAT
VBUS
VOREG-VRCH
VOUT
+
*
-
+
Recharge
*
-
OTG
Termination
VOUT
VCSIN
ITERM
-
+
-
PGND
*
2
(I C Control)
Decoder
DAC
SCL
SDA
PGND
PGND
VBAT
+
PWM Charge
Mode
*
-
VSHORT
*
Signal Deglitched
Figure 21. Function Block Diagram of bq24150A/1A in Charge Mode
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM (Boost Mode)
PMID
bq24150A/1A
PMID
VPMID
PMID
NMOS
NMOS
VBUS
VBUS
SW
SW
SW
VBUS
Q2
CBC
Current
Limiting
Q1
IBLIMIT
PWM
Controller
VREF1
OSC
Charge
Pump
Q3
CSOUT
CSIN
NMOS
-
+
PFM Mode
75mA
+
+
VBUS_FB
VREF
-
VREF
BOOT
-
IBO
VBUS_FB
REFERNCES
& BIAS
PWM_BOOST
VBUS
+
VBUS OVP
VREF1
-
VBUSOVP
VPMID
TJ
+
Thermal
Shutdown
-
TSHTDWN
VBAT
AUXPWR
STAT
CHARGE CONTROL,
TIMER and DISPLAY
LOGIC
Battery OVP
VOUT
+
*
-
VBATMAX
VBAT
+
Low Battery
*
OTG
-
VBATMIN
PGND
2
(I C Control)
Decoder
DAC
SCL
SDA
PGND
PGND
*
Signal Deglitched
Figure 22. Function Block Diagram of bq24150A/1A in Boost Mode
12
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
OPERATIONAL FLOW CHART
Power Up
VBUS>VUVLO
VAUXPWR<VLOWV
and bq24150A?
High Impedance Modeor Host
Controlled Operation Mode
No
POR
2
Yes
Load I C Registers
with Default Value
Reset and Start
32-Minute Timer
Disable Charge
/CE=LOW
/CE=HIGH
Any Charge State
Charge Configure
Mode
Disable Charge
Wait Mode
Delay T
Indicate Power
not Good
INT
Yes
No
Enable ISHORT
32-Minute
Timer Expired?
VAUXPWR<VSHORT
?
Yes
VBUS<VIN(MIN)
?
No
Indicate Short
Circuit condition
No
Regulate
Input Current, Charge
Current or Voltage
Yes
Indicate Charge-In-
Progress
Yes
VBUS<VIN(MIN)
?
Yes
Turn Off Charge
Indicate Fault
Yes
/CE=HIGH
No
Turn Off Charge
Enable IDETECT for
tDETECT
32-Minute
Timer Expired?
No
Battery Removed
No
VAUXPWR < VOREG
VRCH
-
Wait Mode
Delay T
Yes
Reset Charge
Parameters
?
INT
Yes
No
No
VAUXPWR<VSHORT
?
Charge Complete
Indicate DONE
32-Minute Timer
Active?
No
No
Yes
Yes
Termination Enabled
ITERM detected
Charge Complete
VAUXPWR < VOREG
VRCH
-
and VAUXPWR>VOREG-VRCH
?
?
High Impedance
Mode
Yes
Figure 23. Operational Flow Chart of bq24150A/1A in Charge Mode
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
DETAILED FUNCTIONAL DESCRIPTION
For a current limited power source, such as a USB host or hub, the high efficiency converter is critical in fully
using the input power capacity and charging the battery. Due to the high efficiency in a wide range of the input
voltage and battery voltage, the switching mode charger is a good choice for high speed charging with less
power loss and better thermal management.
The bq24150A/1A is a highly integrated synchronous switch-mode charger with bi-directional operation to
achieve boost function for USB OTG support, featuring integrated MOSFETs and small external components,
targeted at extremely space-limited portable applications powered by 1-cell Li-Ion or Li-polymer battery pack.
The bq24150A/1A usually has three operation modes: charge mode, boost mode, and high impedance mode. In
charge mode, the bq24150A/1A supports a precision Li-ion or Li-polymer charging system for single-cell
applications. In boost mode, bq24150A/1A boosts the battery voltage to VBUS for powering attached OTG
devices. In high impedance mode, the bq24150A/1A stops charging or boosting and operates in a mode with low
current from VBUS or battery, to effectively reduce the power consumption when the portable device in standby
mode. Through the proper control, bq24150A/1A can achieve the smooth transition among different operation
modes.
CHARGE MODE OPERATION
Charge Profile
In charge mode, bq24150A/1A has four control loops to regulate input current, charge current, charge voltage
and device junction temperature, as shown in Figure 21. During the charging process, all four loops are enabled
and the one that is dominant will take over the control. The bq24150A/1A supports a precision Li-ion or
Li-polymer charging system for single-cell applications. Figure 24(a) indicates a typical charge profile without
input current regulation loop and it is similar to the traditional CC/CV charge curve, while Figure 24(b) shows a
typical charge profile when input current limiting loop is dominant during the constant current mode, and in this
case the charge current is higher than the input current so the charge process is faster than the linear chargers.
For bq24150A/1A, the input current limits, the charge current, termination current, and charge voltage are all
programmable using I2C interface.
14
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
Voltage
Regulation
Current
Charge Voltage
VSHORT
Charge Current
Termination
I SHORT
Precharge
(Linear Charge)
Fast Charge
(PWM Charge)
(a)
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Voltage
VSHORT
Charge Current
Termination
ISHORT
Fast Charge
Precharge
(Linear Charge)
(PWM Charge)
(b)
Figure 24. Typical Charging Profile of bq24150A/1A for (a) without Input Current Limit, and (b) with Input
Current Limit
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
PWM Controller in Charge Mode
The bq24150A/1A provides an integrated, fixed 3 MHz frequency voltage-mode controller with Feed-Forward
function to regulate charge current or voltage. This type of controller is used to help improve line transient
response, thereby, simplifying the compensation network used for both continuous and discontinuous current
conduction operation. The voltage and current loops are internally compensated using a Type-III compensation
scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors
with low ESR. There is a 0.5-V offset on the bottom of the PWM ramp to allow the device to operate between 0%
to 99.5% duty cycles.
The bq24150A/1A has two back to back common-drain N-channel MOSFETs at the high side and one N-channel
MOSFET at low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than
VAUXPWR. The second high-side N-MOSFET (Q2) behaves as the switching control switch (see Figure 21). A
charge pump circuit is used to provide gate drive for Q1, while a boot strap circuit with an external boot-strap
capacitor is used to boost up the gate drive voltage for Q2.
Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2
is set to a nominal 2.3-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the
PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it
turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from
discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100mA to
minimize power losses.
Battery Charging Process
At the beginning of precharge, while battery voltage is below the V(SHORT) threshold, the bq24150A/1A applies a
short-circuit current, I(SHORT), to the battery.
When the battery voltage is above V(SHORT) and below V(OREG), the charge current ramps up to fast charge
current, IO(CHARGE), or a charge current that corresponds to the input current of I(IN_LIMIT). The slew rate for fast
charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input
current limit (default at 100 mA), IIN_LIMIT, and fast charge current, IO(CHARGE), can be set by the host. Once the
battery voltage is close to the regulation voltage, V(OREG), the charge current is tapered down as shown in
Figure 24. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT
and PGND pins. bq24150A/1A is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to
4.44 V) programmed through I2C interface.
The bq24150A/1A monitors the charging current during the voltage regulation phase. Once the termination
threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the bq24150A/1A
terminates charge. The termination current level is programmable. To disable the charge current termination, the
host can set the charge termination bit (I_Term) of charge control register to 0, see the I2C section for details.
A new charge cycle is initiated when one of the following conditions is detected:
•
•
•
The battery voltage falls below the V(OREG) – V(RCH) threshold.
VBUS Power-on reset (POR), if battery voltage is below the V(LOWV) threshold (bq24150A only).
CE bit toggle or RESET bit is set (host controlled)
Safety Timer in Charge Mode
At the beginning of charging process, the bq24150A/1A starts a 32-minute timer (T32min) that can be stopped by
any write-action performed by host through I2C interface. Once the 32-minute timer is stopped, a 32-second timer
(T32sec) is automatically started. The 32-second timer can be reset by host using I2C interface. Writing "1" to
reset bit of TMR_RST in control register resets the 32-second timer and TMR_RST is automatically set to "0"
after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge
parameters are reset to default values. Then the 32-minute timer starts and the charge resumes.
During normal charging process, the bq24150A/1A is normally in 32-second mode with host control, and
32-minute mode without host control using I2C interface. The process repeats until the battery is fully charged. If
the 32-minute timer expires, bq24150A/1A turns off the charger and enunciates FAULT on the STATx bits of
status register. This function prevents battery over charge if the host fails to reset the safety timer. The safety
timer flow chart is shown in Figure 25. Fault condition is cleared by POR and fault status bits can only be
updated after the status bits are read out by the host.
16
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
Charge Start
Start T32min
Timer
Reset Charge
Parameters
Yes
T32sec Expired?
Start T32sec
Stop T32min
No
No
Yes
Charge
Any I2C Write-
Action?
T32min
Expired?
T32min Active?
Yes
No
No
Host Should Reset
T32sec Timer
Yes
Timer Fault
(a)
Charge Start
(From Host Control)
Timer Fault
Stop Charge
T32sec Expired?
Yes
No
Charge
Host Should Reset
T32sec Timer
(b)
Figure 25. Timer Flow Chart for (a) bq24150A and (b) bq24151A in Charge Mode
USB Friendly Boot-Up Sequence
At power on reset (POR) of VBUS, if the battery voltage is above the weak battery threshold, V(LOWV), bq24150A
operates in a mode dictated by the I2C control registers. If the battery voltage is below V(LOWV) and the host
control through I2C interface is lost (32 minute mode), the bq24150A resets all I2C registers with default values
and enable the charger with an input current limit dictated by the OTG pin voltage level until the host programs
the I2C registers. During this period, the input current limit is 100 mA when the voltage level of OTG pin is low;
while the input current limit is 500 mA when the voltage level of OTG pin is high. This feature can revive the
deeply discharged cell. The charge process continues even the battery is charged to the regulation voltage
(default at 3.54 V) since termination is disabled by default. In another case, if the battery voltage is below
V(LOWV), but the host control using I2C interface is available (32 second mode), the bq24150A operates in a mode
dictated by control registers. However, at POR of VBUS, bq24151A goes to high impedance mode even the
battery voltage is below V(LOWV) and no host control through I2C interface is available. That is the major
difference between bq24150A and bq24151A.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Input Current Limiting
To maximize the charge rate of bq24150A/1A without overloading the USB port, the input current for
bq24150A/1A can be limited to 100mA or 500mA which is programmed in the control register or OTG pin. Once
the input current reaches the input current limiting threshold, the charge current is reduced to keep the input
current from exceeding the programmed threshold. For bq24150A, the default input current limit is controlled by
the OTG pin at VBUS power on reset when V(AUXPWR) is lower than V(LOWV). The input current sensing resistor
and control loop are integrated into bq24150A/1A. The input current limit can also be disabled using I2C control,
see the definition of control register (01H) for details.
Thermal Regulation and Protection
To prevent overheating the chip during the charging process, the bq24150A/1A monitors the junction
temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation
threshold, TCF. The charge current is reduced to zero when the junction temperature increases approximately
10°C above TCF. At any state, if TJ exceeds TSHTDWN, bq24150A/1A suspends charging. At thermal shutdown
mode, PWM is turned off and all timers are frozen. Charging resumes when TJ falls below TSHTDWN by
approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24150A/1A enters the low-power sleep mode if the voltage on VBUS pin falls below sleep-mode entry
threshold, VAUXPWR + VSLP, and VBUS is still higher than the poor source detection threshold, VIN(min). This
feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking
switch Q1 and PWM are turned off.
Input Source Detection
During the charging process, bq24150A/1A continuously monitors the input voltage, VBUS. If VBUS falls to the
low input voltage threshold, VIN(min), poor input power source is detected. Under this condition, bq24150A/1A
terminates the charge process, waits for a delay time of TINT and repeats the charging process, as indicated in
Figure 23. This unique function provides intelligence to bq24150A/1A and so prevents USB power bus collapsing
and oscillation when connecting to a suspended USB port, or a USB-OTG device with low current capability.
Input Overvoltage Protection
The bq24150A/1A provides a built-in input over-voltage protection to protect the device and other components
against damages if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage
condition is detected, bq24150A/1A turns off the PWM converter, sets fault status bits, and sends out fault pulse
in STAT pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge
process resumes.
Battery Protection in Charge Mode
Output Overvoltage Protection
The bq24150A/1A provides a built-in overvoltage protection to protect the device and other components against
damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage
condition is detected, bq24150A/1A turns off the PWM converter, sets fault status bits and sends out fault pulse
in STAT pin. Once V(CSOUT) drops to the battery overvoltage exit threshold, the fault is cleared and charge
process back to normal.
Battery Detection During Normal Charging
For applications with removable battery packs, the bq24150A/1A provides a battery absent detection scheme to
reliably detect insertion or removal of battery packs.
During normal charging process with host control, once the voltage at the AUXPWR pin is above the battery
recharge threshold, V(OREG) – V(RCH), and the termination charge current is detected, bq24150A/1A turns off the
charge and enables a discharge current, I(DETECT), for a period of tDETECT, then checks the battery voltage. If the
18
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
battery voltage is still above recharge threshold, the battery is present and the charge done is detected.
However, if the battery voltage is below battery recharge threshold, the battery is absent. Under this condition,
the charge parameters (such as input current limit) are reset to the default values and charge resumes after a
delay of TINT, as shown in Figure 23. This function ensures that the charge parameters are reset whenever the
battery is replaced.
Battery Detection at Power Up
The bq24150A has a unique battery detection scheme during the start up of the charger. At VBUS power up, if
the timer is in 32-minute mode, the bq24150A starts a 32ms timer when exiting from short circuit mode to PWM
charge mode. If the battery voltage is charged to recharge threshold (V(OREG) – V(RCH)) and the 32ms timer is not
expired yet, the bq2150A determines that the battery is not present; then stops charging and immediately goes to
the high impedance mode. However, if the 32ms timer is expired when the recharge threshold is reached, the
charging process continues as in the normal battery charging process.
Battery Short Protection
During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V(SHORT), the
charger operates in linear charge mode with a lower charge rate of I(SHORT), as shown in Figure 22.
Charge Status Output, STAT Pin
The STAT pin is used to indicate operation conditions for bq24150A/1A. STAT is pulled low during charging and
EN_STAT bit in control register (00H) is set to "1". Under other conditions, the STAT pin acts as a high
impedance (open-drain) output. Under fault conditions, a 128-µs pulse is sent out to notify the host. The status of
STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED
or communicate to the host processor.
Table 1. STAT Pin Summary
CHARGE STATE
Charge in progress and EN_STAT=1
Other normal conditions
STAT
Low
Open-drain
Charge mode faults: Timer fault, sleep mode, VBUS or battery
overvoltage, poor input source, VBUS UVLO, no battery,
thermal shutdown
128-µs pulse, then open-drain
Boost mode faults: Timer fault, over load, VBUS or battery
overvoltage, low battery voltage, thermal shutdown
128-µs pulse, then open-drain
Control Bits in Charge Mode
CE Bit (Charge Mode)
The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this bit
enables the charge and a high logic level (1) disables the charge.
RESET Bit
The bit of RESET in control register is used to reset all the charge parameters. Writing '1" to RESET bit resets all
the charge parameters to default values and RESET bit is automatically cleared to zero once the charge
parameters are reset. It is designed for charge parameter reset before charge starts, and it is not recommended
to set the RESET bit when charging or boosting in progress.
OPA_Mode Bit
OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the bq24150A/1A will go to the charge
related operation modes if HZ_MODE is set to "0", refer to Table 2 for detail.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Table 2. Operation Mode Summary
OPA_MODE HZ_MODE
OPERATION MODE
0
0
Charge (no fault)
Charge configure (fault, Vbus > VUVLO
)
High impedance (Vbus < VUVLO
)
1
0
1
Boost (no faults)
Any fault go to charge configure mode
High impedance
X
Boost Mode Operation
In 32 second mode, when the OTG pin is in active status or the bit of operation mode (OPA_MODE) at control
register is set to 1, the bq24150A/1A operates in boost mode and delivers the power to VBUS from the battery.
At normal boost mode, bq24150A/1A converts the battery voltage (2.5 V to 4.5 V) to VBUS-B (about 5.05 V) and
delivers a current as much as I(BO) (approximately 200 mA) to support other USB OTG devices connected to the
USB connector.
PWM Controller in Boost Mode
Similar to charge mode operation, in boost mode, the bq24150A/1A provides an integrated, fixed 3 MHz
frequency voltage-mode controller to regulate output voltage at PMID pin (VPMID), as shown in Figure 22. The
voltage control loop is internally compensated using a Type-III compensation scheme that provides enough
phase margin for stable operation with a wide load range and battery voltage range
In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is overloaded.
Cycle-by-cycle current limit is sensed through the internal sense MOSFET for Q3. The cycle-by-cycle current limit
threshold for Q3 is set to a nominal 1-A peak current. Synchronous operation is used in PWM mode to minimize
power losses.
Boost Start Up
To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start
up.
PFM Mode at Light Load
In boost mode, the bq2450A/1A operates in pulse skipping mode (PFM mode) to reduce the power loss and
improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once
the inductor current is less than 75 mA; and the PWM is turned back on only when the voltage at PMID pin drops
to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition
between PWM and PFM mode.
Safety Timer in Boost Mode
At the beginning of boost operation, the bq24150A/1A starts a 32-second timer that can be reset by host through
I2C interface. Writing "1" to reset bit of TMR_RST in the control register resets the 32-second timer and
TMR_RST is automatically set to "0" after the 32-second timer is reset. To keep in boost mode, the host must
reset the 32-second timer repeatedly. Once the 32-second timer expires, the bq24150A/1A turns off the boost
converter, enunciate the fault pulse in STAT pin and set fault status bits in status register. Fault condition is
cleared by POR or host control.
Protection in Boost Mode
Output Overvoltage Protection
The bq24150A/1A provides a built-in overvoltage protection to protect the device and other components against
damage if the VBUS voltage goes too high. When an overvoltage condition is detected, the bq24150A/1A turns
off the PWM converter, reset OPA_MODE bit to 0, sets fault status bits, and sends out fault pulse in STAT pin.
Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to "1", or the OTG pin
remains in active status.
20
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
Output Overload Protection
The bq24150A/1A provides a built-in overload protection to prevent the device and battery from damage when
VBUS is over loaded. Once over load condition is detected, Q1 operates in linear mode to limit the output current
while VPMID keeps in voltage regulation. If the overload condition lasts for more than 30 ms, the overload fault is
detected. When an overload condition is detected, the bq24150A/1A turns off the PWM converter, reset
OPA_MODE bit to 0, sets fault status bits, and sends out fault pulse in STAT pin. The boost will not start until the
host clears the fault register.
Battery Voltage Protection
During boosting, when battery voltage is above the battery overvoltage threshold, V(BATMX), or below the minimum
battery voltage threshold, V(BAT)min, the bq24150A/1A turns off the PWM converter, reset OPA_MODE bit to 0,
sets fault status bits, and sends out fault pulse in STAT pin. Once battery voltage goes back to the normal level,
the boost starts after host sets OPA_MODE to "1", or the OTG pin remains in active status.
STAT Pin Boost Mode
During normal boosting process, the STAT pin behaves as a high impedance (open-drain) output. Under fault
conditions, a 128-µs pulse is sent out to notify the host.
High Impedance Mode
When control bit of HZ-MODE is set to "1" and the OTG pin is not in active status, the bq24150A/1A operates in
high impedance mode, with the impedance in VBUS pin higher than 165 kΩ. In high impedance mode, a crude
32-second timer is enabled when the battery voltage is below V(LOWV) to monitor the host control is available or
not. If the crude 32 second timer expires, the bq24150A/1A operates in 32 minute mode and the crude 32
second timer is disabled. In 32 minute mode, when VBUS is below UVLO, the bq24150A/1A operates in high
impedance mode regardless of the setting of the HZ_MODE bit.
Output Inductor and Capacitance Selection Guidelines
The bq24150A/1A provides internal loop compensation. With this scheme, the best stability occurs when the LC
resonant frequency, ƒo, is approximately 40 kHz (20 kHz to 80 kHz). Equation 1 is used to calculate the value of
the output inductor, LOUT, and output capacitor, COUT
.
1
f
=
o
2p ´
L
´ C
OUT
OUT
(1)
To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 µF and 47 µF is
recommended for COUT, see the application section for components selection.
Pre-Regulator Application
Figure 2 shows a typical pre-regulator application that the bq24150A/1A operates as a DC/DC converter, with the
termination disabled. In this application, the host charge controller controls switch Q to achieve pulse-charging
function, and bq24150A/1A converts the input voltage to the lower output voltage (VOREG). The robust internal
compensation design ensures the stable operation when the host-controlled switch Q is turned off. With the input
overvoltage protection, output current regulation and high efficiency power conversion, the bq24150A/1A is an
ideal choice for pre-regulator used in pulse charging applications.
State Machine Table and State Diagram
Based on the previously-described operation modes, the definitions of all operation states are shown in Table 3
and Table 4, whereas the relationship among different states is shown in Figure 26.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Table 3. State Machine Table 1 of bq24150A/1A
MODE
POWER DOWN
CHARGE CONFIGURE
SHORT CIRCUIT
PWM CHARGE
OPA_MODE = 0
HZ_MODE = 0
OTG Inactive
VBUS > VUVLO
VBUS < VBUS(MIN)
or
OPA_MODE = 0
HZ_MODE = 0
OTG Inactive
VBUS > VBUS(MIN)
V(AUXPWR) < V(SHORT)
CE = Low
OPA_MODE = 0
HZ_MODE = 0
OTG Inactive
VBUS > VBUS(MIN)
V(AUXPWR) > V(SHORT)
CE = Low
VBUS < VUVLO
V(AUXPWR) < V(SHORT)
IN Condition
CE = HIGH
or
No Faults
No Faults
Faults During Charge
OPA_MODE = 1
or HZ_MODE = 1
or VBUS < VBUS(MIN)
or V(AUXPWR) > V(SHORT)
or CE = HIGH
OPA_MODE = 1
or HZ_MODE = 1
or VBUS < VBUS(MIN)
or V(AUXPWR) < V(SHORT)
or CE = HIGH
OPA_MODE = 1
or HZ_MODE = 1
or VBUS < VUVLO
or OTG Active
VBUS > VUVLO
or V(AUXPWR) > V(SHORT)
OUT Condition
or Faults
or Faults
or OTG Active
or OTG Active
I2C
Buck
I(SHORT)
Boost
Q1
Off
On
Off
On
Off
On
Off
On
On
On
Off
Off
On
Off
Off
Off
Off
Off
Off
On/Off
Note
POR when out
Table 4. State Machine Table 2 of bq24150A/1A
MODE
HIGH IMPEDANCE
BOOST CONFIGURE
BOOST
HZ_MODE = 0
(OPA_MODE = 1
or OTG active)
V(AUXPWR) > V(BATMIN)
Ready To Start Up
HZ_MODE = 0
(OPA_MODE = 1 or OTG active)
V(AUXPWR) > V(BATMIN)
Start Up Finished
HZ_MODE = 1
or
VBUS < VUVLO and
IN Condition
V(AUXPWR) > V(SHORT)
No Faults
HZ_MODE = 1 or OPA_MODE = 0
or V(AUXPWR) > V(BATMIN)
(OPA_MODE = 0 and OTG Inactive)
or (HZ_MODE = 1 and OTG Inactive)
or V(AUXPWR) < V(BATMIN)or Faults
OUT Condition
HZ_MODE = 0 or OTG Active
or Boost Start Up Finished
I2C
Buck
I(SHORT)
Boost
Q1
On
Off
Off
Off
Off
On
Off
On
Off
Off
On
On
Off
Off
On/Off(1)
(1) Q1 is OFF when VBUS is shorted to ground.
22
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
VBUS<VUVLO
VAUXPWR<VSHORT
VBUS>VUVLO
VAUXPWR<VLOWV
(bq24150A)
ANY STATE
POWER DOWN
VAUXPWR>VSHORT
VBUS
HZ_MODE=1
or VBUS<VUVLO, VAUXPWR>VSHORT
<
VUVLO
VBUS>VUVLO
HZ_MODE=0, OPA_MODE=0
HIGH
IMPEDANCE
CHARGE
CONFIGURE
HZ_MODE=1
OPA_MODE=1
HZ_MODE=0
HZ_MODE=1
Or
VAUXPWR<VLOWV
VAUXPWR>VSHORT
or VBUS<VBUS(MIN)
or FAULTS
OPA_MODE=1
HZ_MODE=0
VAUXPWR>VLOWV
OPA_MODE=0
VAUXPWR<VSHORT
VBUS>VBUS(MIN)
NO FAULTS
BOOST
CONFIGURE
HZ_MODE=1
or
VAUXPWR<VBATMIN
VAUXPWR<VSHORT
or VBUS<VBUS(MIN)
or FAULTS
SHORT
OPA_MODE=1
HZ_MODE=0
CIRCUIT
START UP
No FAULTS
VAUXPWR>VSHORT, VBUS>VBUS(MIN)
NO FAULTS
PWM CHARGE
BOOST
OPA_MODE=0
or FAULTS
Figure 26. State Diagram for bq24150A/1A
SERIAL INTERFACE DESCRIPTION
I2C™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The bq24150A/1A device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus™ Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps
in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be
programmed to new values depending on the instantaneous application requirements. Register contents remain
intact as long as supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off
of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is
recommended that SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as the HS-mode. The bq24150A/1A device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (6BH).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I2C-compatible devices should
recognize a start condition.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
DATA
CLK
S
P
START Condition
STOP Condition
Figure 27. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 28). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 28. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 30). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this
section will result in FFh being read out.
24
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
9
8
1
2
Clock Pulse for
Acknowledgement
START
Condition
Figure 29. Acknowledge on the I2C Bus™
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
Clock Line Held Low While
Interrupts are Serviced
Figure 30. Bus Protocol
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.
This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission
speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of
the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a
STOP condition to prevent the slave I2C logic from remaining in a bad state.
Attempting to read data from register addresses not listed in this section results in FFh being read out.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
bq24150A/1A I2C Update Sequence
The bq24150A/1A requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, bq24150A/1A device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the bq24150A/1A. The bq24150A/1A
performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
For the first update, bq24150A/1A requires a start condition, a valid I2C address, a register address byte, a data
byte. For all consecutive updates, bq24150A/1A needs a register address byte, and a data byte. Once a stop
condition is received, the bq24150A/1A releases the I2C bus, and awaits a new start conditions.
S
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
Data Transferred
A
DATA
P
A/A
‘0’ (Write)
(n Bytes + Acknowledge)
From master to bq24150
From bq24150/1 to master
A
A
= Acknowledge (SDA LOW)
= Not acknowledge (SDA
HIGH)
S
= START condition
Sr = Repeated START condition
= STOP condition
P
(a) F/S-Mode
F/S-Mode
F/S-Mode
HS-Mode
S
HS-MASTER CODE
Sr
SLAVE ADDRESS
R/W
A
REGISTER ADDRESS
A
DATA
P
A
A/A
Data Transferred
HS-Mode
‘0’ (write)
(n Bytes + Acknowledge)
Continues
Sr
Slave A.
(b) HS-Mode
Figure 31. Data Transfer Format in F/S Mode and H/S Mode
Slave Address Byte
MSB
LSB
1
X
1
1
0
1
0
1
The slave address byte is the first byte received following the START condition from the master device. The
address bits are factory preset to ‘1101011’.
Register Address Byte
MSB
LSB
D0
0
0
0
0
0
D2
D1
Following the successful acknowledgment of the slave address, the bus master will send a byte to the
bq24150A/1A, which contains the address of the register to be accessed. The bq24150A/1A contains five 8-bit
registers accessible via a bidirectional I2C-bus interface. Among them, four internal registers have read and write
access; and one has only read access.
26
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
I2C INTERFACE TIMING CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
Standard mode
MIN
TYP
MAX
100
UNIT
kHz
Fast mode
400
kHz
High-speed mode (write operation)
CB - 100 pF max
3.4
2
High-speed mode (read operation)
CB - 100 pF max
fSCL
SCL clock frequency
MHz
High-speed mode (write operation)
CB - 400 pF max
1.7
2
High-speed mode (read operation)
CB - 400 pF max
Standard mode
4.7
1.3
4
Bus free time between a STOP and
START condition
tBUF
µs
µs
ns
Fast mode
Standard mode
Hold time (repeated) START
condition
tHD; tSTA
Fast mode
600
160
4.7
1.3
160
320
4
High-speed mode
Standard mode
µs
Fast mode
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
ns
µs
Fast mode
600
60
tHIGH
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
ns
120
4.7
600
160
250
100
10
µs
Setup time for a repeated START
condition
tSU; tSTA
Fast mode
ns
High-speed mode
Standard mode
tSU; tDAT
Data setup time
Data hold time
Fast mode
ns
High-speed mode
Standard mode
3.45
0.9
µs
Fast mode
tHD; tDAT
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
70
ns
150
1000
300
40
20+0.1CB
20+0.1CB
10
Fast mode
tRCL
Rise time of SCL signal
ns
ns
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
20
80
20+0.1CB
20+0.1CB
10
1000
300
80
Rise time of SCL signal after a
repeated START condition and after
an acknowledge bit
Fast mode
tRCL1
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
20
160
300
300
40
20+0.1CB
20+0.1CB
10
Fast mode
tFCL
Fall time of SCL signal
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
20
80
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
SYMBOL
PARAMETER
TEST CONDITIONS
Standard mode
MIN
20+0.1CB
20+0.1CB
10
TYP
MAX
1000
300
80
UNIT
Fast mode
tRDA
Rise time of SDA signal
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
20
160
300
300
80
20+0.1CB
20+0.1CB
10
Fast mode
tFDA
Fall time of SDA signal
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
Standard mode
20
160
4
µs
ns
pF
tSU; tSTO
Setup time for STOP condition
Capacitive load for SDA and SCL
Fast mode
600
High-speed mode
160
CB
400
I2C Timing Diagrams
SDA
t
tf
SU;DAT
tLOW
t
tr
tHD;STA
t
tr
tf
SP
BUF
SCL
tHD;STA
t
t
SU;STA
SU;STO
tHIGH
tHD;DAT
S
P
S
Sr
Figure 32. Serial Interface Timing for F/S Mode
Sr
Sr P
t
rDA
t
fDA
SDAH
t
t
SU;STO
HD;DAT
t
SU;STA
t
t
HD;STA
SU;DAT
SCLH
t
fCL1
(1)
t
rCL1
t
t
rCL1
rCL1
(1)
t
t
t
t
HIGH
LOW
LOW
HIGH
= MCS current source pull-up
= R resister pull-up
P
Figure 33. Serial Interface Timing for H/S Mode
28
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
REGISTER DESCRIPTION
Table 5. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx
BIT
NAME
READ/WRITE
FUNCTION
Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, 0-OTG pin at Low level, 1-OTG pin at High level
B7 (MSB) TMR_RST/OTG
Read/Write
B6
B5
B4
B3
B2
B1
EN_STAT
STAT2
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
1-Boost mode, 0-Not in boost mode
STAT1
BOOST
FAULT_3
FAULT_2
Charge mode: 000-Normal, 001-VBUS OVP, 010-Sleep mode, 011-Poor input source or
VBUS < UVLO, 100-Output OVP, 101-Thermal shutdown, 110-Timer fault, 111-No
battery
Boost mode: 000-Normal, 001-VBUS OVP, 010-Over load, 011-Battery voltage is too
low, 100-Battery OVP, 101-Thermal shutdown, 110-Timer fault, 111-NA
B0 (LSB)
FAULT_1
Read Only
Table 6. Control Register (Read/Write)
Memory Location: 01, Reset State: 0011 0000 (30H)
BIT
B7 (MSB)
B6
NAME
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Iin_Limit_2
Iin_Limit_1
00-USB host with 100-mA current limit, 01-USB host with 500-mA current limit,
10-USB host/charger with 800-mA current limit, 11-No input current limit (default 00)
(1)
B5
V(LOWV_2)
VLOWV_1(1)
200mV weak battery voltage threshold (default 1)
B4
100mV weak battery voltage threshold (default 1)
B3
TE
1-Enable charge current termination, 0-Disable charge current termination (default 0)
1-Charger is disabled, 0-Charger enabled (default 0)
1-High impedance mode, 0-Not high impedance mode (default 0)
1-Boost mode, 0-Charger mode (default 0)
B2
CE
B1
HZ_MODE
OPA_MODE
B0 (LSB)
(1) The range of the weak battery voltage threshold (V(LOWV)) is 3.4 V to 3.7 V with an offset of 3.4 V and step of 100 mV (default 3.7 V).
Table 7. Control/Battery Voltage Register (Read/Write)
Memory Location: 02, Reset State: 0000 1010 (0AH)
BIT
B7 (MSB)
B6
NAME
VO(REG5)
VO(REG4)
VO(REG3)
VO(REG2)
VO(REG1)
VO(REG0)
OTG_PL
OTG_EN
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Battery Regulation Voltage: 640 mV (default 0)
Battery Regulation Voltage: 320 mV (default 0)
Battery Regulation Voltage: 160 mV (default 0)
Battery Regulation Voltage: 80 mV (default 0)
Battery Regulation Voltage: 40 mV (default 1)
Battery Regulation Voltage: 20 mV (default 0)
1-Active at High level, 0-Active at Low level (default 1)
1-Enable OTG Pin, 0-Disable OTG pin (default 0)
B5
B4
B3
B2
B1
B0 (LSB)
Charge voltage range is 3.5 V to 4.44 V with the offset of 3.5 V and step of 20 mV (default 3.54 V).
Table 8. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0100 x001
BIT
B7 (MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
READ/WRITE
Read Only
Read Only
Read Only
Read Only
Read Only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
Part Number Code: bit 1 (default 0)
B5
B4
B3
PN0
Part Number Code: bit 0 (default 0 for bq24151A, default 1 for bq24150A)
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
Table 8. Vender/Part/Revision Register (Read only)
Memory Location: 03, Reset State: 0100 x001 (continued)
BIT
B2
NAME
READ/WRITE
Read Only
Read Only
Read Only
FUNCTION
Revision2
Revision1
Revision0
011: Revision 1.3;
100-111: Future Revisions
B1
B0 (LSB)
Table 9. Battery Termination/Fast Charge Current Register (Read/Write)
Memory Location: 04, Reset State: 1000 1001 (89H)
BIT
B7 (MSB)
B6
NAME
Reset
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Write: 1-Charger in reset mode, 0-No effect, Read: always get "1"
Charge current sense voltage: 27.2 mV (default 0)
Charge current sense voltage: 13.6 mV(default 0)
Charge current sense voltage: 6.8 mV (default 0)
NA
VI(CHRG2)
VI(CHRG1)
VI(CHRG0)
NA
B5
B4
B3
B2
VI(TERM2)
VI(TERM1)
VI(TERM0)
Termination current sense voltage: 13.6 mV (default 0)
Termination current sense voltage: 6.8 mV (default 0)
Termination current sense voltage: 3.4 mV (default 1)
B1
B0 (LSB)
Default charge current is 550 mA and default termination current is 100 mA, if a 68-mΩ sensing resistor is used.
Both the termination current range and charge current range are depending on the sensing resistor R(SNS)). The
termination current step (IO(TERM_STEP)) is calculated using Equation 2:
V
I(TERM0)
I
=
O(TERM_STEP)
R
(SNS)
(2)
Table 10 shows the termination current settings with two sensing resistors.
Table 10. Termination Current Settings for 68-mΩ and 100-mΩ Sense Resistors
I(TERM) (mA)
R(SNS) = 68mΩ
I(TERM) (mA)
R(SNS) = 100mΩ
BIT
VI(TERM) (mV)
VI(TERM2)
VI(TERM1)
VI(TERM0)
Offset
13.6
6.8
3.4
3.4
200
100
50
136
68
34
50
34
The charge current step (IO(CHARGE_STEP)) is calculated using Equation 3:
V
I(CHRG0)
I
=
O(CHARGE_STEP)
R
(SNS)
(3)
Table 11 shows the charge current settings with two sensing resistors.
Table 11. Charge Current Settings for 68-mΩ and 100-mΩ Sense Resistors
IO(CHARGE) (mA)
R(SNS) = 68mΩ
IO(CHARGE) (mA)
R(SNS) = 100mΩ
BIT
VI(REG) (mV)
VI(CHRG2)
VI(CHRG1)
VI(CHRG0)
Offset
27.2
13.6
6.8
400
200
100
550
272
136
68
37.4
374
30
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
POWER TOPOLOGIES
System Load After Sensing Resistor
One of the simple high-efficiency topologies connects the system load directly across the battery pack, as shown
in Figure 34. The input voltage has been converted to a usable system voltage with good efficiency from the
input. When the input power is on, it supplies the system load and charges the battery pack at the same time.
When the input power is off, the battery pack powers the system directly.
SW
VBUS
Isns
Isys
Ichg
L1
Rsns
VIN
+
-
bq2415xA
System
Load
+
C3
C4
BAT
C1
PMID
C2
PGND
Figure 34. System Load After Sensing Resistor
The advantages:
•
When the AC adapter is disconnected, the battery pack powers the system load with minimum power
dissipations. Consequently, the time that the system runs on the battery pack can be maximized.
•
•
It saves the external path selection components and offers a low-cost solution.
Dynamic power management (DPM) can be achieved. The total of the charge current and the system current
can be limited to a desired value by adjusting charge current. When the system current increases, the charge
current drops by the same amount. As a result, no potential over-current or over-heating issues are caused
by excessive system load demand.
•
The total of the input current can be limited to a desired value by setting input current limit value. So USB
specifications can be met easily.
•
•
The supply voltage variation range for the system can be minimized.
The input current soft-start can be achieved by the generic soft-start feature of the IC.
Design considerations and potential issues:
•
•
•
If the system always demands a high current (but lower than the regulation current), the charging never
terminates. Thus, the battery is always charged, and the lifetime may be reduced.
Because the total current regulation threshold is fixed and the system always demands some current, the
battery may not be charged with a full-charge rate and thus may lead to a longer charge time.
If the system load current is large after the charger has been terminated, the voltage drop across the battery
impedance may cause the battery voltage to drop below the refresh threshold and start a new charge. The
charger would then terminate due to low charge current. Therefore, the charger would cycle between
charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold,
resulting in a much slower cycling.
•
In a charger system, the charge current is typically limited to about 10mA, if the sensed battery voltage is
below 2V short circuit protection threshold. This results in low power availability at the system bus. If an
external supply is connected and the battery is deeply discharged, below the short circuit protection threshold,
the charge current is clamped to the short circuit current limit. This then is the current available to the system
during the power-up phase. Most systems cannot function with such limited supply current, and the battery
supplements the additional power required by the system. Note that the battery pack is already at the
depleted condition, and it discharges further until the battery protector opens, resulting in a system shutdown.
•
If the battery is below the short circuit threshold and the system requires a bias current budget lower than the
short circuit current limit, the end-equipment will be operational, but the charging process can be affected
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
depending on the current left to charge the battery pack. Under extreme conditions, the system current is
close to the short circuit current levels and the battery may not reach the fast-charge region in a timely
manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process.
Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the
application possible.
•
For instance, if the battery pack voltage is too low, highly depleted, or totally dead or even shorted, the
system voltage is clamped by the battery and it cannot operate even if the input power is on.
System Load Before Sensing Resistor
The second circuit is very similar to first one; the difference is that the system load is connected before the sense
resistor, as shown in Figure 35.
Isys
SW
VBUS
Isns
L1
Rsns
Ichg
VIN
+
-
bq2415xA
System
Load
+
C3
C4
BAT
C1
PMID
C2
PGND
Figure 35. System Load Before Sensing Resistor
The advantages of system load before sensing resistor to system load after sensing resistor:
•
The charger controller is based only on the current goes through the current-sense resistor. So, the constant
current fast charge and termination functions work well, and are not affected by the system load. This is the
major advantage of it.
•
•
A depleted battery pack can be connected to the charger without the risk of the safety timer expiration caused
by high system load.
The charger can disable termination and keep the converter running to keep battery fully charged, or let the
switcher terminate when the battery is full and then run off of the battery via the sense resistor.
Design considerations and potential issues:
•
The total current is limited by the IC input current limit, or peak current protection, or the thermal regulation
but not the charge current setting. The charge current does not drop when the system current load increases
until the input current limit is reached. This solution is not applicable if the system requires a high current.
•
Efficiency declines when discharging through the sense resistor to the system.
DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS
Systems Design Specifications:
•
•
•
•
VBUS = 5 V
V(BAT) = 4.2 V (1-Cell)
I(charge) = 1.25 A
Inductor ripple current = 30% of fast charge current
1. Determine the inductor value (LOUT) for the specified charge current ripple:
32
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
VBAT ´ (VBUS - VBAT)
L
=
OUT
VBUS ´ f ´ DI
L
, the worst case is when battery voltage is as close as to half of the input
voltage.
2.5 ´ (5 - 2.5)
L
=
OUT
6
5 ´ (3 ´ 10 ) ´ 1.25 ´ 0.3
LOUT = 1.11 µH
Select the output inductor to standard 1 µH. Calculate the total ripple current with using the 1-µH inductor:
VBAT ´ (VBUS - VBAT)
DI =
L
VBUS ´ f ´ L
OUT
2.5 ´ (5 - 2.5)
DI =
L
6
-6
5 ´ (3 ´ 10 ) ´ (1 ´ 10
)
ΔIL = 0.42 A
Calculate the maximum output current:
DI
L
I
= I +
OUT
LPK
2
0.42
2
I
= 1.25 +
LPK
ILPK = 1.46 A
Select 2.5mm by 2.0mm 1-µH 1.5-A surface mount multi-layer inductor. The suggested inductor part
numbers are shown as following.
Table 12. Inductor Part Numbers
PART NUMBER
LQM2HPN1R0MJ0
INDUCTANCE
SIZE
MANUFACTURER
muRata
1 µH
1 µH
1 µH
1 µH
2.5 x 2.0 mm
2.5 x 2.0 mm
2.5 x 2.0 mm
2.5 x 2.0 mm
MIPS2520D1R0
MDT2520-CN1R0M
CP1008
FDK
TOKO
Inter-Technical
2. Determine the output capacitor value COUT using 40 kHz as the resonant frequency:
1
f
=
o
2p ´
L
´ C
OUT
OUT
1
C
=
OUT
2
4p ´ f
2
´ L
0
OUT
1
C
=
OUT
2
3 2
-6
4p ´ (40 ´ 10 ) ´ (1 ´ 10 )
COUT = 15.8 µF
Select two 0603 X5R 6.3V 10-µF ceramic capacitors in parallel i.e., muRata GRM188R60J106M.
3. Determine the sense resistor using the following equation:
V
(RSNS)
R
=
(SNS)
I
(CHARGE)
The maximum sense voltage across sense resistor is 85 mV. In order to get a better current regulation
accuracy, V(RSNS) should equal 85mV, and calculate the value for the sense resistor.
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
85mV
=
R
(SNS)
1.25A
R(SNS) = 68 mΩ
This is a standard value. If it is not a standard value, then choose the next close value and calculate the real
charge current. Calculate the power dissipation on the sense resistor:
P(RSNS) = I(CHARGE)2 × R(SNS)
P(RSNS) = 1252 × 0.068
P(RSNS) = 0.106 W
Select 0402 0.125-W 68-mΩ 2% sense resistor, i.e. Panasonic ERJ2BWGR068.
4. Measured efficiency and total power loss for different inductors are shown in Figure 36.
Battery Charge Efficiency
Battery Charge Loss
90
89
88
87
86
85
84
800
700
600
T =25°C,
T =25°C,
A
A
TOKO
VBUS = 5 V,
VBAT = 3 V
VBUS = 5 V,
VBAT = 3 V
FDK
muRata
Inter-Technical
muRata
500
400
300
TOKO
FDK
Inter-Technical
200
100
83
82
500 600 700 800 900 1000 1100 1200 1300
Charge Current - mA
500 600 700 800 900 1000 1100 1200 1300
Charge Current - mA
Figure 36. Measured Efficiency and Power Loss
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
•
To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the bq24150A/1A. The output inductor should be placed close to the IC and the output
capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current path loop
area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation
problems, proper layout to minimize high frequency current path loop is critical (see Figure 37). The sense
resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads
connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other
on adjacent layers (do not route the sense leads through a high-current path, see Figure 38).
•
•
Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for
small-signal components). A star ground design approach is typically used to keep circuit block currents
isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A
single ground plane for this design gives good results. With this small layout and a single ground plane, there
is no ground-bounce issue, and having the components segregated minimizes coupling between signals.
•
The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
34
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
www.ti.com ..................................................................................................................................................................................................... SLUS931–APRIL 2009
•
Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor as close to VBUS pin and PGND pin as possible to
make high frequency current loop area as small as possible (see Figure 39).
L1
R1
V
VBUS
BAT
SW
High
Frequency
BAT
V
IN
Current
Path
PMID
C2
PGND
C3
C1
Figure 37. High Frequency Current Path
Charge Current Direction
R
SNS
To Inductor
To Capacitor and battery
Current Sensing Direction
To CSIN and CSOUT pin
Figure 38. Sensing Resistor PCB Layout
VBUS
PMID
Vin+
1uF
SW
Vin-
4.7uF
PGND
Figure 39. Input Capacitor Position and PCB Layout Example
Copyright © 2009, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Link(s): bq24150A bq24151A
bq24150A
bq24151A
SLUS931–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(Top Side Symbol For bq24151A)
WCSP PACKAGE
(Top View)
CHIP SCALE PACKAGE
(Top Side Symbol For bq24150A)
A1
B1
C1
A2
B2
A3
B3
C3
A4
B4
TIYMLLLLS
bq24150A
TIYMLLLLS
bq24151A
C2
C4
D
D1
E1
D2
E2
D3
E3
D4
E4
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code
E
CHIP SCALE PACKAGING DIMENSIONS
The bq24150A/1A devices are available in a 20-bump chip scale package (YFF, NanoFreeTM). The package dimensions are:
· D = 1.976 ± 0.05 mm
· E = 1.946 ± 0.05 mm
36
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24150A bq24151A
PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2009
PACKAGING INFORMATION
Orderable Device
BQ24150AYFFR
BQ24150AYFFT
BQ24151AYFFR
BQ24151AYFFT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DSBGA
YFF
20
20
20
20
3000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
250 Green (RoHS &
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
250 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
BQ24150AYFFR
BQ24150AYFFT
BQ24151AYFFR
BQ24151AYFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
20
20
20
20
3000
250
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
2.18
2.18
2.18
2.18
2.18
2.18
2.18
2.18
0.81
0.81
0.81
0.81
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24150AYFFR
BQ24150AYFFT
BQ24151AYFFR
BQ24151AYFFT
DSBGA
DSBGA
DSBGA
DSBGA
YFF
YFF
YFF
YFF
20
20
20
20
3000
250
217.0
217.0
217.0
217.0
193.0
193.0
193.0
193.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
相关型号：
BQ24150AYFFR
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support
TI
BQ24150AYFFT
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support
TI
BQ24150YFFR
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24150YFFT
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24151
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24151A
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support
TI
BQ24151AYFFR
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support
TI
BQ24151AYFFT
Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support
TI
BQ24151YFFR
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24151YFFT
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24152
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
BQ24152YFFR
Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support
TI
©2020 ICPDF网 联系我们和版权申明