BQ24160_V01 [TI]
bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power Path Management and I2C Interface;
| 型号： | BQ24160_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power Path Management and I2C Interface 电池 |
| 文件： | 总53页 (文件大小：3606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power
Path Management and I2C Interface
1 Features
2 Applications
1
•
High-Efficiency Switched-Mode Charger with
Separate Power Path Control
•
•
•
•
Handheld Products
Portable Media Players
Portable Equipment
–
Instantly Start Up System from a Deeply
Discharged Battery or No Battery
Netbook and Portable Internet Devices
•
•
Compatible with MaxLife™ Technology for Faster
Charging When Used in Conjunction With
bq27530
3 Description
The bq24160, bq24160A, bq24161, bq24161B,
bq24163, and bq24168 are highly integrated single-
cell Li-Ion battery charger and system power path
management devices targeted for space-limited,
portable applications with high-capacity batteries. The
single-cell charger has dual inputs which allow
operation from either a USB port or a higher-power
input supply (that is, AC adapter or wireless charging
input) for a versatile solution. The two inputs are fully
isolated from each other and are easily selectable
using the I2C interface.
Dual Input, Integrated FET Charger for up to 2.5-A
Charging
–
20-V input rating, with Overvoltage Protection
(OVP)
–
–
6.5 V for USB Input up to 1.5 A
10.5 V for IN input (bq24160, bq24160A,
bq24161, bq24163) up to 2.5 A
–
6.5 V for IN input (bq24168) up to 2.5 A
•
Safe and Accurate Battery-Management
Functions
The power path management feature allows the
bq2416xx to power the system from a high-efficiency
–
1% Battery Regulation Accuracy
DC-DC
converter
while
simultaneously
and
–
10% Charge Current Accuracy
independently charging the battery. The power-path
management architecture enables the system to run
with a defective or absent battery pack and enables
instant system turnon even with a totally discharged
battery or no battery.
•
•
Charge Parameters Programmed Using I2C
Interface
Voltage-Based, NTC Monitoring Input
–
JEITA Compatible (bq24160, bq24160A,
bq24161B, bq24163, bq24168)
Device Information
PART NUMBER
bq2416xx
PACKAGE
VQFN (24)
DSBGA (49)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
2.80 mm × 2.80 mm
•
Available in small 2.8-mm × 2.8-mm 49-ball
WCSP or 4-mm × 4-mm VQFN-24 Packages
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Application Schematic
IN
SW
AC Adapter or
Wireless Power
System
Load
PMIDI
USB
VBUS
D+
D–
BOOT
SYS
GND
PMIDU
D+
D–
BAT
SDA
SCL
HOST
INT
TEMP PACK+
TS
PGND
DRV
+
–
V
SYS
PACK–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Table of Contents
9.5 Programming........................................................... 26
9.6 Register Maps......................................................... 29
10 Application and Implementation........................ 34
10.1 Application Information.......................................... 34
10.2 Typical Application ............................................... 34
11 Power Supply Recommendations ..................... 38
11.1 Requirements for SYS Output .............................. 38
11.2 Requirements for Charging................................... 38
12 Layout................................................................... 39
12.1 Layout Guidelines ................................................. 39
12.2 Layout Example .................................................... 40
13 Device and Documentation Support ................. 41
13.1 Related Links ........................................................ 41
13.2 Community Resources.......................................... 41
13.3 Trademarks........................................................... 41
13.4 Electrostatic Discharge Caution............................ 41
13.5 Glossary................................................................ 41
1
2
3
4
5
6
7
8
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Application Schematic .......................................... 1
Revision History..................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
8.1 Absolute Maximum Ratings ...................................... 6
8.2 Handling Ratings....................................................... 6
8.3 Recommended Operating Conditions....................... 6
8.4 Thermal Information.................................................. 7
8.5 Electrical Characteristics........................................... 7
8.6 Typical Characteristics............................................ 10
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 26
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 41
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2014) to Revision G
Page
•
Deleted hyperlink to unpublished application note SLUA727............................................................................................... 26
Changes from Revision E (November 2013) to Revision F
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changed the Ordering Information table to the Device Comparison Table ........................................................................... 4
Changed to VBAD_SOURCE include values for "During Bad Source Detection" ......................................................................... 8
Changed the Functional Block Diagram. Changed the device numbers above D+/D- and PSEL....................................... 13
Changed the PWM Controller in Charge Mode section to include the soft-start function.................................................... 15
•
•
•
•
•
Changed the Battery Charging Process section. New text added starting with "The bq2416xx monitors the charging
current.." ............................................................................................................................................................................... 15
•
•
•
Changed the Input Source Connected section..................................................................................................................... 16
Changed the Input Source Connected section..................................................................................................................... 18
Added the Reverse Boost (Boost Back) Prevention Circuit section..................................................................................... 24
Changes from Revision D (November 2012) to Revision E
Page
•
•
Added Feature: Compatible with MaxLife Technology for Faster Charging When Used in Conjunction With bq27530 ....... 1
Changed From: QFN-24 Package To: VQFN-24 Package throughout the data sheet.......................................................... 1
2
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Changes from Revision C (October 2012) to Revision D
Page
•
Changed the Ordering Information table to include the WSCP package for bq24161BRGR and bq24161BYFF................. 4
Changes from Revision B (September 2012) to Revision C
Page
•
Changed the Ordering Information table to include bq24160A .............................................................................................. 4
Changes from Revision A (March 2012) to Revision B
Page
•
•
•
Changed the Ordering Information table to include bq24161B .............................................................................................. 4
Changed text From: "battery FET (Q6)" To: "battery FET (Q4)" in the Battery Only Connected section ............................ 18
Changed From: VWARM < VTS < VHOT To: VWARM > VTS > VHOT, and Changed From: VCOLD < VTS < VCOOL To: VCOLD
>
VTS > VCOOL in the External NTC Monitoring (TS) section.................................................................................................... 21
•
Changed Figure 33 .............................................................................................................................................................. 40
Changes from Original (November 2011) to Revision A
Page
•
•
•
•
Changed the USB Pin numbers in the YFF pachkage for bq24160/3 From: A5-A6 To: A5-A7............................................. 5
Changed VBATREG - Voltage regulation accuracy ................................................................................................................... 7
Changed Figure 21 .............................................................................................................................................................. 34
Changed Figure 22 .............................................................................................................................................................. 35
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
D-
1
2
3
4
5
6
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
6 Device Comparison Table
TIMERS
(Safety and
Watchdog)
NTC
MONITORING
VBATSHRT/
IBATSHRT
(2)
PART NUMBER(1)
USB OVP
IN OVP
USB DETECTION
VMINSYS
3.0V
50mA
bq24160
bq24160A
bq24161
bq24161B
bq24163
bq24168
6.5V
6.5V
6.5V
6.5V
6.5V
6.5V
10.5V
10.5V
10.5V
10.5V
10.5V
6.5V
D+/D–
D+/D–
Yes
No
JEITA
JEITA
3.5V
3.5V
3.5V
3.5V
3.2V
3.5V
3.0V
50mA
PSEL (0=1.5A,
1=100mA)
2.0V
50mA
Yes
Yes
Yes
No
Standard
JEITA
PSEL (0=1.5A,
1=500mA)
3.0V
50mA
2.0V
50mA
D+/D–
JEITA
PSEL (0=1.5A,
1=100mA)
2.0V
50mA
JEITA
(1) Each of the above are available in as YFF and RGE packages with the following options:
R - tabed and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
(2) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
7 Pin Configuration and Functions
RGE Package
VQFN 24 Pins
Top View
18
17
16
15
14
SW
N.C.
1
2
3
4
5
6
18
17
16
15
SW
PGND
SGND
D+
PSEL
SCL
PGND
SGND
SCL
bq24161
bq24161B
bq241618
bq24160
bq24163
PGND
SYS
SDA
PGND
DRV
PGND
SYS
SDA
GND
DRV
14
13
13 SYS
SYS
YFF Package
WCSP 49 Pins
Top View
bq24161
bq24161B
bq24168
bq24160
bq24163
(Top View)
(Top View)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
IN
IN
IN
PMIDI
SW
IN
USB
USB
USB
IN
IN
IN
IN
USB
USB
USB
A
B
C
D
E
A
B
C
D
E
PMIDI
PMIDI
PMIDI
PMIDU
PMIDU
PMIDU
PMIDI
PMIDI
PMIDI
PMIDI
PMIDU
PMIDU
PMIDU
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
BOOT
PGND
PGND
PGND
PGND
PGND
BOOT
PGND
PGND
PGND
PGND
PGND
PGND
PSEL
D+
D-
CD
SDA
SCL
N.C.
CD
SDA
SCL
SYS
BAT
SYS
BAT
SYS
BAT
SYS
BAT
BGATE
INT
DRV
SYS
BAT
SYS
BAT
SYS
BAT
SYS
BAT
BGATE
INT
DRV
F
F
TS
STAT
PGND
TS
STAT
PGND
G
G
4
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Pin Functions
PIN
NO.
bq24160, 3
NO.
bq24161, 1B, 8
I/O
DESCRIPTION
NAME
YFF
RGE
YFF
RGE
BAT
G1-G4
11, 12
G1-G4
11, 12
I/O Battery Connection – Connect to the positive terminal of the battery. Additionally, bypass BAT
to GND with at least a 1μF capacitor.
BGATE
F5
10
F5
10
O
External Discharge MOSFET Gate Connection – BGATE drives an external P-Channel
MOSFET to provide a very low-resistance discharge path. Connect BGATE to the gate of the
external MOSFET. BGATE is low during high impedance mode and when no input is connected.
BOOT
CD
E7
E4
19
24
E7
E4
19
24
I
I
High Side MOSFET Gate Driver Supply – Connect a 0.01µF ceramic capacitor (voltage rating
> 10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
IC Hardware Chip Disable Input – Drive CD high to place the bq2416xx in high-z mode. Drive
CD low for normal operation. Do not leave CD unconnected.
D+
D–
E2
E3
2
1
—
—
—
—
I
I
D+ and D– Connections for USB Input Adapter Detection – When a charge cycle is initiated
by the USB input, and a short is detected between D+ and D–, the USB input current limit is set
to 1.5A. If a short is not detected, the USB100 mode is selected. The D+/D– detection has no
effect on the IN input.
DRV
F7
6
F7
6
O
Gate Drive Supply – DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass
DRV to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to
10mA. DRV is active whenever the input is connected and VSUPPLY > VUVLO and VSUPPLY > (VBAT
+ VSLP
)
IN
A1- A4
F6
21
7
A1- A4
F6
21
7
I
Input power supply – IN is connected to the external DC supply (AC adapter or alternate power
source). Bypass IN to PGND with at least a 1μF ceramic capacitor.
INT
O
Status Output – INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete or the charger
is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail
through a 100kΩ resistor to communicate with the host processor.
PGND
PMIDI
D1-D7,
E1, G7
5, 15,
16, 17
D1-D7,
E1, G7
5, 15,
16, 17
—
O
Ground terminal – Connect to the thermal pad (for VQFN only) and the ground plane of the
circuit.
B1-B4
B5-B7
—
20
23
—
B1-B4
B5-B7
E2
20
23
2
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power
Input – Bypass PMIDI to GND with at least a 4.7μF ceramic capacitor. Use caution when
connecting an external load to PMIDI. The PMIDI output is not current limited. Any short on
PMIDI will damage the IC.
PMIDU
PSEL
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for USB Input –
Bypass PMIDU to GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an
external load to PMIDU. The PMIDU output is not current limited. Any short on PMIDU will
damage the IC.
USB Source Detection Input – Drive PSEL high to indicate that a USB source is connected to
the USB input. When PSEL is high, the IC starts up with a 100mA (bq24161/8) or 500mA
(bq24161B) input current limit for USB. Drive PSEL low to indicate that an AC Adapter is
connected to the USB input. When PSEL is low, the IC starts up with a 1.5A input current limit
for USB. PSEL has no effect on the IN input. Do not leave PSEL unconnected.
I2C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
I2C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
SCL
E6
E5
G6
3
4
8
E6
E5
G6
3
4
8
I
SDA
STAT
I/O
O
Status Output – STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete or the
charger is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host.
STAT is enabled /disabled using the EN_STAT bit in the control register. Pull STAT up to a logic
rail thruogh an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
SW
C1-C7
F1-F4
18
C1-C7
F1-F4
18
O
I
Inductor Connection – Connect to the switched side of the external inductor.
SYS
13, 14
13,14
System Voltage Sense and Charger FET Connection – Connect SYS to the system output at
the output bulk capacitors. Bypass SYS locally with at least 10μF. A 47μF bypass capacitor is
recommended for optimal transient response.
TS
G5
9
G5
9
I
Battery Pack NTC Monitor – Connect TS to the center tap of a resistor divider from DRV to
GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA
compatibility (160, 161B, 163, 168 only). TS faults are reported by the I2C interface. See the
NTC Monitor section for more details on operation and selecting the resistor values. Connect TS
to DRV to disable the TS function.
USB
A5-A7
—
22
A5-A7
—
22
I
USB Input Power Supply – USB is connected to the external DC supply (AC adapter or USB
port). Bypass USB to PGND with at least a 1μF ceramic capacitor.
Thermal
Pad
Pad
Pad
—
There is an internal electrical connection between the exposed thermal pad and the PGND pin
of the device. The thermal pad must be connected to the same potential as the PGND pin on the
printed circuit board. Do not use the thermal pad as the primary ground input for the device.
PGND pin must be connected to ground at all times.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
20
20
12
7
UNIT
V
IN, USB
PMIDI, PMIDU, BOOT
–0.3
–0.7
–0.3
–0.3
4.5
V
Pin voltage range (with
respect to VSS)
SW
V
SDA, SCL, SYS, BAT, STAT, BGATE, DRV, TS, D+, D–, INT, PSEL, CD
V
BOOT to SW
7
V
SW
A
Output current (Continuous)
SYS, BAT
IN
3.5
A
2.75
1.75
10
A
Input current (Continuous)
Output sink current
USB
STAT
INT
A
mA
mA
°C
°C
° C
1
Operating free-air temperature range
Junction temperature, TJ
–40
–40
300
85
125
Lead temperature (soldering, 10 s)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
8.2 Handling Ratings
MIN
MAX
150
2
UNIT
°C
Tstg
Storage temperature range
–65
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
kV
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.2
MAX UNIT
IN voltage range
18
VIN
IN operating voltage range (bq24160/1/3)
IN operating voltage range (bq24168)
USB voltage range
4.2
4.2
4.2
4.2
10
6
V
18
6
VUSB
V
USB operating range
IIN
Input current, IN input
2.5
1.5
3
A
A
IUSB Input current USB input
ISYS Output Current from SW, DC
A
Charging
2.5
2.5
125
A
IBAT
Discharging, using internal battery FET
A
TJ
Operating junction temperature range
0
ºC
6
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
8.4 Thermal Information
bq2416xx
UNIT
THERMAL METRIC(1)
49 PINS (YFF)
24 PINS (RGE)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
49.8
0.2
1.1
1.1
6.6
n/a
32.6
30.5
3.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
9.3
θJCbot
2.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics
Circuit of Figure 21, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP, TJ
= -40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
PWM switching
15
mA
VUVLO < VSUPPLY < VOVP and
VSUPPLY > VBAT+VSLP
ISUPPLY
Supply current for control (VIN or VUSB
)
PWM NOT switching
5
175
5
0°C < TJ < 85°C, High-Z Mode
μA
μA
IBATLEAK
IBAT_HIZ
Leakage current from BAT to the Supply
0°C < TJ < 85°C, VBAT = 4.2V, VUSB = VIN = 0V
0°C< TJ < 85°C, VBAT = 4.2V, VSUPPLY = 5V or 0V,
SCL, SDA = 0 V or 1.8V, High-Z Mode
Battery discharge current in High Impedance mode,
(BAT, SW, SYS)
55
μA
POWER-PATH MANAGEMENT
bq24160, 1, 1B, 8
bq24163
3.60
3.3
3.7
3.4
3.82
3.5
Charge Enabled, VBAT < VMINSYS
VSYS(REG)
System regulation voltage
V
VBATREG
+ 1.5%
VBATREG
+ 3.0%
VBATREG
+ 4.17%
Battery FET turned off (Charge Disabled, TS Fault or
Charging Terminated)
bq24160, 1, 1B, 8
3.4
3.1
3.5
3.2
3.62
3.3
V
V
Charge enabled, VBAT < VMINSYS
Input current limit or VINDPM active
,
VMINSYS
Minimum system regulation voltage
Enter supplement mode threshold
bq24163
VBAT
–30mV
VBSUP1
VBAT > 2.5V
V
VBAT
–10mV
VBSUP2
Exit supplement mode threshold
VBAT > 2.5V
V
A
ILIM(discharge)
tDGL(SC1)
Current limit, discharge or supplement mode
Current monitored in internal FET only.
7
Deglitch time, SYS short circuit during discharge or
supplement mode
Measured from (VBAT – VSYS) = 300mV to BAT high-
impedance
250
μs
Recovery time, SYS short circuit during discharge or
supplement mode
tREC(SC1)
60
ms
V
Battery range for BGATE and supplement mode
operation
2.5
4.5
BATTERY CHARGER
YFF pkg
RGE pkg
37
50
57
70
Measured from BAT to SYS,
VBAT = 4.2V
RON(BAT-SYS) Internal battery charger MOSFET on-resistance
mΩ
Charge Voltage
Operating in voltage regulation, Programmable range
3.5
–1%
550
4.44
1%
V
VBATREG
Voltage regulation accuracy
Fast charge current range
Fast charge current accuracy
VBATSHRT ≤ VBAT < VBAT(REG) programmable range
2500
+10%
2.1
mA
ICHARGE
0°C to 125°C
–10%
1.9
bq24161, 3, 8
bq24160, 1B
2.0
3.0
50
VBATSHRT
Battery short circuit threshold
100mV Hysteresis
VBAT < VBATSHRT
V
2.9
3.1
IBATSHRT
Battery short circuit current
mA
ms
Deglitch time for battery short circuit to fastcharge
transition
tDGL(BATSHRT)
32
ITERM = 50mA
–35%
–15%
+35%
+15%
ITERM
Termination charge current accuracy
ITERM ≥ 100mA
tDGL(TERM)
VRCH
Deglitch time for charge termination
Recharge threshold voltage
Deglitch time
Both rising and falling, 2mV overdrive, tRISE, tFALL = 100ns
Below VBATREG
32
120
32
ms
mV
ms
tDGL(RCH)
VBAT falling below VRCH, tFALL=100ns
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Electrical Characteristics (continued)
Circuit of Figure 21, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP, TJ
= -40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
During battery detection source cycle
During battery detection sink cycle
Termination enabled (EN_TERM = 1)
MIN
TYP
3.3
3.0
2.5
MAX
UNIT
VDETECT
Battery detection threshold
V
IDETECT
Battery detection current before charge done (sink
current)
mA
tDETECT
VIH
Battery detection time
Termination enabled (EN_TERM = 1)
250
ms
V
PSEL, CD Input high logic level
PSEL, CD Input low logic level
1.3
VIL
0.4
V
INPUT CURRENT LIMITING
IUSBLIM = USB100
90
450
135
800
700
1250
1.35
2.3
95
475
100
500
150
900
800
1500
1.65
2.8
IUSBLIM = USB500
IUSBLIM = USB150
IUSBLIM = USB900
IUSBLIM = USB800
IUSBLIM = 1.5A
142.5
850
USB charge mode, VUSB = 5V,
DC Current pulled from SW
IIN_USB
Input current limit threshold (USB input)
mA
750
1400
1.5
IN charge mode, VIN = 5V,
DC Current pulled from SW
IINLIM = 1.5A
IIN_IN
Input current limit threshold (IN input)
A
V
IINLIM = 2.5A
2.5
Charge mode, programmable via I2C, both inputs
VIN_DPM
Input based DPM threshold range
VIN_DPM threshold accuracy
4.2
4.76
–2
+2%
5.45
450
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
VSUPPLY > 5.45V
5
5.2
V
IDRV
DRV output current
10
mA
mV
VDO_DRV
DRV Dropout voltage (VSUPPLY – VDRV
)
ISUPPLY = 1A, VSUPPLY = 5V, IDRV = 10mA
STATUS OUTPUT (STAT, INT)
VOL
Low-level output saturation voltage
IO = 10mA, sink current
VSTAT = VINT = 5V
0.4
1
V
IIH
High-level leakage current
µA
PROTECTION
VUVLO
IC active threshold voltage
IC active hysteresis
VIN rising
3.6
120
0
3.8
150
40
4
V
VUVLO_HYS
VSLP
VIN falling from above VUVLO
2.0V ≤VBAT ≤VBATREG, VIN falling
2.0V ≤VBAT ≤VBATREG
mV
mV
mV
ms
Sleep-mode entry threshold, VSUPPLY-VBAT
Sleep-mode exit hysteresis
100
175
VSLP_EXIT
40
100
30
Deglitch time for supply rising above VSLP+VSLP_EXIT
Rising voltage, 2mV over drive, tRISE = 100ns
After Bad Source Detection completes
VIN_DPM
– 80 mV
V
VBAD_SOURCE Bad source detection threshold
During Bad Source Detection
VIN_DPM
+ 80 mV
V
tDGL(BSD)
Deglitch on bad source detection
Input supply OVP threshold voltage
32
6.5
ms
USB, VUSB Rising
6.3
10.3
6.3
6.7
10.7
6.7
VOVP
IN, VIN Rising (bq24160/1/1B/3)
IN, VIN Rising (bq24168)
Supply falling from VOVP
10.5
6.5
V
VOVP(HYS)
VBOVP
VOVP hysteresis
100
mV
V
1.025 ×
VBATREG
1.05 ×
VBATREG
1.075 ×
VBATREG
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
Lower limit for VBAT falling from above VBOVP
% of
VBATREG
VBOVP hysteresis
1
1
tDGL(BOVP)
Battery OVP deglitch
BOVP fault shown in register once tDGL(BOVP) expires.
ms
Buck converter shut down immediately when VBAT > VBATOVP
VBATUVLO
ILIMIT
Battery undervoltage lockout threshold
Cycle-by-cycle current limit
Thermal trip
VBAT rising, 100mV hysteresis
VSYS shorted
2.5
4.9
165
10
V
A
4.1
5.6
TSHTDWN
°C
Thermal hysteresis
TREG
Thermal regulation threshold
Safety timer accuracy
Charge current begins to cut off
(bq24160/1/1B/3 Only)
120
°C
–20%
20%
PWM
IIN_LIMIT = 500mA, Measured from USB to PMIDU
IIN_LIMIT = 500mA, Measured from IN to PMIDI
95
45
175
80
Internal top reverse blocking MOSFET on-resistance
mΩ
8
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Electrical Characteristics (continued)
Circuit of Figure 21, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP, TJ
= -40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
65
MAX
175
110
115
1.65
UNIT
Measured from PMIDU to SW
Internal top N-channel Switching MOSFET on-
resistance
mΩ
Measured from PMIDI to SW
Measured from SW to PGND
Internal bottom N-channel MOSFET on-resistance
Oscillator frequency
65
mΩ
fOSC
1.35
0%
1.50
95%
MHz
DMAX
DMIN
Maximum duty cycle
Minimum duty cycle
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling
29.7
37.9
56
30
1
30.5
39.6
56.9
60.4
73
%VDRV
%VDRV
%VDRV
%VDRV
VHYS(HOT)
VWARM
VHYS(WARM)
VCOOL
VHYS(COOL)
VCOLD
Hysteresis on high threshold
High temperature threshold
Hysteresis on high threshold
Low temperature threshold
Hysteresis on low threshold
Low temperature threshold
Hysteresis on low threshold
TS Disable threshold
VTS rising
VTS falling
38.3
1
VTS rising
VTS falling
56.5
1
VTS rising
VTS falling
59.5
70
60
1
VHYS(COLD)
TSOFF
tDGL(TS)
VTS rising
VTS rising, 2%VDRV hysteresis
%VDRV
ms
Deglitch time on TS change
50
0.6
D+/D– DETECTION (bq24160)
VD+_SRC
ID+_SRC
ID-_SINK
ID_LKG
D+ Voltage Source
0.5
7
0.7
14
150
1
V
µA
µA
µA
µA
V
D+ Connection Check Current Source
D- Current Sink
50
100
D–, switch open
D+, switch open
–1
Leakage Current into D+/D-
–1
1
VD+_LOW
D+ Low Comparator Threshold
D- Low Comparator Threshold
D- Pulldown for Connection Check
0.8
250
14.25
VD-_LOWdatref
RD-_DWN
BATGD OPERATION
VBATGD Good Battery threshold
Deglitch for good battery threshold
I2C COMPATIBLE INTERFACE
400
mV
kΩ
24.8
3.6
1.3
3.8
32
3.9
V
VBAT rising to HIGH-Z mode, DEFAULT Mode Only
ms
VIH
Input low threshold level
VPULL-UP = 1.8V, SDA and SCL
VPULL-UP = 1.8V, SDA and SCL
IL = 10mA, sink current
V
V
VIL
Input low threshold level
Output low threshold level
High-Level leakage current
Watchdog timer timeout
0.4
0.4
VOL
V
IBIAS
VPULL-UP = 1.8V, SDA and SCL
(bq24160/1/3 Only)
1
μA
s
tWATCHDOG
30
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
8.6 Typical Characteristics
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 7 V
VIN = 9 V
VUSB = 5 V
VUSB = 6 V
0.1
1
3
0.1
1
2
System Current (A)
System Current (A)
G001
G002
Charge Disabled
SYS loaded
Charge Disabled
SYS loaded
VBATREG = 3.6V
IN2500 ILIM
VBATREG = 3.6V
USB1500 ILIM
Figure 1. IN Efficiency
Figure 2. USB Efficiency
3.9
3.85
3.8
4.21
4.208
4.206
4.204
4.202
4.2
SYSREG Regulation
MINSYS Regulation
3.75
3.7
3.65
3.6
4.198
4.196
4.194
4.192
3.55
3.5
3.45
3.4
−50
4.19
0
0
50
Temperature (°C)
100
150
25
50
75
100
125
Temperature (°C)
G003
G004
VBAT = 3V
VBATREG = 4.2V
No load
Termination Disabled
Figure 3. SYSREG and MINSYS Regulation vs Temperature
Figure 4. Battery Regulation vs Temperature
700
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
USB100 Current Limit
USB500 Current Limit
Falling Edge
Rising Edge
600
500
400
300
200
100
0
−50
0
50
Temperature (°C)
100
150
−50
0
50
100
150
Temperature (°C)
G005
G006
USB100 and USB500 current limit
VUSB = 5V
USB input and IN input (bq24168)
VBAT = 3.6V
Figure 5. USB Input Current Limit vs. Temperature
Figure 6. 6.5V OVP Threshold vs. Temperature
10
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Typical Characteristics (continued)
10.7
2.1
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2
Falling Edge
Rising Edge
10.6
10.5
10.4
10.3
10.2
10.1
10
−50
0
50
100
150
2
2.5
3
3.5
4
4.5
Temperature (°C)
Battery Voltage (V)
G007
G008
ICHARGE = 2A
VIN = 5V
VBATREG = 4.44V
Figure 7. 10.5V OVP Threshold vs. Temperature
Figure 8. Charge Current vs. Battery Voltage
0.055
0.054
0.053
0.052
0.051
0.05
0
0.5
1
1.5
2
2.5
3
Battery Voltage (V)
G009
Figure 9. IBATSHRT vs. Battery Voltage
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
9
Detailed Description
9.1 Overview
The bq24160/bq24160A/bq24161/bq24161B/bq24163/bq24168 devices are highly integrated single-cell Li-Ion
battery chargers and system power path management devices targeted for space-limited, portable applications
with high-capacity batteries. The dual-input, single-cell charger operates from either a USB port or alternate
power source (that is, wall adapter or wireless power input) for a versatile solution.
The power path management feature allows the bq2416xx to power the system from a high-efficiency DC-DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turnon even with a totally discharged battery or no battery. The power-
path management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The 2.5-A current
capability allows for GSM phone calls as soon as the adapter is plugged in regardless of the battery voltage. The
charge parameters are programmable using the I2C interface.
12
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
9.2 Functional Block Diagram
PMIDU
PMIDI
5.2-V Reference
DRV
IN
Q1
USB
5A
BOOT
CbC Current
Limit
IN IINLIM
USB IUSBLIM
IN VINDPM
DC-DC CONVERTER
PWM LOGIC,
COMPENSATION
AND
BATTERY FET CONTROL
Q2
USB VINDPM
VSYS(REG)
IBAT(REG)
SW
VBAT(REG)
DIE Temp
Regulation
Q3
PGND
SYS
VSUPPLY
SUPPLY_SEL
Termination
References
+
VUSB
Reference
VUSBOVP
+
IBAT
OVP Comparators
+
Q4
Termination Comparator
VIN
BAT
VINOVP
Recharge Comparator
+
VBATREG – 0.12V
Start Recharge
Cycle
+
VBAT
VUSB
VSYSREG Comparator
VBAT + VSLP
+
VSYS
Enable Linear
Charge
Sleep Comparators
+
VMINSYS
VIN
+
VBAT
Good Battery
Circuit
VBAT + VSLP
Hi-Z Mode
BGATE
VBATGD
VBATSC Comparator
CD
Hi-Z Mode
+
Enable
IBATSHRT
VBAT
VBATSHRT
SDA
I2C
Interface
Supplement Comparator
+
+
VSYS
SCL
VBAT
VBSUP
VDRV
bq24160, 60A, 3
VBOVP Comparator
+
USB
VBAT
D+
D–
Adapter
Detection
Circuitry
1.5A/USB100
VBATOVP
+
+
DISABLE
1C/0.5C
TS COLD
TS COOL
bq24161, 1B, 8
PSEL
bq24160/2/3
+
+
VBATREG – 0.14V
DISABLE
STAT
INT
TS WARM
TS HOT
CHARGE
CONTROLLER
with Timers (160/1/3)
TS
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
9.3 Feature Description
9.3.1 Charge Mode Operation
9.3.1.1 Charge Profile
The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS voltage, the
internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the battery.
When battery is less than MINSYS, the SYS is regulated to VSYS(REG) and battery is charged using the battery
FET to regulate the charge current. There are 5 loops that influence the charge current:
•
•
•
•
•
Constant current loop (CC)
Constant voltage loop (CV)
Thermal-regulation loop
Minimum system-voltage loop (MINSYS)
Input-voltage dynamic power-management loop (VIN-DPM)
During the charging process, all five loops are enabled and the one that is dominant takes control. The bq2416xx
supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even for a missing or deeply discharged battery. Figure 10 shows a typical charge profile including the minimum
system output voltage feature.
Voltage Regulation
Phase
Precharge
Phase
Current Regulation
Phase
Regulation
voltage
Charge Current
Regulation
Threshold
System Voltage
V
SYS
V
BATSHORT
Battery
Voltage
Charge Current
Termination
Current
Threshold
I
BATSHORT
Linear Charge
to Maintain
Battery
FET
is OFF
50mA Precharge to
Close Pack Protector
Battery FET is ON
Minimum
System
Voltage
Figure 10. Typical bq2416xx Charging Profile
14
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
9.3.1.2 PWM Controller in Charge Mode
The bq2416xx provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to power the system and
supply the charge current. The voltage loop is internally compensated and provides enough phase margin for
stable operation, allowing the use of small ceramic capacitors with low ESR. When starting up, the bq2416xx
uses a "soft-start" function to help limit inrush current. When coming out of High Impedance mode, the bq2416xx
starts up with the input current limit set to 40% of the value programmed in the I2C register. After 80ms, the input
current limit threshold steps up in 256µs steps. The steps are 40% to 50%, then 50% to 60%, then 60% to 70%,
then 70% to 80%, and finally 80% to 100%. After the final step, soft start is complete and will not be restarted
until the bq2416xx enters High Impedance mode.
The input scheme for the bq2416xx prevents battery discharge when the supply voltages are lower than VBAT
and also isolates the two inputs from each other. The high-side N-MOSFET (Q1/Q2) switches to control the
power delivered to the output. The DRV LDO provides a supply for the gate drive for the low side MOSFET,
while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up the gate drive voltage for
Q1 and Q2.
Both inputs are protected by a cycle-by-cycle current limit that is sensed through the high-side MOSFETs for Q1
and Q2. The threshold for the current limit is set to a nominal 5A peak current. The inputs also utilize an input
current limit that limits the current from the power source.
9.3.2 Battery Charging Process
Assuming a vaild input source is attached to IN or USB, as soon as a deeply discharged or shorted battery is
attached to the BAT pin, (VBAT < VBATSHRT), the bq2416xx applies IBATSHRT to close the pack protector switch and
bring the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly regulated
and the system output is regulated to VSYS(REG). Once the battery rises above VBATSHRT, the charge current is
regulated to the value set in the I2C register. The battery FET is linearly regulated to maintain the system voltage
at VSYS(REG). Under normal conditions, the time spent in this region is a very short percentage of the total
charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for
very long. If the die temperature does rise, the thermal regulation circuit reduces the charge current to maintain a
die temperature less than 120°C. If the current limit for the SYS output is reached (limited by the input current
limit, or VIN_DPM), the SYS output drops to the VMINSYS output voltage. When this happens, the charge current is
reduced to provide the system with all the current that is needed while maintaining the minimum system voltage.
If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery
voltage and enter supplement mode. (See the Dynamic Power Path Management section for more details.)
Once the battery is charged enough so that the system voltage begins to rise above VSYS(REG), the battery FET is
turned on fully and the battery is charged with the full programmed charge current set by the I2C interface,
ICHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during
transients. The charge current is regulated to ICHARGE until the battery is charged to the regulation voltage. As the
battery voltage rises above VRCH, the battery regulation loop is activated. This may result in a small step down
in the charge current as the loops transition between the charge current and charge voltage loops. As the battery
voltage charges up to the regulation voltage, VBATREG, the charge current is tapered down as shown in Figure 10
while the SYS output remains connected to the battery. The voltage between the BAT and PGND pins is
regulated to VBATREG. The bq2416xx is a fixed single-cell voltage version, with adjustable regulation voltage (3.5V
to 4.44V), programmed using the I2C interface.
The bq2416xx monitors the charging current during the voltage-regulation phase. If the battery voltage is above
the recharge threshold and the charge current has naturally tapered down to and remains below termination
threshold, ITERM, (without disturbance from events like supplement mode) for 32ms, the charger terminates
charge, turns off the battery charging FET and enters battery detection. Termination is disabled when the charge
current is reduced by a loop other than the voltage regulation loop or the input current limit is set to 100 mA. For
example, when the bq2416xx is in half charge due to TS function, reverse boost protection is active, LOW_CHG
bit is set, or the thermal regulation, VINDPM or input current loops are active, termination will not occur. This
prevents false termination events. During termination, the system output is regulated to the VSYS(REG) and
supports the full current available from the input and the battery supplement mode is available. (See the Dynamic
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
Power Path Management section for more details.) The termination current level is programmable. When setting
the termination threshold less than 150mA, the reverse boost protection may trip falsely with load transients and
very fully charged batteries. This will prevent termination while in the reverse boost protection and may extend
charge time. To disable the charge current termination, the host sets the charge termination bit (TE) of charge
control register to 0, refer to I2C section for details.
A new charge cycle is initiated if CD is low when either
1. VSUPPLY rises above UVLO while a battery with VBAT < VBATREG - VRCH is attached or
2. a battery with VBAT < VBATREG - VRCH is attached while VSUPPLY is above UVLO.
With VSUPPLY above UVLO and V(BAT) < VBOVP, a recharge cycle is initiated when one of the following conditions
is detected:
1. The battery voltage falls below the VBAT(REG)-VRCH threshold.
2. CE bit toggle or RESET bit toggle
3. Supplement mode event occurs
4. CD pin or HI-Z bit toggle
VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold,
the battery OVP circuit shuts the PWM converter off immediately and the battery FET is turned on to discharge
the battery to safe operating levels. If the battery OVP condition exists for the 1ms deglitch, a battery OVP fault is
reported in the I2C status registers. The battery OVP fault is cleared when the battery voltage discharges below
VRCH or if the IC enters hi-impedance mode (HZ_MODE=1 or CD=1). Always write bq2416xx to high impedance
mode before changing VBATREG to clear BOVP condition to ensure proper operation.
If the battery voltage is ever greater than VBATREG (for example, when an almost fully charged battery enters
the JEITA WARM state due to the TS pin) but less than VBOVP, the reverse boost protection circuitry may activate
as explained later in this datasheet. If the battery is ever above VBOVP, the buck converter turns off and the
internal battery FET is turned on. This prevents further overcharging of the battery and allows the battery to
discharge to safe operating levels. The battery OVP event does not clear until the battery voltage falls below
VRCH
.
9.3.3 Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is
pulled from VBAT for tDETECT to verify there is a battery. If the battery voltage remains above VDETECT for the full
duration of tDETECT, a battery is determined to present and the IC enters “Charge Done”. If VBAT falls below
VDETECT, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of battery
detection, the bq2416xx turns on IBATSHORT for tDETECT. If VBAT rises to VDETECT, the current source is turned
offand after tDETECT, the battery detection continues through another current sink cycle. Battery detection
continues until charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and
a new charge cycle begins. Battery detection is not run when termination is disabled.
9.3.4 Dynamic Power Path Management (DPPM)
The bq2416xx features a SYS output that powers the external system load connected to the battery. This output
is active whenever a source is connected to IN, USB or BAT. The following sections discuss the behavior of SYS
with a source connected to the supply or a battery source only.
9.3.5 Input Source Connected
When a valid input source is connected to IN or USB and the bq2416xx is NOT in High Impedance mode, the
buck converter enters soft-start and turns on to power the load on SYS. The STAT/INT pin outputs a 128µs
interrupt pulse to alert the host that an input has been connected. The FAULT bits indicate a normal condition,
and the Supply Status register indicates that a new supply is connected. The CE bit (bit 1) in the control register
(0x02) indicates whether a charge cycle is initiated. By default, the bq2416xx (CE=0) enables a charge cycle
when a valid input source is connected. When the CE bit is '1' and a valid input source is connected, the battery
FET is turned off and the SYS output is regulated to the VSYS(REG) programmed by the VBATREG threshold in the
I2C register. A charge cycle is initiated when the CE bit is written to a 0 value (cleared).
16
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
When the CE bit is a 0 and a valid source is connected to IN or USB, the buck converter starts up using soft-
start. A charge cycle is initiated 64ms after the buck converter iniates startup. When VBAT is high enough that
VSYS > VSYS(REG), the battery FET is turned on and the SYS output is connected to BAT. If the SYS voltage falls
to VSYS(REG), it is regulated to that point to maintain the system output even with a deeply discharged or absent
battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET linearly
regulates the charge current into the battery. The current from the supply is shared between charging the battery
and powering the system load at SYS. The dynamic power-path management (DPPM) circuitry of the bq2416xx
monitors the current limits continuously, and if the SYS voltage falls to the VMINSYS voltage, it adjusts charge
current to maintain the minimum system voltage and supply the load on SYS. If the charge current is reduced to
zero and the load increases further, the bq2416xx enters battery-supplement mode. During supplement mode,
the battery FET is turned on and the battery supplements the system load.
When an input is connected with no battery attached and termination enabled, the startup process proceeds as
normal until the termination deglitch times out. After this, the bq2416xx enters battery detection and waits for a
battery to be connected. Once a battery is connected and passes battery detection, a new charge cycle begins.
Once the battery is applied, the HZMODE bit or CD pin must be toggled before writing the BATREG to a higher
voltage and beginning a new charge cycle. Failure to do this can result in SYS unexpectedly regulating to 15%
above VBATREG
.
2000 mA
1800 mA
ISYS
800 mA
mA
0
1500 mA
~850 mA
IIN
0mA
1A
IBAT
0mA
-200 mA
VSYS(REG)
VMINSYS
DPPM loop active
VOUT
~3.1V
Supplement
Mode
Figure 11. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input Current Limit)
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
9.3.6 Battery Only Connected
When a battery with voltage greater than VBATUVLO is connected with no input source, the battery FET is turned
on similar to supplement mode. In this mode, the current is not regulated; however, there is a short circuit current
limit. If the short circuit limit is reached, the battery FET is turned off for the deglitch time (tDGL(SC1)). After the
recovery time (tREC(SC1)), the battery FET is turned on to test and see if the short has been removed. If it has not,
the FET turns off and the process repeats until the short is removed. This process is to protect the internal FET
from over current. If an external FET is used for discharge, the external FET's body diode prevents the load on
SYS from being disconnected from the battery. If the battery voltage is less than VBATUVLO, the internal battery
FET (Q4) remains off and BAT is high-impedance. This prevents further discharging of deeply-discharged
batteries.
9.3.7 Battery Discharge FET (BGATE)
The bq2416xx contains a MOSFET driver to drive the gate of an external discharge FET between the battery and
the system output. This external FET provides a low impedance path when supplying the system from the
battery. Connect BGATE to the gate of the external discharge MOSFET. BGATE is on under the following
conditions:
1. No input supply connected.
2. HZ_MODE bit = 1
3. CD pin = 1
9.3.8 DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT< VBATGD before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In DEFAULT mode, the I2C registers are reset to the default values. The 27-minute safety timer (no timer for
bq24168) is reset and starts when DEFAULT mode is entered. The default value for VBATREG is 3.6V, and the
default value for ICHARGE is 1A. The input current limit for the IN input is set to 1.5A. The input current limit for the
USB input is determined by the D+/D– detection (bq24160/3) or PSEL (bq24161/1B/8). PSEL and D+/D–
detection have no effect on the IN input. Default mode is exited by programming the I2C interface. Once I2C
communication is established, PSEL has no effect on the USB input. Note that if termination is enabled and
charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.
9.3.9 Safety Timer and Watchdog Timer (bq24160/ bq24161/ bq24161B/ bq24163 only)
At the beginning of charging process, the bq24160/1/1B/3 starts the safety timer. This timer is active during the
entire charging process. If charging has not terminated before the safety timer expires, charging is disabled, the
charge parameters are reset to the default values and the CE bit is written to a “1”. The length of the safety timer
is selectable using the I2C interface. A single 128μs pulse is sent on the STAT and INT outputs and the STATx
bits of the status registers are updated in the I2C. In DEFAULT mode, the safety timer can be reset and a new
charge cycle initiated by input supply power on reset, removing/inserting battery or toggling the CD pin. In HOST
mode, the CE bit is set to a '1' when the safety timer expires. The CE bit must be cleared to a '0' in order to
resume charging and clear the safety timer fault. The safety timer duration is selectable using the TMR_X bits in
the Safety Timer Register/ NTC Monitor register. Changing the safety timer duration resets the safety timer. This
function prevents continuous charging of a defective battery. During the fast charge (CC) phase, several events
increase the timer duration by 2X if the EN_2X_TMR bit is set in the register.
1. The system load current reduces the available charging current.
2. The input current needed for the fast charge current is limited by the input current loop.
3. The input current is reduced because the VINDPM loop is preventing the supply from crashing.
4. The device has entered thermal regulation because the IC junction temperature has exceeded TJ(REG).
5. The LOW_CHG bit is set.
18
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
6. The battery voltage is less than VBATSHORT.
7. The battery has entered the JEITA WARM or COLD state via the TS pin
During these events, the timer is slowed by half to extend the timer and prevent any false timer faults. Starting a
new charge cycle by VSUPPLY POR or removing/replacing the battery or resuming a charge by toggling the CE
or HZ_MODE bits, resets the safety timer. Additionally, thermal shutdown events cause the safety timer to reset.
In addition to the safety timer, the bq24160/1/1B/3 contain a watchdog timer that monitors the host through the
I2C interface. Once a read/write is performed on the I2C interface, a 30-second timer (tWATCHDOG) is started. The
30-second timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit
(TMR_RST) in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is
reset. This process continues until the battery is fully charged or the safety timer expires. If the 30-second timer
expires, the IC enters DEFAULT mode where the default register values are loaded, the safety timer restarts at
27 minutes and charging continues. The I2C may be accessed again to reinitialize the desired values and restart
the watchdog timer. The watchdog timer flow chart is shown in Figure 12.
Start Safety Timer
Yes
Safety timer expired?
fault
Safety timer
No
Charging suspended
Enter suspended
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG < ITERM
mode
Fault indicated in
STAT registers
No
No
I2C Read/Write
performed?
Yes
Start 30 second
watchdog timer
Reset 30 second
watchdog timer
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG < ITERM
No
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Fault indicated in
STAT registers
No
Yes
Received SW watchdog
RESET?
No
30s timer expired?
Yes
Reset to default
values in I2C
register
Restart 27min
safety timer
Figure 12. The Watchdog Timer Flow Chart for bq2416xx
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
9.3.10 D+, D– Based Adapter Detection for the USB Input (D+, D–, bq24160/0A/3)
The bq24160/0A/3 contain a D+, D– based adapter detection circuit that is used to program the input current limit
for the USB input during DEFAULT mode. D+, D– detection is only performed in DEFAULT mode unless forced
by the D+, D–_EN bit in host mode. Writing to register 2 during detection stops the detection routine.
By default the USB input current limit is set to 100mA. When a voltage higher than UVLO is applied to the USB
input, the bq24160/0A/3 performs a charger source identification to determine if it is connected to an SDP (USB
port) or CDP/DCP (dedicated charger). The first step is D+, D- line connection detection as described in BC1.2.
Primary detection begins 10ms after the connection detection complete. The primary detection complies with the
method described in BC1.2. During primary detection, the D+, D- lines are tested to determine if the port is an
SDP or CDP/DCP. If a CDP/DCP is detected the input current limit is increased to 1.5A, if an SDP is detected
the current limit remains at 100mA, until changed via the I2C interface. These two steps require at least 90ms to
complete but if they have not completed within 500ms, the D+, D- detection routine selects 100mA for the
unknown input source. Secondary detection as described in BC1.2 is not performed.
Automatic detection is performed only if VD+ and VD– are less than 0.6V to avoid interfering with the USB
transceiver which may also perform D+, D– detection when the system is running normally. However, D+, D– can
be initiated at any time by the host by setting the D+, D– EN bit in the Control/Battery Voltage Register to 1. After
detection is complete the D+, D– EN bit is automatically reset to 0 and the detection circuitry is disconnected
from the D+, D– pins to avoid interference with USB data transfer.
When a command is written to change the input current limit in the I2C, this overrides the current limit selected by
D+/D– detection. D+, D– detection has no effect on the IN input.
9.3.11 USB Input Current Limit Selector Input (PSEL, bq24161/ 161B/ 168 only)
The bq24161, bq24161B, and bq24168 contain a PSEL input that is used to program the input current limit for
USB during DEFAULT mode. Drive PSEL high to indicate that a USB source is connected to the USB input and
program the 100mA (bq24161/8) or 500mA (bq24161B) current limit for USB. Drive PSEL low to indicate that an
AC Adapter is connected to the USB input. When PSEL is low, the IC starts up with a 1.5A current limit for USB.
PSEL has no effect on the IN input. Once an I2C write is done, the PSEL has no effect on the input current limit
until the watchdog timer expires.
9.3.12 Hardware Chip Disable Input (CD)
The bq2416xx contains a CD input that is used to disable the IC and place the bq2416xx into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
bq2416xx into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving
CD high during HOST mode resets the safety timer and places the bq2416xx into high impedance mode. The
CD pin has precedence over the I2C control.
9.3.13 LDO Output (DRV)
The bq2416xx contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.45V; ideal for protecting voltage sensitive USB circuits from
high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the IN or USB inputs of
the bq2416xx. The DRV is disabled under the following conditions:
1. VSUPPLY < UVLO
2. VSUPPLY < VSLP
3. Thermal Shutdown
20
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
9.3.14 External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the bq2416xx provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The bq24160, bq24160A, bq24161B, bq24163, and bq24168 enable the user
to easily implement the JEITA standard for charging temperature while the bq24161 only monitors the hot and
cold cutoff temperatures and leaves the JEITA control to the host. The JEITA specification is shown in.
1°C
0.5°C
Portion of spec not covered by TS
4.25 V
Implementation on bq24160
4.15 V
4.1 V
T1
(0°C)
T2
(10°C)
T3 T4
(45°C) (50°C)
T5
(60°C)
Figure 13. Charge Current During TS Conditions
To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC
<
0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC ≤ 60°C) and the
hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VWARM
>
VTS > VHOT, the battery regulation voltage is reduced by 140mV from the programmed regulation threshold.
When VCOLD > VTS > VCOOL, the charging current is reduced to half of the programmed charge current.
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 20. The resistor values are
calculated using the following equations:
é
ê
ë
ù
ú
1
1
VDRV ´ RCOLD ´ RHOT ´
-
VCOLD
V
HOT û
RLO =
é
ê
ë
ù
ú
û
é
ê
ë
ù
VDRV
VDRV
RHOT ´
-1 -RCOLD ´
-1
ú
VHOT
VCOLD
û
(1)
(2)
21
VDRV
-1
VCOLD
RHI =
1
+
RLO RCOLD
1
Where:
VCOLD = 0.60 × VDRV
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
VHOT = 0.30 × VDRV
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature.
For the bq24160, bq24161B, bq24163, and bq24168, the WARM and COOL thresholds are not independently
programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using the
following equations:
RLO ´ 0.564 ´ RHI
RCOOL =
RLO - RLO ´ 0.564 - RHI ´ 0.564
(3)
RLO ´ 0.383 ´ RHI
RWARM =
RLO - RLO ´ 0.383 - RHI ´0.383
(4)
VBAT(REG)
1 x Charge/
0.5 x Charge
VDRV
DISABLE -140 mV
TS COLD
+
TS COOL
TS WARM
+
+
VDRV
TS HOT
+
RHI
TS
PACK+
TEMP
bq2416x
RLO
PACK-
Figure 14. TS Circuit
9.3.15 Thermal Regulation and Protection
During the charging process, to prevent chip overheating, the bq2416xx monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq2416xx if the die temperature rises too high. At any state,
if TJ exceeds TSHTDWN, the bq2416xx suspends charging and disables the buck converter. During thermal
shutdown mode, the buck converter is turned off, all timers are suspended, and a single 128μs pulse is sent on
the STAT and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A
new charging cycle begins when TJ falls below TSHTDWN by approximately 10°C.
22
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
9.3.16 Input Voltage Protection in Charge Mode
9.3.16.1 Sleep Mode
The bq2416xx enters the low-power sleep mode if the voltage on VSUPPLY falls below the sleep-mode entry
threshold, VBAT+VSLP, and VSUPPLY is higher than the undervoltage lockout threshold, VUVLO. This feature
prevents draining the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the bq2416xx turns off
the PWM converter, turns the battery FET on and drives BGATE to GND, sends a single 128μs pulse on the
STAT and INT outputs and updates the STATx and FAULT_x bits in the status registers. Once VSUPPLY > VBAT
+
VSLP, the STATx and FAULT_x bits are cleared and the device initiates a new charge cycle.
9.3.16.2 Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage decreases. Once the supply drops to VIN_DPM (default 4.2V for both inputs),
the input current limit is reduced to prevent further supply droop. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature provides
IC compatibility with adapters with different current capabilities without a hardware change. Figure 15 shows the
VIN–DPM behavior to a current-limited source. In this figure the input source has a 750mA current limit and the
charging is set to 750mA. The SYS load is then increased to 1.2A.
Adapter Voltage Falls due
V
IN
5 V Adapter
rated for 750 mA
to Adapter Current Limit
Input Current Reduced by VINDPM function
to Prevent Adapter from Crashing
I
IN
V
SYS
750 mA Charging
750 mA Charging
I
BAT
Supplement Mode
1.2 A Load Step
I
SYS
Figure 15. bq24160 VIN-DPM
9.3.16.3 Bad Source Detection
When a source is connected to IN or USB, the bq2416xx runs a Bad Source Detection procedure to determine if
the source is strong enough to provide some current to charge the battery. A current sink is turned on (30mA for
USB input, 75mA for the IN input) for 32ms. If the source is valid after the 32ms (VBADSOURCE < VSUPPLY < VOVP),
the buck converter starts up and normal operation continues. If the supply voltage falls below VBAD_SOURCE during
the detection, the current sink shuts off for two seconds and then retries, a single 128μs pulse is sent on the
STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status
registers are updated. The detection circuits retry continuously until either a new source is connected to the other
input or a valid source is detected after the detection time. If during normal operation the source falls to
VBAD_SOURCE, the bq2416xx turns off the PWM converter, turns the battery FET on, sends a single 128μs pulse is
sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers, and the
battery/supply status registers are updated. Once a good source is detected, the STATx and FAULT_x bits are
cleared and the device returns to normal operation.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Feature Description (continued)
If two supplies are connected, the supply with precedence is checked first. If the supply detection fails once, the
device switches to the other supply for two seconds and then retries. This allows the priority supply to settle if the
connection was jittery or the supply ramp was too slow to pass detection. If the priority supply fails the detection
a second time, it is locked out and lower priority supply is used. Once the bad supply is locked out, it remains
locked out until the supply voltage falls below UVLO. This prevents continuously switching between a weak
supply and a good supply.
9.3.16.4 Input Overvoltage Protection
The built-in input overvoltage protection to protect the device and other downstream components against
damage from overvoltage on the input supply (Voltage from VUSB or VIN to PGND). During normal operation, if
VSUPPLY > VOVP, the bq2416xx turns off the PWM converter, turns the battery FET and BGATE on, sends a single
128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and
the battery/supply status registers are updated. Once the OVP fault is removed, the STATx and FAULT_x bits
are cleared and the device returns to normal operation.
To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.
This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If the
adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The OVP
circuit is active during normal operation, so if the system standby current plus the charge current is not enough to
pull down the source, operation is suspended.
9.3.16.5 Reverse Boost (Boost Back) Prevention Circuit
A buck converter has two operating modes, continuous conduction mode (CCM) and discontinuous conduction
mode (DCM). In DCM, the inductor current ramps down to zero during the switching cycle while in CCM the
inductor maintains a DC level of current. Transitioning from DCM to CCM during load transients, slows down the
converter's transient response for those load steps, which can result in the SYS rail drooping. To achieve the
fastest possible transient reponse for this charger, this charger's synchronous buck converter is forced to run in
CCM even at light loads when the buck converter would typically revert to DCM. The challenge that presents
itself when forcing CCM with a charger is that the output of the buck converter now has a power source. Thus, if
the battery voltage, V(BAT), is ever greater than VBATREG, the inductor current goes fully negative and pushes
current back to the input supply. This effect causes the input source voltage to rise if the input source cannot sink
current. The input over-voltage protection circuit protects the IC from damage however some input sources may
be damaged if the voltage rises. To prevent this, this charger has implemented a reverse boost prevention circuit.
When reverse current is sensed that is not a result of the supplement comparator tripping, this circuit disables
the internal battery FET and changes the feedback point to VSYSREG for 1 ms. After the 1-ms timeout, the
BATFET is turned on again and the battery is tested to see if it is higher than VBATREG (negative current). The
reverse current protection is only active when VBOVP > VBAT > VBATREG - VRCH. Having VBOVP > VBAT > VBATREG
-
VRCH results in an approximately 100-mV, 1000-Hz ripple on SYS as seen in . The most common trigger for
reverse boost prevention is a load transient on SYS that requires the charger to enter battery supplement mode.
When the IC enters reverse boost prevention, the IC stops charging or exits charge done which may result in
the battery never reaching full charge. With termination enabled and ITERM > 150mA or with a high line
impedance to the battery, the likelihood of activating the reverse boost prevention circuit is small and even when
activated, the charger typically exits reverse boost prevention as the battery relaxes. With termination enabled
and ITERM < 150mA or with a low impedance battery, the likelihood of activating the reverse boost prevention
circuit by a load transient or even the inductor ripple current is higher. In either case, the IC resumes charging
until VBAT drops below VBATREG - VRCH, resulting in the battery always charging to at least 0.97 of full
charge. If full charge is required with ITERM < 150mA then the recommended solution to ensure full charge is
as follows
1.
SET the charger’s enable no battery operation bit ( EN_NOBATOP) = 1 to disable the reverse boost
prevention circuits. Brief, low-amplitude voltage pulses on IN may be observed as the IC enters boost back
to resolve instances where VBAT is greater than the VBATREG, for example when exiting supplement
mode. The I2C communication software must ensure that VBATREG is never written below VBAT. The IC
automatically rewrites the VBATREG register to the default value of 3.6V when existing HOST mode. For
JEITA enabled ICs, the IC automatically lowers the voltage reference to 0.98 of the VBATREG value. The
software must account for these instances as well.
2.
Disable the charger’s termination function and TS functions and use a gas gauge to control
termination and TS through its independent voltage and current measurements.
24
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Feature Description (continued)
Figure 16. V(SYS) when Reverse Boost Prevention Circuit is Active
9.3.17 Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq2416xx. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
Table 1. STAT Pin Summary
Charge State
Charge in progress and EN_STAT=1
STAT and INT behavior
Low
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault,
watchdog expiration, sleep mode, battery temperature fault (TS), battery fault
(OVP or absent), thermal shutdown
128-µs pulse, then High Impedance
9.3.18 Good Battery Monitor
The bq2416xx contains a good battery monitor circuit that places the bq2416xx into high-z mode if the battery
voltage is above the BATGD threshold while in DEFAULT mode. This function is used to enable compliance to
the battery charging standard that prevents charging from an un-enumerated USB host while the battery is above
the good battery threshold. If the bq2416xx is in HOST mode, it is assumed that USB host has been enumerated
and the good battery circuit has no effect on charging.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
9.4 Device Functional Modes
The state machine of the bq2416x automatically changes primary states (Off, sleep, HiZ, charge disabled,
charging, charge done, battery OVP, fault) based on data in the I2C registers, IN and USB pin voltages, BAT pin
voltage and current flow, TS pin voltage, CD pin voltage and status of the safety timer. The BAT and TS pin
voltages as well as current flow into the IN and USB pins, out of SYS pin and into/out of the BAT pin determine
the charging sub-states, including conditioning, constant current (CC), CC with reduced charge current, constant
voltage (CV) with reduced charge current.
9.5 Programming
9.5.1 Serial Interface Description
The bq2416xx uses an I2C-compatible interface to program charge parameters. I2C is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All I2C-compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A
master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible
for generating the SCL signal and device addresses. The master also generates specific conditions that indicate
the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of
the master device.
The bq2416xx device works as a slave and supports the following data transfer modes, as defined in the I2C Bus
Specification: standard mode (100kbps) and fast mode (400kbps). The interface adds flexibility to the battery
charging solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. Register contents remain intact as long as battery voltage remains above 2.5V
(typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is not
connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V
with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq2416xx devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
9.5.1.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 17. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 17. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 18). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 19) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
26
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Programming (continued)
DATA
CLK
Chang
of Data
Allowed
Data Line
Stable
Data Valid
Figure 18. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 20). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 19. Acknowledge on the I2C Bus
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
Programming (continued)
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgment
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
Sr
or
P
ACK
ACK
Clock Line Held Low While
Interrupts are Serviced
Figure 20. Bus Protocol
28
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
9.6 Register Maps
9.6.1 Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write FUNCTION
B7 (MSB)
TMR_RST
Read/Write Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
(bq24160/1/3 only)
B6
B5
B4
STAT_2
STAT_1
STAT_0
Read only 000- No Valid Source Detected
001- IN Ready (shows preferred source when both connected)
010- USB Ready (shows preferred source when both connected)
Read only
Read only
011- Charging from IN
100- Charging from USB
101- Charge Done
110- NA
111- Fault
B3
SUPPLY_SEL
Read/Write 0-IN has precedence when both supplies are connected
1-USB has precedence when both supplies are connected (default 0)
B2
B1
FAULT_2
FAULT_1
FAULT_0
Read only 000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
Read only
B0 (LSB)
Read only
011- Watchdog Timer Expired (bq24160/1/1B/3 only)
100- Safety Timer Expired (bq24160/1/1B/3 only)
101- IN Supply Fault
110- USB Supply Fault
111- Battery Fault
SUPPLY_SEL Bit (Supply Precedence Selector)
The SUPPLY_SEL bit selects which supply has precedence when both supplies are present. In cases
where both supplies are connected, they must remain isolated from each other which means only one
is allowed to charge the battery. Write a “1” to SUPPLY_SEL to select the USB input to have
precedence. Write a “0” to select the IN input.Note the following behavior when switching the
SUPPLY_SEL bit with both supplies attached:
•
•
•
The bq2416xx returns to high impedance mode
The input supply is switched
The bq2416xx begins a full startup cycle starting with bad adapter detection then proceeding to soft-start
Similarly, if charging from the non-preferred supply when the preferred supply is attached, the
bq2416xx follows the same procedure.
STAT_x and FAULT_x Bits
The STAT_x show the current status of the device and are updated dynamically as the IC changes
state. The FAULT_x bits show faults that have occurred and are only cleared by reading the bits,
assuming the fault no longer exists. If multiple faults occur, the first one is the one that is shown.
9.6.2 Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
B7 (MSB)
B6
NAME
Read/Write FUNCTION
INSTAT1
INSTAT0
Read Only 00-Normal
01-Supply OVP
Read Only
10-Weak Source Connected (No Charging)
11- VIN<VUVLO
B5
B4
USBSTAT1
USBSTAT0
Read Only 00-Normal
01-Supply OVP
Read Only
01-Weak Source Connected (No Charging)
11- VUSB<VUVLO
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
BIT
NAME
Read/Write FUNCTION
B3
OTG_LOCK
Read/Write 0 – No OTG supply present. Use USB input as normal.
1 – OTG supply present. Lockout USB input for charging.
(default 0)
B2
B1
BATSTAT1
BATSTAT0
Read Only 00-Battery Present and Normal
01-Battery OVP
Read Only
10-Battery Not Present
11- NA
B0 (LSB)
EN_NOBATOP
Read/ Write 0-Normal Operation
1-Enables No Battery Operation when termination is disabled (default 0)
OTG_LOCK Bit (USB Lockout)
The OTG_LOCK bit is used to prevent any charging from USB input regardless of the SUPPLY_SEL
bit and IN supply status. For systems using OTG supplies, it is not desirable to charge from an OTG
source. Doing so would mean draining the battery by allowing it to effectively charge itself. Write a “1”
to OTG_LOCK to lock out the USB input. Write a “0” to OTG_LOCK to return to normal operation.
During OTG lock, the USB input is ignored and DRV does not come up. The watchdog timer must be
reset while in USB_LOCK to maintain the USB lockout state. This prevents the USB input from being
permanently locked out for cases where the host loses I2C communication with OTG_LOCK set (i.e.,
discharged battery from OTG operation). See the Safety Timer and Watchdog Timer section for more
details.
EN_NOBATOP (No Battery Operation)
The EN_NOBATOP bit enables no battery operation. When using the bq2416x without a battery
attached, it is recommended to first disable charging, then disable charge termination and finally set
this bit to 1. Setting this bit to 1 also disables the reverse boost prevention circuit and the BATOVP
circuit. With a battery attached, setting this bit to 1 may be helpful to ensure full battery charging as
explained in the reverse battery prevention circuit section. In the event of battery overvoltage (e.g.,
recovery from large SYS load transient requiring supplement), the BATOVP protection circuit turns off
the buck converter to allow the battery to discharge through SYS.
9.6.3 Control Register (READ/WRITE)
Memory location: 02, Reset state: 1000 1100
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
RESET
Write only
Write: 1 – Reset all registers to default values
0 – No effect
Read: always get “1”
B6
B5
B4
IUSB_LIMIT_2
IUSB_LIMIT_1
IUSB_LIMIT _0
Read/Write
Read/Write
Read/Write
000 – USB2.0 host with 100mA current limit
001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB host/charger with 800mA current limit
100 – USB3.0 host with 900mA current limit
101 – USB host/charger with 1500mA current limit
110–111 – NA (default 000(1)
)
B3
EN_STAT
Read/Write
1 – Enable STAT output to show charge status,
0-Disable STAT output for charge status. Fault interrupts are still show even when
EN_STAT = 0. (default 1)
B2
B1
TE
CE
Read/Write
Read/Write
Read/Write
1 – Enable charge current termination,
0-Disable charge current termination (default 1)
1 – Charging is disabled
0 – Charging enabled (default 0 bq24160/1/1B/3/8)
B0 (LSB)
HZ_MODE
1 – High impedance mode
0 – Not high impedance mode (default 0)
(1) When in DEFAULT mode, the D+/D– (bq24160) or PSEL (bq24161/8) inputs determine the input current limit for the USB input.
30
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
RESET Bit
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write “1” to
RESET bit to reset all the registers to default values and place the bq2416xx into DEFAULT mode and
turn off the watchdog timer. The RESET bit is automatically cleared to zero once the bq2416xx enters
DEFAULT mode.
CE Bit (Charge Enable)
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic
level (0) on this bit enables the charge and a high logic level (1) disables the charge. When charge is
disabled, the SYS output regulates to VSYS(REG) and battery is disconnected from the SYS.
Supplement mode is still available if the system load demands cannot be met by the supply.
HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance
mode. A low logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low
quiescent current state called high impedance mode. When in high impedance mode, the converter is
off and the battery FET and BGATE are on. The load on SYS is supplied by the battery.
9.6.4 Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
BIT
B7 (MSB)
B6
NAME
VBREG5
VBREG4
VBREG3
VBREG2
VBREG1
VBREG0
IINLIMIT
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Battery Regulation Voltage: 640 mV (default 0)
Battery Regulation Voltage: 320 mV (default 0)
Battery Regulation Voltage: 160 mV (default 0)
Battery Regulation Voltage: 80 mV (default 1)
Battery Regulation Voltage: 40 mV (default 0)
Battery Regulation Voltage: 20 mV (default 1)
B5
B4
B3
B2
B1
Input Limit for IN input-
0 – 1.5A
1 – 2.5A (default 0)
B0 (LSB)
D+/D–_EN
Read/Write
0 – Normal state, D+/D- Detection done
1 – Force D+/D– Detection. Returns to “0” after detection is done. (default 0)
•
•
Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
Before writing to increase VBATREG register following a BATOVP event (e.g., IN or USB voltage is applied,
IC remains in DEFAULT mode and then VBAT>3.6V is attached), toggle the HiZ bit or CD pin to clear the
BATOVP fault.
9.6.5 Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
BIT
B7 (MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
Read/Write
Read only
Read only
Read only
Read only
Read only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
For I2C Address 6Bh:
00: bq2416xx
B5
B4
B3
PN0
01–11: Future product spins
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
BIT
B2
NAME
Read/Write
Read only
Read only
Read only
FUNCTION
Revision2
Revision1
Revision0
000: Revision 1.0
001: Revision 1.1
010: Revision 2.0
011: Revision 2.1
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
B1
B0 (LSB)
9.6.6 Battery Termination/Fast Charge Current Register (READ/WRITE)
Memory location: 05, Reset state: 0011 0010
BIT
B7 (MSB)
B6
NAME
ICHRG4
ICHRG3
ICHRG2
ICHRG1
ICHRG0
ITERM2
ITERM1
ITERM0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Charge current: 1200mA – (default 0)
Charge current: 600mA – (default 0)
Charge current: 300mA – (default 1)
Charge current: 150mA – (default 1)
Charge current: 75 mA (default 0)
B5
B4
B3
B2
Termination current sense voltage: 200mA (default 0)
Termination current sense voltage: 100mA (default 1)
Termination current sense voltage: 50mA (default 0)
B1
B0 (LSB)
•
•
Charge current sense offset is 550mA and default charge current is 1000mA.
Termination threshold offset is 50mA and default termination current is 150mA
9.6.7 VIN-DPM Voltage/ DPPM Status Register
Memory location: 06, Reset state: xx00 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
MINSYS_STATUS
Read Only
1 – Minimum System Voltage mode is active (VBAT<VMINSYS
)
0 – Minimum System Voltage mode is not active
B6
DPM_STATUS
Read Only
1 – VIN-DPM mode is active
0 – VIN-DPM mode is not active
B5
B4
VINDPM2(USB)
VINDPM1(USB)
VINDPM0(USB)
VINDPM2(IN)
VINDPM1(IN)
VINDPM0(IN)
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
USB input VIN-DPM voltage: 320mV (default 0)
USB input VIN-DPM voltage: 160mV (default 0)
USB input VIN-DPM voltage: 80mV (default 0)
IN input VIN-DPM voltage: 320mV (default 0)
IN input VIN-DPM voltage: 160mV (default 0)
IN input VIN-DPM voltage: 80mV (default 0)
B3
B2
B1
B0(LSB)
•
VIN-DPM voltage offset is 4.20V and default VIN-DPM threshold is 4.20V.
9.6.8 Safety Timer/ NTC Monitor Register (READ/WRITE)
Memory location: 07, Reset state: 1001 1xxx
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
2XTMR_EN
Read/Write
1 – Timer slowed by 2x when in thermal regulation, input current limit, VIN_DPM or
DPPM
0 – Timer not slowed at any time (default 0) (bq24160/1 only)
B6
B5
TMR_1
TMR_2
Read/Write
Read/Write
Safety Timer Time Limit –
00 – 27 minute fast charge
01 – 6 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers (default 00) (bq24160/1 only)
B4
NA
Read/Write
NA
32
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
BIT
NAME
Read/Write
FUNCTION
B3
TS_EN
Read/Write
0 – TS function disabled
1 – TS function enabled (default 1)
B2
B1
TS_FAULT1
TS_FAULT0
Read only
Read only
TS Fault Mode:
00 – Normal, No TS fault
01 – TS temp < TCOLD or TS temp > THOT(Charging suspended)
10 – TCOOL > TS temp > TCOLD (Charge current reduced by half, bq24160 only)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 140mV, bq24160 only)
B0 (LSB)
LOW_CHG
Read/ Write
0 – Charge current as programmed in Register 0x05
1 – Charge current is half programmed value in Register 0x05
(default 0)
2xTMR_EN Bit (2x Timer Enable)
The 2xTMR_EN bit is used to slow down the timer when charge current is reduced by the system load.
When 2xTMR_EN is a "1", the safety timer is slowed to half speed effectively doubling the timer time.
The conditions that activate the 2x timer are: Input Current Limit, VINDPM, Thermal Regulation,
LOW_CHG, BATSHRT and TS Cool. When 2xTMR_EN is a "0", the timer operates at normal speed in
all conditions.
LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is
used by systems where battery NTC is monitored by the host and requires a reduced charge current
setting or by systems that need a “preconditioning” current for low battery voltages. Write a “1” to this
bit to charge at half of the programmed charge current (bq24160/1/3/8). Write a “0” to this bit to charge
at the programmed charge current.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
10 Application and Implementation
10.1 Application Information
www.ti.com
A typical application circuit using the bq24160 with a smartphone's GSM power amplifier (PA) powered directly
from the battery is shown in Figure 21. A typical application circuit using the bq24161 with a smartphone's GSM
PA powered from the SYS rail, to allow for calls even with a deeply discharged battery, is shown in Figure 22.
Each circuit shows the minimum capacitance requirements for each pin and typical recommended inductance
value of 1.5 µH. The TS resistor divider for configuring the TS function for the battery's specific thermistor can be
computed from equations Equation 1 and Equation 2. The resistor on STAT is sized per the LED current
requirements. All other configuration settings for VINDPM, input current limit, charge current and charge voltage
are made in EEPROM registers using I2C commands. Options for sizing the inductor outside the 1.5 µH
recommended value and additional SYS pin capacitance are explained in the next section.
10.2 Typical Application
ADAPTER
1.5 mH
IN
SW
PMIDI
System
Load
0.01 mF
1 mF
4.7 mF
BOOT
SYS
USB
VBUS
D+
D-
10 mF
PMIDU
PGND
GND
1 mF
4.7 mF
BGATE
DRV
BAT
TS
VDRV
1 mF
1 mF
GSM
PA
PACK+
STAT
TEMP
VSYS
(1.8V)
D+
D-
PACK-
HOST
bq24160
GPIO1
INT
SDA
SCL
SDA
SCL
Figure 21. bq24160, Shown with no External Discharge FET, PA Connected to Battery
34
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Typical Application (continued)
ADAPTER
1.5 mH
IN
SW
PMIDI
System
Load
0.01 mF
1 mF
4.7 mF
BOOT
SYS
USB
VBUS
D+
10 mF
PMIDU
D-
PGND
GND
1 mF
4.7 mF
BGATE
GSM
PA
DRV
BAT
TS
VDRV
1 mF
1 mF
PACK+
STAT
PSEL
TEMP
VSYS
(1.8V)
USB PHY
PACK-
HOST
bq24161
GPIO1
INT
SDA
SCL
SDA
SCL
Figure 22. bq24161, Shown with External Discharge FET, PA Connected to System for GSM Call Support
with a Deeply Discharged or No Battery
10.2.1 Design Requirements
Min
4.2
4.2
3.3
Typ
Max
10
6
Unit
V
Supply voltage, VIN
USB voltage, VUSB
System voltage, VSYS
Input voltage from ac adapter
Input voltage from USB or equivalent supply
Voltage output at SYS terminal (depends on VBAT voltage and
V
VBATRE
G+4.17%
V
status of VINDPM
)
Battery voltage, VBAT
Supply current, IIN(MAX)
Supply current, IUSB(MAX)
Voltage output at VBAT terminal (registers set via I2C
communication)
2
1.5
4.2
0.5
4.44
V
A
Maximum input current from ac adapter input (registers set via
I2C communication)
2.5
Maximum input current from USB input (registers set via I2C
communication)
0.1
1.5
A
Fast charge current,
ICHRG(MAX)
Battery charge current (registers set via I2C communication)
0.550
-40
2.5
A
Operating junction temperature range, TJ
125
°C
10.2.2 Detailed Design Procedure
10.2.2.1 Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq2416xx is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 to calculate the peak current.
%
æ
ö
RIPPPLE
IPEAK = ILOAD(MAX)
´
1+
ç
÷
2
è
ø
(5)
35
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to
the high currents possible with the bq2416xx, a thermal analysis must also be done for the inductor. Many
inductors have a 40°C temperature-rise rating. The DC component of the current can cause a 40°C temperature
rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used
adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with
peaks at 2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´
I
(
- ILOAD = 1.5A + 0.2 × 2.5A -1 .5A = 1.7A
(
)
)
PEAK
(6)
The bq2416xx provides internal loop compensation. Using this scheme, the bq2416xx is stable with 10µF to
200µF of local capacitance on the SYS output. The capacitance on the SYS rail can be higher if distributed
amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10µF
and 47µF is recommended for local bypass to SYS. A 47µF bypass capacitor is recommended for optimal
transient response.
10.2.3 Application Curves
USB500
1500mA ILIM
925mA Charge Setting
1300mA Charge Setting
Figure 23. USB Plug-In with Battery Connected
Figure 24. IN Plug-in with Battery Connected
Termination Enabled
Figure 25. Adapter Detection USB
Figure 26. Battery Insert During Battery Detection
36
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
Termination Enabled
MINSYS Operation
USB1500
200mA-1400mA Load Step on SYS
Figure 27. Battery Pull During Charging
Figure 28. Load Transient into DPPM
VUSB
5 V/div
5 V/div
VSYS
VBAT
VSTAT/INT
1 V/div
5 V/div
VSW
IUSB
500 mA/div
1 A/div
IBAT
IBAT
500 mA/div
10 ms/div
4 ms/div
MINSYS Operation
USB500
200mA - 1400mA Load Step on SYS
Figure 30. OVP Fault USB Input
Figure 29. Load Transient into Supplement Mode
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 7 V
VIN = 9 V
VUSB = 5 V
VUSB = 6 V
0.1
1
3
0.1
1
2
System Current (A)
System Current (A)
G001
G002
Charge Disabled
SYS loaded
Charge Disabled
SYS loaded
VBATREG = 3.6V
IN2500 ILIM
VBATREG = 3.6V
USB1500 ILIM
Figure 31. IN Efficiency
Figure 32. USB Efficiency
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
11 Power Supply Recommendations
11.1 Requirements for SYS Output
In order to provide an output voltage on SYS, the bq2416xx requires either a power supply between 4.2 V and
6.0 V for USB input on all versions, 4.2 V and 6.0 V for IN input on bq24168 and 4.2 V and 10.0 V on the
remaining versions with at least 100 mA current rating connected to IN or USB OR a single-cell LiIon battery with
voltage > VBATUVLO connected to BAT. The source current rating needs to be at least 2.5 A in order for the
charger's buck converter to provide maximum output power to SYS.
11.2 Requirements for Charging
In order for charging to occur, the source voltage as measured at the IC's USB or IN pins (factoring in cable/trace
losses from the source) must be greater than the VINDPM threshold (but less than the maximum values above)
and the source's current rating must be higher than the buck converter needs to provide the load on SYS. For
charging at a desired charge current of ICHRG, VUSBorINx IUSBorIN x η > VSYS x (ISYS+ ICHRG) where η is the efficiency
estimate from Figure 1 or Figure 2 and VSYS = VBAT when VBAT charges above VMINSYS. The charger limits IUSBorIN
to that input's current limit setting. With ISYS = 0 A, the charger consumes maximum power at the end of CC
mode, when the voltage at the BAT pin is near VBATREG but ICHRG has not started to taper off toward ITERM
.
38
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
12 Layout
12.1 Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 33 provides a sample layout for the high current
paths of the bq2416xx. A list of layout guidelines follows.
•
•
•
To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq2416xx
Minimize the amount of inductance between BAT and the postive connection of the battery terminal. If a large
parasitic board inductance on BAT is expected, increase the bypass capacitance on BAT.
Place 4.7µF input capacitor as close to PMID_ pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
•
The traces from the input connector to the inputs of the bq2416xx should be as wide as possible to minimize
the impedance in the line. Although the VINDPM feature will allow operation from input sources having high
resistances(impedances), the bq2416xx input pins (IN and USB) have been optimized to connect to input
sources with no more than 350mohm of input resistance, including cables and PCB traces
•
•
•
The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
Place all decoupling capacitors close to their respective IC pins and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high-current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
•
•
The high-current charge paths into IN, USB, BAT, SYS and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
www.ti.com
12.2 Layout Example
WCSP
VQFN
Figure 33. Recommended bq2416xx PCB Layout
40
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
www.ti.com
SLUSAO0G –NOVEMBER 2011–REVISED DECEMBER 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
bq24160
bq24160A
bq24161
bq24161B
bq24163
bq24168
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
41
Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RGE
RGE
RGE
RGE
YFF
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
BQ24160ARGER
BQ24160ARGET
BQ24160RGER
BQ24160RGET
BQ24160YFFR
BQ24160YFFT
BQ24161BRGER
BQ24161BRGET
BQ24161BYFFR
BQ24161RGER
BQ24161RGET
BQ24161YFFR
BQ24161YFFT
BQ24163RGER
BQ24163RGET
BQ24163YFFR
ACTIVE
VQFN
VQFN
24
24
24
24
49
49
24
24
49
24
24
49
49
24
24
49
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
BQ
24160A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SNAGCU
BQ
24160A
VQFN
3000
250
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ
24160
VQFN
Green (RoHS
& no Sb/Br)
BQ
24160
DSBGA
DSBGA
VQFN
3000
250
Green (RoHS
& no Sb/Br)
BQ24160
YFF
Green (RoHS
& no Sb/Br)
BQ24160
RGE
RGE
YFF
3000
250
Green (RoHS
& no Sb/Br)
BQ
24161B
VQFN
Green (RoHS
& no Sb/Br)
BQ
24161B
DSBGA
VQFN
3000
3000
250
Green (RoHS
& no Sb/Br)
BQ24161B
RGE
RGE
YFF
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ
24161
VQFN
Green (RoHS
& no Sb/Br)
BQ
24161
DSBGA
DSBGA
VQFN
3000
250
Green (RoHS
& no Sb/Br)
BQ24161
YFF
Green (RoHS
& no Sb/Br)
BQ24161
RGE
RGE
YFF
3000
250
Green (RoHS
& no Sb/Br)
BQ
24163
VQFN
Green (RoHS
& no Sb/Br)
BQ
24163
DSBGA
3000
Green (RoHS
& no Sb/Br)
BQ24163
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ24163YFFT
BQ24168RGER
BQ24168RGET
BQ24168YFFR
BQ24168YFFT
ACTIVE
DSBGA
VQFN
YFF
49
24
24
49
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ24163
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RGE
RGE
YFF
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SNAGCU
SNAGCU
BQ
24168
VQFN
Green (RoHS
& no Sb/Br)
BQ
24168
DSBGA
DSBGA
3000
250
Green (RoHS
& no Sb/Br)
BQ24168
YFF
Green (RoHS
& no Sb/Br)
BQ24168
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
21-Aug-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24160ARGER
BQ24160ARGET
BQ24160RGER
BQ24160RGET
BQ24160YFFR
BQ24160YFFT
BQ24161BRGER
BQ24161BRGET
BQ24161BYFFR
BQ24161RGER
BQ24161RGET
BQ24161YFFR
BQ24161YFFT
BQ24163RGER
BQ24163RGET
BQ24163YFFR
BQ24163YFFT
BQ24168RGER
VQFN
VQFN
RGE
RGE
RGE
RGE
YFF
YFF
RGE
RGE
YFF
RGE
RGE
YFF
YFF
RGE
RGE
YFF
YFF
RGE
24
24
24
24
49
49
24
24
49
24
24
49
49
24
24
49
49
24
3000
250
330.0
180.0
330.0
180.0
180.0
180.0
330.0
180.0
180.0
330.0
180.0
180.0
180.0
330.0
180.0
180.0
180.0
330.0
12.4
12.4
12.4
12.4
8.4
4.25
4.25
4.25
4.25
2.93
2.93
4.25
4.25
2.93
4.25
4.25
2.93
2.93
4.25
4.25
2.93
2.93
4.25
4.25
4.25
4.25
4.25
2.93
2.93
4.25
4.25
2.93
4.25
4.25
2.93
2.93
4.25
4.25
2.93
2.93
4.25
1.15
1.15
1.15
1.15
0.81
0.81
1.15
1.15
0.81
1.15
1.15
0.81
0.81
1.15
1.15
0.81
0.81
1.15
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
4.0
4.0
8.0
12.0
12.0
12.0
12.0
8.0
Q2
Q2
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q1
Q2
VQFN
3000
250
VQFN
DSBGA
DSBGA
VQFN
3000
250
8.4
8.0
3000
250
12.4
12.4
8.4
12.0
12.0
8.0
VQFN
DSBGA
VQFN
3000
3000
250
12.4
12.4
8.4
12.0
12.0
8.0
VQFN
DSBGA
DSBGA
VQFN
3000
250
8.4
8.0
3000
250
12.4
12.4
8.4
12.0
12.0
8.0
VQFN
DSBGA
DSBGA
VQFN
3000
250
8.4
8.0
3000
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24168RGET
BQ24168YFFR
BQ24168YFFT
VQFN
DSBGA
DSBGA
RGE
YFF
YFF
24
49
49
250
3000
250
180.0
180.0
180.0
12.4
8.4
4.25
2.93
2.93
4.25
2.93
2.93
1.15
0.81
0.81
8.0
4.0
4.0
12.0
8.0
Q2
Q1
Q1
8.4
8.0
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24160ARGER
BQ24160ARGET
BQ24160RGER
BQ24160RGET
BQ24160YFFR
BQ24160YFFT
BQ24161BRGER
BQ24161BRGET
BQ24161BYFFR
BQ24161RGER
BQ24161RGET
BQ24161YFFR
BQ24161YFFT
BQ24163RGER
VQFN
VQFN
RGE
RGE
RGE
RGE
YFF
YFF
RGE
RGE
YFF
RGE
RGE
YFF
YFF
RGE
24
24
24
24
49
49
24
24
49
24
24
49
49
24
3000
250
367.0
210.0
367.0
210.0
182.0
182.0
367.0
210.0
182.0
367.0
210.0
182.0
182.0
367.0
367.0
185.0
367.0
185.0
182.0
182.0
367.0
185.0
182.0
367.0
185.0
182.0
182.0
367.0
35.0
35.0
35.0
35.0
20.0
20.0
35.0
35.0
20.0
35.0
35.0
20.0
20.0
35.0
VQFN
3000
250
VQFN
DSBGA
DSBGA
VQFN
3000
250
3000
250
VQFN
DSBGA
VQFN
3000
3000
250
VQFN
DSBGA
DSBGA
VQFN
3000
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Aug-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24163RGET
BQ24163YFFR
BQ24163YFFT
BQ24168RGER
BQ24168RGET
BQ24168YFFR
BQ24168YFFT
VQFN
DSBGA
DSBGA
VQFN
RGE
YFF
YFF
RGE
RGE
YFF
YFF
24
49
49
24
24
49
49
250
3000
250
210.0
182.0
182.0
367.0
210.0
182.0
182.0
185.0
182.0
182.0
367.0
185.0
182.0
182.0
35.0
20.0
20.0
35.0
35.0
20.0
20.0
3000
250
VQFN
DSBGA
DSBGA
3000
250
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
D: Max = 2.771 mm, Min = 2.71 mm
E: Max = 2.771 mm, Min = 2.71 mm
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
BQ24161B_15
bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power Path Management and I2C Interface
TI
©2020 ICPDF网 联系我们和版权申明