BQ24250C [TI]
SYSOFF 模式下具有 1uA 静态电流、I2C 控制型单节 2A 降压型电池充电器;
| 型号： | BQ24250C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYSOFF 模式下具有 1uA 静态电流、I2C 控制型单节 2A 降压型电池充电器 电池 |
| 文件： | 总48页 (文件大小：2415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq24250C
SLUSBY7 –JULY 2014
bq24250C 2A Single Input I2C, Standalone Switch-Mode Li-Ion Battery Charger with
Power-Path Management
1 Features
•
•
AnyBoot Robust Battery Detection Algorithm
Charge Time Optimizer for improved charge times
at any given charge current
1
•
•
•
High-efficiency Switch-mode Charger with
Separate Power Path
•
2.4 x 2.0 mm 30-ball WCSP Packages
Start up System from Deeply Discharged or
Missing Battery
2 Applications
USB Charging Compliant
•
•
•
•
Smart Phones
–
Selectable Input Current Limit of 100 mA,
500 mA, 900 mA, 1.5 A, and 2 A
MP3 Players
Portable Media Players
Handheld Devices
•
In Host Mode (After I2C Communication Starts
and Before Watchdog Timer Times Out)
–
Programmable Battery Charge Voltage,
VBATREG
3 Description
The bq24250C is a highly integrated single-cell Li-Ion
battery charger and system power-path management
–
–
–
Programmable Charge Current (ICHG
Programmable Input Current Limit (ILIM
Programmable Input Voltage Based Dynamic
Power Management threshold, (VIN_DPM
Programmable Input Overvoltage Protection
Threshold (VOVP
Programmable Safety Timer
)
)
device
targeted
for
space-limited,
portable
applications with high capacity batteries. The single
cell charger has a single input that operates from
either a USB port or AC wall adapter for a versatile
solution.
)
–
–
)
Device Information
•
Resistor Programmable Defaults for:
PART NUMBER
PACKAGE
BODY SIZE
–
–
–
ICHG up to 2 A with Current Monitoring Output
(ISET)
bq24250C
DSBGA (30)
2.427 mm × 2.027 mm
ILIM up to 2 A with Current Monitoring Output
(ILIM)
Typical Application
CPMID
1 µF
VIN_DPM (VDPM)
LO
1.0 µH
PMID
IN
SW
•
•
•
Watchdog Timer Disable Bit
Integrated 4.9 V, 50 mA LDO
Complete System Level Protection
VIN
CIN
System Load
R1
CBOOT
33 nF
2.2 µF
3 MHz
PWM
VDPM
LDO
R2
BOOT
PGND
SYS
1 µF
–
Input UVLO, Input Over-voltage Protection
(OVP), Battery OVP, Sleep Mode, VIN_DPM
22 μF
STAT
–
–
–
–
–
–
Input Current Limit
VGPIO
BAT
1 μF
Charge Current Limit
Thermal Regulation
Thermal Shutdown
LDO
R3
SCL
SDA
SCL
SDA
TEMP
PACK+
TS
+
RNTC
R4
GPIO1
INT
/CE
EN1
EN2
Host
PACK-
GPIO2
GPIO3
GPIO4
Voltage Based NTC Monitoring Input
Safety Timer
ILIM
ISET
•
•
•
20 V Maximum Input Voltage Rating
10.5 V Maximum Operating Input Voltage
Low RDS(on) Integrated Power FETs for up to 2 A
Charging Rate
•
•
Open Drain Status Outputs
Synchronous Fixed-frequency PWM Controller
Operating at 3MHz for Small Inductor Support
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24250C
SLUSBY7 –JULY 2014
www.ti.com
Table of Contents
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 18
8.5 Register Maps......................................................... 28
Application and Implementation ........................ 34
9.1 Application Information............................................ 34
9.2 Typical Application ................................................. 34
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (Continued)........................................ 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 Handling Ratings....................................................... 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements.............................................. 10
7.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
9
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Board Layout......................................................... 38
11.3 Package Summary................................................ 39
12 Device and Documentation Support ................. 40
12.1 Trademarks........................................................... 40
12.2 Electrostatic Discharge Caution............................ 40
12.3 Glossary................................................................ 40
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
DATE
REVISION
NOTES
July 2014
*
Initial Release
2
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5 Description (Continued)
The power path management feature allows the bq24250C to power the system from a high efficiency DC/DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The power-
path management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter.
The battery is charged in four phases: trickle charge, pre-charge, constant current and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Additionally, a voltage-based battery pack thermistor monitoring
input (TS) is included that monitors battery temperature for safe charging.
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6 Pin Configuration and Functions
YFF Package
(30-Ball 2.4 mm × 2 mm DSBGA)
Top View
1
2
3
4
5
BAT
SYS
PGND
SW
IN
A
B
C
D
E
F
BAT
BAT
ISET
INT
SYS
SYS
EN2
SCL
SDA
PGND
PGND
EN1
SW
SW
IN
IN
/CE
PMID
BOOT
ILIM
STAT
VDPM
LDO
TS
PGND
bq24250C
Pin Descriptions
PIN
NAME
bq24250C
YFF
bq24250C
I/O
DESCRIPTION
RGE
Analog Ground for QFN only. Connect to the thermal pad and the ground plane
of the circuit.
AGND
–
4
Battery Connection. Connect to the positive pin of the battery. Additionally,
bypass BAT with a >1μF capacitor.
BAT
BOOT
CE
A1, B1, C1
11–12
21
I/O
High Side MOSFET Gate Driver Supply. Connect a 0.033μF ceramic capacitor
(voltage rating > 15V) from BOOT to SW to supply the gate drive for the high
side MOSFETs.
E5
D4
I
I
Charge Enable Active-Low Input. Connect CE to a high logic level to place the
battery charger in standby mode.
1
Charge Status Open Drain Output. CHG is pulled low when a charge cycle
starts and remains low while charging. CHG is high impedance when the
charging terminates and when no supply exists. CHG does not indicate
recharge cycles.
CHG
–
–
O
EN1
EN2
D3
D2
2
3
I
I
Input Current Limit Configuration Inputs. Use EN1, and EN2 to control the
maximum input current and enable USB compliance. See Table 1 for
programming details.
Input Current Limit Programming Input. Connect a resistor from ILIM to GND to
program the input current limit for IN. The current limit is programmable from
0.5A to 2A. ILIM has no effect on the USB input. If an external resistor is not
desired, short to GND for a 2A default setting.
ILIM
IN
F5
22
19
I
I
Input power supply. IN is connected to the external DC supply (AC adapter or
USB port). Bypass IN to PGND with >2μF ceramic capacitor
A5,B5,C5
Status Output. INT is an open-drain output that signals charging status and
fault interrupts. INT pulls low during charging. INT is high impedance when
charging is complete or the charger is disabled. When a fault occurs, a 256μs
pulse is sent out as an interrupt for the host. INT will indicate recharge cycles.
Connect INT to a logic rail through a 10kΩ resistor to communicate with the
host processor.
INT
E1
8
O
4
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Pin Descriptions (continued)
PIN
NAME
bq24250C
YFF
bq24250C
RGE
I/O
DESCRIPTION
Charge Current Programming Input. Connect a resistor from ISET to GND to
program the fast charge current. The charge current is programmable from
300mA to 2A.
ISET
D1
10
I
LDO output. LDO is regulated to 4.9V and drives up to 50mA. Bypass LDO
with a 1μF ceramic Capacitor. LDO is enabled when VUVLO < VIN <18V.
LDO
F4
24
O
PGND
PMID
SCL
A3, B3, C3, F3
15–16
Ground pin. Connect to the ground plane of the circuit.
D5
E2
F2
20
6
I
I
Connection between blocking FET and high-side FET.
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
SDA
5
I/O
Status Output. STAT is an open-drain output that signals charging status and
fault interrupts. STAT pulls low during charging. STAT is high impedance when
charging is complete or the charger is disabled. When a fault occurs, a 256μs
pulse is sent out as an interrupt for the host. STAT is enabled/disabled using
the EN_STAT bit in the control register. STAT will indicate recharge cycles.
Connect STAT to a logic rail using an LED for visual indication or through a
10kΩ resistor to communicate with the host processor.
STAT
E3
7
O
SW
A4, B4, C4
A2, B2, C2
17–18
13–14
O
I
Inductor Connection. Connect to the switching side of the external inductor.
System Voltage Sense and SMPS output filter connection. Connect SYS to the
system output at the output bulk capacitors. Bypass SYS locally with >20μF.
SYS
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider
from LDO to GND. The NTC is connected from TS to GND. See the NTC
Monitor section for more details on operation and selecting the resistor values.
TS
F1
9
I
Input DPM Programming Input. Connect a resistor divider between IN and GND
with VDPM connected to the center tap to program the Input Voltage based
Dynamic Power Management threshold (VIN_DPM). The input current is reduced
to maintain the supply voltage at VIN_DPM. The reference for the regulator is
1.2V. Short pin to GND if external resistors are not desired—this sets a default
of 4.68V for the input DPM threshold (EN1=1,EN2=0).
VDPM
E4
23
I
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.7
–0.3
–0.3
–0.3
–0.3
MAX UNIT
IN
20
12
20
7
V
V
V
V
V
V
SW
Pin Voltage (with respect
to GND)
BOOT
LDO,STAT, INT, CHG, EN1, EN2, CE, ILIM, ISET, VDPM, TS
SYS, BAT
5
BOOT relative to SW
7
IN
2
Output Current
(Continuous)
A
SYS, BAT
STAT, CHG
4
Output Sink Current
5
mA
°C
°C
W
Operating free-air temperature
Junction temperature, TJ
–40
–40
85
125
15
Input Power
IN
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.2 Handling Ratings
MIN MAX UNIT
TSTG
Storage temperature range
Human body model (HBM)(1)
–65 150 °C
V(ESD)
Electrostatic discharge
0
2000
V
(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
7.3 Recommended Operating Conditions
All voltages are with respect to PGND if not specified. Currents are positive into, negative out of the specified pin. Consult
Packaging Section of the data book for thermal limitations and considerations of packages
MIN
4.35
4.35
MAX UNIT
IN voltage range
18(1)
10.5
2
V
VIN
IN operating voltage range
Input current
IIN
A
A
ICHG
IDISCHG
RISET
RILIM
PIN
Current in charge mode, BAT
Current in discharge mode, BAT
Charge current programming resistor range
Input current limit programming resistor range
Input Power
2
4
A
75
Ω
105
Ω
12
W
°C
TJ
Operating junction temperature range
0
125
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. Small
routing loops for the power nets in layout minimize switching noise.
7.4 Thermal Information
bq24250C
THERMAL METRIC(1)
UNIT
YFF
76.5
0.2
RGE
32.9
32.8
10.6
0.3
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJB
43.4
N/A
10.7
2.3
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VDPM < VIN < VOVP AND VIN > VBAT+VSLP
PWM switching, CE Enable
13
mA
IIN
Supply current from IN
VDPM < VIN < VOVP AND VIN > VBAT+VSLP
PWM switching, CE Disable
5
225
22
0°C< TJ < 85°C, High-Z Mode
170
16
μA
0°C< TJ < 85°C, VBAT = 4.2 V,
VIN = 0V or 5V, High-Z Mode
Battery discharge current in high
impedance mode, (BAT, SW, SYS)
IBAT
μA
0°C< TJ < 85°C, VBAT = 4.2 V,
VIN < UVLO, SYSOFF Mode
Battery discharge current in
1
SYSOFF mode, (BAT, SW, SYS)
6
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Electrical Characteristics (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-PATH MANAGEMENT
MINSYS stage (no DPM or DPPM)
MINSYS stage (DPM or DPPM active)
–1%
3.52
1%
VMINSYS
–200mV
–1.50%
1.50%
VSYSREG
System Regulation Voltage
V
VBAT
+ ICHG Ron
BATREG stage
SYSREG stage
VBAT = 3.6V
VBATREG
+2.1%
VBATREG
+3.1%
VBATREG
+4.1%
VBAT
–
Enter supplement mode voltage
threshold
VSPLM
ISPLM
V
40mV
Exit supplement mode current
threshold
VBAT = 3.6V
20
mA
BATTERY CHARGER
Measured from BAT to SYS,
VBAT = 4.2V (WCSP)
Internal battery charger MOSFET
on-resistance
RON(BAT-SYS)
20
30
mΩ
Operating in voltage regulation,
Programmable Range
I2C host mode
3.5
4.44
V
SA mode or I2C default mode
4.2
VBATREG
TJ = 25°C
–0.5%
–0.75%
500
0.5%
0.75%
2000
7%
Voltage Regulation Accuracy
TJ = 0°C to 125°C
ICHG
Fast Charge Current Range
Fast Charge Current Accuracy
Low Charge Current Setting
VLOWV ≤ VBAT < VBAT(REG)
mA
I2C mode
–7%
Set via I2C
ICHG-LOW
297
330
250
363
mA
K
ISET
ISET
Programmable Fast Charge
Current Factor
I
=
KISET
232.5
267.5
AΩ
CHG
R
Maximum ISET pin voltage (in
regulation)
VISET
0.39
40
0.42
55
0.45
75
V
Ω
RISET-SHORT
Short circuit resistance threshold
Pre-charge to fast charge
threshold
Rising
Battery voltage falling
2.9
3
3.1
V
VLOWV
Hysteresis for VLOWV
100
10
mV
Pr-charge current (VBATUVLO < VBAT Ipre-chg is a precentile of the external fast
IPRECHG
8%
12%
2.65
< VLOWV
)
charge settings.
Battery Under voltage lockout
threshold
VBAT_UVLO
VBAT rising
2.39
2.52
200
2
V
mV
Battery UVLO hysteresis
Trickle charge to pre-charge
threshold
VBATSHRT
1.9
25
2.1
50
V
Hysteresis for VBATSHRT
Trickle charge mode charge
Battery voltage falling
Termination current on SA only
Below VBATREG
100
35
mV
IBATSHRT
mA
current (VBAT < VBATSHRT
)
Termination Current Threshold
10
%ICHG
ITERM
Termination Current Threshold
Tolerance
–10%
70
10%
160
VRCH
Recharge threshold voltage
115
mV
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Electrical Characteristics (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY DETECTION
Battery Detection High Regulation
Voltage
VBATREG_HI
VBATREG_LO
VBATDET Hi
VBATDET LO
Same as VBATREG
VBATREG
V
V
V
Battery Detection Low Regulation
Voltage
VBATREG
–480mV
360 mV offset from VBATREG
VBATREG = VBATREG_HI
VBATREG
–120mV
Battery detection comparator
Battery detection comparator
VBATREG
+120mV
VBATREG = VBATREG_LO
V
IDETECT
Tsafe
Battery Detection Current Sink
Safety Timer Accuracy
Always on during battery detection
7.5
mA
–10%
+10%
INPUT PROTECTION
IIN_LIMIT = 100 mA
IIN_LIMIT = 150 mA
IIN_LIMIT = 500 mA
IIN_LIMIT = 900 mA
IIN_LIMIT = 1500 mA
IIN_LIMIT = 2000 mA
90
135
95
142.5
475
100
150
mA
450
500
810
860
910
IIN
Input current limiting
1400
1850
1475
1950
1550
2050
K
ILIM
I
=
IIN_LIMIT = External
LIM
R
ILIM
Maximum input current limit
programmable range for IN input
ILIM
500
240
2000
300
mA
Maximum input current factor for
IN input
KILIM
ILIM = 500 mA to 2.0 A
270
AΩ
Maximum ILIM pin voltage (in
regulation)
VILIM
0.42
83
V
RILIM-SHORT
Short circuit resistance threshold
55
4.2
4.2
105
10
Ω
SA mode
I2C mode
VIN_DPM threshold range
4.76
USB100, USB150, USB500, USB900,
current limit selected. Also I2C register
default.
VIN_DPM threshold for USB Input in
SA mode
4.27
4.36
4.45
V
VIN_DPM
VIN_DPM threshold with adaptor
current limit and VDPM shorted to
GND
Must set to external resistor settings via the
EN1/EN2 pins or the I2C register interface.
VIN_DPM
–2%
VIN_DPM
+2%
VIN_DPM
Both I2C and SA mode
VIN_DPM threshold Accuracy
DPM regulation voltage
–2%
1.15
2%
VREF_DPM
External resistor setting only
1.2
0.3
1.25
V
V
If VDPM is shorted to ground, VIN_DPM
threshold will use internal default value
VDPM_SHRT
VIN_DPM short threshold
IC active threshold voltage
IC active hysteresis
VIN rising
3.15
3.35
175
3.5
V
VUVLO
VIN falling from above VUVLO
mV
Sleep-mode entry threshold,
VIN-VBAT
2.0 V ≤ VBAT ≤ VBATREG, VIN falling
2.0 V ≤ VBAT ≤ VBATREG
0
50
100
160
mV
mV
VSLP
Sleep-mode exit hysteresis,
VIN-VBAT
40
100
Input supply OVP threshold
voltage
Input OVP
–200mV
Input OVP
+200mV
IN rising
Input OVP
V
VOVP
VOVP hysteresis
IN falling from VOVP
100
105
1
mV
VBAT threshold over VBATREG to turn off
charger during charge
Battery OVP threshold voltage
VBOVP hysteresis
102.5
107.5 % VBATREG
% VBATREG
VBOVP
Lower limit for VBAT falling from above VBOVP
8
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Electrical Characteristics (continued)
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM CONVERTER
Internal blocking MOSFET on-
resistance
RON(BLK)
Measured from IN to PMID
60
100
110
100
150
165
mΩ
mΩ
mΩ
Internal high-side MOSFET on-
resistance
RON(HS)
RON(LS)
Measured from PMID to SW
Internal low-side MOSFET on-
resistance
Measured from SW to PGND
VSYS shorted
ICbC
Cycle-by-cycle current limit
Oscillator frequency
Maximum duty cycle
Minimum duty cycle
Thermal trip
2.6
2.7
3.2
3
3.8
3.3
A
fOSC
DMAX
DMIN
MHz
95%
0%
150
10
°C
TSHTDWN
Thermal hysteresis
TREG
LDO
VLDO
ILDO
Thermal regulation threshold
Charge current begins to cut off
VIN = 5.5 V, ILDO = 0 to 50 mA
VIN = 5.0 V, ILDO = 50 mA
125
LDO Output Voltage
4.65
50
4.95
200
5.25
300
V
Maximum LDO Output Current
LDO Dropout Voltage (VIN – VLDO
mA
mV
VDO
)
BATTERY-PACK NTC MONITOR (1)
VHOT
High temperature threshold
VTS falling
VTS rising
VTS falling
VTS rising
29.6
0.6
30
0.9
30.4
1.2
VHYS(HOT)
VWARM
Hysteresis on high threshold
Warm temperature threshold
37.9
0.6
38.3
0.9
38.7
1.2
VHYS(WARM)
Hysteresis on warm temperature
threshold
VCOOL
Cool temperature threshold
VTS rising
VTS falling
48.1
0.6
48.5
0.9
48.9
1.2
% VLDO
Hysteresis on cool temperature
threshold
VHSY(COOL)
VCOLD
VHYS(COLD)
VFRZ
Low temperature threshold
Hysteresis on low threshold
Freeze temperature threshold
Hysteresis on freeze threshold
TS current in charge mode
VTS rising
59.6
0.6
62
60
0.9
60.4
1.2
63
VTS falling
VTS rising
62.5
0.9
VHYS(FRZ)
ITS
VTS falling
0.6
1.2
0.1
VIN = 5.0 V, VTS = 2.0 V, VBAT = 3.5 V
0.005
µA
INPUTS (EN1, EN2, CE, SCL, SDA)
VIH
VIL
Input high threshold
Input low threshold
1
V
V
0.4
STATUS OUTPUTS (CHG, STAT, INT)
VOL
IIH
Low-level output saturation voltage IO = 5 mA, sink current
0.4
1
V
High-level leakage current
Hi-Z and 5V applies
µA
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7.6 Timing Requirements
VUVLO < VIN < VOVP and VIN > VBAT+VSLP, TJ = 0ºC-125°C and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-PATH MANAGEMENT
Deglitch Time, OUT Short Circuit
during Discharge or Supplement
Mode
Measured from
(VBAT – VSYS) = 300 mV
tDGL(SC1)
740
64
μs
Recovery Time, OUT Short Circuit
during Discharge or Supplement
Mode
tREC(SC1)
ms
BATTERY CHARGER
Deglitch time for pre-charge to fast
charge transition
tDGL(LOWV)
32
ms
µs
Deglitch time for trickle charge to
pre-charge transition
tDGL(BATSHRT)
256
Deglitch time for charge
termination
Both rising and falling, 2-mV over-drive,
tRISE, tFALL = 100 ns
tDGL(TERM)
tDGL(RCH)
64
32
ms
ms
Deglitch time
VBAT falling below VRCH, tFALL = 100 ns
BATTERY DETECTION
tDETECT
Battery detection time
For both VBATREG_HI and VBATREG_LO
32
32
ms
ms
INPUT PROTECTION
Rising voltage, 2-mV over drive,
tRISE = 100 ns
Deglitch time for IN rising above
VIN+VSLP_EXIT
tDGL(SLP)
Deglitch time for IN Rising above
VOVP
tDGL(OVP)
IN rising voltage, tRISE = 100 ns
Battery entering/exiting BOVP
32
1
ms
ms
tDGL(BOVP)
BOVP Deglitch
BATTERY-PACK NTC MONITOR (1)
tDGL(TS)
Deglitch time on TS change
32
ms
TIMERS
45 min safety timer
6 hr safety timer
9 hr safety timer
Watch dog timer
2700
21600
32400
50
tSAFETY
s
s
tWATCH-DOG
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7.7 Typical Characteristics
Figure 1. Battery Detection
Figure 2. Battery Removal
88
86
84
82
80
78
76
74
72
70
4.350
4.345
4.340
4.335
4.330
4.325
4.320
4.315
4.310
4.305
4.300
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
0.0
0.5
1.0
1.5
2.0
2.5
C001
C004
VBAT (V)
ISYS (A)
Figure 3. Efficiency vs Battery Voltage
Figure 4. System Voltage Regulation vs Load Current
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V = 5 V
IN
V = 5 V
IN
V
= 7 V
V
= 7 V
IN
IN
V
= 10 V
V
= 10 V
IN
IN
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
C002
C003
Output Current (mA)
Output Current (mA)
Figure 5. Efficiency vs Output Current
Figure 6. Efficiency vs Output Current
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Typical Characteristics (continued)
18
16
14
1±
10
8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
6
4
±
0
±±
0.0 0.5 1.0 1.5 ±.0 ±.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
C007
C010
VBAT (V)
VBAT (V)
Figure 7. BAT IQ, SYSOFF = 0
Figure 8. BAT IQ, SYSOFF = 1
20
500
450
400
350
300
250
200
150
100
50
CE EN
18
CE DIS
16
14
12
10
8
6
4
2
0
0
0
5
10
15
20
25
0
5
10
15
20
25
C008
C009
Input Voltage (V)
Input Voltage (V)
Figure 9. Input IQ With Charge DIS and EN
Figure 10. Input IQ with Charge Enable and Hi-Z
21ꢀ
21.
31ꢀ
21.
21ꢀ
±1ꢀ
±1.
±1.
±1ꢀ
ꢀ1.
.1ꢀ
ꢀ1ꢀ
.1.
±ꢀ1.
±±1ꢀ
±±1.
ꢀ.. mA
.ꢀꢀ mA
± A
±.1ꢀ
±±1.
± A
±1ꢀ A
±1. A
.
±. 2. 3. 4. ꢀ. 6. 7. 8. 9. ±.. ±±. ±2. ±3.
ꢀ
±ꢀ 2ꢀ 3ꢀ 4ꢀ .ꢀ 6ꢀ 7ꢀ 8ꢀ 9ꢀ ±ꢀꢀ ±±ꢀ ±2ꢀ ±3ꢀ
C.±±
Cꢀ±2
Temperature (ƒC)
Temperature (ƒC)
Figure 11. ICHG Accuracy with Internal Settings, VBAT = 3.3 V
Figure 12. ICHG Accuracy with Internal Settings, VBAT = 3.8 V
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Typical Characteristics (continued)
Figure 13. Input OVP Event with INT
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8 Detailed Description
8.1 Overview
The bq24250C is a highly-integrated, single-cell, Li-Ion battery charger with integrated current sense resistors
targeted for space-limited, portable applications with high-capacity batteries. The single-cell charger has a single
input that operates from either a USB port or AC wall adapter for a versatile solution.
The bq24250C device has two modes of operation: 1) I2C mode, and 2) standalone mode. In I2C mode, the host
adjusts the charge parameters and monitors the status of the charger operation. In standalone mode, the
external resistor sets the input-current limit, and charge current limit. Standalone mode also serves as the default
settings when a DCP adapter is present. It enters host mode while the I2C registers are accessed and the
watchdog timer has not expired (if enabled). The battery is charged in four phases: trickle charge, pre-charge,
constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction
temperature and reduces the charge current if the internal temperature threshold is exceeded.
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8.2 Functional Block Diagram
PMID
Q1
LDO
LDO
IN
Charge
Pump
Q2
ILIM
BOOT
+
CbC
Comparator
IIN_LIM
Amp
_
VREF_INLIM
VIN_DPM
Amp
+
_
VDPM
VREF_DPM
PWM
LOOP SELECT
COMPENSATION
DRIVER
Host
SW
+
_
VDPM_DAC
V LDO
I2C Only
Q3
TJ
+
PGND
125 C
MINSYS
Amp
_
+
VREF_MINSYS
+
ICHG
Amp
VSYSMIN
_
+
ISET
SYS
VBATREG
Amp
_
+
Sleep
Comparator
_
VREF_BATREG
VREF_ICHG
+
VBAT +VSLP
VREF_TERM
+
LDO
Termination
Comparator
EN1 / D+
EN2 / D-
Input
current limit
decoder /
D+ and D-
Decoder
Batt Detect Or
VMINSYS
Reference
Q4
Precharge
Recharge Comparator
+
Current Source
VBATREG – 0.12V
VBAT
MINSYS
ICHG Amp
BAT
SCL
SDA
VOUTMIN Comparator
+
I2C
Controller
+
VOUT
Charge
Pump
CHARGE
CONTROLLER
MINSYS Comparator
INT / PG
+
VSYS
VMINSYS
BATSHORT Comparator
+
VBAT
STAT/CHG
VBATSHRT
Supplement Comparator
+
VSYS
VBSUP
VLDO
VBAT
DISABLE
+
TS -10°C
+
/CE
TS 0°C
+
TS 10°C
TS 45°C
+
+
TS 60°C
TS
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8.3 Feature Description
8.3.1 Dynamic Power Path Management
The bq24250C features a SYS output that powers the external system load connected to the battery. This output
is active whenever a valid source is connected to IN or BAT. The following discusses the behavior of SYS with a
source connected to the supply or a battery source only.
When a valid input source is connected to the input and the charge is enabled, the charge cycle is initiated. In
case of VBAT > ~3.5V, the SYS output is connected to VBAT. If the SYS voltage falls to VMINSYS, it is
regulated to the VSYSREG threshold to maintain the system output even with a deeply discharged or absent
battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly
regulated to regulate the charge current into the battery. The current from the supply is shared between charging
the battery and powering the system load at SYS.
The dynamic power path management (DPPM) circuitry of the bq24250C monitors the current limits continuously
and if the SYS voltage falls to the VMINSYS voltage, it adjusts charge current to maintain the minimum system
voltage and supply the load on SYS. If the charge current is reduced to zero and the load increases further, the
bq24250C enters battery supplement mode. During supplement mode, the battery FET is turned on and the
battery supplements the system load.
If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off and
the battery FET is turned on to discharge the battery to safe operating levels. Battery OVP FAULT is shown in
the I2C FAULT registers.
When no input source is available at the input and the battery is connected, the battery FET is turned on similar
to supplement mode. The battery must be above VBATUVLO threshold to turn on the SYS output. In this mode,
the current is not regulated;
8.3.2 Production Test Mode
To aid in end mobile device product manufacturing, the bq24250C includes a Production Test Mode (PTM),
where the device is essentially a DC-DC buck converter. In this mode the input current limit to the charger is
disabled and the output current limit is limited only by the inductor cycle-by-cycle current (e.g. 3.5A). The PTM
mode can be used to test systems with high transient loads such as GSM transmission without the need of a
battery being present.
As a means of safety, the Anyboot algorithm determines if a battery is not present at the output prior to enabling
the PTM mode. If a battery is present and the software attempts to enter PTM mode, the device will not enable
PTM mode.
8.3.3 AnyBoot Battery Detection
The bq24250C includes a sophisticated battery detection algorithm used to provide the system with the proper
status of the battery connection. The AnyBoot battery algorithm also ensures the detection of voltage based
battery protectors that may have a long closure time (due to the hysteresis of the protection switch and the cell
capacity). The AnyBoot battery detection algorithm utilizes a dual-voltage based detection methodology where
the system rail switches between two primary voltage levels. The period of the voltage level shift is 64ms and
therefore the power supply rejection of the down-system electronics detects this shift as essentially DC.
The AnyBoot algorithm has essentially 3 states. The 1st state is used to determine if the device has terminated
with a battery attached. If it has terminated due to the battery not being present, then the algorithm moves to the
2nd and 3rd states. The 2nd and 3rd states shift the system voltage level between 4.2V and 3.72V. In each state
there are comparator checks to determine if a battery has been inserted. The two states ensure the detection of
a battery even if the voltage of the cell is at the same level of the comparator thresholds. The algorithm will
remain in states 2 and 3 until a battery has been inserted. The flow diagram details for the Anyboot algorithm are
shown in Figure 14.
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Feature Description (continued)
Enter Battery
Detection
BATREG = Vreg
setting – 480 mV
No
Battery Detected, STAT
register updated, and PTM
mode aborted (if enabled)
Yes
VBAT >
BATREG+120 mV?
Yes
32 ms Timer Expired?
No
No
32 ms Timer Expired?
Yes
BATREG = 4.2 V
No
Battery Detected, STAT
register updated and
Exit Battery Detection
Yes
Yes
VBAT < 4.08 V?
32 ms Timer Expired?
No
No
32ms Timer Expired?
Yes
ONLY ON FIRST LOOP ITERATION
“No Battery” Condition
BATREG = 4.2 V
Update STAT Registers and send Fault Pulse
Yes
Enter PTM mode
Exit Battery Detection
Force PTM = 1?
No
BATREG = 3.72 V
No
Battery Detected, STAT
register updated and
Exit Battery Detection
Yes
Yes
VBAT > 3.84 V?
No
32 ms Timer Expired?
No
32 ms Timer Expired?
Yes
Figure 14. AnyBoot Battery Detection Flow Diagram
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8.4 Device Functional Modes
8.4.1 Charge Profile
The bq24250C provides a switch-mode buck regulator with output power path and a charge controller to provide
optimum performance over the full battery charge cycle. The control loop for the buck regulator has 7 primary
feedback loops that can set the duty cycle:
1. Constant Current (CC)
2. Constant Voltage (CV)
3. Minimum System Voltage (MINSYS)
4. Input Current (IILIM
)
5. Input Voltage (VIN_DPM
)
6. Die Temperature
7. Cycle by Cycle Current
The feedback with the minimum duty cycle will be chosen as the active loop. The bq24250C supports a precision
Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path Management (DPPM)
feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled even with a missing or
deeply discharged battery. This provides a much better overall user experience in mobile applications. The figure
below illustrates a typical charge profile while also demonstrating the minimum system output voltage regulation.
Trickle
Charge
Pre-
charge
Current Regulation
Phase(CC)
Voltage Regulation
Phase(CV)
Termination
VBATREG
ICHG
ICHG
VMINSYS
(3.5 V)
VSYS
VBAT
VLOWV
VBATSHRT
IPRECHG
ITERM
I BATSHRT
Linear trickle
charge
Linear
Pre- charge
Linear
fast charger
BATFET on-- PWM fast charge
BATFET off
MINSYS
regulation
BATREG
regulation
SYSREG
regulation
Figure 15. Typical Charge Profile
Figure 16 demonstrates a measured charge profile with the bq24250C while charging a 2700mAh Li-Ion battery
at a charge rate of 1A.
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Device Functional Modes (continued)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
BAT
V
SYS
I
BAT
0
2k
4k
6k
8k
10k
12k
14k
16k
C005
Time (s)
Figure 16. bq24250C Charge Profile while Charging a 2700 mAh Battery at a 1A Charge Rate
Figure 17 illustrates the precharge behavior of the above charge profile by narrowing the time axis to 0 – 120
seconds.
3.7
3.5
3.3
3.1
2.9
2.7
2.5
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
BAT
V
SYS
I
BAT
0
20
40
60
80
100
120
C006
Time (s)
Figure 17. bq24250C Charge Profile While Charging a 2700-mAh Battery at a 1A Charge During
Precharge
8.4.2 EN1/EN2 Pins
The bq24250C is I2C and Stand Alone part. The EN1 and EN2 pins are available in this IC spin to support USB
2.0 compliance. These pins are used for Input Current Limit Configuration I. Set EN1 and EN2 to control the
maximum input current and enable USB compliance. See Table 1 below for programming details.
When the input current limit pins change state, the VIN_DPM threshold changes as well. See Table 1 for the
detailed truth table:
Table 1. EN1, and EN2 Truth Table(1)
EN2
EN1
Input Current Limit
VIN_DPM Threshold
0
0
1
1
0
1
0
1
500mA
4.36V
Externally programmed by ILIM (up to 2.0A)
Externally programmed VDPM
100mA
4.36V
None
Input Hi-Z
(1) USB3.0 support available. Contact your local TI representative for details.
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8.4.3 I2C Operation (Host Mode / Default Mode)
There are two primary modes of operation when interacting with the charge parameters of the bq24250C
charger: 1) Host mode operation where the I2C registers set the charge parameters, and 2) Default mode where
the register defaults set the charge parameters.
Figure 18 illustrates the behavior of the bq24250C when transitioning between host mode and stand alone mode:
Battery or Input
is Inserted
No
VIN or VBAT GOOD?
Yes
ILIM=EN1/EN2
No
VDPM=External Default
ISET=External Default
I2C command received?
Yes
ILIM=Register Value
VDPM=Register Value
ISET=Register Value
No
Yes
50s Watchdog Expired?
Host Mode
Figure 18. Host Mode and Stand Alone Mode Handoff
Once the battery or input is inserted and above the good thresholds, the device determines if an I2C command
has been received in order to discern whether to operate from the I2C registers or the internal register defaults. In
stand-alone mode the input current limit is set by the EN1/EN2 pins. If the watch dog timer is enabled, the device
will enter stand alone operation once the watchdog timer expires and re-initiate the default charge settings.
8.4.4 External Settings: ISET, ILIM and VIN_DPM
If the external resistor settings are used, the following equations can be followed to configure the charge settings.
The fast charge current resistor (RISET) can be set by using the following formula:
KISET
=
250
RISET
=
IFC
IFC
(1)
Where IFC is the desired fast charge current setting in Amperes.
The input current limit resistor (RILIM) can be set by using the following formula:
KILIM
270
=
RILIM
=
I
I
IC
IC
(2)
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Where IIC is the desired input current limit in Amperes.
Based on the application diagram reference designators, the resistor R1 and R2 can be calculated as follows to
set VIN_DPM
:
R1 + R2
R1 + R2
V
= VREF _DPM
´
= 1.2V ´
IN_DPM
R2
R2
(3)
VIN_DPM should be chosen first along with R1. Choosing R1 first will ensure that R2 will be greater than the
resistance chosen. This is the case since VIN_DPM should be chosen to be greater than 2x VREF_DPM
.
If external resistors are not desired in order to reduce the BOM count, the VDPM and the ILIM pins can be
shorted to set the internal defaults. The ISET resistor cannot be shorted in order to avoid an unstable charging
state.Note that floating the ILIM pin will result in zero charge current if the external ISET is configured via the I2C
register. Table 2 summarizes the settings when the ILIM, ISET, and VIN_DPM pins are shorted to GND:
Table 2. ILIM, VDPM, and ISET Short Behaviors
PIN SHORTED
ILIM
BEHAVIOR
Input current limit = 2A
VIN_DPM = 4.68V
VDPM
ISET
Fault—Charging Suspended
8.4.5 Transient Response
The bq24250C includes an advanced hybrid switch mode control architecture. When the device is regulating the
charge current (fast-charge), a traditional voltage mode control loop is used with a Type-3 compensation
network. However, the bq24250C switches to a current mode control loop when the device enters voltage
regulation. Voltage regulation occurs in three charging conditions: 1) Minimum system voltage regulation (battery
below MINSYS), 2) Battery voltage regulation (IBAT < ICHG), and 3) Charge Done (VSYS = VBAT + 3.5%). This
architecture allows for superior transient performance when regulating the voltage due to the simplification of the
compensation when using current mode control. The below transient response plot illustrates a 0A to 2A load
step with 4.7ms full cycle and 12% duty cycle. A 3.9V Li-Ion battery is used. The input voltage is set to 5V,
charge current is set to 0.5A and the input current is limited to 0.5A. Note that a high line impedance input supply
was used to indicate a realistic input scenario (adapter and cable). This is illustrated by the change in VIN seen at
the input of the IC.
Figure 19 shows a ringing at both the input voltage and the input current. This is caused by the input current limit
speed up comparator.
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Figure 19. 2A Load Step Transient
8.4.6 Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage deceases. Once the supply drops to VIN_DPM, the input current limit is
reduced down to prevent the further drop of the supply. When the IC enters this mode, the charge current is
lower than the set. This feature ensures IC compatibility with adapters with different current capabilities without a
hardware change.
8.4.7 Sleep Mode
The bq24250C enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
VBAT+VSLP, and VIN is higher than the under-voltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VIN. When VIN < VBAT+VSLP, the bq24250C turns off the PWM converter,
turns on the battery FET, sends a single 256µs pulse is sent on the STAT and INT outputs and the FAULT/STAT
bits of the status registers are updated in the I2C. Once VIN > VBAT+VSLP with the hysteresis, the FAULT bits
are cleared and the device initiates a new charge cycle.
8.4.8 Input Over-Voltage Protection
The bq24250C provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq24250C turns off the PWM converter, turns
the battery FET, sends a single 256μs pulse is sent on the STAT and INT outputs and the FAULT/STAT bits of
the status registers and the battery/supply status registers are updated in the I2C. Once the OVP fault is
removed, the FAULT bits are cleared and the device returns to normal operation. The OVP threshold for the
bq24250 is programmable from 6.5V to 10.5V using VOVP bits in register #7.
8.4.9 NTC Monitor
The bq24250C includes the integration of an NTC monitor pin that complies with a modified JEITA specification
(PSE also available upon request). The voltage based NTC monitor allows for the use of any NTC resistor with
the use of the circuit shown in Figure 20.
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LDO
TS
R
2
R
NTC
3
Figure 20. Voltage Based NTC circuit
The use of R3 is only necessary when the NTC does not have a beta near 3500K. When deviating from this
beta, error will be introduced in the actual temperature trip thresholds. The trip thresholds are summarized below
which are typical values provided in the specification table. Note that the TWARM threshold is just a warning for the
warm temperature, the device will generate an interrupt but it will not affect the charging process.
Table 3. Ratiometric TS Trip Thresholds
VHOT
VWARM
VCOOL
VCOLD
30.0%
38.3%
48.5%
60%
When sizing for R2 and R3, it is best to solve two simultaneous equations that ensure the temperature profile of
the NTC network will cross the VHOT and VCOLD thresholds. The accuracy of the VWARM and VCOOL threshold will
depend on the beta of the chosen NTC resistor. The two simultaneous equations are shown below:
æ
ç
ç
è
ö
÷
÷
ø
R3 RNTC
TCOLD
R3 + RNTC
TCOLD
%VCOLD
=
=
´100
æ
ç
ç
è
ö
÷
÷
ø
R3 RNTC
TCOLD
+ R2
R3 + RNTC
TCOLD
æ
ö
÷
÷
ø
R3 RNTC
THOT
ç
ç
è
R3 + RNTC
THOT
%VHOT
´100
æ
ç
ç
è
ö
÷
÷
ø
R3 RNTC
THOT
+ R2
R3 + RNTC
THOT
(4)
(5)
Where the NTC resistance at the VHOT and VCOLD temperatures must be resolved as follows:
1
1
-
b
(
= Roe
)
TCOLD To
RNTC
TCOLD
1
1
-
β
(
)
THOT To
RNTC THOT =Roe
To be JEITA compliant, TCOLD must be 0°C and THOT must be 60°C. If an NTC resistor is chosen such that the
beta is 4000K and the nominal resistance is 10kΩ, the following R2 and R3 values result from the above
equations:
R2 = 5 kΩ
R3 = 9.82 kΩ
Figure 21 illustrates the temperature profile of the NTC network with R2 and R3 set to the above values.
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Example NTC Network Profile of %LDO vs. TEMP
60
55
50
45
40
35
30
T
COOL
0
10
20
30
Temperature (C)
40
50
60
Figure 21. Voltage Based NTC Circuit Temperature Profile
Once the resistors are configured, the internal JEITA algorithm will apply the below profile at each trip point for
battery voltage regulation and charge current regulation.
Programmed VBAT_REG
No Charge
No Charge
Programmed ICHG
(1C)
0.5C
No Charge
No Charge
VCOLD VCOOL
VWARM VHOT
Figure 22. Modified JEITA Profile for Voltage and Current Regulation Loops
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8.4.10 Safety Timer
At the beginning of charging process, the bq24250C starts the safety timer. This timer is active during the entire
charging process. If charging has not terminated before the safety timer expires, the IC enters suspend mode
where charging is disabled. The safety timer time is selectable using the I2C interface. A single 256μs pulse is
sent on the STAT and INT outputs and the FAULT/ bits of the status registers are updated in the I2C. This
function prevents continuous charging of a defective battery if the host fails to reset the safety timer. When
2xTMR_EN bit is set to “1”, the safety timer runs at a rate 2x slower than normal (the timer is extended) under
the following conditions:
•
•
•
Pre-charge or linear mode (minimum system voltage mode),
During thermal regulation where the charge current is reduced,
During TS fault where the charge current is reduced
The safety timer is suspended during OVP, TS fault where charge is disabled, thermal shut down, and sleep
mode.
8.4.11 Watchdog Timer
In addition to the safety timer, the bq24250C contains a 50-second watchdog timer that monitors the host
through the I2C interface. Once a write is performed on the I2C interface, a watchdog timer is reset and started.
The watchdog timer can be disabled by writing “0” on WD_EN bit of register #1. Writing “1” on that bit enables it
and reset the timer.
If the watchdog timer expires, the IC enters DEFAULT mode where the default charge parameters are loaded
and charging continues. The I2C may be accessed again to re-initialize the desired values and restart the
watchdog timer as long as the safety timer has not expired. Once the safety timer expires, charging is disabled.
8.4.12 Thermal Regulation and Thermal Shutdown
During the charging process, to prevent overheat of the chip, bq24250C monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG.
The charge current is reduced when the junction temperature increases above TREG. Once the charge current is
reduced, the system current is reduced while the battery supplements the load to supply the system. This may
cause a thermal shutdown of the IC if the die temperature rises too. At any state, if TJ exceeds TSHTDWN,
bq24250C suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned
off, all safety timers are suspended, and a single 256μs pulse is sent on the STAT and INT outputs and the
FAULT/STAT bits of the status registers are updated in the I2C. A new charging cycle begins when TJ falls below
TSHTDWN by approximately 10°C.
8.4.13 Fault Modes
The bq24250C includes several hardware fault detections. This allows for specific conditions that could cause a
safety concern to be detected. With this feature, the host can be alleviated from monitoring unsafe charging
conditions and also allows for a “fail-safe” if the host is not present. The table below summarizes the faults that
are detected and the resulting behavior.
FAULT CONDITION
Input OVP
CHARGER BEHAVIOR
VSYS and ICHG Disabled
SAFETY TIMER BEHAVIOR
Suspended
Reset
Input UVLO
VSYS and ICHG Disabled
Sleep (VIN < VBAT)
TS Fault (Batter Over Temp)
Thermal Shutdown
Timer Fault
VSYS and ICHG Disabled
Suspended
Suspended
Suspended
Reset
VSYS Active and ICHG Disabled
VSYS and ICHG Disabled
VSYS Active and ICHG Disabled
VSYS Active and ICHG Disabled
VSYS Active and ICHG Disabled
VSYS and ICHG Disabled
No Battery
Suspended
Suspended
Suspended
ISET Short
Input Fault & LDO Low
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8.4.14 Serial Interface Description
The bq24250C uses an I2C compatible interface to program charge parameters. I2C is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I2C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device.
Thebq24250C device works as a slave and supports the following data transfer modes, as defined in the I2C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from IN when a supply is connected.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq24250C device only supports 7-bit addressing. The device 7-bit address is
defined as ‘1101010’ (0x6Ah).
To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the transaction takes longer than
tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
8.4.14.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 23. All I2C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 23. START and STOP Condition
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 24). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 24. Bit Transfer on the Serial Interface
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The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
9
8
1
2
Clock Pulse for
Acknowledgement
START
Condition
Figure 25. Acknowledge on the I2C Bus
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
Figure 26. Bus Protocol
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8.5 Register Maps
Register #1
Memory location: 00, Reset state: x0xx xxxx
BIT
NAME
READ/WRITE
FUNCTION
Read:0 – No fault
1 – WD timeout if WD enabled
B7(MSB)
WD_FAULT
Read only
0 – Disable
1 – Enable (also resets WC timer)
B6
B5
WD_EN
STAT_1
Read/Write
Read only
00 – Ready
01 – Charge in progress
10 – Charge done
11 – Fault
B4
STAT_0
Read only
B3
B2
B1
FAULT_3
FAULT_2
FAULT_1
Read only
Read only
Read only
0000 – Normal
0001 – Input OVP
0010 – Input UVLO
0011 – Sleep
0100 – Battery Temperature (TS) Fault
0101 – Battery OVP
0110 – Thermal Shutdown
0111 – Timer Fault
B0(LSB)
FAULT_0
Read only
1000 – No Battery connected
1001 – ISET short
1010 – Input Fault and LDO low
WD_FAULT
WD_EN
‘0’ indicates no watch dog fault has occurred, where a ‘1’ indicates a fault has previously
occurred.
Enables or disables the internal watch dog timer. A ‘1’ enables the watch dog timer and a
‘0’ disables it. '1' is default for bq24251 only.
STAT
Indicates the charge controller status.
FAULT
Indicates the faults that have occurred. If multiple faults occurred, they can be read by
sequentially addressing this register (e.g. reading the register 2 or more times). Once all
faults have been read and the device is in a non-fault state, the fault register will show
“Normal”. Regarding the "Input Fault & LDO Low" the IC indicates this if LDO is low and
at the same time the input is below UVLO or coming out of UVLO with LDO still low.
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Register #2
Memory location: 01, Reset state: xxxx 1100
BIT
NAME
READ/WRITE
FUNCTION
Write:
B7(MSB)
Reset
Write only
1 – Reset all registers to default values
0 – No effect
B6
B5
IIN_ILIMIT_2
IIN_ILIMIT_1
Read/Write
Read/Write
000 – USB2.0 host with 100mA current limit
001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB3.0 host with 900mA current limit
100 – Charger with 1500mA current limit
101 – Charger with 2000mA current limit
110 – External ILIM current limit
B4
IIN_ILIMIT _0
Read/Write
111- No input current limit with internal clamp at 3A (PTM MODE)
0 – Disable STAT function
1 – Enable STAT function
B3
B2
B1
EN_STAT
EN_TERM
CE
Read/Write
Read/Write
Read/Write
Read/Write
0 – Disable charge termination
1 – Enable charge termination
0 – Charging is enabled
1 – Charging is disabled
0 – Not high impedance mode
1 – High impedance mode
B0 (LSB)
HZ_MODE
IIN_LIMIT
Sets the input current limit level. When in host mode this register sets the regulation
level. However, when in standalone mode (e.g. no I2C writes have occurred after power
up or the WD timer has expired) the external resistor setting for IILIM sets the regulation
level.
EN_STAT
EN_TERM
Enables and disables the STAT pin. When set to a ‘1’ the STAT pin is enabled and
function normally. When set to a ‘0’ the STAT pin is disabled and the open drain FET is
in HiZ mode.
Enables and disables the termination function in the charge controller. When set to a ‘1’
the termination function will be enabled. When set to a ‘0’ the termination function will be
disabled. When termination is disabled, there are no indications of the charger
terminating (i.e. STAT pin or STAT registers).
CE
The charge enable bit which enables or disables the charge function. When set to a ‘0’,
the charger operates normally. With a valid input, when set the bit to a ‘1’, the charger is
disabled by turning off the BAT FET between SYS and BAT. The SYS pin continues to
stay active via the switch mode controller. Without a valid input, When set the bit to a '1',
the BAT FET will not be turned off.
HZ_MODE
Sets the charger IC into low power standby mode. When set to a ‘1’, the switch mode
controller is disabled but the BAT FET remains ON to keep the system powered. When
set to a ‘0’, the charger operates normally.
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Register #3
Memory location: 02, Reset state: 1000 1111
BIT
B7(MSB)
B6
NAME
READ/WRITE
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
FUNCTION
VBATREG_5(1)
VBATREG_4(1)
VBATREG_3(1)
VBATREG_2(1)
VBATREG_1(1)
VBATREG_0(1)
Battery Regulation Voltage: 640mV (default 1)
Battery Regulation Voltage: 320mV (default 0)
Battery Regulation Voltage: 160mV (default 0)
Battery Regulation Voltage: 80mV (default 0)
Battery Regulation Voltage: 40mV (default 1)
Battery Regulation Voltage: 20mV (default 1)
B5
B4
B3
B2
B1(4)(5)
B0(LSB)
USB_DET_1/EN1
Return USB detection result or pin EN1/EN0 status –
00 – DCP detected / EN1=0, EN0=0
01 – CDP detected / EN1=0, EN0=1
USB_DET_0/EN0
Read Only
10 – SDP detected / EN1=1, EN0=0
11 – Apple/TT or non-standard adaptor detected / EN1=1, EN0=1
(1) Charge voltage range is 3.5V—4.44V with the offset of 3.5V and step of 20mV (default 4.2V)
VBATREG
Sets the battery regulation voltage
USB_DET/EN
Provides status of the D+/D– detection-results for spins that include the D+/D– pins or
the state of EN1/EN2 for spins that include the EN1/EN2 pins
Register #4
Memory location: 03, Reset state: 1111 1000
BIT
NAME
READ/WRITE
FUNCTION
Charge current
800mA – (default 1)
B7(MSB)
ICHG_4(1) (2)
Read/Write
Charge current:
400mA – (default 1)
B6
B5
B4
B3
ICHG_3(1) (2)
ICHG_2(1) (2)
ICHG_1(1) (2)
ICHG_0(1) (2)
Read/Write
Read/Write
Read/Write
Read/Write
Charge current:
200mA – (default 1)
Charge current:
100mA – (default 1)
Charge current:
50mA – (default 1)
B2
B1
ITERM_2(3)
ITERM_1(3)
ITERM_0(3)
Read/Write
Read/Write
Read/Write
Termination current sense threshold: 100mA (default 0)
Termination current sense threshold: 50mA (default 0)
Termination current sense threshold: 25mA (default 0)
B0(LSB)
(1) Charge current offset is 500 mA and default charge current is external (maximum is 2.0A)
(2) When all bits are 1’s, it is external ISET charging mode
(3) Termination threshold voltage offset is 50mA. The default termination current is 50mA if the charge is selected from I2C. Otherwise,
termination is set to 10% of ICHG in external I_set mode with +/-10% accuracy.
ICHG
Sets the charge current regulation
ITERM
Sets the current level at which the charger will terminate
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Register #5
Memory location: 04, Reset state: xx00 x010
BIT
NAME
READ/WRITE
FUNCTION
B7(MSB)
LOOP_STATUS1(1)
Read Only
00 – No loop is active that slows down timer
01 – VIN_DPM regulation loop is active
10 – Input current limit loop is active
11 – Thermal regulation loop is active
B6
LOOP_STATUS0(1)
Read Only
0 – Normal charge current set by 03h
1 – Low charge current setting 330mA (default 0)
B5
B4
B3
LOW_CHG
DPDM_EN
Read/Write
Read/Write
Read Only
0 – Bit returns to 0 after D+/D– detection is performed
1 – Force D+/D– detection (default 0)
0 – CE low
1 – CE high
CE_STATUS
(2)
B2
B1
VINDPM_2
Read/Write
Read/Write
Read/Write
Input VIN-DPM voltage: 320mV (default 0)
Input VIN-DPM voltage: 160mV (default 1)
Input VIN-DPM voltage: 80mV (default 0)
(2)
VINDPM_1
(2)
B0(LSB)
VINDPM_0
(1) LOOP_STATUS bits show if there are any loop is active that slow down the safety timer. If a status occurs, these bits announce the
status and do not clear until read. If more than one occurs, the first one is shown.
(2) VIN-DPM voltage offset is 4.20V and default VIN_DPM threshold is 4.36V.
LOOP_STATUS
LOW_CHG
Provides the status of the active regulation loop. The charge controller allows for only
one loop can regulate at a time.
When set to a ‘1’, the charge current is reduced 330mA independent of the charge
current setting in register 0x03. When set to ‘0’, the charge current is set by register
0x03.
DPDM_EN
CE_STATUS
VINDPM
Forces a D+/D- detection routine to be executed once a ‘1’ is written. This is
independent of the input being supplied.
Provides the status of the CE pin level. If the CE pin is forced high, this bit returns a
‘1’. If the CE pin is forced low, this bit returns a ‘0’.
Sets the input VDPM level.
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Register #6
Memory location: 05, Reset state: 101x 1xxx
BIT
NAME
READ/WRITE FUNCTION
0 – Timer not slowed at any time
Read/Write
B7(MSB)
B6
2XTMR_EN
TMR_1
1 – Timer slowed by 2x when in thermal regulation, VIN_DPM or DPPM (default 1)
Read/Write
Read/Write
Safety Timer Time Limit
00 – 0.75 hour fast charge
01 – 6 hour fast charge (default 01)
10 – 9 hour fast charge
B5
TMR_2
11 – Disable safety timers
0 – SYSOFF disabled
1 – SYSOFF enabled
B4
B3
SYSOFF
TS_EN
Read/Write
Read/Write
0 – TS function disabled
1 – TS function enabled (default 1)
B2
B1
TS_STAT2
TS_STAT1
Read only
Read only
TS Fault Mode:
000 – Normal, No TS fault
100 – TS temp < TCOLD (Charging suspended for JEITA and Standard TS)
101 – TFREEZE < TS temp < TCOLD (Charging at 3.9V and 100mA and only for PSE option
only)
110 – TS temp < TFREEZE (Charging suspended for PSE option only)
111 – TS open (TS disabled)
B0(LSB)
TS_STAT0
Read only
2xTMR_EN
When set to a ‘1’, the 2x Timer function is enabled and allows for the timer to be
extended if a condition occurs where the charge current is reduced (i.e. VIN_DPM
,
thermal regulation, etc.). When set to a ‘0’, this function is disabled and the normal
timer will always be executed independent of the current reduce conditions.
SYSOFF
When set to a ‘1’ and the input is removed, the internal battery FET is turned off in
order to reduce the leakage from the BAT pin to less than 1µA. Note that this
disconnects the battery from the system. When set to a ‘0’, this function is disabled.
TS_EN
Enables and disables the TS function. When set to a ‘0’ the TS function is disabled
otherwise it is enabled. Only applies to spins that have a TS pin.
TS_STAT
Provides status of the TS pin state for spins that have a TS pin.
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Register #7
Memory location: 06, Reset state: 1110 0000
BIT
B7(MSB)
B6
NAME
READ/WRITE
FUNCTION
VOVP_2
VOVP_1
VOVP_0
Read/Write
Read/Write
Read/Write
OVP voltage:
000 – 6.0V; 001 – 6.5V; 010 – 7.0V; 011 – 8.0V
100 – 9.0V; 101 – 9.5V; 110 – 10.0V; 111 –10.5V
B5
0 – Keep D+ voltage source on during DBP charging
1 – Turn off D+ voltage source to release D+ line
B4
B3
B2
CLR_VDP
Read/Write
Read/Write
Read/Write
0 – Enter the battery detection routine only if TERM is true or Force PTM is true
1 – Enter the battery detection routine
FORCE_BAT
DET
0 – PTM mode is disabled
1 – PTM mode is enabled
FORCE_PTM
B1
N/A
N/A
Read/Write
Read/Write
Not available. Keep set to 0.
Not available. Keep set to 0.
B0(LSB)
VOVP
Sets the OVP level
CLR_VDP
When the D+/D– detection has finished, some cases require the D+ pin to force a
voltage of 0.6V. This bit allows the system to clear the voltage prior to any
communication on the D+/D– pins. A ‘1’ clears the voltage at the D+ pin if present.
FORCE_BATDET
FORCE_PTM
Forces battery detection and provides status of the battery presence. A logic ‘1’
enables this function.
Puts the device in production test mode (PTM) where the input current limit is
disabled. Note that a battery must not be present prior to using this function.
Otherwise the function will not be allowed to execute. A logic ‘1’ enables the PTM
function
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9 Application and Implementation
9.1 Application Information
The bq24250C is a high-efficiency switch-mode charger. The device has integrated power FETs that are able to
charge at up to a 2-A charging rate, and an integrated 50-mA LDO. In I2C mode, the device has programmable
battery charge voltage (VBATREG), charge current (ICHG), input current limit (ILIM), and input over-voltage
protection threshold (VOVP). The charge current and the input current limit are programmed using external
resistors (RISET and RILIM) connected from the ISET and ILIM pins to ground. The range of these resistors can
be found in the datasheet. Both of these currents can be programmed up to 2 A. The device also has complete
system-level protection such as input under-voltage lockout (UVLO), input over-voltage protection (OVP), battery
OVP, sleep mode, thermal regulation and thermal shutdown, voltage-based NTC monitoring input, and safety
timers.
9.2 Typical Application
CPMID
1 µF
PMID
LO
1.0 PH
IN
SW
VIN
CIN
2.2 µF
System Load
R1
R2
CBOOT
33 nF
3 MHz
PWM
VDPM
LDO
BOOT
PGND
SYS
1 PF
22 ꢀF
Charge Controller
STAT
VGPIO
BAT
TS
1 ꢀF
LDO
R3
SCL
SCL
SDA
TEMP
PACK+
SDA
GPIO1
GPIO2
GPIO3
GPIO4
RNTC
R4
INT
/CE
EN1
EN2
Host
-
PACK
ILIM
ISET
Figure 27. bq24250C Typical Application Circuit
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Typical Application (continued)
9.2.1 Design Requirements
Use the following typical application design procedure to select external components values for the bq24250C
device.
Table 4. Design Parameters
SPECIFICATION
Input DC voltage, VIN
Input current
TEST CONDITION
Recommended input voltage range
Recommended input current range
Fast charge current range
MIN
TYP
MAX
10.5
2
UNIT
4.35
V
A
A
V
Charge current
0.5
3.5
2
Output regulation voltage
Standalone mode or I2C default mode
4.2
4.9
I2C host mode: operating in voltage regulation,
programmable range
Output regulation voltage
LDO
4.44
V
V
LDO output voltage
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The inductor selection depends on the application requirements. The bq24250C is designed to operate at around
1 µH. The value will have an effect on efficiency, and the ripple requirements, stability of the charger, package
size, and DCR of the inductor. The 1μH inductor provides a good tradeoff between size and efficiency and ripple.
Once the inductance has been selected, the peak current is needed in order to choose the saturation current
rating of the inductor. Make sure that the saturation current is always greater than or equal to the calculated
IPEAK. The following equation can be used to calculate the current ripple:
ΔIL = {VBAT (VIN – VBAT)}/(VIN x ƒs x L)
(6)
Then use current ripple to calculate the peak current as follows:
IPEAK = Load x (1 + ΔIL/2)
(7)
In this design example, the regulation voltage is set to 4.2V, the input voltage is 5V and the inductance is
selected to be 1µH. The maximum charge current that can be used in this application is 1A and can be set by
I2C command. The peak current is needed in order to choose the saturation current rating of the inductor. Using
equation 6 and 7, ΔIL is calculated to be 0.224A and the inductor peak current is 1.112A. A 1µF BAT cap is
needed and 22µF SYS cap is needed on the system trace.
The default settings for external fast charge current and external setting of current limit are chosen to be
IFC=500mA and ILIM=1A. RISET and RILIM need to be calculated using equation 1 and 2 in the data sheet.
The fast charge current resistor (RISET) can be set as follows:
RISET=250/0.5A=500Ω
The input current limit resistor (RILIM) can be set as follows:
RILIM= 270/1A=270Ω
The external settings of VIN_DPM can be designed by calculating R1 and R2 according to equation 3 in this data
sheet and the typical application circuit. VIN_DPM should be chosen first along with R1. VIN_DPM is chosen to
be 4.48V and R1 is set to 274KΩ in this design example. Using equation 3, the value of R2 is calculated to be
100KΩ.
In this design example, the application needs to be JEITA compliant. Thus, TCOLD must be 0°C and THOT must be
60°C. If an NTC resistor is chosen such that the beta is 4500K and the nominal resistance is 13KΩ, the
calculated R3 and R4 values are 5KΩ and 8.8KΩ respectively. These results are obtained from equation 4 and 5
in this data sheet.
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9.2.3 Application Curves
Figure 28. Startup
Figure 29. VDPM Startup, 4.2 V
Figure 31. 2A Load Step Transient
Figure 30. 1.0 µH CCM Operation
36
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bq24250C
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SLUSBY7 –JULY 2014
10 Power Supply Recommendations
The devices are designed to operate from an input voltage range between 4.35V and 10.5V. This input supply
must be well regulated. If the input supply is located more than a few inches from the bq24250C charger,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
1. Place the BOOT, PMID, IN, BAT, and LDO capacitors as close as possible to the IC for optimal performance.
2. Connect the inductor as close as possible to the SW pin, and the SYS cap as close as possible to the
inductor minimizing noise in the path.
3. Place a 1-μF PMID capacitor as close as possible to the PMID and PGND pins, making the high frequency
current loop area as small as possible.
4. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of the IC.
This minimizes the current path loop area from the SW pin through the LC filter and back to the PGND pin.
5. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do not
place components such that routing interrupts power-stage currents). All small control signals must be routed
away from the high-current paths.
6. To reduce noise coupling, use a ground plane if possible, to isolate the noisy traces from spreading its noise
all over the board. Put vias inside the PGND pads for the IC.
7. The high-current charge paths into IN, Micro-USB, BAT, SYS, and from the SW pins must be sized
appropriately for the maximum charge current to avoid voltage drops in these traces.
8. For high-current applications, the balls for the power paths must be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.
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11.2 Board Layout
Figure 32. Recommended bq24250C PCB Layout for WCSP Package
38
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11.3 Package Summary
YFF Package
(Top View)
YFF Package Symbol
(Top Side Symbol for bq24250C)
A1
B1
C1
D1
E1
F1
A2
B2
C2
D2
E2
F2
A3
B3
C3
D3
E3
F3
A4
A5
B5
C5
D5
E5
F5
B4
C4
D4
E4
F4
TI YMLLLLS
bq24250C
D
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
The bq24250C device is available in a 30-bump chip scale package (YFF, NanoFree™). The package
dimensions are:
D – 2.427mm ±0.035mm
E – 2.027mm ±0.035mm
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12 Device and Documentation Support
12.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ24250CYFFR
BQ24250CYFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
30
30
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ24250C
BQ24250C
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24250CYFFR
BQ24250CYFFT
DSBGA
DSBGA
YFF
YFF
30
30
3000
250
180.0
180.0
8.4
8.4
2.09
2.09
2.59
2.59
0.78
0.78
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24250CYFFR
BQ24250CYFFT
DSBGA
DSBGA
YFF
YFF
30
30
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0030
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
F
E
D: Max = 2.418 mm, Min =2.357 mm
E: Max = 2.018 mm, Min =1.957 mm
D
C
SYMM
2
TYP
B
A
0.4 TYP
1
2
4
5
3
0.3
30X
0.4 TYP
0.2
0.015
C A B
4219433/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
30X ( 0.23)
(0.4) TYP
2
4
5
1
A
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219433/A 03/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0030
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
30X ( 0.25)
(R0.05) TYP
1
3
2
4
5
A
B
(0.4)
TYP
METAL
TYP
C
D
E
F
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219433/A 03/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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