BQ24311 [TI]

过压和过流保护及锂离子电池充电器前端保护 IC;


型号：	BQ24311
厂家：	TEXAS INSTRUMENTS
描述：	过压和过流保护及锂离子电池充电器前端保护 IC 电池
文件：	总25页 (文件大小：1949K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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bq24311

ZHCSCP1 –JULY 2014

bq24311 过压和过流保护 IC 以及

锂电池充电器前端保护 IC

1 特性

•

针对三个变量提供保护：

3 说明

–

输入过压、快速响应小于 1μs

带有电流限制的用户可编程过流

电池过压

bq24311 是一个高度集成的电路，旨在保护锂离子电

池免受充电电路故障的影响。该 IC 可持续监视输入电

压、输入电流和电池电压。输入过压保护通过关断内

部开关立即停止为充电电路供电。输入保护可将系统

电流限制为用户可编程的值，如果过流情况仍存在，则

在一个消隐周期之后关断导通元件。此外，该 IC 还会

监控自身的芯片温度，并在过热时切断电源。

•

30V 最大输入电压

支持高达 0.3A 的输入电流

防止由电流瞬变造成的错误触发

过热保护

使能输入

该 IC 可由一个处理器控制并且可为主机提供关于故障

条件的状态信息。

状态指示

2 应用

器件信息

•

手机和智能电话

部件号

封装

封装尺寸（标称值）

bq24311

WSON (8)

2.00mm x 2.00mm

掌上电脑 (PDA)

MP3 播放器

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

低功耗手持器件

Bluetooth™ 耳机

4 应用信息

AC Adapter

VDC

OUT

1 mF

GND

bq24080

Charger IC

bq24311DSG

SYSTEM

VBAT

FAULT

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLUSBT8

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8.1 Overview ................................................................... 8

8.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 9

8.4 Device Functional Modes.......................................... 9

Application and Implementation ........................ 12

9.1 Typical Application Circuit....................................... 12

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

应用信息................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ..................................... 4

7.2 Handling Ratings....................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements................................................ 5

7.7 Typical Characteristics.............................................. 6

Detailed Description .............................................. 8

10 Power Supply Requirements ............................. 16

11 Layout................................................................... 17

11.1 Layout Guidelines ................................................. 17

11.2 Layout Example .................................................... 17

12 器件和文档支持 ..................................................... 18

12.1 Trademarks........................................................... 18

12.2 Electrostatic Discharge Caution............................ 18

12.3 术语表 ................................................................... 18

13 机械封装和可订购信息 .......................................... 18

5 修订历史记录

日期

修订版本

注释

6 月

最初发布。

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6 Pin Configuration and Functions

DSG PACKAGE

(TOP VIEW)

VSS

OUT

ILIM

VBAT

FAULT 4

Pin Functions

I/O

DESCRIPTION

NAME

DSG

Input power, connect to external DC supply. Connect external 1μF ceramic capacitor

(minimum) to VSS.

Output pin to the charging system. Connect external 1 μF ceramic capacitor (minimum) to

VSS.

OUT

VBAT

ILIM

I/O

Battery voltage sense input. Connect to pack positive pin through a resistor.

Input overcurrent threshold programming. Connect a resistor to VSS to set the overcurrent

threshold.

Chip enable input. Active low. When CE = High, the input FET is off. Internally pulled down.

Device status, open-drain output. FAULT = Low indicates that the input FET Q1 has been

turned on due to input overvoltage, input overcurrent, battery overvoltage, or thermal

shutdown.

FAULT

–

VSS

Ground pin

This pin may have internal circuits used for test purposes. Do not make any external

connections at these pins for normal operation.

There is an internal electrical connection between the exposed thermal pad and the VSS pin

of the device. The thermal pad must be connected to the same potential as the VSS pin on

the printed circuit board. Do not use the thermal pad as the primary ground input for the

device. The VSS pin must be connected to ground at all times.

Thermal PAD

–

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7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

–0.3

MAX

UNIT

IN (with respect to VSS)

Input voltage

OUT (with respect to VSS)

ILIM, FAULT, CE, VBAT (with respect to VSS)

Input current

0.5

Output current

OUT

FAULT

Output sink current

Junction temperature, T_J

°C

–40

150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

Electrostatic discharge

–65

150

°C

Human body model (HBM), per

–2000

2000

500

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_ESD

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins

–500

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_IN

I_IN

Input voltage range

300

500

125

Input current, IN pin

kΩ

I_OUT

R_ILIM

T_J

Output current, OUT pin

OCP Programming resistor

Junction temperature

83.3

–40

°C

7.4 Thermal Information

DSG

THERMAL METRIC⁽¹⁾

UNITS

8 PINS

86.3

116.9

56.1

8.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJCtop

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

56.4

25.9

R_θJCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

over junction temperature range –40°C to 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Undervoltage lock-out, input power

detected threshold

V_(UVLO)

CE = Low, V_INincreasing from 0 V to 3 V

CE = Low, V_INdecreasing from 3 V to 0 V

2.6

2.7

260

400

2.8

V_{(UVLO_HYS)}Hysteresis on UVLO

200

300 mV

CE = Low, No load on OUT pin,

V_IN= 5 V, R_(ILIM)= 200 kΩ

I_DD

Operating current

500

μA

I_(STDBY)

Standby current

CE = High, V_IN= 5 V

INPUT TO OUTPUT CHARACTERISTICS

V_(DO)Drop-out voltage IN to OUT

INPUT OVERVOLTAGE PROTECTION

CE = Low, V_IN= 5 V, I_OUT= 0.125 A

35 mV

V_(OVP)

Input overvoltage protection threshold CE = Low, V_INincreasing from 5V to 7.5 V

Hysteresis on OVP CE = Low, V_INdecreasing from 7.5 V to 5 V

5.71

5.85

6.00

V_HYS-OVP

110 mV

INPUT OVERCURRENT PROTECTION

Input overcurrent protection threshold

300 mA

range

I_(OCP)

CE = Low, R_ILIM= 200 kΩ,

3 V ≤ V_IN< V_OVP

T_J= 0°C to 85°C

T_J= 0°C to 125°C

110

125

135

140

Input overcurrent protection threshold

BATTERY OVERVOLTAGE PROTECTION

Battery overvoltage protection

threshold

V_(BOVP)

CE = Low, V_IN> 4.4 V

4.30

200

4.35

275

4.4

V_(HYS-BOVP)Hysteresis on V_(BOVP)

CE = Low, V_IN> 4.4 V

V_BAT= 4.4 V, T_J= 25°C

320 mV

I_(VBAT)

Input bias current on VBAT pin

THERMAL PROTECTION

T_J(OFF)

Thermal shutdown temperature

140

150

°C

T_J(OFF-HYS)Thermal shutdown hysteresis

LOGIC LEVELS ON CE

V_IL

V_IH

I_IL

Low-level input voltage

High-level input voltage

Low-level input current

High-level input current

0.4

1.4

V_CE= 0 V

μA

I_IH

V_CE= 1.8 V

LOGIC LEVELS ON FAULT

V_OL

Output low voltage

I_(SINK)= 5 mA

V_(FAULT)= 5 V

0.2

I_(HI-Z)

Leakage current, FAULT pin HI-Z

μA

7.6 Timing Requirements

MIN

TYP

MAX

UNIT

μs

CE = Low. Time measured from V_IN0 V → 5 V 1

μs rise-time, to output turning ON

t_DGL(PGOOD)

t_PD(OVP)

Deglitch time, input power detected status

Input OV propagation delay⁽¹⁾

CE = Low

Recovery time from input overvoltage

condition

CE = Low, Time measured from

V_IN7.5 V → 5 V, 1μs fall-time

t_ON(OVP)

176

μs

t_BLANK(OCP)

t_REC(OCP)

Blanking time, input overcurrent detected

Recovery time from input overcurrent

condition

CE = Low, V_IN> 4.4 V. Time measured from

V_(VBAT)rising from 4.1 V to 4.4 V to FAULT going

low.

t_DGL(BOVP)

Deglitch time, battery overvoltage detected

176

μs

(1) Not tested in production. Specified by design.

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7.7 Typical Characteristics

Test conditions (unless otherwise noted) for typical operating performance: V_IN= 5 V, C_IN= 1 μF, C_OUT= 1 μF,

R_(ILIM)= 200 kΩ, R_(BAT)= 100 kΩ, T_A= 25°C, V_(PU)= 3.3 V (see Figure 11 for the Typical Application Circuit)

2.75

V_IN= 5 V

V_IN= 4 V

2.7

V_INIncreasing

2.65

2.6

2.55

2.5

V_INDecreasing

2.45

2.4

-50

-30

-10

110

130

100

120

140

Temperature - °C

Temperature (qC)

D002

Figure 1. Undervoltage Lockout vs Free-Air Temperature

Figure 2. Dropout Voltage (In to Out) vs Free-Air

Temperature

5.88

350

300

250

200

150

100

5.86

5.84

5.82

V_INIncreasing

5.8

V_INDecreasing

5.78

100

200

300

400

500

600

-50

-30

-10

130

110

R_ILIM(k:)

Temperature - °C

D002

Figure 3. Overvoltage Threshold Protection vs Free-Air

Temperature

Figure 4. Input Overcurrent Protection vs ILIM Resistance

4.4

128

127

126

125

124

123

122

121

4.35

V_(BOVP)(V_VBATIncreasing)

4.3

4.25

4.2

4.15

Bat-OVP Recovery (V_VBATDecreasing)

4.1

4.05

-50

-30 -10

110 130

-50

100

150

Temperature (qC)

Temperature (^oC)

D002

Figure 6. Battery Overvoltage Protection vs Free-Air

Temperature

Figure 5. Input Overcurrent Protection vs Free-Air

Temperature

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Typical Characteristics (continued)

2.5

900

800

700

600

500

400

300

200

100

I_(DD(/CE = Low)

I_(STDBY(/CE = High)

1.5

0.5

-50

-30 -10

110 130

V_IN(V)

Temperature (^oC)

D002

Figure 7. Leakage Current (VBAT Pin) vs Free-Air

Temperature

Figure 8. Supply Current vs Input Voltage

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8 Detailed Description

8.1 Overview

The bq24311 is a highly integrated circuit designed to protect Li-ion batteries from charging circuit failures. The

IC continuously monitors the input voltage, input current, and battery voltage. The input overvoltage protection

immediately removes power from the charging circuit by turning off an internal switch. The input protection limits

the system current at the user-programmable value, and if the overcurrent persists, switches the pass element

OFF after a blanking period. Additionally, the IC also monitors its own die temperature and switches off if it

becomes too hot.

8.2 Functional Block Diagram

OUT

Charge Pump,

Bandgap,

Bias Gen

V_BG

SNS

ILIM

Current limiting

loop

ILIMREF

OFF

OCP comparator

ILIMREF- Δ

t_BLANK(OCP)

SNS

FAULT

COUNTERS,

CONTROL,

AND STATUS

OVP

t_DGL(PGOOD)

UVLO

VBAT

THERMAL

SHUTDOW

t_DGL(BOVP)

VSS

Figure 9. Simplified Block Diagram

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8.3 Feature Description

8.3.1 Power Down

The device remains in power down mode when the voltage at the IN pin is below the undervoltage threshold

V_UVLO. The FET Q1 connected between IN and OUT pins is off, and the status output, FAULT, is set to Hi-Z.

8.3.2 Power-On Reset

The device resets when the voltage at the IN pin exceeds the UVLO threshold. All internal counters and other

circuit blocks are reset. The IC then waits for duration t_DGL(PGOOD)for the input voltage to stabilize. If, after

t_DGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature

to control the inrush current which minimizes the ringing at input during power up, as shown in Figure 15 (ringing

occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant

circuit). Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold,

the device will not switch on at all, instead it will go into protection mode and indicate a fault on the FAULT pin,

as shown in Figure 16.

8.4 Device Functional Modes

8.4.1 Operation

The device continuously monitors the input voltage, input current, and battery voltage as described in detail in the

following sections.

8.4.1.1 Input Overvoltage Protection

If the input voltage rises above V_OVP, the internal FET Q1 is turned off, removing power from the circuit. As

shown in Figure 17, the response is rapid, with the FET turning off in less than a microsecond. The FAULT pin is

driven low. When the input voltage returns below V_OVP– V_HYS-OVP(but is still above V_UVLO), the FET Q1 is turned

on again after a deglitch time of t_ON(OVP)to ensure that the input supply has stabilized. Figure 18 shows the

recovery from input OVP.

8.4.1.2 Input Overcurrent Protection

If the load current tries to exceed the I_OCPthreshold, the device limits the current for a blanking period,

t_BLANK(OCP). If the load current returns to less than I_OCPbefore t_BLANK(OCP)times out, the device continues to

operate. However, if the overcurrent situation persists for t_BLANK(OCP), the FET Q1 is turned off for a duration of

t_REC(OCP), and the FAULT pin is driven low. The FET is then turned on again after t_REC(OCP)and the current is

monitored all over again. Each time an OCP fault occurs, an internal counter is incremented. If 15 OCP faults

occur in one charge cycle, the FET is turned off permanently, as shown in Figure 19. The counter is cleared

either by removing and re-applying input power, or by disabling and re-enabling the device with the CE pin.

Figure 19 and Figure 20 show what happens in an overcurrent fault.

To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is turned off slowly,

resulting in a “soft-stop”, as shown in Figure 22.

8.4.1.3 Battery Overvoltage Protection

The battery overvoltage threshold V_(BOVP)is internally set to 4.35V. If the battery voltage exceeds the V_(BOVP)

threshold, the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on once the battery

voltage drops to V_(BOVP)– V_HYS-BOVP(see Figure 22 and Figure 23). Each time a battery overvoltage fault occurs,

an internal counter is incremented. If 15 such faults occur in one charge cycle, the FET is turned off permanently,

as shown in Figure 23. The counter is cleared either by removing and re-applying input power, or by disabling

and re-enabling the device with the CE pin. In the case of a battery overvoltage fault, Q1 is switched OFF

gradually, resulting in a soft-stop (see Figure 22).

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Device Functional Modes (continued)

8.4.1.4 Thermal Protection

If the junction temperature of the device exceeds T_J(OFF), the FET Q1 is turned off, and the FAULT pin is driven

low. The FET is turned back on when the junction temperature falls below T_J(OFF)– T_J(OFF-HYS)

8.4.1.5 Enable Function

The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the

internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The OCP

counter and the Bat-OVP counter are both reset when the device is disabled and re-enabled. The CE pin has an

internal pulldown resistor and can be left floating. Note that the FAULT pin functionality is also disabled when the

CE pin is high.

8.4.1.6 Fault Indication

The FAULT pin is an active-low open-drain output. It is in a high-impedance state when operating conditions are

safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of

these events occurs:

•

Input overvoltage

Input overcurrent

Battery overvoltage

IC Overtemperature

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Device Functional Modes (continued)

Power Down

All IC functions OFF

FAULT = HiZ

Any State

if V(IN) < V (UVLO),

go to Power Down

V(IN) > V(UVLO) ?

Any State

if CE = Hi,

go to Reset

Yes

Reset

Timers reset

Counters reset

FAULT = HiZ

FET off

CE = Low ?

Turn off FET

FAULT = Low

V(IN) < V(OVP) ?

Yes

Go to Reset

CE = Hi ?

Yes

Turn off FET

FAULT = Low

Incr OCP counter

Wait t

REC(OCP)

I < IOCP ?

Yes

count <15?

Yes

Go to Reset

CE = Hi ?

Turn off FET

FAULT = Low

Incr BAT counter

< BATOVP ?

Yes

count <15?

BAT

< T

Turn off FET

FAULT = Low

J(OFF)

Yes

Turn on FET

FAULT = HiZ

Figure 10. Flow Diagram

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9 Application and Implementation

9.1 Typical Application Circuit

V_OVP= 5.85 V, I_OCP= 125 mA, V_(BOVP)= 4.35 V.

AC Adapter

VDC

GND

OUT

bq24080

Charger IC

1 mF

bq24311DSG

BAT

SYSTEM

VBAT

100 kW

47 kW

FAULT

Host

Controller

47 kW

ILM

200 kW

Figure 11.

9.1.1 Design Requirements

9.1.1.1 Selection of R_ILIM

The overcurrent threshold is programmed by a resistor, R_ILIM, connected from the ILIM pin to VSS. Figure 4

shows the OCP threshold as a function of R_ILIM, and may be approximated by the following equation:

I_OCP= 25 ÷ R_ILIM(current in A, resistance in kΩ)

(1)

Choose a I_OCPbetween 50 mA and 300 mA and apply the above equation to select a R_ILIMresistor value from

500 kΩ to 83.3 kΩ respectively. However, at lower OCP limits, approaching 50 mA, the precision of the current

protection circuit decreases the achievable accuracy of the OCP threshold.

9.1.1.2 Selection of R_BAT

It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some

failure modes of the IC, the voltage at the IN pin may appear on the VBAT pin. This voltage can be as high as 30

V, and applying 30 V to the battery in case of the failure of the bq24311 can be hazardous. Connecting the VBAT

pin through R_(BAT)prevents a large current from flowing into the battery in case of a failure of the IC. In the

interests of safety, R_BATshould have a high value. The problem with a large R_(BAT)is that the voltage drop across

this resistor because of the VBAT bias current I_(VBAT)causes an error in the V_(BOVP)threshold. This error is over

and above the tolerance on the nominal 4.35V V_(BOVP)threshold.

Choosing R_BATin the range 100 kΩ to 470 kΩ is a good compromise. In the case of an IC failure, with R_BAT

equal to 100kΩ, the maximum current flowing into the battery would be (30 V – 3 V) ÷ 100 kΩ = 246 μA, which is

low enough to be absorbed by the bias currents of the system components. R_(BAT)equal to 100 kΩ would result

in a worst-case voltage drop of R_(BAT)× I_(VBAT)= 1 mV. This is negligible to compared to the internal tolerance of

50mV on V_(BOVP)threshold.

If the Bat-OVP function is not required, the VBAT pin should be connected to VSS.

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ZHCSCP1 –JULY 2014

Typical Application Circuit (continued)

9.1.1.3 Selection of R_(CE), R_(FAULT), and R_(PU)

The CE pin can be used to enable and disable the IC. If host control is not required, the CE pin can be tied to

ground or left un-connected, permanently enabling the device.

In applications where external control is required, the CE pin can be controlled by a host processor. As in the

case of the VBAT pin (see Selection of Rbat), the CE pin should be connected to the host GPIO pin through as

large a resistor as possible. The limitation on the resistor value is that the minimum V_OHof the host GPIO pin

less the drop across the resistor should be greater than V_IHof the bq24311 CE pin. The drop across the resistor

is given by R_(CE)× I_IH.

The FAULT pin is an open-drain output that goes low during OV, OC, battery-OV, and OT events. If the

application does not require monitoring of the FAULT pin, it can be left unconnected. But if the FAULT pin has to

be monitored, it should be pulled high externally through R_(PU), and connected through R_(FAULT)to the host.

R_(FAULT)prevents damage to the host controller if the bq24311 fails (see Selection of Rbat). The resistors should

be of high value, in practice values between 22 kΩ and 100 kΩ should be sufficient.

9.1.1.4 Selection of Input and Output Bypass Capacitors

The input capacitor C_INin Figure 11 is for decoupling, and serves an important purpose. Whenever there is a

step change downwards in the system load current, the inductance of the input cable causes the input voltage to

spike up. C_INprevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a

ceramic capacitor of at least 1μF be used at the input of the device. It should be located in close proximity to the

IN pin.

C_OUTin Figure 11 is also important: If a fast (< 1 μs rise time) overvoltage transient occurs at the input, the

current that charges C_OUTcauses the device’s current-limiting loop to kick in, reducing the gate-drive to FET Q1.

This results in improved performance for input overvoltage protection. C_OUTshould also be a ceramic capacitor of

at least 1 μF, located close to the OUT pin. C_OUTalso serves as the input decoupling capacitor for the charging

circuit downstream of the protection IC.

9.1.2 Detailed Design Procedures

9.1.2.1 Powering Accessories

In some applications, the equipment that the protection IC resides in may be required to provide power to an

accessory (that is, a cellphone may power a headset or an external memory card) through the same connector

pins that are used by the adapter for charging. Figure 12 and Figure 13 illustrate typical charging and accessory-

powering scenarios:

that is,

cellphone

DIS

Accessory

power supply

to rest of

OUT

bq24311

system

AC Adapter

Charger

Battery

pack

Figure 12. Charging - The Red Arrows Show the Direction of Current Flow

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Typical Application Circuit (continued)

that is,

cellphone

Accessory

power supply

to rest of

system

OUT

Charger

Battery

pack

bq24311

DIS

Figure 13. Powering an Accessory - The Red Arrows Show the Direction of Current Flow

In the second case, when power is being delivered to an accessory, the bq24311 device is required to support

current flow from the OUT pin to the IN pin.

If V_OUT> V_(UVLO)+ 0.7 V, FET Q1 is turned on, and the reverse current does not flow through the diode but

through Q1. Q1 will then remain ON as long as V_OUT> V_(UVLO)– V_(HYS-UVLO)+ R_DS(on)x I_(ACCESSORY). Within this

voltage range, the reverse current capability is the same as the forward capability, 0.5 A. It should be noted that

there is no overcurrent protection in this direction.

OUT

Charge Pump,

Bandgap,

Bias Gen

Figure 14.

bq24311

www.ti.com.cn

ZHCSCP1 –JULY 2014

Typical Application Circuit (continued)

9.1.3 Application Curves

V(IN)

V(OUT)

FAULT

I(OUT)

Time 2 ms/div

V_IN= 0 V to 10 V

t_r= 50 μs

R_OUT= 50 Ω

Figure 16. OVP at Power-On

Figure 15. Normal Power-On Showing Soft-Start

V(IN)

V(OUT)

I(OUT)

V(OUT)

FAULT

Time 2 ms/div

Time 20 ms/div

V_IN= 15 V to 5 V

t_r= 400 μs

V_IN= 5 V to 12 V

t_r= 20 μs

Figure 18. Recovery from OVP

Figure 17. OVP Response for Input Step

V(IN)

V(OUT)

I(OUT)

FAULT

V(OUT)

I(OUT)

FAULT

Time 2 ms/div

Time 200 ms/div

OCP Counter Counts to 15 Before Switching OFF the Device

Figure 20. OCP, Zoom-in on the First Cycle of Figure 19

Figure 19. OCP, Powering Up into a Short Circuit on OUT

bq24311

ZHCSCP1 –JULY 2014

www.ti.com.cn

Typical Application Circuit (continued)

V(IN)

V(BAT)

V(OUT)

I(OUT)

FAULT

Time 100 ms/div

Time 2 ms/div

Figure 22. BAT-OVP, V_(VBAT)Steps from 4.3 V to 4.4 V,

Shows t_DGL(BAT-OVP)and Soft-Stop

Figure 21. OCP, R_OUTSwitches from 130 Ω to 30 Ω, Shows

Current Limiting and Soft-Stop

V(OUT)

V(BAT)

FAULT

Time 100 ms/div

Figure 23. BAT-OVP, V_(VBAT)Steps from 3.9V to 4.4V,

Shows BAT-OVP Counter

10 Power Supply Requirements

In a typical application, the system is powered by a USB port or USB wall adapter.

The minimum input voltage, where the protector starts to pass current assuming V_BATis acceptable, could be

2.7 V. The maximum supported input voltage is up to 5.85 V; the overvoltage protection kicks in at 5.85 V and

the maximum input voltage rating is 30 V input rating.

bq24311

www.ti.com.cn

ZHCSCP1 –JULY 2014

11 Layout

11.1 Layout Guidelines

•

This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages.

Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of

PCB traces satisfy the design rules for high voltages.

The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should

be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly

under the IC. This copper pad should be connected to the ground plane with an array of thermal vias.

C_INand C_OUTshould be located close to the IC. Other components like R_ILIMand R_BATshould also be located

close to the IC.

11.2 Layout Example

bq24311

ZHCSCP1 –JULY 2014

www.ti.com.cn

12 器件和文档支持

12.1 Trademarks

PowerPAD is a trademark of Texas Instruments.

Bluetooth is a trademark of Bluetooth SIG, Inc.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

19-Nov-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ24311DSGR

BQ24311DSGT

ACTIVE

WSON

DSG

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

SHN

Samples

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

19-Nov-2022

Addendum-Page 2

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

0.32

0.18

PIN 1 INDEX AREA

2.1

1.9

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8

0.7

SEATING PLANE

0.05

0.00

SIDE WALL

0.08 C

METAL THICKNESS

DIM A

OPTION 1

0.1

OPTION 2

0.2

EXPOSED

THERMAL PAD

(DIM A) TYP

0.9 0.1

6X 0.5

1.5

1.6 0.1

0.32

0.18

PIN 1 ID

(45 X 0.25)

0.4

0.2

0.1

C A B

0.05

4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

8X (0.25)

(0.55)

SYMM

(1.6)

6X (0.5)

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

SYMM

8X (0.25)

(0.45)

SYMM

(0.7)

6X (0.5)

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

BQ24311 [TI]

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