BQ24351 [TI]
Over-Voltage and Over-Current Charger; 过电压和过电流充电器
| 型号： | BQ24351 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Over-Voltage and Over-Current Charger |
| 文件： | 总18页 (文件大小：1534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24351
www.ti.com
SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
Over-Voltage and Over-Current Charger
Protection IC With Integrated Charging FET and LDO Mode
Check for Samples: bq24351
1
FEATURES
Controller
2
•
Robust Protection
•
•
•
•
•
Soft-Start to Prevent Inrush Currents
Soft-Stop to Prevent Voltage Spikes
30V Maximum Input Voltage
–
–
–
–
–
Input Over-Voltage Protection
Input Over-Current Protection
Accurate Battery Over-Voltage Protection
Thermal Shutdown
Supports Up to 1A Load Current
Small 2mm × 2mm 8pin SON Package
Output Short-Circuit Protection
APPLICATIONS
•
•
•
•
•
Integrated Charging FET
10.5V Over-Voltage Protection
LDO Mode Operation
Mobile Phones
Low-Power Handheld Devices
–
6.38V Output Voltage Regulation
•
Current Limited Power Supply for Host
DESCRIPTION
The bq24351 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the
charging circuit. The IC continuously monitors the input voltage and the battery voltage. In case of an input
over-voltage condition, the IC will turn off the internal power FET after a blanking time. If the battery voltage rises
to unsafe levels during charging process, power is removed from the system. If the input current exceeds the
over current threshold for a limited time, the IC will turn off the output power. The integrated charging FET can
regulate the charge voltage and current according to the control from the host. The device can also provide a
voltage source with over voltage and over current protection for host controller.
WHITE SPACE
WHITE SPACE
TYPICAL APPLICATION CIRCUIT
WHITE SPACE
PIN ASSIGNMENT
WHITE SPACE
Analog
Base Band
Chip
bq24351
CHGIN
1
2
8
7
OUT
OUT
ACIN
ACIN
GND
VBAT
ACIN
AC
CHGIN
C
C
CHGIN
ACIN
Q1
1 mF
1 mF
3
4
6
5
CHGIN
GATDRV
OUT
Q2
GATDRV
ISENS
GATDRV
0.2 W
R
GND
BAT
VBAT
VBAT
200 kW
PACK+
PACK-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
bq24351
SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Q 2
Q 1
V
V
OUT
ACIN
ACIN
OUT
IIN
Protection &
+
-
Gate Control
IO(OCP)
INPUT UVLO
tBLK ( CHGIN)
V
+
-
ACIN
V
UVLO
V
CHGIN
+
-
INPUT OVP
tDGL(OVP )
GND
CHGIN
V
+
-
ACIN
V
OREG
500 W
Control
L ogic
V
OVP
CHGIN Discharge
V
+
-
ACIN
SLEEP
VOUT
Battery OVP
tDGL (BOVP )
Protection
Control
VBAT
+
-
BV
OVP
GATDRV
VBAT
Thermal
Shutdown
V
BAT
PIN FUNCTIONS
PIN
NAME
ACIN
I/O
DESCRIPTION
NO.
1,2
I
Power Supply Input, connect to an external DC supply. Connect an external 1-mF ceramic capacitor
(minimum) to GND.
OUT
VBAT
7,8
4
O
I
Output terminal to the charging system.
Battery voltage sense input. Connected to pack positive terminal through a resistor. Connected to ground if
battery OVP function is not used.
GATDRV
CHGIN
5
6
I
P-FET gate drive input , connected to gate drive pin of the host charger controller
O
Output power pin for power input of host charger controller. Connect an external ceramic bypass capacitor
(1.0-mF minimum) to GND.
GND
3
–
Ground terminal
Thermal PAD
There is an internal electrical connection between the exposed thermal pad and the GND pin of the device.
The thermal pad must be connected to the same potential as the GND pin on the printed circuit board. Do not
use the thermal pad as the primary ground input for the device. GND pin must be connected to ground at all
times.
ORDERING INFORMATION(1)
INPUT OVP
THRESHOLD
PART NUMBER
MARKING
MEDIUM
QUANTITY
PACKAGE
bq24351DSGR
bq24351DSGT
QUO
QUO
Tape and Reel
Tape and Reel
3000
250
2mm × 2mm SON
2mm × 2mm SON
10.5 V
10.5 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
2
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SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
–0.3 V to 30 V
–0.3 V to 7V
Input voltage
Output voltage
Input voltage
Input current
ACIN (with respect to GND)
OUT, CHGIN (with respect to GND)
VBAT, GATDRV (with respect to GND)
ACIN
–0.3 V to 7 V
–1.8 A(2) to 1.4 A
–40°C to 150°C
–65°C to 150°C
Junction temperature, TJ
Storage temperature, TSTG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
(2) Reverse current is specified for a maximum of 50 hours at TJ < 150°C.
THERMAL INFORMATION
bq24351
THERMAL METRIC(1)
SON
8 PINS
61.8
61.3
15.4
0.4
UNITS
qJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
qJCtop
qJB
°C/W
yJT
yJB
15.4
8.6
qJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNITS
VACIN
IACIN
TJ
ACIN voltage range
Current, ACIN pin
Junction temperature
4.4
15
1
V
A
–40
125
°C
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SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
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ELECTRICAL CHARACTERISTICS
Refer to the typical application circuit shown in Figure 1 . These specifications apply over ACIN = 5V, TJ = -40 to 125°C,
unless otherwise specified. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
ACIN
ACIN: 3V → 2V, ACIN falling
1.8 1.95
2.1
VUVLO
Under-voltage lock-out threshold
V
ACIN: 2V → 3V, ACIN rising
ACIN rising to CHGIN rising
No load on OUT and CHGIN pin
2.5
10
tBLK(CHGIN) Input power on blanking time
IDD Operating current
ms
500
mA
INPUT TO OUTPUT CHARACTERISTICS
On resistance from ACIN to OUT
IOUT = 1.0A, ACIN = 5V, GATDRV = 0V
ICHGIN = 1.0A, ACIN = 5V, IOUT = 0A
415 685
250 495
mΩ
mΩ
On resistance from ACIN to CHGIN
INPUT OVER-VOLTAGE PROTECTION (OVP)
ACIN = 7.1V, GATDRV = CHGIN, ICHGIN = 0 to
1A
VOREG
CHGIN voltage in LDO mode
6.25 6.38 6.52
V
VOVP
Input OVP threshold
ACIN rising
10.2 10.5 10.8
V
VHYS-OVP
tDGL(OVP)
tREC(OVP)
Input OVP recovery hysteresis
Input OVP deglitch time
Input OVP recovery time
ACIN: 12V → 9V
145 160 175
mV
mS
ms
ACIN rising to CHGIN falling
ACIN falling below VOVP to CHGIN rising
256
8.2
INPUT OVER CURRENT LIMITING AND PROTECTION (OCP)
IO(OCP)
OCP threshold
1.02
1.2 1.38
176
A
tDGL(OCP)
tREC(OCP)
OCP blanking time
OCP recovery time
µs
ms
131
BATTERY OVER-VOLTAGE PROTECTION
BVOVP Battery OVP threshold
VHYS-BOVP Battery OVP hysteresis
VBAT rising
VBAT falling
4.3 4.35
4.4
V
200 250 300
mV
VBAT = 4.25V, series connection of a 200-kΩ
resistor, TJ = 25°C
IVBAT
VBAT pin leakage current
10
nA
tDGL(BOVP) Battery OVP deglitch time
tREC(BOVP) Battery OVP recovery time
CHGIN
VBAT rising to CHGIN falling
8.2
ms
ms
VBAT falling below BVOVP to CHGIN rising
131
Sleep mode exit threshold and CHGIN turn
on threshold, ACIN-OUT
VSEXIT
ACIN rising, OUT = 4.2 V
ACIN falling, OUT = 4.2 V
24
10
90 160
55 105
10
mV
mV
Sleep mode entry threshold and CHGIN
turn off threshold, ACIN-OUT
VSENTRY
OUT = 4.2 V, GATDRV = 4.2 V,
ACIN = VSS
IDDSLP
RDIS
Sleep mode supply current
mA
Ω
CHGIN discharge resistor
500
OUT = 4.2 V, GATDRV = 4.2 V, CHGIN = 0 V,
ACIN = 0 V, TJ = 85°C
Leakage current from OUT to CHGIN
1
mA
INTEGRATED P-FET PARAMETERS
Vt
Threshold voltage, CHGIN-GATDRV
CHGIN = 5V, OUT = 3.6V, IOUT = 10mA
500 680 800
mV
mA
mA
Ig
GATDRV pin leakage current
0.1
1
1
Ioff
Off state leakage current at OUT pin
ACIN = 5V, GATDRV = CHGIN, OUT = 0V
IOUT = 1.0A, ACIN = 5V, GATDRV = 0V
On resistance of P-FET (from CHGIN to
OUT)
Ronp
165 225
mΩ
Gm
Cg
Forward transconductance
ACIN = 5V, IOUT = 5mA, GATDRV = 3.5V
CHGIN = GATDRV = 5V
27
mA/V
pF
Input capacitance at the GATDRV pin
104
THERMAL PROTECTION
TJ(OFF)
Thermal shutdown threshold
Junction temperature rising
Junction temperature falling
140 150 160
20
°C
°C
TJ(OFF-HYS) Thermal shutdown hysteresis
4
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SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
TYPICAL APPLICATION CIRCUIT
ACIN = 5V, ICHARGE = 1A, VBAT = 4.2V
Analog
Base Band
Chip
bq24351
ACIN
CHGIN
AC
CHGIN
C
C
ACIN
Q1
CHGIN
1 mF
1 mF
GATDRV
OUT
Q2
GATDRV
ISENS
0.2 W
R
GND
BAT
VBAT
VBAT
200 kW
PACK+
PACK-
Figure 1. Host Controlled One-Cell Charger Application Circuit
TYPICAL PERFORMANCE CHARACTERISTICS
Using circuit shown in typical application circuit Figure 1, TA = 25°C, unless otherwise specified.
ACIN RAMP UP
ACIN RAMP DOWN
GATDRV 2 V/div
ACIN 2 V/div
CHGIN Pull Down
CHGIN 2 V/div
ACIN 2 V/div
Soft-Start
Soft-Stop
VACIN = 5.2 V, CHGIN = 4.5 V, ICHG = 0.6 A,
VGATDRV = 3.5 V, VBAT = 3.4 V
CHGIN 2 V/div
I
0.5 A/div
ACIN
I
0.5 A/div
ACIN
VACIN = 5.2 V, CHGIN = 4.5 V, ICHG = 0.6 A,
VGATDRV = 3.5 V, VBAT = 3.4 V
Time: 2 mS/div
Time: 1 mS/div
Figure 2.
Figure 3.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
ACIN OVP (BLANKING TIME)
ACIN OVP
16 V
16 V
ACIN 5 V/div
ACIN 5 V/div
CHGIN 1 V/div
CHGIN 1 V/div
5 V
5 V
6.5 V
6.5 V
VACIN = 5 to 16 V, Rise Time 0.5 ms
VACIN = 5 to 16 V, Rise Time 0.5 ms
ICHGIN 0.1 A/div
ICHGIN 0.1 A/div
Figure 4.
Figure 5.
ACIN OVP
CHGIN OCP
ACIN 5 V/div
VACIN = 5 V, ICHGIN = 0 to 1.3 A
CHGIN 2 V/div
VACIN = 5 to 16 V, Rise Time 0.5 ms
ICHGIN 2 V/div
I
0.5 A/div
CHGIN
1.3 A
CHGIN 2 V/div
ICHGIN 0.1 A/div
Time: 100 mS/div
Figure 6.
Figure 7.
CHGIN OCP
BATTERY OVP
Connect 3 W Load
VACIN = 5 V, ICHGIN = 0 to1.3 A
VBAT 2 V/div
CHGIN 2 V/div
VACIN = 5 V, VBAT = 3.4 V to 5 V
CHGIN 2 V/div
ICHGIN 0.5 A/div
ICHGIN 0.1 A/div
Time: 100 mS/div
Time: 50 mS/div
Figure 8.
Figure 9.
6
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SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
BATTERY OVP
Rdson vs Vgs
10000
VBAT 2 V/div
VACIN = 5 V, VBAT = 3.4 V to 5 V
1000
CHGIN 2 V/div
VCHGIN = 5 V,
V
100
10
1
-V = 200 mV
OUT
CHGIN
IACIN 0.5 A/div
Q2
Time: 2 mS/div
0.1
0
1000
2000
3000
4000
5000
Vgs - Vchgin-Vgatdrv - mV
Figure 10.
Figure 11.
FET ON RESISTANCE vs TEMPERATURE
600
550
500
450
Q1 +Q2
400
350
300
Q1
Q2
250
200
150
100
-50
0
50
100
150
T
- Junction Temperature - °C
J
Figure 12.
BACKGROUND
During the charging process for portable devices, input voltage spikes usually happen when the AC/DC adaptor
is plugged in, or charge current is cut off quickly under fault conditions, such as input OVP, OCP, or battery OVP
and so on. The over voltage stress may damage the analog baseband chip which has lower voltage rating due to
its increased complexity. Therefore, over voltage protection is needed for the safe operation of portable devices.
Another challenge arises from the charge circuit that uses external charging FET in series with a reverse
blocking diode as the charging device. The battery may not be fully charged when input voltage is low due to the
additional diode voltage drop. bq24351 will provide the solution for above problems since it has input OVP, OCP,
battery OVP function, together with integrated charging FET which will eliminate the reverse blocking diode in the
previously mentioned charge circuit, as shown in Figure 1.
DETAILED FUNCTIONAL DESCRIPTION
The bq24351 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the
charging circuit. The IC continuously monitors the input voltage and the battery voltage. In case of an input
over-voltage condition, the IC will turn off the internal power FET after a blanking time. If the battery voltage rises
to unsafe levels during charging process, power is removed from the system. If the input current exceeds the
over current threshold for a limited time, the IC will turn off the output power. The integrated charging FET can
regulate the charge voltage and current according to the control from the host. The device can also provide a
voltage source with over-voltage and over-current protection for host controller.
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POWER DOWN
The device remains in power down mode when the input voltage at the ACIN pin is below the under-voltage
threshold VUVLO. The FET Q1 and Q2 connected between ACIN and OUT pins are off.
POWER-ON RESET
The device resets when the input voltage at the ACIN pin exceeds the UVLO threshold. All internal counters and
other circuit blocks are reset. The IC then waits for duration tBLK(CHGIN) for the input voltage to stabilize. If, after
tBLK(CHGIN), the input voltage and battery voltage are in normal range, FET Q1 is turned ON. The IC has a
soft-start feature to control the inrush current. The soft-start minimizes the ringing at the input, where the ringing
occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant
circuit. Once the soft-start sequence starts, the IC monitors the load current. If the load current is larger than
IO(OCP) for more than tDGL(OCP), FET Q1 and Q2 are switched off. The IC then repeats the power-on sequence
after tREC(OCP)
.
When a short-circuit is detected at power-on and Q1 is switched off, to prevent the input voltage from spiking up
due to resonance between the inductance of the input cable and the input capacitor, Q1 is turned off slowly by
reducing its gate-drive gradually, resulting in a “soft-stop”.
SLEEP MODE
When ACIN falls to below sleep mode entry threshold (VSENTRY), the device operates in sleep mode and turns off
Q1 and Q2 by internal circuit regardless of the gate drive signal from GARDRV pin. The device exits sleep mode
when ACIN rising to above sleep mode exit threshold (VSEXIT). In this way, the device behaves like a diode and
no external reverse blocking diode is needed in the application circuit.
OPERATING
The device continuously monitors the input voltage, the input current and the battery voltage as described in
detail below:
Input Over-Voltage Protection and LDO Mode Operation
The CHGIN output of the IC operates similar to a linear regulator. Figure 13 shows the typical input OVP
performance. When the ACIN input voltage is less than VO(REG), and above the VUVLO, the CHGIN output voltage
tracks the input voltage with a voltage drop caused by RDS(on) of the protection FET Q1. When the ACIN input
voltage is greater than VO(REG) plus the RDS(on) drop of Q1, and less than VOVP, the CHGIN output voltage is
regulated to VO(REG), and this is also referred as LDO mode operation. If the input voltage rises above VOVP, the
internal FET Q1 and Q2 are turned off after a blanking time of tDGL(OVP), removing power from the circuit. When
the input voltage drops below VOVP – VHYS-OVP, and is still above VUVLO, the FET Q1 and Q2 are turned on again
after a deglitch time of tREC(OVP) , which ensures that the input supply is stabilized when the IC starts up again.
V
>V
IN OREG
V
<V
IN OREG
V
OVP
V
POR
ACIN
V
O(REG)
CHGIN
t
t
DGL(OVP)
t
REC(OVP)
BLK(CHGIN)
ACIN OVP
Figure 13. Input OVP Timing Diagram
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SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
Over Current Limiting and Protection
The device includes a low drop out linear regulator. This current regulator uses Q1 as the controlling power
device. Once the soft start sequence starts, the input current is limited to the Over Current Protection (OCP)
threshold, IO(OCP). If the input current through the IC attempts to exceed the OCP threshold, the switch Q1 is
opened only enough to maintain the current at the OCP level. Once the soft start sequence ends, the input
current is no longer limited and can go beyond the OCP threshold. However, if the current remains above the
OCP threshold for longer than the deglitch period, tDGL(OCP), both the switch Q1 and Q2 are opened completely,
as shown in Figure 14. In this fault case, the switch Q1 is turned off slowly, typically taking 100 µS.
Once the OCP feature has been activated, the switch Q1 and Q2 will remain off for the OCP recovery time,
tREC(OCP). Following this time the switch will turn on, using the soft start sequence. If the current through the IC
remains below the OCP threshold, the switch will remain closed and normal operation resumes. If the current
through the IC attempts to exceed the OCP threshold again, the operation described above repeats.
IACIN
OCP
Threshold
Threshold
OCP
CHGIN
Soft Start
Control by
GATDRV
VOUT
t
t
t
t
DGL(OCP)
DGL(OCP) REC(OCP)
REC(OCP)
Figure 14. Charge Current OCP Timing Diagram
Battery Over-Voltage Protection
The battery over-voltage threshold, BVOVP, is internally set to 4.35V. If the battery voltage exceeds the BVOVP
threshold, the FET Q1 and Q2 are turned off after a deglitch time of tDGL(BOVP). The FET is turned on once the
battery voltage drops to BVOVP – VHYS-BOVP and remains below this threshold for tREC(BOVP), as shown in
Figure 15. In this battery over-voltage fault case, Q1 is switched OFF gradually for a smooth transient response.
V
BAT
VBAT
OVP
CHGIN
t
t
t
REC(BOVP)
t
DGL(BOVP)
REC(BOVP)
DGL(BOVP)
Figure 15. Battery OVP Timing Diagram
Thermal Protection
If the junction temperature of the device exceeds TJ(OFF), the FET Q1 and Q2 are turned off. The FET is turned
back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS)
.
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APPLICATION INFORMATION
Selection of RBAT
It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some
failure modes of the IC, the voltage at the ACIN pin may appear on the VBAT pin. This voltage can be as high as
30V, and applying 30V to the battery in case of the failure of the device can be hazardous. Connecting the VBAT
pin through RBAT prevents a large current from flowing into the battery in case of failure of the IC. In the interests
of safety, RBAT should have a very high value. The problem with a large RBAT is that the voltage drop across this
resistor because of the VBAT bias current IVBAT causes an error in the BVOVP threshold. This error is over and
above the tolerance on the nominal 4.35V BVOVP threshold.
Choosing RBAT in the range 100kΩ to 470kΩ is a good compromise. In the case of IC failure, with RBAT equal to
100kΩ, the maximum current flowing into the battery would be (30V – 3V) ÷ 100kΩ = 270mA, which is low
enough to be absorbed by the bias currents of the system components. RBAT equal to 100kΩ would result in a
worst-case voltage drop of RBAT × IVBAT ≉ 1mV. This is negligible compared to the internal tolerance of 50mV on
the BVOVP threshold.
If the Battery OVP function is not required, the VBAT pin should be connected to GND.
Selection of Input and Output Bypass Capacitors
The input capacitor CACIN is for decoupling, and serves an important purpose. Whenever there is a step change
downwards in the system load current, the inductance of the input cable causes the input voltage to spike up.
CACIN prevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a
ceramic capacitor of at least 1mF be used at the input of the device. It should be located in close proximity to the
ACIN pin.
CCHGIN should also be a ceramic capacitor of at least 1mF, located close to the CHGIN pin. CCHGIN also serves as
the input decoupling capacitor for the charging circuit downstream of the protection IC.
PCB Layout Guidelines
1. This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages.
Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of
PCB traces satisfy the design rules for the maximum voltages expected to be seen in the system.
2. The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should
be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly
under the IC. This copper pad should be connected to the ground plane with an array of thermal vias.
3. CACIN and CCHGIN should be located close to the IC. Other components like RBAT should also be located close
to the IC.
10
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24351
bq24351
SLUSA62A –OCTOBER 2010–REVISED NOVEMBER 2010
Page
www.ti.com
Changes from Original (October 2010) to Revision A
•
Changed title from: Over-Voltage and Over-Current Charger Front-End Protection IC With Integrated Charging FET,
to: Over-Voltage and Over-Current Charger Protection IC With Integrated Charging FET and LDO Mode ........................ 1
•
•
Added 10.5V Over-Voltage Protection to Features .............................................................................................................. 1
Added 6.38V Output Voltage Regulation to Features .......................................................................................................... 1
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): bq24351
PACKAGE OPTION ADDENDUM
www.ti.com
23-Oct-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ24351DSGR
BQ24351DSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24351DSGR
BQ24351DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
179.0
179.0
8.4
8.4
2.2
2.2
2.2
2.2
1.2
1.2
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Oct-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24351DSGR
BQ24351DSGT
WSON
WSON
DSG
DSG
8
8
3000
250
195.0
195.0
200.0
200.0
45.0
45.0
Pack Materials-Page 2
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