BQ24630_技术文档

bq24630

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SLUS894 –JANUARY 2010

Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with System

Power Selector and Low I_q

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1

FEATURES

•

24-Pin 4×4-mm²QFN Package

•

300 kHz NMOS-NMOS Synchronous Buck

Converter

Energy Star Low Quiescent Current I_q

–

< 15 mA Off-State Battery Discharge current

Stand-alone Charger Specifically for Lithium

Phosphate

< 1.5 mA Off-State Input Quiescent Current

5V–28V VCC Input Operating Range, Support

1-7 Battery Cells

APPLICATIONS

•

Power Tool and Portable Equipment

Personal Digital Assistants

Handheld Terminals

Industrial and Medical Equipment

Netbook, Mobile Internet Device and

Ultra-Mobile PC

High-Accuracy Voltage and Current Regulation

–

±0.5% Charge Voltage Accuracy

±3% Charge Current Accuracy

±3% Adapter Current Accuracy

•

Integration

–

Automatic System Power Selection from

DESCRIPTION

Adapter or Battery

The bq24630 is highly integrated switch-mode battery

charge controller designed specifically for Lithium

Phosphate battery. It offers a constant-frequency

synchronous PWM controller with high accuracy

current

preconditioning,

–

Internal Loop Compensation

Internal Soft Start

Dynamic Power Management (DPM)

and

voltage

termination,

regulation,

adapter

charge

current

Safety Protection

–

Input Over-Voltage Protection

regulation, and charge status monitoring.

Battery Thermistor Sense Suspend Charge

at Hot/Cold and Automatically I_CHARGE/8 at

Hot/Cold or Warm/Cool

The bq24630 charges the battery in three phases:

preconditioning, constant current, and constant

voltage. Charge is terminated when the current

reaches

a

minimum user-selectable level.

A

–

Battery Detection

programmable charge timer provides

a

safety

Reverse Protection Input FET

Programmable Safety Timer

Charge Over-Current Protection

Battery Short Protection

Battery Over-Voltage Protection

Thermal Shutdown

backup. The bq24630 automatically restarts the

charge cycle if the battery voltage falls below an

internal threshold, and enters a low-quiescent current

sleep mode when the input voltage falls below the

battery voltage.

PACKAGE AND PINOUT

•

Status Outputs

–

Adapter Present

24

23

22

21

20

19

Charger Operation Status

18

17

1

2

ACN

ACP

REGN

GND

•

Charge Enable Pin

OAT

(bq24630)

QFN-24

ACDRV

16

15

14

13

3

4

5

6

ACSET

ISET 2

SRP

6V Gate Drive for Synchronous Buck

Converter

CE

STAT1

TS

•

30ns Driver Dead-time and 99.95% Max

Effective Duty Cycle

SRN

7

8

9

10

11

12

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24630

SLUS894 –JANUARY 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The bq24630 controls external switches to prevent battery discharge back to the input, connect the adapter to

the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. The

bq24630 features Dynamic Power Management (DPM). These features reduce battery charge current when the

input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger

simultaneously. A highly-accurate current-sense amplifier enables precise measurement of input current from the

AC adapter to monitor the overall system power.

Q1 (ACFET)

SI7617DN

R17

10Ω

SYSTEM

ADAPTER+

ADAPTER-

P

C9

10 μF

RAC

0.010 W

C8

10 µF

R20

2Ω

R14

100 kW

Q2 (ACFET)

SI7617DN

C14

0.1 mF

C16

2.2μF

C15

0.1 µF

ACN

ACP

C3

0.1 µF

C7

1 µF

VCC

C2

R15

100 kW

0.1 µF

P

VREF

Q3 (BATFET)

SI7617DN

BATDRV

HIDRV

ACDRV

R19

1 kΩ

R18

1 kΩ

R3

100 kW

R5

100 kW

R7

100 kW

Q4

SIS412DN

N

RSR

0.010

ISET1

ISET2

ACSET

PH

L1

W

VBAT

PACK+

PACK-

BTST

C6

0.1 µF

8.2 µH*

D1

REGN

BAT54

R4

32.4 kW

R6

10 kW

R8

22.1 kW

C5

1 µF

bq24630

C12 C13

10 µF* 10 µF*

Q5

SIS412DN

VREF

CE

LODRV

GND

N

C4

R2

Cff

22 pF

1 µF

500kW

C10

0.1 µF

C11

0.1 µF

R11 10 kW

D2

D3

D4

STAT1

STAT2

PG

SRP

SRN

R1

100

R12 10 kW

R13 10 kW

R16

kW

ADAPTER

+

VREF

R9

VFB

TTC

Pack

Thermistor

Sense

103AT

2.2 kW

100 W

TS

CTTC

PwrPad

C1

0.1 μF

R10

0.11 μF

6.8 kW

NOTE: VIN=19V, BAT=3-cell LiFePO₄, I_{adapter_limit}=4A, I_charge=3A, I_pre-charge=0.125A, I_term=0.3A, 2.5hr safety timer

Figure 1. Typical System Schematic

2

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ORDERING INFORMATION

ODERING NUMBER

PART NUMBER

IC MARING

PACKAGE

QUANTITY

(Tape and Reel)

bq24630RGER

bq24630RGET

3000

250

bq24630

OAT

24-Pin 4×4 mm²QFN

PACKAGE THERMAL DATA⁽¹⁾

T_A= 25°C

POWER RATING

DERATING FACTOR

ABOVE T_A= 25°C

PACKAGE

q_JP

q_JA

(2)

QFN – RGE

4°C/W

43°C/W

2.3W

0.023 W/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×2 via matrix. q_JAhas 5% improvement by 3x3 via matrix.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS^{(1) (2) (3)}

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

Voltage range

VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1,

STAT2, PG

–0.3 to 33

V

PH

–2 to 36

–0.3 to 16

–0.3 to 7

V

VFB

REGN, LODRV, ACSET, TS, TTC

BTST, HIDRV with respect to GND

VREF, ISET1, ISET2

ACP–ACN, SRP–SRN

V

–0.3 to 39

–0.3 to 3.6

–0.5 to 0.5

–40 to 155

–55 to 155

V

Maximum difference voltage

Junction temperature range, T_J

Storage temperature range, T_stg

V

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

(3) Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16V. Usually the resistor

divider top resistor will take care of this.

RECOMMENDED OPERATING CONDITIONS

VALUE

–0.3 to 28

–2 to 30

UNIT

V

Voltage range

VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG

PH

V

VFB

–0.3 to 14

–0.3 to 6.5

–0.3 to 34

–0.3 to 3.3

3.3

V

REGN, LODRV, ACSET, TS, TTC

BTST, HIDRV with respect to GND

ISET1, ISET2

V

VREF

V

Maximum difference voltage ACP–ACN, SRP–SRN

Junction temperature range

–0.2 to 0.2

0 to 125

V

T_J

°C

T_stg

Storage temperature range

–55 to 155

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ELECTRICAL CHARACTERISTICS

5.0V ≤ V(VCC) ≤28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

OPERATING CONDITIONS

V_{VCC_OP}VCC Input voltage operating range

QUIESCENT CURRENTS

Total battery discharge current (sum of

TEST CONDITIONS

MIN

TYP

MAX

UNIT

5.0

28.0

15

V

currents into VCC, BTST, PH, ACP, ACN,

V_VCC< V_SRN, V_VCC> V_UVLO(SLEEP)

mA

SRP, SRN, VFB), VFB ≤2.1 V

I_BAT

Battery discharge current (sum of currents V_VCC> V_SRN, V_VCC> V_UVLOCE = LOW

5

into BTST, PH, SRP, SRN, VFB), VFB ≤

2.1 V

V_VCC> V_SRN, V_VCC> V_VCCLOWCE = HIGH, Charge done

µA

V_VCC> V_SRN, V_VCC> V_UVLOCE = LOW

1

2

1.5

5

Adapter supply current (current into

VCC,ACP,ACN pin)

V_VCC> V_SRN, V_VCC>V_VCCLOW, CE = HIGH, charge done

I_AC

mA

V

V_VCC> V_SRN, V_VCC>V_VCCLOW, CE = HIGH, Charging,

Qg_total = 20 nC, V_VCC=20V

12

V_FB

Feedback regulation voltage

1.8

T_J= 0°C to 125°C

T_J= –40°C to 125°C

VFB = 1.8 V

–0.5%

–0.7%

0.5%

0.7%

100

Charge voltage regulation accuracy

Input leakage current into VFB pin

nA

CURRENT REGULATION – FAST CHARGE

V_ISET1

ISET1 voltage range

2

V

V_{IREG_CHG}

SRP–SRN current sense voltage range

V_{IREG_CHG}= V_SRP– V_SRN

100

mV

Charger current set factor amps of charge

current per volt on ISET1 pin)

K_(ISET1)

R_SENSE= 10 mΩ

5

A/V

V_{IREG_CHG}= 40 mV

V_{IREG_CHG}= 20 mV

V_{IREG_CHG}= 5 mV

–3%

–4%

3%

4%

Charge current regulation accuracy

–25%

–40%

25%

40%

100

V_{IREG_CHG}= 1.5 mV (V_SRN> 3.1 V)

V_ISET1= 2 V

I_ISET1

Leakage current in to ISET1 Pin

nA

CURRENT REGULATION – PRECHARGE

Precharge current

R_SENSE= 10 mΩ, VFB < V_LOWV

50

125

200

mA

CHARGE TERMINATION

V_ISET2

ISET2 voltage range

2

V

A

Termination current range

R_SENSE= 10 mΩ

Termination current set factor (amps of

termination current per volt on ISET2 pin)

K_TERM

1

A/V

V_ITERM= 20 mV

V_ITERM= 5 mV

–4%

–25%

–45%

4%

25%

45%

Termination current accuracy

V_ITERM= <1.5 mV

Deglitch time for termination (both edge)

Termination qualification time

100

250

2

ms

mA

nA

t_QUAL

I_QUAL

I_ISET2

V_BAT> V_RECHand I_CHARGE< I_TERM

Discharge current once termination is detected

V_ISET2= 2 V

Termination qualification time

Leakage current into ISET2 pin

100

INPUT CURRENT REGULATION

V_ACSET

ACSET voltage range

0

2

V

V_{IREG_DPM}

ACP-ACN current sense voltage range

V_{IREG_DPM}= V_ACP– V_ACN

100

mV

Input current set factor (amps of input

current per volt on ACSET pin)

K_(ACSET)

R_SENSE= 10 mΩ

5

A/V

nA

V_{IREG_DPM}= 40 mV

V_{IREG_DPM}= 20 mV

V_{IREG_DPM}= 5 mV

V_ACSET= 2 V

–3%

–4%

3%

4%

Input current regulation accuracy

Leakage current into ACSET pin

–25%

25%

100

I_ACSET

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)

V_UVLO

AC under-voltage rising threshold

AC under-voltage hysteresis, falling

Measure on VCC

3.65

3.85

350

4

V

V_{UVLO_HYS}

mV

4

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC LOWV COMPARATOR

Falling threshold, disable charge

Rising threshold, resume charge

Measure on VCC

4.1

V

4.35

4.5

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)

V_{SLEEP _FALL}

V_{SLEEP_HYS}

SLEEP falling threshold

SLEEP hysteresis

V_VCC– V_SRNto enter SLEEP

40

100

500

1

150

mV

ms

SLEEP rising delay

VCC falling below SRN, Delay to turn off ACFET

VCC rising above SRN, Delay to turn on ACFET

VCC falling below SRN, Delay to enter SLEEP mode

VCC rising above SRN, Delay to exit out of SLEEP mode

SLEEP falling delay

30

ms

SLEEP rising shutdown deglitch

SLEEP falling powerup deglitch

100

30

ms

ACN / SRN COMPARATOR

V_{ACN-SRN_FALL}ACN to SRN falling threshold

V_{ACN-SRN_HYS}ACN to SRN rising hysteresis

ACN to SRN rising deglitch

V_ACN–V_SRNto turn on BATFET

100

200

100

2

310

mV

ms

V_ACN– V_SRN> V_{ACN-SRN_RISE}

V_ACN– V_SRN< V_{ACN-SRN_FALL}

ACN to SRN falling deglitch

50

BAT LOWV COMPARATOR

Precharge to fastcharge transition (LOWV

threshold)

V_LOWV

Measured on VFB pin, rising

0.333

0.35

0.367

V

V_{LOWV_HYS}

LOWV hysteresis

LOWV rising deglitch

LOWV falling deglitch

100

25

mV

ms

VFB falling below VLOWV

VFB rising above VLOWV

25

RECHARGE COMPARATOR

Recharge threshold (with respect to

V_RECHG

Measured on VFB pin, rising

110

125

140

mV

VREG)

Recharge rising deglitch

Recharge falling deglitch

VFB decreasing below V_RECHG

VFB increasing above V_RECHG

10

ms

BAT OVER-VOLTAGE COMPARATOR

V_{OV_RISE}

V_{OV_FALL}

Over-voltage rising threshold

Over-voltage falling threshold

As percentage of V_FB

108%

105%

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

V_ACOV

AC over-voltage rising threshold on VCC

AC over-voltage falling hysteresis

AC over-voltage deglitch (both edge)

AC over-voltage rising deglitch

31.04

32

1

32.96

V

V_{ACOV_HYS}

V

Delay to changing the STAT pins

Delay to disable charge

1

ms

1

AC over-voltage falling deglitch

Delay to resume charge

20

THERMAL SHUTDOWN COMPARATOR

T_SHUT

Thermal shutdown rising temperature

Temperature increasing

145

15

°C

ms

T_{SHUT_HYS}

Thermal shutdown hysteresis

Thermal shutdown rising deglitch

Thermal shutdown falling deglitch

Temperature increasing

Temperature decreasing

100

10

ms

THERMISTOR COMPARATOR

V_LTF

Cold temperature rising threshold

Charger suspended below this temperature

72.5% 73.5% 74.5%

0.2% 0.4% 0.6%

V_{LTF_HYS}

Cold temperature hysteresis

Charger enabled, cuts back to I_CHARGE/8 below this

temperature

V_COOL

Cool Temperature rising threshold

70.2% 70.7% 71.2%

V_{COOL_HYS}

V_WARM

Cool temperature hysteresis

Warm temperature rising threshold

Warm temperature hysteresis

0.2%

47.5%

1.0%

0.6%

48% 48.5%

1.2% 1.4%

1.0%

Charger cuts back to I_CHARGE/8 above this temperature

V_{WARM_HYS}

Charger suspended above this temperature before

initiating charge

V_HTF

V_TCO

Hot temperature rising threshold

36.2%

37% 37.8%

Charger suspended above this temperature during

initiating charge

Cut-off temperature rising threshold

33.7% 34.4% 35.1%

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Deglitch time for Temperature Out of

Range Detection

V_TS> V_LTF, or V_TS< V_TCO, or V_TS< V_HTF

400

ms

Deglitch time for Temperature in Valid

Range Detection

V_TS< V_LTF– V_{LTF_HYS}or V_TS>V_TCO, or V_TS> V_HTF

V_TS> V_COOL, or V_TS< V_WARM

20

25

ms

Deglitch time for current reduction to

I_CHARGE/8 due to warm or cool temperature

Deglitch time to charge at I_CHARGEfrom

I_CHARGE/8 when resuming from warm or

cool temperatures

V_TS< V_COOL- V_{COOL_HYS}, or V_TS> V_WARM- V_{WARM_HYS}

25

ms

Charge current due to warm or cool

temperatures

V_COOL< V_TS< V_LTF, or V_WARM< V_TS< V_HTF, or V_WARM

V_TS< V_TCO

<

I_CHARGE

/8

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

Current rising, in non-synchronous mode, mesure on

45.5

160%

50

mV

V_(SRP-SRN), V_SRP< 2 V

Charge over-current falling threshold

Current rising, as percentage of V_{(IREG_CHG)}, in

synchronous mode, V_SRP> 2.2V

V_OC

Minimum OCP threshold in synchronous mode, measure

on V_(SRP-SRN), V_SRP> 2.2V

Charge over-current threshold floor

Charge over-current threshold ceiling

mV

Maximum OCP threshold in synchronous mode, measure

on V_(SRP-SRN), V_SRP> 2.2V

180

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

V_ISYNSETCharge under-current falling threshold

Switch from SYNCH to NON-SYNCH, V_SRP> 2.2V

V_SRPfalling

1

5

2

9

mV

V

BATTERY SHORTED COMPARATOR (BATSHORT)

BAT Short falling threshold, forced

V_BATSHT

non-synchronous mode

V_{BATSHT_HYS}

V_{BATSHT_DEG}

BAT short rising hysteresis

Deglitch on both edge

200

1

mV

ms

LOW CHARGE CURRENT COMPARATOR

Average low charge current falling

threshold

Measure on V_(SRP-SRN), forced into non-synchronous

mode

V_LC

1.25

mV

V_{LC_HYS}

V_{LC_DEG}

Low charge current rising hysteresis

Deglitch on both edge

1.25

1

mV

ms

VREF REGULATOR

V_{VREF_REG}VREF regulator voltage

I_{VREF_LIM}VREF current limit

REGN REGULATOR

V_{REGN_REG}REGN regulator voltage

I_{REGN_LIM}

V_VCC> V_UVLO, ( 0 – 35mA load)

V_VREF= 0 V, V_VCC> V_UVLO

3.267

35

3.3

6.0

3.333

6.3

V

mA

V_VCC> 10 V, CE = HIGH (0 – 40mA load)

V_REGN= 0 V, V_VCC> V_UVLO

5.7

40

V

REGN current limit

mA

TTC INPUT

T_PRECHG

(1)

Precharge time before fault occurs

Tchg = C_TTC× K_TTC

1440

1

1800

2160

10

sec

Hr

Precharge safety timer range

Fast charge saftey timer range, with +/-

10% accuracy⁽¹⁾

T_CHARGE

Fast charge timer accuracy⁽¹⁾

0.047 mF ≤ C_TTC≤ 0.47 mF

–10%

10%

K_TTC

Timer multiplier

1.4

min/nF

V

V_TTCbelow this threshold disables the safety timer and

termination

TTC low threshold

0.4

55

TTC comparator high threshold

TTC comparator low threshold

TTC source/sink current

1.5

1

V

45

50

mA

BATTERY SWITCH (BATFET) DRIVER

R_{DS_BAT_OFF}

R_{DS_BAT_ON}

BATFET turn-off resistance

BATFET turn-on resistance

V_ACN> 5V

150

20

Ω

kΩ

V_{BATDRV_REG}= V_ACN– V_BATDRVwhen V_ACN> 5V and

BATFET is on

V_{BATDRV_REG}

BATFET drive voltage

4.2

7

V

(1) Verified by design

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ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<T_J<+125°C,typical values are at T_A=25°C, with respect to GND unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC SWITCH (ACFET) DRIVER

R_{DS_AC_OFF}

R_{DS_AC_ON}

ACFET turn-off resistance

ACFET turn-on resistance

V_VCC> 5V

30

20

Ώ

kΏ

V_{ACDRV_REG}= V_VCC– V_ACDRVwhen V_VCC> 5 V and

ACFET is on

V_{ACDRV_REG}

ACFET drive voltage

4.2

7

V

AC / BAT MOSFET DRIVERS TIMING

Driver dead time

Dead time when switching between AC and BAT

10

ms

BATTERY DETECTION

t_WAKE

Wake timer

Max time charge is enabled

R_SENSE= 10 mΩ

500

125

1

ms

mA

sec

mA

mV

V

I_WAKE

Wake Current

50

200

t_DISCHARGE

I_DISCHARGE

I_FAULT

Discharge timer

Max time discharge current is applied

Discharge current

8

Fault current after a timeout fault

Wake threshold ( with-respect-to V_REG

Discharge threshold

2

V_WAKE

)

Voltage on VFB to detect battery absent during Wake

Voltage on VFB to detect battery absent during Discharge

125

0.35

V_DISCH

PWM HIGH SIDE DRIVER (HIDRV)

R_{DS_HI_ON}

R_{DS_HI_OFF}

High Side driver (HSD) turn-on resistance

High Side driver turn-off resistance

V_BTST– V_PH= 5.5 V

3.3

1

6

Ω

1.3

Bootstrap refresh comparator threshold

voltage

V_{BTST_REFRESH}

V_BTST– V_PHwhen low side refresh pulse is requested

4.0

4.2

V

PWM LOW SIDE DRIVER (LODRV)

R_{DS_LO_ON}Low side driver (LSD) turn-on resistance

R_{DS_LO_OFF}Low side driver turn-off resistance

PWM DRIVERS TIMING

4.1

1

7

Ω

1.4

Dead time when switching between LSD and HSD, no

load at LSD and HSD

30

Driver dead time

ns

PWM OSCILLATOR

V_{RAMP_HEIGHT}PWM ramp height

As percentage of VCC

7

%

PWM switching frequency⁽²⁾

255

300

345

kHz

INTERNAL SOFT START (8 steps to regulation current ICHG)

Soft start steps

8

step

ms

Soft start step time

1.6

CHARGER SECTION POWER-UP SEQUENCING

Delay from when adapter is detected to when the charger

is allowed to turn on

Charge-enable delay after power-up

LOGIC IO PIN CHARACTERISTICS

1.5

s

V_{IN_LO}

V_{IN_HI}

CE input low threshold voltage

CE input high threshold voltage

CE input bias current

0.8

V

2.1

V_{BIAS_CE}

V = 3.3 V (CE has internal 1MΩ pulldown resistor)

6

0.5

1.2

mA

STAT1, STAT2, PG output low saturation

voltage

V_{OUT_LO}

I_{OUT_HI}

Sink current = 5 mA

V = 32 V

V

Leakage current

µA

(2) Verified by design

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TYPICAL CHARACTERISTICS

Table 1. Table of Graphs

Figure

REF REGN and PG Power Up (CE=1)

Charge Enable

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Current Soft-Start (CE=1)

Charge Disable

Continuous Conduction Mode Switching Waveforms

Cycle-by-Cycle Synchronous to Nonsynchronous

100% Duty and Refresh Pulse

Transient System Load (DPM)

Battery Insertion

Battery to Ground Short Protection

Battery to ground Short Transition

Efficiency vs Output Current

Input ACOV Transition

Input ACOV Resume Normal Transition

PH

VCC

/PG

LODRV

VREF

REGN

IBAT

CE

t − Time = 4 ms/div

t − Time = 200 ms/div

Figure 2. REF REGN and PG Power Up (CE=1)

Figure 3. Charge Enable

PH

LDRV

LODRV

IBAT

IL

CE

t − Time = 4 μs/div

t − Time = 4 ms/div

Figure 4. Current Soft-Start (CE=1)

Figure 5. Charge Disable

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PH

HIDRV

PH

LODRV

IL

t – Time = 200 ns/div

t − Time = 200 ns/div

Figure 6. Continuous Conduction Mode Switching Waveform

Figure 7. Cycle-by-Cycle Synchronous to Nonsynchronous

IIN

PH

ISYS

LODRV

IL

IBAT

t − Time = 200 μs/div

t − Time = 400 ns/div

Figure 8. 100% Duty and Refresh Pulse

Figure 9. Transient System Load (DPM)

PH

LDRV

IL

VBAT

t – Time = 4 ms/div

t – Time = 200 ms/div

Figure 10. Battery Insertion

Figure 11. Battery to GND Short Protection

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98

96

94

92

90

88

86

84

82

80

PH

LDRV

24 Vin, 6 cell

24 Vin, 5 cell

IL

12 Vin, 2 cell

12 Vin, 1 cell

VBAT

t – Time = 8 μs/div

0

1

2

3

4

5

6

7

8

IBAT - Output Current - A

Figure 12. Battery to GND Short Transition

Figure 13. Efficiency vs Output Current

VCC

/ACDRV

/BATDRV

/PG

t – Time = 10 ms/div

t – Time = 20 ms/div

Figure 14. Input ACOV Transition

Figure 15. Input ACOV Resume Normal Transition

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Pin Functions – 24-Pin QFN

FUNCTION DESCRIPTION

NO.

NAME

1

ACN

Adapter current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.

2

3

ACP

Adapter current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.

ACDRV

AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET

and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and

slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to

source of the ACFET is used to slow down the ON and OFF times.

4

5

6

CE

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor.

STAT1

TS

Open-drain charge status pin to indicate various charger operation.

Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold

temperature window with a resistor divider from VREF to TS to GND.

7

8

TTC

PG

SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer

and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed.

Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH

when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor.

9

STAT2

VREF

Open-drain charge status pin to indicate various charger operation.

10

3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for

programming of voltage and current regulation and for programming the TS threshold.

11

12

ISET1

VFB

Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point.

Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to

adjust the output battery regulation voltage.

13

14

SRN

SRP

Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.

Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.

15

16

ISET2

Termination current set input. The voltage of ISET2 pin programs termination current trigger point.

ACSET

Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power

Management (DPM)

17

18

GND

Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.

REGN

PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin, close to the IC. Use for

low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.

19

20

LODRV

PH

PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from PH to BTST.

21

22

HIDRV

BTST

PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from SW to BTST.

23

BATDRV

Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from

the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.

Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the

system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical

to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an

optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.

24

VCC

IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side P-channel MOSFET

and source of reverse-blocking power P-channel MOSFET. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.

PowerPAD

Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND

and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.

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BLOCK DIAGRAM

VREF

bq24630

VCC

ACN

VOLTAGE

REFERENCE

VCC- 6 V

VCC

VCC- 6 V

REG

ACN-6 V

VCC- 6 V

REG

-

VCC

SLEEP

UVLO

+

SRN+100 mV

-

VCC

SLEEP

UVLO

SYSTEM

POWER

SELECTOR

LOGIC

V

UVLO

+

3.3 V

LDO

ACDRV

VCC

VREF

ACN

+

-

ACN- SRN

ACOV

VCC- 6 V

ACN

SRN+200 mV

BATDRV

CE

1 M

ACN- 6 V

ACP

+

V(ACP-ACN)

+

-

20X

-

COMP

ERROR

AMPLIFIER

CE

BTST

HIDRV

PH

ACN

-

ACSET

+

-

PWM

+

1V

+

-

LEVEL

SHIFTER

VFB

SRP

SRN

1.8 V

BAT_OVP

SYNCH

20mA

+

SRP- SRN

PWM

CONTROL

LOGIC

-

+

VCC

+

20X

5mV

-

V(SRP-SRN)

+

-

IBAT_ REG

CE

REGN

LODRV

REFRESH

6 V LDO

-

BTST

_

20mA

PH

+

4.2V

DISCHARGE

OR

CHARGE

FAULT

V(SRP-SRN)

160% X IBAT_REG

-

CHG_OCP

+

8 mA 2 mA

GND

FAULT

Safety Timer

STAT1

30 minute

Precharge

timer

CHARGE

STAT1

TTC

IC Tj

TSHUT

+

-

STAT2

145 °C

PG

STAT2

PG

ISET1

8

ISET1

STATE

MACHINE

LOGIC

DISCHARGE

VREF

ISET1

IBAT_ REG

+

-

BAT

BAT_OVP

-

LTF

1.25 mV

108% X VBAT_REG

+

BATTERY

DETECTION

LOGIC

DISABLE

TMR/TERM

-

TTC

-

COOL

VFB

+

-

LOWV

+

0.4 V

+

0.35V

-

+

-

WARM

COOL

+

-

VCC

ACOV

WARM

TS

SUSPEND

VFB

-

+

V

RCHRG

ACOV

+

-

HTF

TCO

+

1.675V

-

+

-

RCHRG

TERM

-

ISET2

100X V(SRP -SRN)

bq24630

TERM

+

ISET2

TERMINATE CHARGE

Figure 16. Functional Block Diagram of bq24630

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OPERATIONAL FLOWCHART

POR

Turn on

BATDRV FET

SLEEP MODE

Indicate SLEEP

VCC > SRN

Yes

No

Turn off BATFET

Turn on ACFET

Enable VREF LDO&

Chip Bias

30 ms delay

Battery

present?

Initiate battery

detect algorithm

Indicate battery

absent

No

Yes

See Enabling and Disabling

Charg e Section

Indicate NOT

CHARGING,

Suspend timers

Conditions met

?

Conditions met

for charge?

No

for charge

Yes

Regulate

precharge current

Start 30 minute

precharge timer

Precharge

timer expired?

VFB < VLOWV

Yes

VFB < VLOWV

Yes

Indicate Charge-

In-Progress

Start Fastcharge

timer

No

Regulate

fastcharge current

Yes

Indicate NOT

CHARGING,

Suspend timers

Conditions met

for charge?

No

Yes

Indicate Charge-

In-Progress

No

Turn off charge,

FAULT

Enable I

for1

DISCHG

FAULT

second

VFB > VRECH

&

ICHG < ITERM

Fastcharge

Timer Expired?

Yes

No

Yes

Indicate Charge In

Progress

Indicate FAULT

Charge Complete

Indicate DONE

Yes

No

VFB > VRECH

VFB < VRECH

No

Battery Removed

Yes

Indicate BATTERY

ABSENT

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DETAILED DESCRIPTION

Precharge

Current

Fastcharge Current

Regulation Phase

Fastcharge Voltage

Regulation Phase

Termination

Regulation

Phase

Regulation Voltage

V

RECH

Regulation Current

Charge

Current

Charge

Voltage

V

LOWV

I

& I

TERM

PRECH

Precharge

Time

Fastcharge Safety Time

Figure 17. Typical Charging Profile

BATTERY VOLTAGE REGULATION

The bq24630 uses a high accuracy voltage bandgap and regulator for the high accuracy charging voltage. The

charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB

pin. The voltage at the VFB pin is regulated to 1.8V, giving Equation 1 for the regulation voltage:

R1

é

ù

V

= 1.8 V ´ 1+

BAT

ê

ú

R2

ë

û

(1)

where R2 is connected from VFB to the battery and R1 is connected from VFB to GND

BATTERY CURRENT REGULATION

The ISET1 input sets the maximum fast charging current. Battery charge current is sensed by resistor R_SR

connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100mV. Thus, for

a 10mΩ sense resistor, the maximum charging current is 10A. Equation 2 is for charge current

V

ISET1

I

=

CHARGE

20 ´ R

SR

(2)

V_ISET1, the input voltage range of ISET1 is between 0 and 2V. The SRP and SRN pins are used to sense voltage

across R_SRwith default value of 10mΩ. However, resistors of other values can also be used. A larger sense

resistor will give a larger sense voltage, a higher regulation accuracy; but, at the expense of higher conduction

loss.

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PRECHARGE

On power-up, if the battery voltage is below the V_LOWVthreshold, the bq24630 applies 125mA precharge current

to the battery⁽¹⁾. The precharge feature is intended to revive deeply discharged cells. If the V_LOWVthreshold is not

reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status

pins.

INPUT ADAPTER CURRENT REGULATION

The total input from an AC adapter or other DC sources is a function of the system supply current and the battery

charging current. System current normally fluctuates as portions of the systems are powered up or down. Without

Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the

maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging

current when the input current exceeds the input current limit set by ACSET. The current capability of the AC

adaptor can be lowered, reducing system cost.

Similar to setting battery regulation current, adaptor current is sensed by resistor R_ACconnected between ACP

and ACN. Its maximum value is set by ACSET using Equation 3:

V

ACSET

I

=

DPM

20 ´ R

AC

(3)

V_ACSET, the input voltage range of ACSET is between 0 and 2V. The ACP and ACN pins are used to sense

voltage across R_ACwith default value of 10mΩ. However, resistors of other values can also be used. A larger the

sense resistor will give a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher

conduction loss.

CHARGE TERMINATION, RECHARGE, AND SAFETY TIMER

The bq24630 monitors the charging current during the voltage regulation phase. When V_TTCis valid, termination

is detected while the voltage on the VFB pin is higher than the V_RECHthreshold AND the charge current is less

than the I_TERMthreshold, as calculated in Equation 4:

V

ISET2

I

=

TERM

100 ´ R

SR

(4)

V_ISET2, the input voltage of ISET2 is between 0 and 2V. The minimum termination current is clamped to be

around 125mA with default 10mΩ sensing resistor. To avoid early termination during WARM/COOL condition, set

I_TERM≤ I_CHARGE/10. As a safety backup, the bq24630 also provides a programmable charge timer. The charge

time is programmed by the capacitor connected between the TTC pin and GND, and is given by Equation 5

t

= C

´ K

CHARGE

TTC TTC

(5)

where C_TTC(range from 0.047µF to 0.47µF to give 1-10hr safety timer) is the capacitor connected from TTC pin

to GND, and K_TTCis the constant multiplier (1.4min/nF).

A new charge cycle is initiated and safety timer is reset when one of the following conditions occur:

•

The battery voltage falls below the recharge threshold.

A power-on-reset (POR) event occurs.

CE is toggled.

The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,

the bq24630 will continue to allow termination but disable the safety timer. TTC taken low will reset the safety

timer. When ACOV, VCCLOWV and SLEEP mode resume normal, the safety timer will be reset.

(1) assuming a 10mΩ sense resistor. 1.25mV will be regulated across SRP-SRN, regardless of the value of the sense resistor.

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POWER UP

The bq24630 uses a SLEEP comparator to determine the source of power on the VCC pin, since VCC can be

supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24630 will

enable the ACFET and disable BATFET. If all other conditions are met for charging, bq24630 will then attempt to

charge the battery (See Enabling and Disabling Charging). If the SRN voltage is greater than VCC, indicating

that the battery is the power source, bq24630 enables the BATFET, and enters a low quiescent current (<15mA)

SLEEP mode to minimize current drain from the battery.

If VCC is below the UVLO threshold, the device is disabled, ACFET turns off and BATFET turns on.

ENABLE AND DISABLE CHARGING

The following conditions have to be valid before charge is enabled:

•

CE is HIGH

The device is not in Under-Voltage-Lockout (UVLO) and not in VCCLOWV mode

The device is not in SLEEP mode

The VCC voltage is lower than the AC over-voltage threshold (VCC < V_ACOV

30 ms delay is complete after initial power-up

The REGN LDO and VREF LDO voltages are at the correct levels

Thermal Shut (TSHUT) is not valid

)

TS fault is not detected

One of the following conditions will stop on-going charging

•

CE is LOW

Adapter is removed, causing the device to enter UVLO, VCCLOWV, or SLEEP mode

Adapter is over voltage

The REGN or VREF LDOs are overloaded

TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis)

TS voltage goes out of range indicating the battery temperature is too hot or too cold

TTC saftey timer times out

SYSTEM POWER SELECTOR

The bq24630 automatically switches adapter or battery power to the system load. The battery is connected to the

system by default during power up or during SLEEP mode. The battery is disconnected from the system and

then the adapter is connected to the system 30ms after exiting SLEEP. An automatic break-before-make logic

prevents shoot-through currents when the selectors switch.

The ACDRV is used to drive a pair of back-to-back p-channel power MOSFETs between adapter and ACP with

sources connected together and to VCC. The FET connected to adapter prevents reverse discharge from the

battery to the adapter when turned off. The p-channel FET with the drain connected to the adapter input provides

reverse battery discharge protection when off; and also minimizes system power dissipation, with its low-R_DSON

,

compared to a Schottky diode. The other p-channel FET connected to ACP separates battery from adapter, and

provides a limited dI/dt when connecting the adapter to the system by controlling the FET turn-on time. The

BATDRV controls a p-channel power MOSFET placed between BAT and system.

When adapter is not detected, the ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from

system. BATDRV stays at ACN-6V to connect battery to system.

Approximately 30ms after the device comes out of SLEEP mode, the system begins to switch from battery to

adapter. The break-before-make logic keeps both ACFET and BATFET off for 10µs before ACFET turns on. This

prevents shoot-through current or any large discharging current from going into the battery. The /BATDRV is

pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on p-channel ACFET,

connecting the adapter to the system.

When the adapter is removed, the system waits until VCC drops back to within 200mV above SRN to switch from

adapter back to battery. The break-before-make logic still keeps 10ms dead time. The ACDRV is pulled up to

VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on p-channel BATFET, connecting

the battery to the system.

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Asymmetrical gate drive for the ACDRV and BATDRVdrivers provides fast turn-off and slow turn-on of the

ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The

soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power

MOSFETs.

AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT

The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge

to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists

of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.

Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this

function.

CONVERTER OPERATION

The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A

type III compensation network allows using ceramic capacitors at the output of the converter. The compensation

input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The

feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output

(EAO). The LC output filter is selected to give a resonant frequency of 10 kHz – 15 kHz for bq24630, where

resonant frequency, f_o, is given by Equation 6:

1

f_o

=

2p L_oC_o

(6)

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the

converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input

adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop

compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is

below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%

duty-cycle PWM request. Internal gate drive logic allows achieving 99.95% duty-cycle while ensuring the

N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below

4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side

n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the

high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again

due to leakage current discharging the BTST capacitor below the 4.2 V, and the reset pulse is reissued.

The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,

battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible

noise region. Also see Application Information for how to select inductor, capacitor and MOSFET.

Synchronous and Non-Synchronous Operation

The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for

a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is

break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where

both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the

low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During

synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode

(CCM), creating a fixed two-pole system.

The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor

current for a 10mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is

lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.

During non-synchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor

current after the high-side n-channel power MOSFET turns off. When the load current decreases and the

inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become

discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel

power MOSFET will turn-on for around 80ns when the bootstrap capacitor voltage drops below 4.2V, then the

low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power

MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is

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always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for

battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can

both source and sink current. The 80ns low-side pulse pulls the PH node (connection between high and low-side

MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80ns, the

low-side MOSFET is kept off to prevent negative inductor current from occurring.

At very low currents during non-synchronous operation, there may be a small amount of negative inductor

current during the 80ns recharge pulse. The charge should be low enough to be absorbed by the input

capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on,

and the low-side MOSFET does not turn on (only 80ns recharge pulse) either, and there is almost no discharge

from the battery.

During the DCM mode the loop response automatically changes and has a single pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means at very low currents the loop response is slower, as there is less sinking current

available to discharge the output voltage.

Cycle-by-Cycle Charge Under Current Protection

If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the

average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the

switching cycle to prevent negative inductor current. During DCM, the low-side FET will only turn on for at around

80ns when the bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap

capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input

voltage increases as power is transferred from the battery to the input capacitors and lead to an over-voltage

stress on the VCC node and potentially cause damage to the system.

INPUT OVER VOLTAGE PROTECTION (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage

reaches the ACOV threshold, charge is disabled and the battery is switched to system instead of adapter.

INPUT UNDER VOLTAGE LOCK OUT (UVLO)

The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from

either input adapter or battery, since a conduction path exists from the battery to VCC through the high side

NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the gate

drive bias to ACFET and BATFET are disabled.

BATTERY OVER-VOLTAGE PROTECTION

The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 105% of the regulation

voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed

or the battery is disconnected. An 8mA current sink from SRP to GND is on only during charge and allows

discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP will also

suspend the safety timer.

CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION

The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents

the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the

over-current is detected, and automatically resumes when the current falls below the over-current threshold.

THERMAL SHUTDOWN PROTECTION

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the

ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and

self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off

until the junction temperature falls below 130°C. Then the charger will soft-start again if all other enable charge

conditions are valid. Thermal shutdown will also suspend the safety timer.

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TEMPERATURE QUALIFICATION

The controller continuously monitors battery temperature by measuring the voltage between the TS pin and

GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this

voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.

To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery

temperature is outside of this range, the controller suspends charge and the safety timer and waits until the

battery temperature is within the V(LTF) to V(HTF) range. During the charge cycle the battery temperature must

be within the V(LTF) to V(TCO) thresholds. If battery temperature is outside of this range, the controller suspends

charge and safety timer and waits until the battery temperature is within the V(LTF) to V(HTF) range. If the

battery temperature is between the V(LTF) and the V(COOL) thresholds or between the V(HTF) and V(WARM)

thresholds, charge is automatically reduced to I_CHARGE/8. To avoid early termination during COOL/WARM

condition, set I_TERM≤ I_CHARGE/10. The controller suspends charge by turning off the PWM charge FETs. Figure 18

and Figure 19 summarizes the operation.

TEMPERATURE RANGE TO

INITIATE CHARGE

TEMPERATURE RANGE

DURING A CHARGE CYCLE

VREF

CHARGE SUSPENDED

CHARGE at I_CHARGE/8

CHARGE at I_CHARGE

CHARGE SUSPENDED

V

LTF

LTF_HYS

V

LTF

CHARGE at I_CHARGE/8

V

COOL

V

COOL_HYS

CHARGE at I_CHARGE

V

WARM

V

WARM_HYS

CHARGE at I_CHARGE/8

CHARGE SUSPENDED

CHARGE at I_CHARGE/8

CHARGE SUSPENDED

V

HTF

V

TCO

GND

Figure 18. TS, Thermistor Sense Thresholds

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Charge

Current

Charge

Suspended

Charge

Suspended

Charge at I_CHG

Programmed

Charge Current

(I_CHARGE

)

1/8 x Programmed

Charge Current

(I_CHARGE/8)

Temperature

/V_TCO

V

HTF

WARM

LTF

COOL

Figure 19. Typical Charge Current vs Temperature Profile

Assuming a 103AT NTC thermistor on the battery pack as shown in the Typical System Schematic, the value

RT1 and RT2 can be determined by using Equation 7 and Equation 8:

æ

ç

è

ö

÷

ø

1

V_VREF´ RTH_COOL´ RTH_WARM

´

-

V_COOL

V_WARM

RT2 =

æ

ç

è

ö

æ

ö

÷

ø

V_VREF

RTH_WARM

´

-1 - RTH

´

-1

÷

ç

COOL

V_WARM

V_COOL

ø

è

(7)

(8)

V_VREF

-1

V_COOL

RT1 =

1

+

RT2

RTH_COOL

VREF

RT1

RT2

bq24630

TS

RTH

103 AT

Figure 20. TS Resistor Network

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For example, 103AT NTC thermistor is used to monitor the battery pack temperature. Select T_COOL= 0ºC, T_WARM

= 60ºC. From the calculation and select standard 5% resistor value. We can get R_T1= 2.2kΩ, R_T2= 6.8kΩ, and

T_COLDis -17ºC (target -20ºC); T_HOTis 77ºC (target 75ºC), and T_CUT-OFFis 86ºC (target 80ºC). A small RC filter is

suggested to protect TS pin from system-level ESD.

Timer Fault Recovery

The bq24630 provides a recovery method to deal with timer fault conditions. The following summarizes this

method:

Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.

Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and

battery detection will begin. Taking CE low or a POR condition will also clear the fault.

Condition 2: The battery voltage is below the RECHARGE threshold and a timeout fault occurs.

Recovery Method: Under this scenario, the bq24630 applies the IFAULT current to the battery. This small

current is used to detect a battery removal condition and remains on as long as the battery voltage stays below

the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24630 disables the fault

current and executes the recovery method described in Condition 1. Taking CE low or a POR condition will also

clear the fault.

PG Output

The open drain PG(power good) output indicates whether the VCC voltage is valid or not. The open drain FET

turns on whenever bq24630 has a valid VCC input ( not in UVLO or ACOV or SLEEP mode). The PG pin can be

used to drive an LED or communicate to the host processor.

CE (Charge Enable)

The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables

charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high to low

transition on this pin also resets all timers and fault conditions. There is an internal 1 MΩ pulldown resistor on the

CE pin, so if CE is floated the charge will not turn on.

INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES

The bq24630 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant

frequency, f_o, is approximately 10kHz – 15kHz per Equation 9:

1

f_o

=

2p L_oC_o

(9)

Table 2 provides a summary of typical LC components for various charge currents

Table 2. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current

CHARGE CURRENT

Output Inductor Lo

Output Capacitor Co

Sense Resistor

2A

4A

6A

8A

10A

8.2 mH

20 mF

10 mΩ

8.2 mH

20 mF

10 mΩ

5.6 mH

30 mF

10 mΩ

4.7 mH

40 mF

10 mΩ

4.7 mH

40 mF

10 mΩ

CHARGE STATUS OUTPUTS

The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 3. These

status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the

open-drain transistor is turned off.

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Table 3. STAT Pin Definition for bq24630

CHARGE STATE

STAT1

ON

STAT2

OFF

ON

Charge in progress

Charge complete

OFF

Charge suspend, timer fault, over-voltage, sleep mode, battery absent

OFF

BATTERY DETECTION

For applications with removable battery packs, bq24630 provides a battery absent detection scheme to reliably

detect insertion or removal of battery packs.

POR or RECHARGE

The battery detection routine runs on

power up, or if VFB falls below VRECH

due to removing a battery or

discharging a battery

Apply 8 mA discharge

current, start 1s timer

1s timer

expired

No

VFB < V

LOWV

No

Yes

Battery Present,

Begin Charge

Disable 8 mA

discharge current

Enable 125 mA Charge,

Start 0.5s timer

0.5s timer

expired

No

VFB > V

Yes

No

RECH

Yes

Battery Present,

Begin Charge

Disable 125 mA

Charge

Battery Absent

Figure 21. Battery Detection Flowchart

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Once the device has powered up, an 8mA discharge current will be applied to the SRN terminal. If the battery

voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is

turned on at low charge current (125mA). If the battery voltage gets up above the recharge threshold within

500ms, there is no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before

the respective thresholds are hit, a battery is detected and a charge cycle is initiated.

Battery not Detected

V

REG

V

RECH

Battery

Inserted

(V_WAKE

)

V

LOWV

Battery Detected

(V_DISH

)

t

WAKE

t

RECH_DEG

LOWV_DEG

Figure 22. Battery Detect Timing Diagram

Care must be taken that the total output capacitance at the battery node is not so large that the discharge current

source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum

output capacitance can be calculated as seen in Equation 10:

I_DISCH´ t_DISCH

C_MAX

=

é

ù

R

ê

²ú

1.425 ´ 1+

R₁

ë

û

(10)

Where C_MAXis the maximum output capacitance, I_DISCHis the discharge current, t_DISCHis the discharge time, and

R₂and R₁are the voltage feedback resistors from the battery to the VFB pin. The 1.425 factor is the difference

between the RECHARGE and the LOWV thresholds at the VFB pin.

EXAMPLE

For a 3-cell LiFePO₄charger, with R2 = 500k, R1 = 100k (giving 10.8V for voltage regulation), I_DISCH= 8mA,

t_DISCH= 1 second,

8mA ´ 1sec

C_MAX

=

= 930 mF

500k

é

ù

1.425 ´ 1+

ê

ú

100k

ë

û

(11)

Based on these calculations, no more than 930 mF should be allowed on the battery node for proper operation of

the battery detection circuit.

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Component List for Typical System Circuit of Figure 1

PART DESIGNATOR

QTY

3

2

1

3

2

1

2

1

4

2

4

2

1

4

1

3

2

1

2

1

DESCRIPTION

P-channel MOSFET, –30 V,–35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN

N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN

Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C

LED Diode, Green, 2.1V, 20mA, LTST-C190GKT

Sense Resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F

Inductor, 6.8 µH, 5.5A, Vishay-Dale IHLP2525CZ

Capacitor, Ceramic, 0.1 µF, 50V, 10%, X7R

Capacitor, Ceramic, 1 µF, 50V, 10%, X7R

Capacitor, Ceramic, 10 µF, 35 V, 20%, X7R

Capacitor, Ceramic, 1 µF, 25 V, 10%, X7R

Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R

Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R

Capacitor, Ceramic, 2.2 µF, 35V, 10%, X7R

Capacitor, Ceramic, 22 pF, 25V, 10%, X7R

Capacitor, Ceramic, 0.11 µF, 25V, 5%, X7R

Resistor, Chip, 100 kΩ, 1/16W, 0.5%

Q1, Q2, Q3

Q4, Q5

D1

D2, D3, D4

R_AC, R_SR

L1

C2, C10

C7

C8, C9, C12, C13

C4, C5

C1, C3, C6, C11

C14, C15 (Optional)

C16

C_ff

C_TTC

R1, R3, R5, R7

R2

Resistor, Chip, 500 kΩ, 1/16W, 0.5%

R4

Resistor, Chip, 32.4 kΩ, 1/16W, 0.5%

R6

Resistor, Chip, 10 kΩ, 1/16W, 0.5%

R8

Resistor, Chip, 22.1 kΩ, 1/16W, 0.5%

R9

Resistor, Chip, 2.2 kΩ, 1/16W, 5%

R10

Resistor, Chip, 6.8 kΩ, 1/16W, 5%

R11, R12, R13

R14, R15 (optional)

R16

Resistor, Chip, 10 kΩ, 1/16W, 5%

Resistor, Chip, 100 kΩ, 1/16W, 5%

Resistor, Chip, 100 Ω, 1/16W, 5%

R17

Resistor, Chip, 10 Ω, 1/4W, 5%

R18, R19

R20

Resistor, Chip, 1 kΩ, 1/16W, 5%

Resistor, Chip, 2 Ω, 1W, 5%

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APPLICATION INFORMATION

Inductor Selection

The bq24630 has 300kHz switching frequency to allow the use of small inductor and capacitor values. Inductor

saturation current should be higher than the charging current (I_CHARGE) plus half the ripple current (I_RIPPLE):

I

³ I

+ (1/2) I

SAT

CHG RIPPLE

(12)

The inductor ripple current depends on input voltage (V_IN), duty cycle (D=V_OUT/V_IN), switching frequency (f_s) and

inductance (L):

V

´ D ´ (1 - D)

IN

I_RIPPLE

=

f_S´ L

(13)

The maximum inductor ripple current happens with D = 0.5. For example, the battery charging voltage range is

from 2.8V to 14.4V for 4-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum

inductor ripple current.

Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between

inductor size and efficiency for a practical design.

The bq24630 has cycle-by-cycle charge under current protection (UCP) by monitoring charging current sensing

resistor to prevent negative inductor current. The Typical UCP threshold is 5mV falling edge corresponding to

0.5A falling edge for a 10mΩ charging current sensing resistor.

Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at

50% duty cycle, then the worst case capacitor RMS current I_CINoccurs where the duty cycle is closest to 50%

and can be estimated by the following equation:

I_CIN= I_CHG

´

D ´ (1-D)

(14)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred

for 20V input voltage. 20µF capacitance is suggested for typical of 3-4A charging current.

Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current I_COUTis given:

I

RIPPLE

I

=

» 0.29 ´ I

RIPPLE

COUT

2 ´

3

(15)

The output capacitor voltage ripple can be calculated as follows:

æ

ç

è

ö

÷

ø

V_OUT

DV_o=

1-

2

V

8LCf_s

IN

(16)

At certain input/output voltage and switching frequenccy, the voltage ripple can be reduced by increasing the

output filter LC.

The bq24630 has internal loop compensator. To get good loop stability, the resonant frequency of the output

inductor and output capacitor should be designed between 10 kHz and 15 kHz. The preferred ceramic capacitor

is 25V, X7R or X5R for 4-cell application.

Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are

internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are

preferred for 20V input voltage and 40V MOSFETs are prefered for 20-28V input voltage.

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Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction

loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,

R_DS(ON), and the gate-to-drain charge, Q_GD. For bottom side MOSFET, FOM is defined as the product of the

MOSFET's on-resistance, R_DS(ON), and the total gate charge, Q_G.

FOM_top= R_DS(on)´ Q_GD

FOM_bottom= R_DS(on)´ Q_G

(17)

The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON)has higher cost with the same

package size.

The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle

(D=V_OUT/V_IN), charging current (I_CHARGE), MOSFET's on-resistance R_DS(ON)), input voltage (V_IN), switching

frequency (F), turn on time (t_on) and turn off time (t_toff):

1

2

= D ´ I_CHG´ R_DS(on)

P

+

´ V ´ I_CHG

´

t_on+ t_off´ f

S

(

)

top

IN

2

(18)

The first item represents the conduction loss. Usually MOSFET R_DS(ON)increases by 50% with 100ºC junction

temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are

given by:

Q

SW

t

=

, t

=

off

on

I

on

off

(19)

where Q_swis the switching charge, I_onis the turn-on gate driving current and Ioff is the turn-off gate driving

current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge

(Q_GD) and gate-to-source charge (Q_GS):

1

Q

= Q

+

´ Q

GS

SW

GD

2

(20)

Gate driving current total can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_plt), total

turn-on gate resistance (Ron) and turn-off gate resistance R_off) of the gate driver:

V_REGN- V_plt

V_plt

I_on

=

, I_off=

R_on

R_off

(21)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in

synchronous continuous conduction mode:

2

= (1 - D) ´ I_CHG´ R_DS(on)

P

bottom

(22)

If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the

average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the

switching cycle to prevent negative inductor current.

As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum

charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing

resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body

diode capable of carrying the maximum non-synchronous mode charging current.

MOSFET gate driver power loss contributes to the domainant losses on controller IC, when the buck converter is

switching. Choosing the MOSFET with a small Q_{g_total}will reduce the IC power loss to avoid thermal shut down.

P

= V ×Q_{g_total}×f_s

IN

ICLoss_driver

(23)

Where Q_{g_total}is the total gate charge for both upper and lower MOSFET at 6V V_REGN.

The VREF load current is another component on VCC input current (Do not overload VREF) where total IC loss

can be described by following equations:

P_VREF= (V_IN- V_VREF)×I_VREF

P

= P

+ P_VREF+ P_Quiescent

ICLOSS

ICLOSS _ driver

(24)

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Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second

order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The

input filter must be carefully designed and tested to prevent over voltage event on VCC pin. ACP/ACN pin needs

to be placed after the input ACFETs in order to avoid the over voltage stress and high dv/dt during hot-plug-in.

There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic

capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin

voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.

However these two solutions may not have low cost or small size.

A cost effective and small size solution is shown in Figure 23. The R1 and C1 are composed of a damping RC

network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used

for reverse voltage protection for VCC pin ( it can be the body diode of input ACFET). C2 is VCC pin decoupling

capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form a damping RC network to

further protect the IC from high dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can

dominant the equivalent ESR value to get enough damping effetc for hot plug-in. R1 and R2 package must be

sized enough to handle static current and inrush current power loss according to resistor manufacturer’s

datasheet. The filter components value always need to be verified with real application and minor adjustments

may need to fit in the real application circuit.

D1

(1206)

R2

4.7-30W

R1

2 W

(2010)

Adapter

connector

VCC pin

C1

2.2 mF

C2

0.1-1 mF

Figure 23. Input Filter

PCB Layout

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Figure 24) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper

layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use

shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on

different layers and using vias to make this connection.

2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal

traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching

MOSFETs.

3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to

carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop

area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for

best current accuracy). Place decoupling capacitor on these traces next to the IC.

5. Place output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor

ground before connecting to system ground.

7. Route analog ground separately from power ground and use single ground connection to tie charger power

ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins

to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground

and power ground together using PowerPAD as the single ground connection point. Or using a 0Ω resistor to

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tie analog ground to power ground (PowerPAD should tie to analog ground in this case). A star-connection

under PowerPAD is highly recommended.

8. It is critical that the exposed PowerPAD on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

10. All via size and number should be enough for a given current path.

L1

R1

V

BAT

SW

High

Frequency

Current

Path

V

BAT

IN

C2

C3

C1

PGND

Figure 24. High Frequency Current Path

Current Direction

R

SNS

Current Sensing Direction

To SRP - SRN pin or ACP - ACN pin

Figure 25. Sensing Resistor PCB Layout

Refer to the EVM design (SLUU396) for the recommended component placement with trace and via locations.

For the QFN information, refer to SCBA017 and SLUA271.

28

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Product Folder Link(s): bq24630

PACKAGE OPTION ADDENDUM

www.ti.com

1-Feb-2010

PACKAGING INFORMATION

Orderable Device

BQ24630RGER

BQ24630RGET

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGE

24

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

VQFN

RGE

24

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24630RGER

BQ24630RGET

VQFN

RGE

24

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Jul-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24630RGER

BQ24630RGET

VQFN

RGE

24

3000

250

346.0

190.5

346.0

212.7

29.0

31.8

Pack Materials-Page 2

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ24630
厂家：	TEXAS INSTRUMENTS
描述：	Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with System Power Selector and Low Iq 独立同步开关模式磷酸锂电池充电器与系统电源选择器和低Iq 电池开关
文件：	总35页 (文件大小：1980K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ24630 [TI]

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