BQ24702 [TI]
MULTICHEMISTRY BATTERY CHARGER CONTROLLER AND SYSTEM POWER SELECTOR; 多化学类型电池充电控制器和系统电源选择器
| 型号： | BQ24702 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTICHEMISTRY BATTERY CHARGER CONTROLLER AND SYSTEM POWER SELECTOR |
| 文件： | 总32页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS553D − MAY 2003 − REVISED JULY 2005
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FEATURES
DESCRIPTION
D
D
Dynamic Power Management, DPM
Minimizes Battery Charge Time
The bq24702/bq24703 is a highly integrated battery
charge controller and selector tailored for notebook and
sub-notebook PC applications.
Integrated Selector Supports Battery
Conditioning and Smart Battery Learn Cycle
The bq24702/bq24703 uses dynamic power
management (DPM) to minimize battery charge time by
maximizing use of available wall-adapter power. This is
achieved by dynamically adjusting the battery charge
current based on the total system (adapter) current.
D
Zero Volt Operation
D
Selector Feedback Circuit Ensures
Break-Before-Make Transition
D
0.4% Charge Voltage Accuracy, Suitable for
Charging Li-Ion Cells
The bq24702/bq24703 uses a fixed frequency, pulse
width modulator (PWM) to accurately control battery
charge current and voltage. Charge current limits can
be programmed from a keyboard controller DAC or by
external resistor dividers from the precision 5-V, 0.6%,
externally bypassed voltage reference (VREF),
supplied by the bq24702/bq24703.
D
4% Charge Current Accuracy
D
300-kHz Integrated PWM Controller for
High-Efficiency Buck Regulation
D
D
D
Depleted Battery Detection and Indication to
Protect Battery From Over Discharge
20-µA Sleep Mode Current for Low Battery
Drain
24-Pin TSSOP Package and 5 mm × 5 mm
QFN package (bq24703 only)
bq24702, bq24703
PW PACKAGE
(TOP VIEW)
bq24703
RHD PACKAGE
(BOTTOM VIEW)
ACDET
ACPRES
ACSEL
BATDEP
SRSET
ACSET
VREF
ACDRV
BATDRV
VCC
1
24
23
22
21
20
19
18
17
16
15
14
2
28
27
26
25
24
23
22
8
9
ACSEL
ACPRES
ACDET
ACDRV
BATDRV
NC
ACN
ACP
NC
3
PWM
VHSP
ALARM
VS
4
10
11
12
13
14
5
6
NC
7
BATP
IBAT
NC
ENABLE
BATSET
COMP
GND
8
SRP
9
SRN
10
11
VCC
ACN
IBAT
ACP 12
13 BATP
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003 − 2004, Texas Instruments Incorporated
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1
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SLUS553D − MAY 2003 − REVISED JULY 2005
DESCRIPTION (continued)
The battery voltage limit can be programmed by using the internal 1.196-V, 0.5% precision reference, making it
suitable for the critical charging demands of lithium-ion cells. Also, the bq24702/bq24703 provides an option to
override the precision reference and drive the error amplifier either directly from an external reference or from a
resistor divider off the 5 V supplied by the integrated circuit.
The selector function allows the manual selection of the system power source, battery or wall-adapter power. The
bq24702/bq24703 supports battery-conditioning and battery-learn cycles through the ACSEL function. The ACSEL
function allows manual selection of the battery or wall power as the main system power. It also provides autonomous
switching to the remaining source (battery or ac power) should the selected system power source terminate (refer
to Table 1 for the differences between the bq24702 and the bq24703). The bq24702/bq24703 also provides an alarm
function to indicate a depleted battery condition.
The bq24702/bq24703 PWM controller is ideally suited for operation in a buck converter for applications when the
wall-adapter voltage is greater than the battery voltage.
DISSIPATION RATINGS
MAXIMUM POWER DISSIPATION
(LOW K BOARD)
MAXIMUM POWER DISSIPATION
(HIGH K BOARD)
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.40
1.20
1
1.60
1.40
1.20
1
MAX Pd (W) @ 500 LFM
MAX Pd (W) @ 250 LFM
MAX Pd (W) @ 500 LFM
MAX Pd (W) @ 250 LFM
MAX Pd (W) @ 150 LFM
MAX Pd (W) @ 0 LFM
MAX Pd (W) @ 150 LFM
MAX Pd (W) @ 0 LFM
0.80
0.60
0.40
0.80
0.60
0.40
0.20
0
θ
θ
θ
θ
= 89.37 C/W @ 0 LFM,
= 77.98 C/W @ 150 LFM,
= 73.93 C/W @ 250 LFM,
= 68.23 C/W @ 500 LFM
JA
JA
JA
JA
θ
θ
θ
θ
= 150.17 C/W @ 0 LFM,
= 110.95 C/W @ 150 LFM,
= 99.81 C/W @ 250 LFM,
= 86.03 C/W @ 500 LFM
JA
JA
JA
JA
0.20
0
25
50
70
85
25
50
70
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
†
‡
The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch, two layer board with 2 ounce copper traces on top of the board.
The JEDEC high K (1s) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1 ounce internal power and ground
planes and 2 ounce copper traces on top and bottom of the board.
2
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SLUS553D − MAY 2003 − REVISED JULY 2005
Table 1. Available Options
SELECTOR OPERATION
CONDITION
−20°C ≤ T ≤ 125°C
bq24702PW
bq24703RHD
J
Battery as Power Source
Battery removal
Automatically selects ac + alarm
Selection based on selector inputs
Automatically selects ac + alarm
Adapter latched until adapter is removed or ac select
toggles.
Battery reinserted
AC as Power Source
AC removal
Automatically selects battery
Automatically selects battery
AC reinserted
Selection based on selector inputs
Selection based on selector inputs
Depleted Battery Condition
Automatically selects ac
Sends ALARM signal
Battery as power source Sends ALARM signal
AC as power source
Sends ALARM signal
Sends ALARM signal
ALARM Signal Active
Depleted battery condition
Depleted battery condition
When selector input is not equal to selector
output (single pulse alarm)
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
Ĕ}
(unless otherwise noted)
Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Battery voltage range: SRP, SRN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Input voltage: ACN, ACP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V
Virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
J
Maximum source/sink current VHSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Maximum ramp rate for V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V/ µs
CC
Maximum sink current ACPRES, COMP, ALARM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 mA
Maximum ramp rate for V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V/ µs
(BAT)
Maximum source/sink current BATDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum source/sink current ACDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum source/sink current PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Maximum source/sink current pulsed ACDRV, (10-µs rise time, 10-µs fall time, 1-ms pulse width, single pulse) 50 mA
Maximum source current VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Maximum source current SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Maximum difference voltage SRP − SRN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
Storage temperature range T
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals. Consult the Packaging section of
the data book for thermal limitations and considerations of the package.
3
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SLUS553D − MAY 2003 − REVISED JULY 2005
RECOMMENDED OPERATING CONDITIONS
(T = T
A OPR
) all voltages relative to Vss
MIN
MAX
28
28
28
28
28
28
5
UNIT
Analog and PWM operation
Selector operation
7.0
Supply voltage, (VCC)
V
4.5
Negative ac current sense, (ACN)
Positive ac current sense, (ACP)
Negative battery current sense, (SRN)
Positive battery current sense, (SRP)
AC or adapter power detection (ACDET)
AC power indicator (ACPRES)
7.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
7.0
5
5
0
0
5
AC adapter power select (ACSEL)
Depleted battery level (BATDEP)
0
5
0
5
Battery charge current programming voltage (SRSET)
Charge enable (ENABLE)
0
2.5
5
0
External override to an internal 0.5% precision reference (BATSET)
Inverting input to the PWM comparator (COMP)
0
2.5
5
0
Battery charge regulation voltage measurement input to the battery—voltage g amplifier (BATP)
m
0
5
Battery current differential amplifier output (IBAT)
System load voltage input pin (VS)
Depleted battery alarm output (ALARM)
Gate drive output (PWM)
0
5
0
0
2.5
5
VHSP
0
VCC
28
VCC
2.5
85
Battery power source select output (BATDRV)
AC or adapter power source selection output (ACDRV)
ACSET
VHSP
0
Operating free-air temperature, T
−40
A
4
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 125°C, 7.0 V
≤ VCC ≤ 28 V , all voltages relative to V ) (unless otherwise specified)
DC DC ss
J
Quiescent Current
PARAMETER
TEST CONDITIONS
MIN
TYP
1.6
22
MAX
6
UNIT
mA
I
I
)
Total chip operating current
ACPRES = High EN = 0
,
1
DD(OP
Total battery sleep current, ac not present
ACPRES = Low
28
µA
DD(SLEEP)
logic interface dc characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
UNIT
V
V
V
V
Low-level output voltage (ACPRES, ALARM)
Low-level input voltage (ACSEL, ENABLE)
High-level input voltage (ACSEL, ENABLE)
Sink current (ACPRES)
I
= 1 mA
OL
OL
0.6
V
IL
1.8
1.5
1.5
V
IH
I
V
V
= 0.4
= 0.4
2
2
2.5
2.5
mA
mA
(SINK1)
(SINK2)
OL
I
Sink current (ALARM)
OL
PWM Oscillator
PARAMETER
TEST CONDITIONS
0°C ≤ T ≤ 85°C
MIN
260
TYP
300
300
MAX
340
UNIT
J
f
Oscillator frequency
kHz
OSC(PWM)
−40°C ≤ T ≤ 125°C
240
350
J
Maximum duty cycle
100%
3.8
Input voltage for maximum dc (COMP)
Minimum duty cycle
V
0%
0.8
Input voltage for minimum dc (COMP)
Oscillator ramp voltage (peak-to-peak)
V
V
1.85
2.15
3.8
2.30
(RAMP)
IK(COMP)
S(COMP)
V
Internal input clamp voltage
(tracks COMP voltage for maximum dc)
4.5
I
Internal source current (COMP)
Error amplifier = OFF, V
= 1 V
70
110
140
µA
(COMP)
Leakage Current
PARAMETER
TEST CONDITIONS
= 5 V
MIN
TYP
MAX
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
UNIT
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
I
I
I
I
I
I
I
I
I
I
I
Leakage current, ACDET
Leakage current, SRSET
Leakage current, ACSET
Leakage current, BATDEP
Leakage current, VS
V
V
V
V
V
V
V
V
V
V
V
L(ACDET)
L(SRSET)
L(ACSET)
L(BATDEP)
L(VS)
(ACDET)
(SRSET)
(ACSET)
(BATDEP)
= 2.5 V
= 2.5 V
= 5 V
= 5 V
(VS)
Leakage current, ALARM
Leakage current, ACSEL
Leakage current, ENABLE
Leakage current, ACPRES
Leakage current, BATP
Leakage current, BATSET
= 5 V
= 5 V
L(ALARM)
L(ACSEL)
L(ENABLE)
L(ACPRES)
L(BATP)
(ALARM)
(ACSEL)
(ENABLE)
(ACPRES)
= 5 V
= 5 V
= 5 V
(BATP)
= 2.5 V
L(BATSET)
(BATSET)
5
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ T ≤ 125°C, 7.0 V
DC
≤ VCC ≤ 28 V , all voltages relative to V ) (unless otherwise specified)
J
DC
ss
Battery Current-Sense Amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
120
90
MAX
UNIT
g
m
Transconductance gain
75
175 mA/V
dB
CMRR Common-mode rejection ratio
See Note 1
Common-mode input (SRP, SRN)
voltage range
V
VCC = SRN, SRP + 2 V
COMP = 1 V,
5
0.5
70
30
2.5
110
V
ICR
I
Sink current (COMP)
(SRP − SRN) = 10 mV
SRSET = 2.5 V,
1.5
85
mA
(SINK)
V
= 16 V,
(SRP)
Input bias current (SRP), See Note 2
Input bias current accuracy
(SRP − SRN) = 100 mV VCC = 28
I
IB
µA
(SRP − SRN) = 100 mV, SRSET= 2.5 V,
−3
0
0
3
2.5
26
(I
I
)
VCC = 28 V, 0 ≤ T ≤ 125°C
SRP − SRN
J
Battery current programming voltage
(SRSET)
V
(SET)
V
0.65 V ≤ SRSET ≤ 2.5 V, 8 V ≤ SRN ≤ 16 V,
See Note 3
A
V
Battery current set gain
24
25
V/V
SRSET = 1.25 V, T = 25°C, See Note 4
−5%
−6%
−3%
−4%
5%
6%
3%
4%
Total battery current-sense mid-scale
accuracy
J
SRSET = 1.25 V, See Note 4
SRSET = 2.5 V, T = 25°C, See Note 4
Total battery current-sense full-scale
accuracy
J
SRSET = 2.5 V, See Note 4
NOTES: 1. Specified by design. Not production tested.
2
I
= I
= (V
/ 50 kΩ) + ((V
− V / 3 kΩ)
(SRN)
(SRN)
(SRP) (SRN)
(SRSET)
(SRP)
example: If (V
= 2.5 V) , (V
− V
= 100 mV) Then I = 83 µA
= I
(SRSET)
(SRP)
(SRP) (SRN)
SRSET
1
3.
I
+
BAT
R
A
SENSE
V
4. Total battery-current set is based on the measured value of (SRP−SRN) = ∆m, and the calculated value of (SRP−SRN) = ∆C, using
(
)
Dm * Dc
SRSET
the measured gain, A . Dc +
, Total accuracy in % +
100, I(SRP) * I(SRN) + 0
V
Dc
A
V
6
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ T ≤ 125°C, 7.0 V
DC
≤ VCC ≤ 28 V , all voltages relative to V ) (unless otherwise specified)
J
DC
ss
Adapter Current-Sense Amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
130
90
MAX UNIT
175 mA/V
dB
g
m
Transconductance gain
75
CMRR Common-mode rejection ratio
See Note 1
V
Common-mode input voltage range (ACP)
Sink current (COMP)
7.0
0.5
V
V
ICR
CC
2.5
I
COMP = 1 V, (ACP − ACN) = 10 mV
1.5
50
mA
(SINK)
ACP = ACN = 28 V,
VCC = 28 V, ACSET = 2.5 V
Input bias current (ACP, ACN)
40
65
I
IB
µA
Input bias current accuracy ratio
ACP = ACN = 28 V, VCC = 28 V,
−3
0
0
3
(I
, I
)
ACSET = 2.5 V, 0 ≤ T ≤ 125°C
(ACP) (ACN)
J
V
(SET)
AC current programming voltage (ACSET)
AC current set gain
2.5
V
0.65 V ≤ ACSET ≤ 2.5 V, 12 V ≤ ACP ≤ 20 V,
See Note 5
A
V
24.5
25.3
26.5
V/V
ACSET = 1.25 V, T = 25°C, See Note 6
−5%
−6%
5%
6%
J
Total ac current-sense mid-scale accuracy
Total ac current-sense full-scale accuracy
ACSET = 1.25 V, See Note 6
ACSET = 2.5 V, T = 25°C, See Note 6
−3.5%
−4%
3.5%
4%
J
ACSET = 2.5 V, See Note 6
Battery Voltage Error Amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
g
Transconductance gain
75
135
90
175 mA/V
dB
m
CMRR Common-mode rejection ratio
See Note 1
V
V
BATSET common-mode input voltage range
1
2.5
V
V
ICR
Internal reference override input threshold voltage
0.20
0.25
1.5
0.35
IT
COMP = 1 V,
(BATP − BATSET) = 10 mV,
BATSET = 1.25 V
I
Sink current COMP
0.5
2.5
mA
V
(SINK)
T = 25°C
J
1.190 1.196 1.202
1.183 1.196 1.203
1.178 1.196 1.204
T = 0°C to 85°C
J
V
Error-amplifier precision reference voltage
ACSET
(FB)
T = −40°C to 125°C
J
1
NOTE: 5. Calculation of the ac current: I
+
AC
R
A
SENSE
V
6. Total ac-current set accuracy is based on the measured value of (ACP−ACN) = ∆c, using the measured gain, A
V.
(
)
Dm * Dc
Dc
ACSET
Dc +
, Total accuracy in % +
100, I(ACP) * I(ACN) + 0
A
V
7
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ T ≤ 125°C, 7.0 V
DC
≤ VCC ≤ 28 V , all voltages relative to V ) (unless otherwise specified)
J
DC
ss
Battery Current Output Amplifier
PARAMETER
TEST CONDITIONS
(SRP − SRN) = 5 mV, See Note 7
(SRP − SRN) = 5 mV, SRP = 12 V,
MIN
TYP
MAX
UNIT
G
Transfer gain
20
V/V
(TR)
Battery current readback output
voltage (IBAT)
V
100
10
mV
I(BAT)
VCC = 18 V,
T = 25°C
J
Line rejection voltage
T = 25°C
J
mV/V
V
CM
Common-mode input range (SRP)
5
0
28
Battery current output voltage range
(IBAT)
V
2.5
V
O(IBAT)
I
Output source current (IBAT)
(SRP − SRN) = 100 mV
(SRP − SRN) = 50 mV, T = 25°C, See Note 7
5
−3%
7.1
9.4
2.4%
20%
mA
S(O)
J
(SRP − SRN) = 50 mV, 0°C ≤ T ≤ 85°C
−20%
−1.5%
−6%
Total battery current readback
full-scale accuracy
J
(SRP − SRN) = 100 mV, T = 25°C, See Note 7
1.2%
8.5%
J
(SRP − SRN) = 100 mV, 0°C < T < 85°C
J
5-V Voltage Reference
PARAMETER
TEST CONDITIONS
MIN
4.985
4.946
4.946
4.926
TYP
5
MAX
5.013
5.013
5.03
UNIT
T = 25°C
J
V
T = 0°C to 85°C
5
J
V
ref
Output voltage (VREF)
T = 40°C to 85°C
5
V
V
J
T = −40°C to 125°C
5
5.03
J
Line regulation
I
= 5 mA
0.1
1.1
20
0.37 mV/V
LOAD
1 mA ≤ I
Load regulation
≤ 5 mA
4
30
mV/mA
mA
LOAD
Short circuit current
8
2.2
5
5V REF output capacitor
Output capacitor equivalent resistor
Capacitance
ESR
10
µF
1000
mΩ
Half Supply Regulator
PARAMETER
TEST CONDITIONS
MIN
− 11
TYP
MAX
UNIT
I
I
= 20 mA, V
CC
= 18 V
V
V
− 10.2
V
CC
− 8.5
1.5
(SINK)
CC
CC
V
Voltage regulation
V
(HSP)
= 1 mA, V
V
= 7 V
(SINK)
CC
IBAT
NOTE: 7. Battery readback transfer gain G
+
TR
(
)
SRP * SRN
8
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SLUS553D − MAY 2003 − REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (CONTINUED)
(−40°C ≤ T ≤ 125°C, 7.0 V
≤ VCC ≤ 28 V , all voltages relative to V ) (unless otherwise specified)
J
DC
DC
ss
MOSFET Gate Drive
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
150
UNIT
Ω
AC driver R
AC driver R
high
low
V
CC
V
CC
V
CC
V
CC
= 18 V, I
= 18 V, I
= 18 V, I
= 1 mA
= 1 mA
85
55
DS(on)
(ACDRV)
(ACDRV)
(BATDRV)
110
600
115
Ω
DS(on)
Battery driver R
high
= 1 mA
= 1 mA
315
70
Ω
DS(on)
DS(on)
Battery driver R
low
= 18 V, I
(BATDRV)
Ω
Time delay from ac driver off to battery
driver on
t
t
ACSEL 2.4 V ⇓ 0.2 V
ACSEL 0.2 V ⇑ 2.4 V
1.2
2.4
2
µs
µs
da
Time delay from battery driver off to ac
driver on
3.3
db
I
I
= −10 mA, VCC = 18 V
V
−0.18
V
−0.09
−0.8
7
O
CC
CC
V
PWM driver high-level output voltage
V
OH
OL
= −50 mA, VCC = 18 V
V
CC
−1.2
V
CC
O
PWM driver R
DS(on)
high
14
+0.4
+1.2
8.5
Ω
I
I
= 10 mA, VCC = 18 V
= 50 mA, VCC = 18 V
V
+0.1
+0.6
5
V
V
O
HSP
HSP
V
PWM driver low-level output voltage
V
V
O
HSP
HSP
PWM driver R
DS(on)
low
Ω
Selector
PARAMETER
TEST CONDITIONS
MIN
TYP
1.246
1.246
1%
MAX UNIT
1.194
1.208
1.286
V
V
AC presence detect voltage
V
(ACPRES)
−40°C to 85°C
1.285
AC presence hysteresis
IT(ACPRES)
d(ACPRES)
t
Deglitch delay for adapter insertion
100
µs
See Note 8
1.194
1.208
0.869
0.880
1.246
1.246
1
1.286
V
V
Battery depletion ALARM trip voltage
No battery detect, switch to ACDRV
V
(BATDEP)
−40°C to 85°C
1.285
bq24702 only, See Note 8
−40°C to 85°C
1.144
V
(NOBAT)
1
1.118
VS < BATP, 50% threshold,
ACSEL 2.4 V ⇓ 0.2 V
t
t
Battery select time (ACSEL low to BATDRV low)
1
2.5
3.5
µs
(BATSEL)
AC select time (ACSEL high to ACDRV low)
VS voltage to enable BATDRV
VS voltage hysteresis
ACSEL 0.2 V ⇑ 2.4 V
BATP = 1 V
1
0.98
20
2.5
1
3.5
1.02
85
µs
V
(ACSEL)
V
(VS)
V
VS > BATP
35
mV
IT(VS)
Zero Volt Operation
PARAMETER
TEST CONDITIONS
MIN
TYP
5.3
MAX UNIT
r
Static drain source on-state resistance
V
CC
= 7 V, T = 125°C, I = 100 mA
8.7
0.840
0.656
Ω
DS(on)
J
O
BATDEP increasing
BATDEP decreasing
0.743
0.570
0.794
0.62
zero volt operation threshold
V
NOTES: 8. Total battery current readback accuracy is based on the measured value of V
, V
, and the calculated value of V ,
IBAT
IBAT IBATm
V
, using the measured value of the transfer gain, GTR.
V
IBATc
* V
IBATm
IBATm
V
IBATc
(
)
V
+ SRP * SRN GTR Total Accuracy in % +
100
IBATc
9. Refer to Table 1 to determine the logic operation of the bq24702 and the bq24703.
9
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SLUS553D − MAY 2003 − REVISED JULY 2005
APPLICATION DIAGRAM
10
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SLUS553D − MAY 2003 − REVISED JULY 2005
BLOCK DIAGRAM
VHSP
20
VCC
22
VREF
7
VREF
VHSP
VOLTAGE
REGULATOR
REFERENCE
ACPRES
ACDET
2
1
ACPRES
ACPRES
300 kHz
HYST
VCC
+
S
R
Q
Q
2 V
PWM
LOGIC
LEVEL
SHIFT
HIGH−SIDE
DRIVE
21
PWM
V
OSC
ACPRES
+
VHSP
ACSEL
3
8
5 V
ENABLE
µ
100
A
BATDA
VTBD
+
BATTERY
Zero Volt
Charging
VOLTAGE
ERROR
13
9
BATP
AMPLIFIER
5 V
+
COMP
ACP
10
12
11
6
BATSET
VCC
Ω
2 k
0.25 V
+
+
V
FB
ACN
ac
SRN
CURRENT
ERROR
Ω
2 k
ACSET
16
15
5
SRP
+
+
AMPLIFIER
SRN
BATTERY
+
CURRENT
ERROR
SRSET
25
AMPLIFIER
VCC
Ω
k
+
0.8 x V
NOBAT
25
ADAPTER
SELECT
DRIVE
Ω
k
NO BATTERY
24
ACDRV
V
+
BATDEP
COMPARATOR
BATDEP
4
DEPLETED
BATTERY
VHSP
2
COMPARATOR
VCC
BATTERY SELECT
LOGIC
BATP
+
BATTERY
SELECT
DRIVE
VS
18
19
AND
23
17
BATDRV
GND
SWITCH TO
BATTERY
ACPRES
ANTI−CROSS
CONDUCT
ALARM
ACSEL
ACDRV
VCC
1
SRP
+
ACSEL
SRN
A=20
14
IBAT
1
2
bq24702 ONLY
bq24703 ONLY
UDG−00137
11
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SLUS553D − MAY 2003 − REVISED JULY 2005
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ACDET
bq24702 bq24703
(PW)
(QFN)
26
25
8
1
I
O
I
AC or adapter power detection
ACDRV
ACN
24
11
12
2
AC or adapter power source selection output
Negative differential input
Positive differential input
ACP
9
I
ACPRES
ACSEL
ACSET
ALARM
BATDEP
BATDRV
BATP
27
28
3
O
I
AC power indicator
3
AC adapter power select
6
I
Adapter current programming voltage
Alarm output
19
4
19
1
O
I
Depleted battery level
23
13
9
24
12
6
O
I
Battery power source select output
Battery charge regulation voltage measurement input to the battery-voltage g amplifier
m
BATSET
COMP
ENABLE
GND
I
External override to an internal precision reference
Inverting input to the PWM comparator
Charge enable
10
8
7
O
I
5
17
14
21
15
16
5
17
13
21
15
16
2
O
O
O
I
Supply return and ground reference
Battery current differential amplifier output
Gate drive output
IBAT
PWM
SRN
Negative differential battery current sense amplifier input
Positive differential battery current sense amplifier input
Battery charge current programming voltage
Operational supply voltage
SRP
I/O
I
SRSET
VCC
22
20
7
22
20
4
I
VHSP
VREF
VS
O
O
I
Voltage source to drive gates of the external MOSFETs
Precision 5-V reference
18
18
System (load) voltage input pin
12
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SLUS553D − MAY 2003 − REVISED JULY 2005
Pin Assignments
ACDET: AC or adapter power detection. This input pin is used to determine the presence of the ac adapter.
When the voltage level on the ACDET pin is less than V , the bq24702/bq24703 is in sleep mode, the
ACPRES
PWM control is disabled, the BATDRV is driven low, and the ACDRV is driven high. This feature can be used
to automatically select battery as the system power source.
ACDRV: AC or adapter power source select output. This pin drives an external P-channel MOSFET used to
switch to the ac wall-adapter as the system power source. When the ACSEL pin is high while the voltage on
the ACDET pin is greater than V
when the ACDET is less than V
, the output ACDRVpin is driven low (V
). This pin is driven high (V
)
ACPRES
HSP
CC
.
ACPRES
ACN, ACP: Negative and positive differential inputs, respectively for ac-to-dc adapter current sense resistor.
ACPRES: This open-drain output pin is used to indicate the presence of ac power. A logic high indicates there
is a valid ac input. A low indicates the loss of ac power. ACPRES is high when the voltage level on the ACDET
pin is greater than V
.
ACPRES
ACSEL: AC adapter power select. This input selects either the ac adapter or the battery as the power source.
A logic high selects ac power, while a logic low selects the battery.
ACSET: Adapter current programming voltage. This input sets the system current level at which dynamic power
management occurs. Adapter currents above this programmed level activate the dynamic power management
and proportionally reduce the available power to the battery.
ALARM: Depleted battery alarm output. This open-drain pin indicates that a depleted battery condition exists.
A pullup on ALARM goes high when the voltage on the BATDEP pin is below V
ALARM output also activates when the selector inputs do not match the selector state.
. On the bq24702, the
ACPRES
BATDEP: Depleted battery level. A voltage divider network from the battery to BATDEP pin is used to set the
battery voltage level at which depletion is indicated by the ALARM pin. See ALARM pin for more details. A
battery depletion is detected when BATDEP is less than V
. A no-battery condition is detected when the
ACPRES
battery voltage is < 80% of the depleted threshold. In a no-battery condition, the bq24702 automatically selects
ac as the input source. If ENABLE = 1, the PWM remains enabled.
BATDRV: Battery power source select output. This pin drives an external P-channel MOSFET used to switch
the battery as the system’s power source. When the voltage level on the ACDET pin is less than V
, the
ACPRES
output of the BATDRV pin is driven low, GND. This pin is driven high (V ) when ACSEL is high and ACDET
CC
> V
.
ACPRES
BATP: Battery charge regulation voltage measurement input to the battery-voltage g amplifier. The voltage
m
on this pin is typically derived from a voltage divider network connected across the battery. In a voltage loop,
BATP is regulated to the V precision reference of the battery voltage g amplifier.
FB
m
BATSET: An external override to an internal precision reference. When BATSET is > 0.25 V, the voltage level
on the BATSET pin sets the voltage charge level. When BATSET ≤ 0.25 V, an internal V reference is
FB
connected to the inverting input of the battery error amplifier. To ensure proper battery voltage regulation with
BATSET, BATSET must be > 1.0 V. Simply ground BATSET to use the internal reference.
COMP: The inverting input to the PWM comparator and output of the g amplifiers. A type II compensation
m
network between COMP and GND is recommended.
ENABLE: Charge enable. A high on this input pin allows PWM control operation to enable charging while a low
on this pin disables and forces the PWM output to a high state. Battery charging is initiated by asserting a logic
1 on the ENABLE pin.
GND: Supply return and ground reference
IBAT: Battery current differential amplifier output. The output of this pin produces a voltage proportional to the
battery charge current. This voltage is suitable for driving an ADC input.
13
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SLUS553D − MAY 2003 − REVISED JULY 2005
PWM: Gate drive output pin drives the P-channel MOSFET for PWM control. The PWM control is active when
ACPRES, ACSEL, and ENABLE are high. PWM is driven low to V
and high to V
.
HSP
CC
SRN, SRP: Differential amplifier inputs for battery current sense. These pins feed back the battery charge
current for PWM control. SRN is tied to the battery terminal. SRP is the source pin for zero volt operation.
SRSET: Battery charge current programmed voltage. The level on this pin sets the battery charge current limit.
VCC: Operational supply voltage.
VHSP: The VHSP pin is connected to a 1-µF capacitor (close to the pin) to provide a stable voltage source to
drive the gates of the external MOSFETs. VHSP = VCC − 10 V for VCC > 10.5 V and VHSP = VCC − 0.5 V for
VCC <10.5 V. A 13-V Zener diode should be placed between VCC and VHSP to prevent MOSFET overstress
during start-up.
VREF: Bypassed precision voltage 5-V output. It can be used to set fixed levels on the inverting inputs of any
one of the three error amplifiers if desired. The tight tolerance is suitable for charging lithium-ion batteries.
VS: System (Load) voltage input pin. The voltage on this pin indicates the system voltage in order to insure a
break before make transition when changing from ac power to battery power. The battery is protected from an
over-voltage condition by disabling the P-channel MOSFET connected to the BATDRV pin if the voltage at VS
is greater than BATP. This function can be eliminated by grounding the VS pin.
14
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SLUS553D − MAY 2003 − REVISED JULY 2005
APPLICATION INFORMATION
Programming the Thresholds
The input-referenced thresholds for battery depleted, ac detection and charge voltage are defined by
dimensioning the external dividers connected to pins BATDEP, ACDET and BATP. This calculation is simple,
and consists of assuming that when the input voltage equals the desired threshold value the voltage at the
related pin is equal to the pin internal reference voltage:
Vinput = Vpin × (1 + Kres)
where:
Vinput = Target threshold, referenced to input signal
Vpin = Internal reference(1.196 V for BATP; 1.246 V for BATDEP, ACDET)
Kres = External resistive divider gain ( for instance: R24/R25 for BATP)
When using external dividers with high absolute value the input bias currents for those pins must be included
in the threshold calculation. On the bq24702/3 the input bias currents increase the actual value for the threshold
voltage, when compared to the values calculated using the internal references and divider gain only:
Vinput = Vpin × (1+Kres) + Vbias
The increase on the threshold voltage is given by:
Vbias = Rdiv × Ipin
where:
Vbias = Voltage increase due to pin bias current
Rdiv = External resistor value for resistor connected from pin to input voltage
Ipin = Maximum pin leakage current
The effect of IB can be reduced if the resistor values are decreased.
Dynamic Power Management
The dynamic power management (DPM) feature allows a cost effective choice of an ac wall-adapter that
accommodates 90% of the system’s operating-current requirements. It minimizes battery charge time by
allocating available power to charge the battery (i.e. I
= I
− I
). If the system plus battery charge
BAT
ADPT
SYS
current exceeds the adapter current limit, as shown in Figure 1, the DPM feature reduces the battery charge
current to maintain an overall input current consumption within user defined power capability of the wall-adapter.
As the system’s current requirements decrease, additional current can be directed to the battery, thereby
increasing battery charge current and minimizing battery charge time.
The DPM feature is inherently designed into the PWM controller by inclusion of the three control loops,
battery-charge regulation voltage, battery-charge current, and adapter-charge current, refer to Figure 2. If any
of the three user programmed limits are reached, the corresponding control loop commands the PWM controller
to reduce duty cycle, thereby reducing the battery charge current.
15
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SLUS553D − MAY 2003 − REVISED JULY 2005
ADAPTER CURRENT LIMIT
ADAPTER CURRENT
SYSTEM CURRENT
BATTERY CHARGE CURRENT
NO
CHARGE
MAXIMUM
CHARGE CURRENT
DYNAMIC POWER
MANAGEMENT
MAXIMUM
CHARGE CURRENT
UDG−00113
Figure 1. Dynamic Power Management
ACDET Operation
The ACDET function senses the loss of adequate adapter power. If the voltage on ACDET drops below the
internal V reference voltage, a loss of ADAPTER power is declared and the bq24702/bq24703 switches
ACPRES
to battery power as the main system power. In addition, the bq24702/bq24703 shuts down its 5-V VREF and
enters a low power sleep mode.
Battery Charger Operation
The bq24702/bq24703 fixed-frequency, PWM controller is designed to provide closed-loop control of battery
charge-current (I ) based on three parameters, battery-float voltage (V
), battery-charge current, and
CH
BAT
adapter charge current (I
). The bq24702/bq24703 is designed primarily for control of a buck converter
ADPT
using a high side P-channel MOSFET device (SW, refer to Figure 2).
The three control parameters are voltage programmable through resistor dividers from the bq24702/bq24703
precision 5-V reference, an external or internal precision reference, or directly via a DAC interface from a
keyboard controller.
Adapter and battery-charge current information is sensed and fed back to two transconductance (g ) amplifiers
m
via low-value-sense resistors in series with the adapter and battery respectively. Battery voltage information is
sensed through an external resistor divider and fed back from the battery to a third g amplifier.
m
Precharge Operation
The precharge operation must be performed using the PWM regulator. The host can set the precharge current
externally by monitoring the ALARM pin to detect a battery depleted condition and programming SRSET voltage
to obtain the desired precharge current level.
16
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SLUS553D − MAY 2003 − REVISED JULY 2005
Zero Volt Operating
The zero volt operation is intended to provide a low current path to close open packs and protect the system
in the event of a pack cell short-circuit condition or if a short is applied to the pack terminal. It is not designed
to precharge depleted packs, as it is disabled at voltages that are not within normal pack operating range for
precharge.
If the voltage at BATDEP pin is below the zero volt operation threshold , charge is enabled (EN=HI), and ac is
selected (ACSEL=HI) the bq24702/3 enters the zero volt operation mode. When the zero volt operation mode
is on, the internal PWM is disabled, and an internal power MOSFET connects SRP to V . The battery charge
CC
current is limited by the filter resistor connected to SRP pin (R19). R19 must be dimensioned to withstand the
worst case power dissipation when in zero volt operation mode.
The zero volt operation mode is disabled when BATDEP is above the zero volt operation threshold, and the main
PWM loop is turned on if charge is enabled, regulating the current to the value set by SRSET voltage. To avoid
errors on the charge current both resistors on the SRP, SRN filter must have the same value. Note, however,
that R21 (connected to SRN) does not dissipate any power when in zero volt operation and can be of minimum
size.
PWM Operation
The three open collector g amplifiers are tied to the COMP pin (refer to Figure 2), which is internally biased
m
up by a 100-µA constant current source. The voltage on the COMP pin is the control voltage (V ) for the PWM
C
comparator. The PWM comparator compares V to the sawtooth ramp of the internally fixed 300-kHz oscillator
C
to provide duty cycle information for the PWM drive. The PWM drive is level-shifted to provide adequate gate
voltage levels for the external P-channel MOSFET. Refer to PWM selector switch gate drive section for gate
drive voltage levels.
Q1
SW
I
+
SW
V
ADPT
V
D1
BAT
ENABLE
CLK
LATCH OUT
S
Q
VCC
OSC
5 V
PWM
DRIVE
RAMP
LEVEL
SHIFT
R
Q
21
PWM
PWM COMPARATOR
FROM ENABLE LOGIC
VHSP
µ
A
100
COMP
10
+
13
BATP
+
BATTERY
VOLTAGE
Z
COMP
ENABLE
1.25 V
BATTERY CHARGE
CURRENT
ADP CURRENT
gm
AMPLIFIERS
UDG−00114
Figure 2. PWM Controller Block Diagram
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Softstart
Softstart is provided to ensure an orderly start-up when the PWM is enabled. When the PWM controller is
disabled (ENABLE = Low), the 100-µA current source pullup is disabled and the COMP pin is actively pulled
down to GND. Disabling the 100-µA pullup reduces current drain when the PWM is disabled. When the
bq24702/bq24703 PWM is enabled (ENABLE = High), the COMP pin is released and the 100-µA pullup is
enabled (refer to Figure 2). The voltage on the COMP pin increases as the pullup charges the external
compensation network connected to the COMP pin. As the voltage on the COMP pin increases the PWM duty
cycle increases linearly as shown in Figure 3.
PERCENT DUTY CYCLE
vs
COMPENSATION VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
1.2
1.7
2.2
2.7
3.2
V
− Compensation Voltage − V
COMP
Figure 3
As any one of the three controlling loops approaches the programmed limit, the g amplifier begins to shunt
m
current away from the COMP pin. The rate of voltage rise on the COMP pin slows due to the decrease in total
current out of the pin, decreasing the rate of duty cycle increase. When the loop has reached the programmed
limit the g amplifier shunts the entire bias current (100 µA) and the duty cycle remains fixed. If any of the control
m
parameters tries to exceed the programmed limit, the g amplifier shunts additional current from the COMP pin,
m
further reducing the PWM duty cycle until the offending parameter is brought into check.
Setting the Battery Charge Regulation Voltage
The battery charge regulation voltage is programmed through the BATSET pin, if the internal precision
reference is not used. The BATSET input is a high-impedance input that is driven by either a keyboard controller
DAC or via a resistor divider from a precision reference (see Figure 4).
The battery voltage is fed back to the g amplifier through a resistor divider network. The battery charge
m
regulation voltage can be defined as:
(
)
R1 ) R2 V
BATSET
V
+
V ) I
R1
BATTERY
BATP
R2
(1)
where I
= input bias current for pin BATP
BATP
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SLUS553D − MAY 2003 − REVISED JULY 2005
The overall accuracy of the battery charge regulation voltage is a function of the bypassed 5-V reference voltage
tolerance as well as the tolerances on R1 and R2. The precision voltage reference has a 0.5% tolerance making
it suitable for the tight battery voltage requirements of Li-ion batteries. Tolerance resistors of 0.1% are
recommended for R1 and R2 as well as any resistors used to set BATSET.
The bq24702/bq24703 provides the capability of using an internal precision voltage reference through the use
of a multiplexing scheme, refer to Figure 4, on the BATSET pin. When BATSET voltage is less than 0.25 V, an
internal reference is switched in and the BATSET pin is switched out from the g amplifier input. When the
m
BATSET voltage is greater than 0.25 V, the BATSET pin voltage is switched in to the input of the g amplifier
m
and the voltage reference is switched out.
NOTE:The minimum recommended BATSET is 1.0 V, if BATSET is used to set the voltage loop.
V
BAT
BATP
COMP
13
9
10
gm AMPLIFIER
+
BATSET
0.25 V
1.25 V
V
BAT
(a) V
BATSET
< 0.25 V
R1
BATP
COMP
VREF = 5 V
13
9
10
gm AMPLIFIER
+
R2
BATSET
0.25 V
1.196 V
UDG−00116
(b) V
BATSET
> 1 V
Figure 4. Battery Error Amplifier Input Multiplexing Scheme
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SLUS553D − MAY 2003 − REVISED JULY 2005
Programming the Battery Charge Current
The battery charge current is programmed via a voltage on the SRSET pin. This voltage can be derived from
a resistor divider from the 5-V VREF or by means of an DAC. The voltage is converted to a current source that
is used to develop a voltage drop across an internal offset resistor at one input of the SR g amplifier. The charge
m
current is then a function of this voltage drop and the sense resistor (R ), refer to Figure 5.
S
R
S
COMP 10
SRP
SRN
2 k
Ω
16
15
+
V
REF
SRSET
5
+
25 kΩ
UDG−00117
Figure 5. Battery Charge Current Input Threshold Function
The battery charge current can be defined as:
V
SRSET
I
+
BAT
25 R
S
(2)
where V
is the programming voltage on the SRSET pin. V
maximum is 2.5 V.
SRSET
SRSET
Programming the Adapter Current
Like the battery charge current described previously, the adapter current is programmed via a voltage on the
ACSET pin. That voltage can either be from an external resistor divider from the 5-V VREF or from an external
DAC. The adapter current is defined as:
V
ACSET
I
+
ADPT
25 R
S2
(3)
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SLUS553D − MAY 2003 − REVISED JULY 2005
COMPONENT SELECTION
MOSFET Selection
MOSFET selection depends on several factors, namely, gate-source voltage, input voltage, and input current.
The MOSFET must be a P-channel device capable of handling at least 15-V gate-to-source with a drain-source
breakdown of V ~ V +1 V. The average input current can be approximated by:
BV
IN
(
)
I
avg + D Ichg
A
IN
D = Duty cycle
Ichg = Charge current
(4)
(5)
The RMS current through the MOSFET is defined as:
Ǹ
(
)
I
RMS + Ichg
D A
IN
RMS
The rise/fall times for pin PWM for the selected MOSFET should be greater than 40 nsec.
Schottky Rectifier (Freewheeling)
The freewheeling Schottky rectifier must also be selected to withstand the input voltage, V . The average
IN
current can be approximated from:
(
)
(
)
I
avg + Ichg 1 * D A
D1
(6)
Choosing an Inductance
Low inductance values result in a steep current ramp or slope. Steeper current slopes result in the converter
operating in the discontinuous mode at a higher power level. Steeper current slopes also result in higher output
ripple current, which may require a higher number or more expensive capacitors to filter the higher ripple current.
In addition, the higher ripple current results in an error in the sensed battery current particularly at lower charging
currents. It is recommended that the ripple current not exceed 20% to 30% of full scale dc current.
D ǒVIN
Ǔ
* V
BAT
Ichg Ripple
L +
F
S
Ripple = % Ripple allowed (Ex.: 0,2 for 20% ripple)
(7)
Too large an inductor value results in the current waveform of Q1 and D1 in Figure 2 approximating a
squarewave with an almost flat current slope on the step. In this case, the inductor is usually much larger than
necessary, which may result in an efficiency loss (higher DCR) and an area penalty.
Selecting an Output Capacitor
For this application the output capacitor is used primarily to shunt the output ripple current away from the battery.
The output capacitor should be sized to handle the full output ripple current as defined as:
ǒVIN
Ǔ
* V
D
BAT
L
(
)
I
RMS +
A
c
RMS
F
S
(8)
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Selecting an Input Capacitor
The input capacitor is used to shunt the converter ripple current on the input lines. The capacitor(s) must have
a ripple current (RMS) rating of:
2
2
+ Ǹ[
(
)]
[
]
(
)
I
Ichg 1–D D ) Ichg D 1–D
A
RMS
RMS
(9)
In addition to shunting the converter input ripple when the PWM is operating, the input capacitor also acts as
part of an LC filter, where the inductance component is defined by the ac adapter cable inductance and board
trace inductance from adapter connector to filter capacitor. Overshoot conditions can be observed at V
during fast load transients when the adapter powers the load or when the adapter is hot-plugged .
line
CC
Increasing the input capacitor value decreases the overshoot at V . Avoid overshoot voltages at V
CC
of the absolute maximum ratings for that pin.
in excess
CC
Compensating the Loop
For the bq24702/bq24703 used as a buck converter, the best method of compensation is to use a Type II
compensation network from the output of the transconductance amplifiers (COMP pin) to ground (GND) as
shown in Figure 2. A Type II compensation adds a pole-zero pair and an additional pole at dc.
The Type II compensation network places a zero at
1
2
1
F
+
ǒ
ǒ
Ǔ
Ǔ
Hz
Hz
Z
p R
C
COMP
Z
(10)
(11)
and a pole at
1
2
1
F
+
P
p R
C
COMP
P
For this battery charger application the following component values: C = 4.7 µF, C = 150 pF, and
Z
P
R
= 100 Ω, provides a closed loop response with more than sufficient phase margin, as long as the LC
COMP
pole [1/2 × PI × sqrt (l×c)] is set below 10 kHz. The SRP/SRN filter (R19, R21, C8) and ACP/ACN filter
(R13/R15/C3) are required to filter noise associated with the PWM switching. To avoid adding secondary poles
to the PWM closed loop system those filters should be set with cutoff frequencies higher than 1 kHz.
Selector Operation
The bq24702/bq24703 allows the host controller to manually select the battery as the system’s main power
source, without having to remove adapter power. This allows battery conditioning through smart battery learn
cycles. In addition, the bq24702/bq24703 supports autonomous supply selection during fault conditions on
either supply. The selector function uses low R
battery run times.
P-channel MOSFETs for reduced voltage drops and longer
DS(on)
NOTE: Selection of battery power whether manual or automatic results in the suspension of battery
charging.
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SLUS553D − MAY 2003 − REVISED JULY 2005
ADAPTER SELECT SWITCH
ADAPTER
INPUT
SYSTEM
LOAD
(bq24702)
PWM
BATTERY
CHARGER
BATTERY
SELECT
SWITCH
BAT
ACDRV
(bq24702) 24
BATTERY
SELECTOR
CONTROL 23
BATDRV
UDG−00119
Figure 6. Selector Control Switches
Autonomous Selection Operation
Adapter voltage information is sensed at the ACDET pin via a resistor divider from the adapter input. The voltage
on the ACDET pin is compared to an internally fixed threshold. An ACDET voltage less than the set threshold
is considered as a loss of adapter power regardless of the actual voltage at the adapter input. Information
concerning the status of adapter power is fed back to the host controller through ACPRES. The presence of
adapter power is indicated by ACPRES being set high. A loss of adapter power is indicated by ACPRES going
low regardless of which power source is powering the system. During a loss of adapter power, the
bq24702/bq24703 obtains operating power from the battery through the body diode of the P-channel battery
select MOSFET. Under a loss of adapter power, ACPRES (normally high) goes low, if adapter power is selected
to power the system, the bq24702/bq24703 automatically switches over to battery power by commanding
ACDRV high and BATDRV low. During the switch transition period, battery power is supplied to the load via the
body diode of the battery select P-channel MOSFET. When adapter power is restored, the bq24702/bq24703
configures the selector switches according to the state of signals; ACSEL, and ACPRES. If the ACSEL pin is
left high when ac power is restored, the bq24702/bq24703 automatically switches back to ac power. To remain
on battery power after ac power is restored, the ACSEL pin must be brought low.
Conversely, if the battery is removed while the system is running on battery power and adapter power is present,
the bq24702/bq24703 automatically switches over to adapter power by commanding BATDRV high and
ACDRV low.
NOTE: For the bq24702 any fault condition that results in the selector MOSFET switches not
matching their programmed states is indicated by the ALARM pin momentarily going high. Refer
to Battery Depletion Detection Section for more information on the ALARM discrete.
When switching between the ac adapter and battery the internal logic monitors the voltage at pins ACDRV and
BATDRV to implement a break-before-make function, with typical dead time on the order of 150 nsec.
The turnon times for the external ac/battery switches can be increased to minimize inrush peak currents; that
can be accomplished by adding external resistors in series with the MOSFET gates(R18 and R26). Note,
however, that adding those resistors effectively disables the internal break-before-make function for
ac/battery-switches, as the MOSFET gate voltages can not be monitored directly. If external resistors are added
to increase the rise/fall times for battery/ac switches the break-before-make has to be implemented with discrete
external components, to avoid shoot-through currents between ac adapter and battery pack. This functionality
can be implemented by adding diodes (D2/D9) that bypass the external resistors when turning off the external
FETs.
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SLUS553D − MAY 2003 − REVISED JULY 2005
Smart Learn Cycles When Adapter Power Is Present
Smart learn cycles can be conducted when adapter power is present by asserting and maintaining the ACSEL
pin low. The adapter power can be reselected at the end of the learn cycle by a setting ACSEL to a logic high,
provided that adapter power is present. Battery charging is suspended while selected as the system power
source.
NOTE: On the bq24703 the ac adapter is switched to the load when the battery voltage reaches
the battery depleted threshold; it can be used when the learn cycle does not require the battery
voltage to go below the battery depleted threshold. If the learn cycle algorithm requires the battery
voltage to go lower than the battery depleted voltage, the bq24702 should be used, as it does not
switch the ac adapter to load upon battery depleted detection.
System Break Before Make Function
When selecting the battery as the system primary power source, the adapter power select MOSFET turns off,
in a break-before-make fashion, before the battery select MOSFET turns on. To ensure that this happens under
all load conditions, the system voltage (load voltage) can be monitored through a resistor divider on the VS pin.
This function provides protection against switching over to battery power if the adapter selector switch were
shorted and adapter power present. Setting the VS resistive divider gain with the same gain selected for the
BATP resistive divider assures the battery switch is turned on only when the system voltage is equal or less than
the battery voltage. This function can be eliminated by grounding the VS pin.
The ACDET function senses the adapter voltage via a resistive divider (refer to application circuit).The divider
can be connected either to the anode of the input blocking diode (directly to the adapter supply) or to the cathode
of the input blocking diode (bq24702/3 VCC pin). When the divider is connected to the adapter supply, the
adapter power removal is immediately identified and the sleep mode is entered, disabling the
break-before-make function for system voltage (see section for system power switching) and coupling system
voltage to the battery line. In normal operation with a battery present, the battery low impedance prevents any
over-voltage conditions. However, if a pack is not present or the pack is open, the battery line voltage has a
transient equal to the adapter voltage. The bq24703 SRP/SRN pins are designed to withstand this over-voltage
condition, but avoid connection to the battery line of any external devices that are not rated to withstand the
adapter voltage.
Connecting the ACDET resistive divider input to the VCC node keeps the system break-before-make function
enabled until the voltage at pin VS is lower than the voltage at pin BATP. However, note that when using this
topology the VCC pin voltage can be held by capacitive loads at either the VCC or system (ac switch is on) nodes
when the ac adapter is removed. As the ACDET divider is connected to the VCC line there is a time delay from
ac adapter removal to ac adapter removal detection by the IC. This time is dependent on load conditions and
capacitive load values at VCC and system lines.
Battery Depletion Detection
The bq24702/bq24703 provides the host controller with a battery depletion discrete, the ALARM pin, to alert
the host when a depleted battery condition occurs. The battery depletion level is set by the voltage applied to
the BATDEP pin through a voltage divider network. The ALARM output asserts high and remains high as long
as the battery deplete condition exists, regardless of the power source selected.
For the bq24702, the host controller must take appropriate action during a battery deplete condition to select
the proper power source. The bq24702 remains on the selected power source. The bq24703, however,
automatically reverts over to adapter power, provided the adapter is present, during a deep discharge state. The
battery is considered as being in a deep discharge state when the battery voltage is less than (0.8 × depleted
level).
Feature sets for the bq24702 and bq24703 are detailed in Table 1.
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SELECTOR/ALARM TIMING EXAMPLE
The selector and ALARM timing example in Figure 7 illustrates the battery conditioning support.
NOTE: For manual selection of wall power as the main power source, both the ACPRES and
ACSEL signals must be a logic high.
ACPRES
ACSEL
ACDRV
BATDRV
ALARM
BATTERY
DEPLETE
bq24703 ONLY
CONDITION
UDG−00122
ACSEL
(ACPRES)
t
BATSEL
ACDRV
t
ACSEL
BATDRV
BATDEP< 1 V
t
ACSEL
BATDRV
ACDRV
t
BATSEL
UDG−00120
Figure 7. Battery Selector and ALARM Timing Diagram
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PWM SELECTOR SWITCH GATE DRIVE
Because the external P-channel MOSFETs (as well as the internal MOSFETs) have a maximum gate-source
voltage limitation of the input voltage, VCC, cannot be used directly to drive the MOSFET gate under all input
conditions. To provide safe MOSFET-gate-drive at input voltages of less than an intermediate gate drive voltage
rail was established (VSHP). Where V
all operating conditions.
= VCC − 10 V. This ensures adequate enhancement voltage across
HSP
An external zener diode (D3) connected between VCC and VHSP is required for transient protection; its
breakdown voltage should be above the maximum value for internal VHSP/VCC clamp voltage for all operating
conditions.
TRANSIENT CONDITIONS AT SYSTEM, OVER-VOLTAGE AT SYSTEM TERMINAL
Overshoot conditions can be observed at the system terminal due to fast load transients and inductive
characteristics of the system terminal to load connection. An overshoot at the system terminal can be directly
coupled to the VCC and VBAT nodes, depending on the switch mode of operation. If the capacitors at VBAT
and VCC can not reduce this overshoot to values below the absolute maximum ratings, it is recommended that
an additional capacitor is added to the system terminal to avoid damage to IC or external components due to
voltage overstress under those transient conditions.
AC ADAPTER COLLAPSING DUE TO TRANSIENT CONDITIONS
The ac adapter voltage collapses when the ac switch is on and a current load transient at the system exceeds
the adapter current limit protection. Under those conditions the ac switch is turned off when the ac adapter
voltage falls below the ac adapter detection threshold. If the system terminal to load impedance has an inductive
characteristic, a negative voltage spike can be generated at the system terminal and coupled into the battery
line via the battery switch backgate diode.
In normal operation, with a battery present, this is not an issue, as the low battery impedance holds the voltage
at battery line. However, if a battery is not present or the pack protector switches are open the negative spike
at the system terminal is directly coupled to the SRP/SRN pins via the R19/R21 resistors.
Avoid damage to the SRP/SRN pins if this transient condition happens in the application. If a negative voltage
spike happens at system terminal and R19/R21 limit the current sourced from the pin to less than −50 mA (Ipin
= Vsystem/R19), the pins SRP/SRN are not damaged and the external protection schottky diodes are not
required. However, if the current under those transient conditions exceeds −50 mA, external schottky diodes
must be added to clamp the voltage at pins SRP/SRN so they do not exceed the absolute maximum ratings
specified (−0.3 V).
IBAT AMPLIFIER
A filter with a cutoff frequency smaller than 10 kHz should be added to the IBAT output to remove switching
noise.
POWER DISSIPATION CALCULATION
During PWM operation, the power dissipated internally to the IC increases as the internal driver is switching the
PWM FET on/off. The power dissipation figures are dependent on the external FET used, and can be calculated
using the following equation:
Pd(max) = [IDDOP + Qg × Fs(max)] × VADAP
where:
Qg= Total gate charge for selected PWM MOSFET
IDDOP = Maximum quiescent current for IC
VADAP = Maximum adapter voltage
Fs(max) = Maximum PWM switching frequency
The maximum junction temperature for the IC must be limited to 125°C, under worst case conditions.
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SLUS553D − MAY 2003 − REVISED JULY 2005
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER REFERENCE
BYPASSED 5-V REFERENCE
vs
JUNCTION TEMPERATURE
vs
JUNCTION TEMPERATURE
5.1
5.08
5.06
5.04
5.02
1.215
1.21
1.205
1.2
V
CC
= 18 V
V
CC
= 18 V
1.195
1.19
5
4.98
4.96
4.94
1.185
1.18
4.92
4.9
1.175
−40
−40
10
60
110 125
10
60
110 125
T
J
− Junction Temperature − _C
T
J
− Junction Temperature − _C
Figure 8
Figure 9
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
TOTAL SLEEP CURRENT
vs
JUNCTION TEMPERATURE
335
325
315
305
295
285
275
265
255
245
235
26
24
22
20
18
V
= 18 V
CC
V
CC
= 18 V
16
14
−40
10
60
110 125
−40
10
60
110 125
T
J
− Junction Temperature − _C
T
J
− Junction Temperature − _C
Figure 10
Figure 11
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SLUS553D − MAY 2003 − REVISED JULY 2005
BATTERY CURRENT SET ACCURACY
AC CURRENT SET ACCURACY
vs
vs
BATTERY CURRENT SET VOLTAGE
AC CURRENT SET VOLTAGE
25
20
15
10
25
20
15
10
ACSET Full Scale = 2.5 V
SRSET Full Scale = 2.5 V
= Max Programmed Current
= Max Programmed Current
T
J
= 25°C
T
J
= 25°C
5
0
5
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
V
− Battery Current Set Voltage − V
SRSET
V
ACSET
− AC Current Set Voltage − V
Figure 12
Figure 13
BOARD LAYOUT GUIDELINES
Recommended Board Layout
Follow these guidelines when implementing the board layout:
1. Do not place lines and components dedicated to battery/adapter voltage sensing (ACDET,BATDEP, VS),
voltage feedback loop (BATP, BATSET if external reference is used) and shunt voltage sensing
(SRP/SRN/ACP/ACN) close to lines that have signals with high dv/dt (PWM, BATDRV, ACDRV, VHSP) to
avoid noise coupling.
2. Add filter capacitors for SRP/SRN (C8) and ACP/ACN (C3) close to IC pins
3. Add Reference filter capacitor C1 close to IC pins
4. Use an isolated, clean ground for IC ground pin and resistive dividers used in voltage sensing; use an
isolated power ground for PWM filter cap and diode (C11/D4). Connect the grounds to the battery PACK−
and adapter GND.
5. Place C7 close to VCC pin.
6. Place input capacitor C12 close to PWM switch (U3) source and R14.
7. Position ac switch (U2) to minimize trace length from ac switch source to input capacitor C12.
8. Minimize inductance of trace connecting PWM pin and PWM external switch U3 gate
9. Maximize power dissipation planes connected to PWM switch
10. Maximize power dissipation planes connected to SRP resistor if steady state in zero volt mode is possible
11. Maximize power dissipation planes connected to D1
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PACKAGE OPTION ADDENDUM
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27-Sep-2005
PACKAGING INFORMATION
Orderable Device
BQ24702PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
24
24
24
24
28
28
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BQ24702PWG4
BQ24702PWR
BQ24702PWRG4
BQ24703PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BQ24703PWR
BQ24703PWRG4
BQ24703RHDR
BQ24703RHDRG4
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RHD
RHD
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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