BQ24750A_技术文档

bq24750A

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Host-Controlled Multi-Chemistry Battery Charger with Low I_qand Integrated System

Power Selector

1

FEATURES

•

28-pin, 5x5-mm QFN package

Energy Star Low I_q

•

NMOS-NMOS Synchronous Buck Converter

with 300 kHz Frequency and >95% Efficiency

–

< 10 µA Off-State Battery Discharge Current

30-ns Minimum Driver Dead-time and 99.5%

Maximum Effective Duty Cycle

< 1.5 mA Off-State Input Qiescent Current

High-Accuracy Voltage and Current Regulation

APPLICATIONS

•

Notebook and Ultra-Mobile Computers

Portable Data-Capture Terminals

Portable Printers

Medical Diagnostics Equipment

Battery Bay Chargers

–

±0.5% Charge Voltage Accuracy

±3% Charge Current Accuracy

±3% Adapter Current Accuracy

±2% Input Current Sense Amp Accuracy

•

Integration

Battery Back-up Systems

–

Automatic System Power Selection From

AC/DC Adapter or Battery

Internal Loop Compensation

Internal Soft Start

DESCRIPTION

–

The bq24750A is a high-efficiency, synchronous

battery charger with integrated compensation and

system power selector logic, offering low component

count for space-constrained multi-chemistry battery

charging applications. Ratiometric charge current and

voltage programming allows high regulation

accuracies, and can be either hardwired with resistors

or programmed by the system power-management

microcontroller using a DAC or GPIOs.

Safety

–

Input Overvoltage Protection (OVP)

Dynamic Power Management (DPM) with

Status Indicator

–

Programmable Inrush Adapter Power

(ACOP) and Overcurrent (ACOC) Limits

–

Reverse-Conduction Protection Input FET

Battery Thermistor Sense Input (TS) for

Charge Qualification

•

Supports Two, Three, or Four Li+ Cells

5–24 V AC/DC-Adapter Operating Range

28 27 26 25 24 23 22

CHGEN

ACN

1

2

3

4

5

6

7

21

20

19

DPMDET

CELLS

SRP

Analog Inputs with Ratiometric Programming

via Resistors or DAC/GPIO Host Control

bq24750A

28 LD QFN

TOP VIEW

ACP

–

Charge Voltage (4–4.512 V/cell)

ACDRV

ACDET

ACSET

ACOP

18 SRN

Charge Current (up to 10 A, with 10 mΩ

BAT

17

sense resistor)

SRSET

IADAPT

16

15

–

Adapter Current Limit (DPM)

•

Status and Monitoring Outputs

–

AC/DC Adapter Present with Programmable

Voltage Threshold

8

9

10 11 12 13 14

–

DPM Loop Active

Current Drawn from Input Source

Supports Any Battery Chemistry: Li+, NiCd,

NiMH, Lead Acid, etc.

•

Charge Enable

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24750A

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The bq24750A charges two, three, or four series Li+ cells, supporting up to 10 A of charge current, and is

available in a 28-pin, 5x5-mm QFN package.

The bq24750A controls external switches to prevent battery discharge back to the input, connect the adapter to

the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. For

maximum system safety, inrush-power limiting provides instantaneous response to high input voltage multiplied

by current. This AC Over-Power protection (ACOP) feature limits the input-switch power to the programmed level

on the ACOP pin, and latches off if the high-power condition persists to prevent overheating.

The bq24750A features Dynamic Power Management (DPM) and input power limiting. These features reduce

battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying

the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise

measurement of input current from the AC adapter to monitor the overall system power.

ADAPTER +

ADAPTER -

SYSTEM

R10

2 Ω

C7

C6

RAC

0.010 Ω

P

10 µF

Q1 (ACFET)

SI4435

Q2 (ACFET)

SI4435

C1

2.2 µF

C3

C2

0.1 µF

ACN

432 kΩ

1%

PVCC

0.1 µF

R1

C8

0.1 µF

ACP

/ACDRV

/BATDRV

HIDRV

Q3(BATFET)

SI4435

ACDET

AGND

P

Q4

FDS6680A

66.5 kΩ

1%

R3

VREF

R5

10 kΩ

R2

N

L1

RSR

0.010 Ω

PH

bq24750A

5.6 kΩ

1%

8.2 µH

BTST

PACK+

PACK-

/ACGOOD

TS

D1

BAT54

C9

0.1 µF

C12

10 µF

C11

10 µF

PACK

THERMISTER

SENSE

REGN

R4

118 kΩ

1%

C10

1 µF

C13

0.1 µF

Q5

FDS6680A

SRSET

DAC

LODRV

PGND

C14

0.1 µF

ACSET

VREF

N

C4

1 µF

R6

10 kΩ

SRP

SRN

HOST

/DPMDET

CELLS

/CHGEN

VDAC

GPIO

BAT

C15

0.1 µF

ACOP

C16

0.47 µF

DAC

ADC

VADJ

PowerPad

IADAPT

C5

100 pF

A. V_IN=20 V, V_BAT= 3-cell Li-Ion, I_CHARGE= 3 A, I_{ADAPTER_LIMIT}= 4 A, T_BAT= 0-45°C

Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC

2

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ADAPTER +

ADAPTER -

SYSTEM

R10

2 Ω

C7

C6

RAC

0.010 Ω

P

10 µF

Q1 (ACFET)

SI4435

Q2 (ACFET)

SI4435

C1

2.2 µF

C3

C2

0.1 µF

ACN

432 kΩ

1%

PVCC

0.1 µF

R1

C8

0.1 µF

ACP

/ACDRV

/BATDRV

HIDRV

Q3(BATFET)

SI4435

ACDET

AGND

P

Q4

FDS6680A

66.5 kΩ

1%

VREF

R5

R2

N

L1

R3

5.6 kΩ

1%

RSR

0.010 Ω

PH

bq24750A

10 kΩ

8.2 µH

BTST

PACK+

PACK-

/ACGOOD

TS

D1

BAT54

C9

0.1 µF

C12

10 µF

C11

10 µF

PACK

THERMISTER

SENSE

VREF

REGN

R4

118 kΩ

1%

R7

100 kΩ

C10

1 µF

VREF

R11

C13

0.1 µF

Q5

FDS6680A

SRSET

R8

100 kΩ

43 kΩ

LODRV

PGND

C14

0.1 µF

ACSET

VREF

N

R9

66.5 kΩ

C4

1 µF

R6

10 kΩ

SRP

SRN

HOST

/DPMDET

CELLS

/CHGEN

VDAC

GPIO

BAT

C15

0.1 µF

ACOP

VREF

REGN

C16

0.47 µF

VADJ

PowerPad

IADAPT

ADC

C5

100 pF

A. V_IN=20 V, V_BAT= 3-cell Li-Ion, I_CHARGE= 3 A, I_{ADAPTER_LIMIT}= 4 A, T_BAT= 0-45°C

Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor

ORDERING INFORMATION

ORDERING NUMBER

PART NUMBER

PACKAGE

QUANTITY

(TAPE and REEL)

bq24750ARHDT

bq24750ARHDR

250

bq24750A

28-PIN 5 x 5 mm QFN

3000

PACKAGE THERMAL DATA

over operating free-air temperature range (unless otherwise noted)

POWER RATING

DERATING FACTOR ABOVE

T_A= 70 °C

PACKAGE

θ_JA

T_A= 70°C

QFN – RHD⁽¹⁾⁽²⁾

39 °C/W

2.36 W

0.028 W/°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2x3 via matrix.

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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN

TERMINAL

DESCRIPTION

NAME

NO.

CHGEN

1

Charge enable active-low logic input. LO enables charge. HI disables charge.

Adapter current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND for common-mode

filtering.

ACN

ACP

2

3

Adapter current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide

differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

AC adapter to system-switch driver output. Connect directly to the gate of the ACFET P-channel power MOSFET and

the reverse conduction blocking P-channel power MOSFET. Connect both FETs as common-source. Connect the

ACFET drain to the system-load side. The PVCC should be connected to the common-source node to ensure that the

driver logic is always active when needed. If needed, an optional capacitor from gate to source of the ACFET is used

to slow down the ON and OFF times. The internal gate drive is asymmetrical, allowing a quick turn-off and slower

turn-on in addition to the internal break-before-make logic with respect to the BATDRV. The output goes into linear

regulation mode when the input sensed current exceeds the ACOC threshold. ACDRV is latched off after ACOP

voltage exceeds 2 V, to protect the charging system from an ACFET-overpower condition.

ACDRV

4

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter

input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The I_ADAPT

current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. Input overvoltage, ACOV, disables

charge and ACDRV when ACDET > 3.1 V. ACOV does not latch.

ACDET

ACSET

ACOP

5

6

7

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current

regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC

to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to

the VDAC pin.

Input power limit set input. Program the input over-power time constant by placing a ceramic capacitor from ACOP to

AGND. The capacitor sets the time that the input current limit, ACOC, can be sustained before exceeding the

power-MOSFET power limit. When the ACOP voltage exceeds 2 V, then the ACDRV latches off to protect the charge

system from an over-power condition, ACOP. Reset latch by toggling ACDET or PVCC_UVLO.

Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot

and cold temperature window with a resistor divider from VREF to TS to AGND.

TS

8

9

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the

analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

AGND

VREF

3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage

could be used for ratiometric programming of voltage and current regulation.

10

Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery

voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,

VDAC

11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins

to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output

to VADJ, SRSET, or ACSET.

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage

regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the

output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the

VADJ

12

default of 4.2 V per cell.

Valid adapter active-low detect logic open-drain output. Pulled low when Input voltage is above programmed ACDET.

Connect a 10-kΩ pullup resistor from ACGOOD to VREF, or to a different pullup-supply rail.

ACGOOD

13

Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the

system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path

from battery to system and while discharging the battery pack to the system load. Connect this pin directly to the gate

14 of the input BAT P-channel power MOSFET. Connect the source of the FET to the system load voltage node. Connect

the drain of the FET to the battery pack positive node. An optional capacitor is placed from the gate to the source to

slow-down the switching times. The internal gate drive is asymmetrical to allow a quick turn-off and slower turn-on, in

addition to the internal break-before-make logic with respect to the ACDRV.

BATDRV

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a

100-pF or less ceramic decoupling capacitor from IADAPT to AGND.

IADAPT

SRSET

15

Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current

16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the

output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT

17 pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter

high-frequency noise.

BAT

4

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Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)

TERMINAL

DESCRIPTION

NAME

NO.

Charge current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide

SRN

18 differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from SRN pin to AGND for common-mode

filtering.

Charge current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to provide

differential-mode filtering. A 0.1-µF ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.

SRP

19

CELLS

20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input

21 current is being limited by reducing the charge current. Connect 10-kΩ pullup resistor from DPMDET to VREF or a

different pullup-supply rail. Time delay is 10 ms.

DPMDET

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of

22 low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND

through the PowerPad underneath the IC.

PGND

LODRV

REGN

23 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.

PWM low side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND, close to the

24 IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST. REGN

is disabled when CHGEN is high.

PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET

PH

25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1-µF bootstrap capacitor from from PH to

BTST.

HIDRV

BTST

26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

PWM high side driver positive supply. Connect a 0.1-µF bootstrap ceramic capacitor from BTST to PH. Connect a

27

small bootstrap Schottky diode from REGN to BTST.

IC power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET

28 and source of reverse-blocking power P-channel MOSFET. Place a 0.1-µF ceramic capacitor from PVCC to PGND pin

close to the IC.

PVCC

Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad

to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a

thermal pad to dissipate the heat.

PowerPad

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

VALUE

–0.3 to 30

–1 to 30

–0.3 to 7

UNIT

PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV

PH

REGN, LODRV, VADJ, ACSET, SRSET, TS, ACDET, ACOP, CHGEN, CELLS,

ACGOOD

Voltage range

V

VDAC

–0.3 to 5.5

–0.3 to 3.6

–0.3 to 36

–0.5 to 0.5

–40 to 155

–55 to 155

VREF, IADAPT

BTST, HIDRV with respect to AGND and PGND

Maximum difference voltage ACP–ACN, SRP–SRN, AGND–PGND

Junction temperature range

V

°C

Storage temperature range

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

–1

0

NOM

MAX

24

UNIT

PH

PVCC, ACP, ACN, SRP, SRN, BAT, BATDRV, ACDRV

24

REGN, LODRV

0

6.5

3.6

VDAC, IADAPT

0

Voltage range

VREF

3.3

V

ACSET, SRSET, TS, ACDET, ACOP, CHGEN, CELLS, ACGOOD, DPMDET

0

5.5

6.5

30

VADJ

BTST, HIDRV with respect to AGND and PGND

AGND, PGND

0

–0.3

–40

–55

0.3

125

150

Maximum difference voltage: ACP–ACN, SRP–SRN

Junction temperature range, T_J

V

°C

Storage temperature range, T_stg

ELECTRICAL CHARACTERISTICS

7 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, typical values are at T_A= 25°C, with respect to AGND (unless otherwise noted)

PARAMETER

OPERATING CONDITIONS

V_{PVCC_OP}PVCC Input voltage operating range

CHARGE VOLTAGE REGULATION

V_{BAT_REG_RNG}BAT voltage regulation range

V_{VDAC_OP}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

5

24

V

4-4.512 V per cell, times 2,3,4 cells

8 V, 8.4 V, 9.024 V

8

2.6

18.048

3.6

V

VDAC reference voltage range

VADJ voltage range

V_{ADJ_OP}

0

REGN

0.5%

–0.5%

Charge voltage regulation accuracy 12 V, 12.6 V, 13.536 V

16 V, 16.8 V, 18.048 V

Charge voltage regulation set to

default to 4.2 V per cell

VADJ connected to REGN, 8.4 V, 12.6 V,

16.8 V

–0.5%

0.5%

CHARGE CURRENT REGULATION

Charge current regulation differential

voltage range

V_{IREG_CHG}

V_{SRSET_OP}

V_{IREG_CHG}= V_SRP– V_SRN

0

100

mV

V

SRSET voltage range

0

–3%

VDAC

3%

V_{IREG_CHG}= 40–100 mV

V_{IREG_CHG}= 20 mV

–5%

5%

Charge current regulation accuracy

V_{IREG_CHG}= 5 mV

–25%

–33%

25%

33%

V_{IREG_CHG}= 1.5 mV (V_BAT>4V)

INPUT CURRENT REGULATION

Adapter current regulation

V_{IREG_DPM}

V_{ACSET_OP}

V_{IREG_DPM}= V_ACP– V_ACN

0

100

mV

V

differential voltage range

ACSET voltage range

0

–3%

VDAC

3%

V_{IREG_DPM}= 40–100 mV

V_{IREG_DPM}= 20 mV

V_{IREG_DPM}= 5 mV

–5%

5%

Input current regulation accuracy

–25%

–33%

25%

33%

V_{IREG_DPM}= 1.5 mV

VREF REGULATOR

V_{VREF_REG}

VREF regulator voltage

VREF current limit

V_ACDET> 0.6 V, 0-30 mA

3.267

35

3.3 3.333

80

V

I_{VREF_LIM}

V_VREF= 0 V, V_ACDET> 0.6 V

mA

6

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, typical values are at T_A= 25°C, with respect to AGND (unless otherwise noted)

PARAMETER

REGN REGULATOR

V_{REGN_REG}

I_{REGN_LIM}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REGN regulator voltage

REGN current limit

V_ACDET> 0.6 V, 0-75 mA, PVCC > 10 V

V_REGN= 0 V, V_ACDET> 0.6 V

5.6

90

5.9

6.2

V

135

mA

ADAPTER CURRENT SENSE AMPLIFIER

V_{ACP/N_OP}

V_IADAPT

I_IADAPT

Input common mode range

IADAPT output voltage range

IADAPT output current

Voltage on ACP/ACN

0

24

2

V

1

mA

V/V

A_IADAPT

Current sense amplifier voltage gain A_IADAPT= V_IADAPT/ V_{IREG_DPM}

V_{IREG_DPM}= 40–100 mV

20

–2%

–3%

–25%

–33%

1

2%

3%

V_{IREG_DPM}= 20 mV

Adapter current sense accuracy

V_{IREG_DPM}= 5 mV

25%

33%

V_{IREG_DPM}= 1.5 mV

I_{IADAPT_LIM}

Output current limit

V_IADAPT= 0 V

mA

pF

C_{IADAPT_MAX}

Maximum output load capacitance

For stability with 0 mA to 1 mA load

100

ACDET COMPARATOR

ACDET adapter-detect rising

threshold

Min voltage to enable charging, V_ACDET

rising

V_{ACDET_CHG}

2.376

518

2.40 2.424

40

V

V_{ACDET_CHG_HYS}

ACDET falling hysteresis

ACDET rising deglitch

ACDET falling deglitch

V_ACDETfalling

VACDET rising

VACDET falling

mV

ms

µs

700

10

908

Min voltage to enable all bias, V_ACDET

rising

V_{ACDET_BIAS}

ACDET enable-bias rising threshold

0.56

0.62

0.68

V

V_{ACDET_BIAS_HYS}

Adapter present falling hysteresis

ACDET rising deglitch

V_ACDETfalling

V_ACDETrising

V_ACDETfalling

20

10

mV

µs

ACDET falling deglitch

µs

PVCC / BAT COMPARATOR (REVERSE DISCHARGING PROTECTION)

Differential Voltage from PVCC to

BAT

V_{PVCC-BAT_OP}

–20

140

V

24

V_{PVCC-BAT_FALL}

V_{PVCC-BAT_HYS}

PVCC to BAT falling threshold

PVCC to BAT hysteresis

V_PVCC– V_BATto turn off ACFET

185

50

10

6

240

mV

µs

PVCC to BAT Rising Deglitch

PVCC to BAT Falling Deglitch

V_PVCC– V_BAT> V_{PVCC-BAT_RISE}

V_PVCC– V_BAT< V_{PVCC-BAT_FALL}

µs

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO

AC Undervoltage rising threshold

AC Undervoltage hysteresis, falling

Measured on PVCC

3.5

4

4.5

V

UVLO_(HYS)

260

mV

AC LOW VOLTAGE COMPARATOR (ACLOWV)

AC low voltage rising threshold

V_ACLOWV

3.6

3

Measure on ACP pin

V

AC low voltage falling threshold

ACN / BAT COMPARATOR

V_{ACN-BAT_FALL}

V_{ACN-BAT_HYS}

ACN to BAT falling threshold

ACN to BAT hysteresis

V_ACN– V_BATto turn on BATDRV

175

285

50

20

6

340

mV

µs

ACN to BAT rising deglitch

ACN to BAT falling deglitch

V_ACN– V_BAT> V_{ACN-BAT_RISE}

V_ACN– V_BAT< V_{ACN-BAT_FALL}

µs

BAT OVERVOLTAGE COMPARATOR

V_{OV_RISE}Overvoltage rising threshold

V_{OV_FALL}Overvoltage falling threshold

As percentage of V_{BAT_REG}

104%

102%

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, typical values are at T_A= 25°C, with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHARGE OVERCURRENT COMPARATOR

V_OC

Charge overcurrent falling threshold As percentage of I_{REG_CHG}

Minimum current Limit (SRP-SRN)

145%

50

mV

CHARGE UNDERCURRENT COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)

Charge undercurrent falling

threshold

Changing from synchronous to

non-sysnchronous

V_{ISYNSET_FALL}

V_{ISYNSET_HYS}

9.75

13 16.25

mV

Charge undercurrent rising

hysteresis

8

Charge undercurrent, falling-current

deglitch

20

V_{IREG_DPM}< V_ISYNSET

µs

Charge undercurrent, rising-current

deglitch

640

INPUT OVER-POWER COMPARATOR (ACOP)

ACOC Gain for initial ACOC current Begins 700 ms after ACDET

%

V_ACOC

limit (Percentage of programmed

VIREG_DPM)

Input current limited to this threshold for

fault protection

150

100

2

V_{IREG_DPM}

Maximum ACOC input current limit

(V_ACP–V_ACN)max

Internally limited ceiling

V_{ACOC_MAX}= (V_ACP– V_ACN)max

V_{ACOC_CEILING}

mV

ms

ACOP Latch Blankout Time with

ACOC active

(begins 700 ms after ACDET)

Begins 700 ms after ACDET

(does not allow ACOP latch-off, and no

ACOP source current)

ACOP pin latch-off threshold voltage

(See ACOP in Terminal Functions

table )

V_ACOP

1.95

2

2.05

V

Current source on when in ACOC limit.

Function of voltage across power FET

I_{ACOP_SOURCE}= K_ACOP× (V_PVCC- V_ACP

Gain for ACOP Source Current

when in ACOC

K_ACOP

18

µA / V

)

ACOP Sink Current when not in

ACOC

ACOP Latch is reset by going below

ACDET or UVLO

I_{ACOP_SINK}

Current sink on when not in ACOC

5

µA

INPUT OVERVOLTAGE COMPARATOR (ACOV)

AC Over-voltage rising threshold on

V_ACOV

ACDET

Measured on ACDET

3.007

3.1 3.193

V

(See ACDET in Terminal Functions)

AC Over-voltage rising deglitch

AC Over-voltage falling deglitch

1.3

V_{ACOV_HYS}

ms

THERMAL SHUTDOWN COMPARATOR

Thermal shutdown rising

temperature

T_SHUT

Temperature Increasing

155

20

°C

T_{SHUT_HYS}

Thermal shutdown hysteresis, falling

THERMISTER COMPARATOR (TS)

V_LTF

Cold temperature rising threshold

Rising hysteresis

As percentage to V_VREF

72.5% 73.8% 74.2%

0.5% 1% 1.5%

V_{LTF_HYS}

V_TCO

Cut-off temperature rising threshold As percentage to V_VREF

Hot temperature rising threshold As percentage to V_VREF

Deglitch time for temperature out of V_TS> V_LTF, or V_TS< V_TCO, or

range detection V_TS< V_HTF

Deglitch time for temperature in valid V_TS> V_LTF– V_{LTF_HYS}or V_TS> V_TCO

28.7% 29.3% 29.9%

33.7% 34.4% 35.1%

V_HTF

10

ms

,

range detection

or V_TS> V_HTF

8

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, typical values are at T_A= 25°C, with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BATTERY SWITCH (BATDRV) DRIVER

R_{DS(off)_BAT}

R_{DS(on)_BAT}

BATFET Turn-off resistance

V_ACN> 5 V

160

3

Ω

BATFET Turn-on resistance

kΩ

V_{BATDRV_REG}= V_ACN– V_BATDRVwhen

V_ACN> 5 V and BATFET is on

V_{/BATDRV_REG}

BATFET drive voltage

6.5

V

Delay to turn off BATFET after adapter is

detected (after ACDET > 2.4)

BATFET Power-up delay

518

700

908

ms

AC SWITCH (ACDRV) DRIVER

R_{DS(off)_AC}ACFET turn-off resistance

R_{DS(on)_AC}

V_PVCC> 5 V

80

Ω

ACFET turn-on resistance

ACFET drive voltage

2.5

kΩ

V_{/ACDRV_REG}= V_PVCC– V_/ACDRVwhen

V_PVCC> 5 V and ACFET is on

V_{/ACDRV_REG}

6.5

V

Delay to turn on ACFET after adapter is

detected (after ACDET > 2.4)

ACFET Power-up Delay

518

700

908

ms

AC / BAT MOSFET DRIVERS TIMING

Driver dead time

Dead time when switching between

ACDRV and BATDRV

10

µs

PWM HIGH SIDE DRIVER (HIDRV)

High side driver (HSD) turn-on

resistance

R_{DS(on)_HI}

V_BTST– V_PH= 5.5 V, tested at 100 mA

3

6

Ω

V

R_{DS(off)_HI}

High side driver turn-off resistance

0.7

1.4

Bootstrap refresh comparator

threshold voltage

V_BTST– V_PHwhen low side refresh pulse

is requested

V_{BTST_REFRESH}

4

PWM LOW SIDE DRIVER (LODRV)

Low side driver (LSD) turn-on

R_{DS(on)_LO}

REGN = 6 V, tested at 100 mA

3

6

Ω

resistance

R_{DS(off)_LO}

Low side driver turn-off resistance

0.6

1.2

PWM DRIVERS TIMING

Driver Dead Time — Dead time

when switching between LODRV

and HIDRV. No load at LODRV and

HIDRV

30

ns

PWM OSCILLATOR

F_SW

PWM switching frequency

PWM ramp height

240

300

6.6

360

10

kHz

V_{RAMP_HEIGHT}

As percentage of PVCC

%PVCC

QUIESCENT CURRENT

Total off-state quiescent current into

V_BAT= 16.8 V, V_ACDET< 0.6 V,

V_PVCC> 5 V, T_J= 0 to 85°C

I_{OFF_STATE}

pins: SRP, SRN, BAT, BTST, PH,

PVCC, ACP, ACN

7

µA

I_AC

Adapter quiescent current

V_PVCC= 20 V, charge disabled

1

1.5

mA

Total quiescent current into pins:

SRP, SRN, BAT, BTST, PH

Adapter present, VACDET>2.4V, charge

disabled

I_{BATQ_CD}

100

200

µA

INTERNAL SOFT START (8 steps to regulation current)

Soft start steps

8

step

ms

Soft start step time

1.7

CHARGER SECTION POWER-UP SEQUENCING

Delay from when adapter is detected to

when the charger is allowed to turn on

Charge-enable delay after power-up

518

700

908

ms

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V_PVCC≤ 24 V, 0°C < T_J< +125°C, typical values are at T_A= 25°C, with respect to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

0.8

1

UNIT

LOGIC INPUT PIN CHARACTERISTICS (CHGEN,LEARN)

V_{IN_LO}

Input low threshold voltage

Input high threshold voltage

Input bias current

V

V_{IN_HI}

2.1

I_BIAS

V_/CHGEN= 0 to V_REGN

µA

t_{CHGEN_DEGLITCH}

Charge enable deglitch time

ACDET > 2.4 V, CHGEN rising

2

ms

LOGIC INPUT PIN CHARACTERISTICS (CELLS)

V_{IN_LO}

Input low threshold voltage, 3 cells

CELLS voltage falling edge

0.5

1.8

CELLS voltage rising for MIN,

CELLS voltage falling for MAX

V_{IN_MID}

V_{IN_HI}

Input mid threshold voltage, 2 cells

0.8

2.5

–1

V

Input high threshold voltage, 4 cells CELLS voltage rising

Input bias float current for 2-cell

V_/CHGEN= 0 to V_REGN

selection

I_{BIAS_FLOAT}

1

µA

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACGOOD)

V_{OUT_LO}

Output low saturation voltage

Delay, ACGOOD falling

Delay, ACGOOD rising

Sink Current = 4 mA

0.5

V

518

700

10

908

ms

µs

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( DPMDET )

V_{OUT_LO}

Output low saturation voltage

Delay, DPMDET rising/falling

Sink Current = 5 m

0.5

V

10

ms

10

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TYPICAL CHARACTERISTICS

Table of Graphs⁽¹⁾

Figure

VREF Load and Line Regulation

REGN Load and Line Regulation

BAT Voltage

vs Load Current

Figure 3

vs Load Current

Figure 4

vs VADJ/VDAC Ratio

vs SRSET/VDAC Ratio

vs ACSET/VDAC Ratio

vs Charge Current

Figure 5

Charge Current

Figure 6

Input Current

Figure 7

BAT Voltage Regulation Accuracy

Charge Current Regulation Accuracy

Input Current Regulation (DPM) Accuracy

V_IADAPTInput Current Sense Amplifier Accuracy

Input Regulation Current (DPM), and Charge Current

Transient System Load (DPM) Response

Charge Current Regulation

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

vs System Current

vs BAT Voltage

Efficiency

vs Battery Charge Current

Battery Removal (from Constant Current Mode)

ACDRV and BATDRV Startup

REF and REGN Startup

System Selector on Adapter Insertion with 390-µF SYS-to-PGND System Capacitor

System Selector on Adapter Removal with 390-µF SYS-to-PGND System Capacitor

System Selector on Adapter Insertion

Selector Gate Drive Voltages, 700 ms delay after ACDET

System Selector when Adapter Removed

Charge Enable / Disable and Current Soft-Start

Nonsynchronous to Synchronous Transition

Synchronous to Nonsynchronous Transition

Near 100% Duty Cycle Bootstrap Recharge Pulse

Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation

Continuous Conduction Mode (CCM) Switching Waveforms

Discontinuous Conduction Mode (DCM) Switching

Waveforms

(1) Test results based on Figure 2 application schematic. V_IN= 20 V, V_BAT= 3-cell Li+, I_CHG= 3 A, I_{ADAPTER_LIMIT}= 4 A, T_A= 25°C, unless

otherwise specified.

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VREF LOAD AND LINE REGULATION

REGN LOAD AND LINE REGULATION

vs

Load Current

LOAD CURRENT

0

0.50

0.40

-0.50

-1

0.30

0.20

0.10

PVCC = 10 V

-1.50

-2

PVCC = 10 V

0

PVCC = 20 V

-2.50

-3

-0.10

-0.20

PVCC = 20 V

40 50

0

10

20

30

40

50

0

10

20

30

60

70

80

VREF - Load Current - mA

REGN - Load Current - mA

Figure 3.

Figure 4.

BAT VOLTAGE

vs

VADJ/VDAC RATIO

CHARGE CURRENT

vs

SRSET/VDAC RATIO

10

18.2

18

VADJ = 0 -VDAC,

4-Cell,

No Load

SRSET Varied,

4-Cell,

Vbat = 16 V

9

17.8

17.6

17.4

17.2

17

8

7

6

5

4

3

2

16.8

16.6

16.4

1

0

16.2

16

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

SRSET/VDAC Ratio

VADJ/VDAC Ratio

Figure 5.

Figure 6.

INPUT CURRENT

vs

ACSET/VDAC RATIO

BAT VOLTAGE REGULATION ACCURACY

vs

CHARGE CURRENT

0.2

10

9

ACSET Varied,

4-Cell,

Vbat = 16 V

V

= 16.8 V

reg

8

7

6

5

4

3

2

1

0.1

0

-0.1

-0.2

0

4000

2000

8000

6000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Charge Current - mA

ACSET/VDAC Ratio

Figure 7.

Figure 8.

12

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BAT VOLTAGE REGULATION ACCURACY

CHARGE CURRENT REGULATION ACCURACY

0.10

0.08

0.06

0.04

0.02

0

2

1

4-Cell, VBAT = 16 V

SRSET Varied

VADJ = 0 -VDAC

0

-1

-2

-3

-4

-5

-6

4-Cell, no load

-0.02

-0.04

-7

-8

-0.06

-0.08

-0.10

-9

-10

0

2

4

6

8

16.5

17

17.5

18

18.5

19

I

- Setpoint - A

V

- Setpoint - V

(CHRG)

(BAT)

Figure 9.

Figure 10.

INPUT CURRENT REGULATION (DPM) ACCURACY

V_IADAPTINPUT CURRENT SENSE AMPLIFIER ACCURACY

5

10

9

8

7

6

5

4

3

2

1

0

ACSET Varied

0

V

= 20 V, CHG = EN

I

-5

4-Cell, VBAT = 16 V

V

= 20 V, CHG = DIS

I

-10

-15

-20

-25

Iadapt Amplifier Gain

-1

-2

0

1

2

3

4

5

6

- A

7

8

9

10

0

1

2

3

4

5

6

I

Input Current Regulation Setpoint - A

(ACPWR)

Figure 11.

Figure 12.

INPUT REGULATION CURRENT (DPM), AND CHARGE

CURRENT

vs

SYSTEM CURRENT

TRANSIENT SYSTEM LOAD (DPM) RESPONSE

5

4

3

V

= 20 V,

I

4-Cell,

V

= 16 V

bat

Input Current

2

1

0

System Current

Charge Current

0

1

2

3

4

System Current - A

Figure 13.

Figure 14.

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CHARGE CURRENT REGULATION

EFFICIENCY

vs

BATTERY CHARGE CURRENT

vs

BAT VOLTAGE

5

100

90

V

= 16.8 V

(BAT)

4

3

2

V

= 12.6 V

reg

V

= 8.4 V

reg

80

70

1

0

Ichrg_set = 4 A

8000

0

2

4

6

8

10

12

14

16

18

0

6000

2000

4000

Battery Voltage - V

Battery Charge Current - mA

Figure 15.

Figure 16.

BATTERY REMOVAL

ACDRV AND BATDRV STARTUP

V_ACDET

V_BATDRV

V_ACDRV

V_ACGOOD

t − Time = 100 ms/div

Figure 17.

Figure 18.

SYSTEM SELECTOR ON ADAPTER INSERTION WITH

REF AND REGN STARTUP

390 µF SYS-TO-PGND SYSTEM CAPACITOR

V

BAT

V

SYS

V

ACDRV

V

BATDRV

t − Time = 400 ms/div

Figure 19.

Figure 20.

14

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SYSTEM SELECTOR ON ADAPTER REMOVAL WITH

390 µF SYS-TO-PGND SYSTEM CAPACITOR

SYSTEM SELECTOR ON ADAPTER INSERTION

V

BAT

SYS

V

ACPWR

V

ACDRV

V

ACDRV

V

ACGOOD

V

BATDRV

I

L

t − Time = 2 ms/div

t − Time = 400 ms/div

Figure 21.

Figure 22.

SELECTOR GATE DRIVE VOLTAGES, 700 MS DELAY

AFTER ACDET

SYSTEM SELECTOR ON ADAPTER REMOVAL

V_IN

V

SYS

V_BAT

V

ACDRV

V

ACOP

I_L

I

BAT

t − Time = 200 ms/div

t − Time = 1 ms/div

Figure 23.

Figure 24.

CHARGE ENABLE / DISABLE AND CURRENT

SOFT-START

NONSYNCHRONOUS TO SYNCHRONOUS TRANSITION

V

CHGEN

V

BAT

V

PH

I_BAT

t − Time = 4 ms/div

Figure 25.

Figure 26.

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NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE

SYNCHRONOUS TO NONSYNCHRONOUS TRANSITION

PULSE

Figure 27.

Figure 28.

BATTERY SHORTED CHARGER RESPONSE,

OVERCURRENT PROTECTION (OCP) AND CHARGE

CURRENT REGULATION

CONTINUOUS CONDUCTION MODE (CCM) SWITCHING

WAVEFORMS

Figure 29.

Figure 30.

DISCONTINUOUS CONDUCTION MODE (DCM)

SWITCHING WAVEFORMS

Figure 31.

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FUNCTIONAL BLOCK DIAGRAM

700ms

ENA_BIAS

2.4V

-

0.6V

ACGOOD

PVCC

-

ADAPTER DETECTED

Delay

Rising

+

ACDET

ACOP

VREF

PVCC

-

Isrc=K*V(PVCC-ACP)

K=18 µA/V

ENA_SRC

ENA_SNK

PVCC-6V

LDO

BAT

+

ACOPDET

185mV

PVCC- BAT

-

PVCC

5 µA

2V

ENA_BIAS

ACOP_LATCH

+

S

R

Q

-

SYSTEM

POWER

ACDET

PVCC_UVLO

ACDRV

SELECTOR

LOGIC

CHGEN

VREF

PVCC-6V

ACN

ENA_BIAS

PVCC

3.3V

LDO

EAI

EAO

BATDRV

ACN-6V

ACP

ACN

ACFET_ON

FBO

+

-

V(ACP-ACN)

IIN_ER

-

IIN_REG

COMP

ERROR

AMPLIFIER

+

BTST

CHGEN

-

V(ACN-BAT)

VBAT_REG

-

+

285mV

1V

BAT_OVP

CHG_OCP

ACOV

LEVEL

SHIFTER

BAT_ER

HIDRV

BAT

SRP

-

+

20uA

ACOP

PH

DC-DC

CONVERTER

PWM LOGIC

V(ACN-BAT)

3.5 mA

+

–

V(SRP-SRN)

20x

ICH_ER

-

IBAT_ REG

UVLO

+

PVCC

REGN

LODRV

PGND

IADAPT

DPMDET

20 µA

6V LDO

SRN

ACLOWV

3.5 mA

ENA_BIAS

CHGEN

SYNCH

REFRESH

C^BTST

BTST

4V

CHRG_ON

-

+

_

+

-

V(SRP - SRN)

SYNCH

PH

ACSET

SRSET

VADJ

+

-

13 mV

IC Tj

TSHUT

+

-

155°C

ACP

ACN

+

V(IADAPT)

20x

-

BAT

VBATSET

IBATSET

IINSET

BAT_OVP

CHG_OCP

VBAT_REG

IBAT_REG

IIN_REG

+

104% X VBAT_REG

DPM_LOOP_ON

RATIO

PROGRAM

V(SRP-SRN)

-

+

145% X IBAT_REG

VREF

VDAC

ACDET

-

ACOV

UVLO

+

3.1 V

-

LTF

+

CELLS

AGND

+

-

PVCC

-

TS

ACP

3.0V

ACLOWV

+

-

HTF

TCO

+

-

+

4 V

SUSPEND

-

+

-

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DETAILED DESCRIPTION

Battery Voltage Regulation

The bq24750A uses a high-accuracy voltage regulator for the charging voltage. The internal default

battery-voltage setting is V_BATT= 4.2 V × cell count. The regulation voltage is ratiometric with respect to VDAC.

The ratio of VADJ and VDAC provides an extra 12.5% adjustment range on the V_BATTregulation voltage. By

limiting the adjustment range to 12.5% of the regulation voltage, the external resistor mismatch error is reduced

from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, even while using

1%-mismatched resistors. Ratiometric conversion also allows compatibility with D/As or microcontrollers (µC).

The battery voltage is programmed through VADJ and VDAC using Equation 1.

é

ù

ú

û

æ

ö

÷

ø

V_VADJ

V_BATT= cell count´ 4 V + 0.512´

ê

ç

V_VDAC

ê

ë

è

(1)

The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. V_BATTdefaults

to 4.2 V × cell count when VADJ is connected to REGN.

CELLS pin is the logic input for selecting cell count. Connect CELLS to charge 2,3, or 4 Li+ cells. When charging

other cell chemistries, use CELLS to select an output voltage range for the charger.

CELLS

Float

CELL COUNT

2

3

4

AGND

VREF

The per-cell charge-termination voltage is a function of the battery chemistry. Consult the battery manufacturer to

determine this voltage.

The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the

battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is

recommended to be as close to the BAT pin as possible to decouple high frequency noise.

Battery Current Regulation

The SRSET input sets the maximum charge current. Battery current is sensed by resistor R_SRconnected

between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a

0.010-Ω sense resistor, the maximum charging current is 10 A. SRSET is ratiometric with respect to VDAC using

Equation 2:

V

SRSET 0.10

I

+

CHARGE

V

R

VDAC

SR

(2)

The input voltage range of SRSET is between 0 and V_DAC, up to 3.6 V.

The SRP and SRN pins are used to sense across R_SR, with a default value of 10 mΩ. However, resistors of other

values can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation

accuracy. However, this is at the expense of a higher conduction loss.

Input Adapter Current Regulation

The total input current from an AC adapter or other DC sources is a function of the system supply current and

the battery charging current. System current normally fluctuates as portions of the systems are powered up or

down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system

current and the maximum charger input current simultaneously. By using DPM, the input current regulator

reduces the charging current when the input current exceeds the input current limit set by ACSET. The current

capacity of the AC adapter can be lowered, reducing system cost.

Similar to setting battery regulation current, adapter current is sensed by resistor R_ACconnected between ACP

and ACN. Its maximum value is set ACSET, which is ratiometric with respect to VDAC, using Equation 3.

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V

ACSET 0.10

I

+

ADAPTER

V

R

VDAC

AC

(3)

The input voltage range of ACSET is between 0 and V_DAC, up to 3.6 V.

The ACP and ACN pins are used to sense R_ACwith a default value of 10 mΩ. However, resistors of other values

can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.

However, this is at the expense of a higher conduction loss.

Adapter Detect and Power Up

An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The adapter-detect

threshold should typically be programmed to a value greater than the maximum battery voltage, and lower than

the minimum allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense

the true adapter input voltage whether the ACFET is on or off. Before the adapter is detected, BATFET stays on

and ACFET turns off.

If PVCC is below 5 V, the device is disabled.

If ACDET is below 0.6 V but PVCC is above 5 V, part of the bias is enabled, including a crude bandgap

reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent

current is less than 10 µA.

When ACDET rises above 0.6 V and PVCC is above 5 V, all the bias circuits are enabled and VREF goes to 3.3

V. If CHGEN is LOW, REGN output goes to 6 V. IADAPT becomes valid to proportionally reflect the adapter

current.

When ACDET keeps rising and passes 2.4 V, a valid AC adapter is present. 700 ms later, the following occurs:

•

ACGOOD goes low through external pull-up resistor to the host digital voltage rail;

ACFET can turn on and BATFET turns off consequently; (refer to System Power Selector)

Charging begins if all the conditions are satisfied. (refer to Enable and Disable Charging)

Enable and Disable Charging

The following conditions must be valid before charge is enabled:

•

CHGEN is LOW

PVCC > UVLO, UVLO = 4 V

Adapter is detected

Adapter voltage is higher than BAT + 285 mV

Adapter is not over voltage (ACOV)

700 ms delay is complete after the adapter is detected plus 10 ms ACOC time

Regulators are at 80% of final voltage

Thermal Shut (TSHUT) is not valid

TS is within the temperature qualification window

VDAC > 2.4 V

System Power Selector

The bq24750A automatically switches between connecting the adapter or battery power to the system load. By

default, the battery is connected to the system during power up or when a valid adapter is not present. When the

adapter is detected, the battery is first disconnected from the system, then the adapter is connected. An

automatic break-before-make algorithm prevents shoot-through currents when the selector transistors switch.

The ACDRV signal drives a pair of back-to-back p-channel power MOSFETs (with sources connected together

and to PVCC) connected between the adapter and ACP. The FET connected to the adapter prevents reverse

discharge from the battery to the adapter when it is turned off. The p-channel FET with the drain connected to

the adapter input provides reverse battery discharge protection when off; and also minimizes system power

dissipation, with its low R_DS(on), compared to a Schottky diode. The other p-channel FET connected to ACP

separates the battery from the adapter, and provides both ACOC current limit and ACOP power limit to the

system. The BATDRV signal controls a p-channel power MOSFET placed between BAT and the system.

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When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the

adapter from system. BATDRV stays at ACN – 6 V to connect the battery to system.

At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The ACN

voltage must be 285 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET

and BATFET for 10µs before ACFET turns on. This isolates the battery from shoot-through current or any large

discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to PVCC – 6 V by an

internal regulator to turn on the p-channel ACFET, connecting the adapter to the system.

When the adapter is removed, the system waits till ACN drops back to within 285 mV above BAT to switch from

the adapter back to the battery. The break-before-make logic ensures a 10-µs dead time. The ACDRV output is

pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the p-channel

BATFET, connecting the battery to the system.

Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the

ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The

soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power

MOSFETs.

Automatic Internal Soft-Start Charger Current

The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure

there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of

stepping-up the charger regulation current into 8 evenly divided steps up to the programmed charge current.

Each step lasts approximately 1 ms, for a typical rise time of 8 ms. No external components are needed for this

function.

Converter Operation

The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward

control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the

converter. The compensation input stage is internally connected between the feedback output (FBO) and the

error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input

(EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8

kHz–12.5 kHz.

1

f_o+

Ǹ

2p L_oC_o

The resonant frequency, f_o, is given by:

where (from Figure 1 schematic)

•

C_O= C11 + C12

L_O= L1

An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the

converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to

the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and

simplifies the loop compensation. The ramp is offset by 200 mV in order to allow a 0% duty cycle when the EAO

signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate

with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that

the N-channel upper device always has enough voltage to stay fully on. If the BTST-to-PH voltage falls below 4 V

for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel power

MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver

returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to leakage

current discharging the BTST capacitor below 4 V, and the reset pulse is reissued.

The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input

voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of

the audible noise region. The charge-current sense resistor R_SRshould be designed with at least half or more of

the total output capacitance placed before the sense resistor, contacting both sense resistor and the output

inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance

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should be divided and placed on both sides of the charge-current sense resistor. A ratio of 50:50 percent gives

the best performance; but the node in which the output inductor and sense resistor connect should have a

minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching

noise and give better current-sense accuracy. The Type-III compensation provides phase boost near the

cross-over frequency, giving sufficient phase margin.

Synchronous and Non-Synchronous Operation

The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET internal

setting value. Otherwise, the charger operates in synchronous mode.

During synchronous mode, the low-side N-channel power MOSFET is on when the high-side N-channel power

MOSFET is off. The internal gate-drive logic uses break-before-make switching to prevent shoot-through

currents. During the 30-ns dead time where both FETs are off, the back-diode of the low-side power MOSFET

conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safe

charging at high currents. During synchronous mode, the inductor current always flows, and the device operates

in Continuous Conduction Mode (CCM), creating a fixed two-pole system.

During non-synchronous operation, after the high-side N-channel power MOSFET turns off, and after the

break-before-make dead-time, the low-side N-channel power MOSFET will turn-on for around 80ns, then the

low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power

MOSFET is turned on again. The low-side MOSFET 80-ns on-time is required to ensure that the bootstrap

capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is

important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a

voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between

high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value.

After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring. The

inductor current is blocked by the turned-off low-side MOSFET, and the inductor current becomes discontinuous.

This mode is called Discontinuous Conduction Mode (DCM).

During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole

is proportional to the load current, because the converter does not sink current, and only the load provides a

current sink. This means that at very low currents, the loop response is slower, because there is less sinking

current available to discharge the output voltage. At very low currents during non-synchronous operation, there

may be a small amount of negative inductor current during the 80-ns recharge pulse. The charge should be low

enough to be absorbed by the input capacitance.

Whenever BTST – PH < 4 V, the 80-ns recharge pulse occurs on LODRV, the high-side MOSFET does not turn

on, and the low-side MOSFET does not turn on (only 80-ns recharge pulse).

In the bq24750A, V_ISYNSET=I_SYN×R_SRis internally set to 13mV as the charge-current threshold at which the

charger changes from non-synchronous to synchronous operation. The low-side driver turns on for only 80 ns to

charge the boost capacitor. This is important to prevent negative inductor current, which may cause a boost

effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This

boost effect can lead to excessive voltage on the PVCC node and potential system damage. The inductor ripple

current is given by

I_{RIPPLE_MAX}

£ I_SYN£ I_{RIPPLE_ MAX}

2

and

V_BAT

1

V_IN- V_BAT

(

´

V ´ 1-D ´D´

IN

)

(

)

V

f_s

IN

I_RIPPLE

=

L

(4)

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where:

V_IN

=

adapter voltage

BAT voltage

V_BAT

f_{S =}switching frequency

L = output inductor

D = duty-cycle

I_{RIPPLE_MAX}Happens when the duty-cycle(D) is mostly near to 0.5 at given V_IN, f_s, and L.

The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SRN and

internal threshold. The threshold is set to 13 mV on the falling edge, with an 8-mV hysteresis on the rising edge

with a 10% variation.

High Accuracy IADAPT Using Current Sense Amplifier (CSA)

An industry-standard, high-accuracy current-sense amplifier (CSA) allows a host processor or discrete logic to

monitor the input current through the analog voltage output of the IADAPT pin. The CSA amplifies the input

sensed voltage of ACP – ACN by 20× through the IADAPT pin. The IADAPT output is a voltage source 20× the

input differential voltage. When PVCC is above 5V and ACDET is above 0.6V, IADAPT no longer stays at

ground, but becomes active. If the designer needs to lower the voltage, a resistor divider from IOUT to AGND

can be used, while still achieving accuracy over temperature as the resistors can be matched for their thermal

coefficients.

A 200-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional

RC filter is optional, after the maximum 200-pF capacitor, if additional filtering is desired. Note that adding

filtering also adds additional response delay.

Input Overvoltage Protection (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. The controller enters ACOV

when ACDET > 3.1 V. Charge is disabled, the adapter is disconnected from the system by turning off ACDRV,

and the battery is connected to the system by turning on BATDRV. ACOV is not latched—normal operation

resumes when the ACDET voltage returns below 3.1 V.

Input Undervoltage Lockout (UVLO)

The system must have 5 V minimum of PVCC voltage for proper operation. This PVCC voltage can come from

either the input adapter or the battery, using a diode-OR input. When the PVCC voltage is below 5 V, the bias

circuits REGN, VREF, and the gate drive bias to ACFET and BATFET stay inactive, even with ACDET above

0.6 V.

AC Lowvoltage (ACLOWV)

ACLOWV clears the break-before-make protection latch when ACP < 3V in addition to UVLO clearing this latch

when PVCC < UVLO. It ensures the BATDRV is off when ACP < 3V, and thus this function allows the ACDRV to

turn on the ACFET again when ACP < 3V or PVCC < UVLO.

Battery Overvoltage Protection

The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will

not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This

allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is

disconnected.

Charge Overcurrent Protection

The charger has a secondary overcurrent protection feature. It monitors the charge current, and prevents the

current from exceeding 145% of regulated charge current. The high-side gate drive turns off when the

overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.

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Thermal Shutdown Protection

The QFN package has low thermal impedance, providing good thermal conduction from the silicon to the

ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and

self-protects when the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays off until

the junction temperature falls below 135°C.

Status Register (ACGOOD, DPMDET Pins)

Two status outputs are available, and both require external pullup resistors to pull the pins to the system digital

rail for a high level.

ACGOOD goes low when ACDET is above 2.4 V and the 700-ms delay time is over. It indicates that the adapter

voltage is high enough.

The DPMDET open-drain output goes low (after a 10-ms delay) when the DPM loop is active to reduce the

battery charge current.

Temperature Qualification

The controller continuously monitors the battery temperature by measuring the voltage between the TS pin and

AGND. In a typical application, a negative-temperature-coefficient thermistor (NTC) and an external voltage

divider develop this voltage. The controller compares this voltage against its internal thresholds to determine if

charging is allowed. To initiate a charge cycle, the battery temperature must be within the V_LTFto V_HTF

thresholds. If the battery temperature is outside of this range, the controller suspends charging and waits until the

battery temperature is within the V_LTFto V_HTFrange. During the charge cycle, the battery temperature must be

within the V_LTFto V_TCOthresholds. If the battery temperature is outside this range, the controller suspends

charging and waits until the battery temperature is within the V_LTFto V_HTFrange. The controller suspends

charging by turning off the PWM charge FETs. The V_TSDETvoltage threshold is used to detect whether a battery

is connected. Figure 32 summarizes the operation.

VREF

CHARGE SUSPENDED

V

LTF

V

LTF-HYS

TEMPERATURE RANGE

TO INITIATE CHARGE

TEMPERATURE RANGE

DURING A CHARGE

CYCLE

V

HTF

V

TCO

CHARGE SUSPENDED

AGND

Figure 32. TS, Thermistor Sense Thresholds

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Assuming a 103AT NTC thermistor on the battery pack, as shown in Figure 33, the value RT1 and RT2 can be

determined by using the following equations:

V_VREF

-1

V_LTF

RT1=

1

+

RT2 RTH_COLD

and

æ

ç

è

ö

÷

ø

1

V_VREF´RTH_COLD´RTH_HOT

´

-

V_LTFV_HTF

RT2 =

æ

ç

è

ö

æ

ç

è

ö

V_VREF

RTH_HOT

´

-1 -RTH

´

-1

÷

COLD

V_HTF

V_LTF

ø

(5)

VREF

RT1

RT2

bq24750A

TS

RTH

103AT

Figure 33. TS Resistor Network

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Input Over-Power Protection (ACOP)

The ACOC/ACOP circuit provides a reliable layer of safety protection that can complement other safety

measures. ACOC/ACOP helps to protect from input current surge due to various conditions including:

•

Adapter insertion and system selector connecting adapter to system where system capacitors need to charge

Learn mode exit when adapter is reconnected to the system; system load over-current surge

System shorted to ground

Battery shorted to ground

Phase shorted to ground

High-side FET shorted from drain to source (SYSTEM shorted to PH)

BATFET shorted from drain to source (SYSTEM shorted to BAT)

Several examples of the circuit protecting from these fault conditions are shown below.

For designs using the selector functions, an input overcurrent (ACOC) and input over-power protection function

(ACOP) is provided. The threshold is set by an external capacitor from the ACOP pin to AGND. After the adapter

is detected (ACDET pin > 2.4V), there is a 700-ms delay before ACGOOD is asserted low, and Q3 (BATFET) is

turned-off. Then Q1/Q2 (ACFET) are turned on by the ACDRV pin. When Q1/Q2 (ACFET) are turned on, the

ACFET allows operation in linear-regulation mode to limit the maximum input current, ACOC, to a safe level. The

ACOC current limit is 1.5 times the programmed DPM input current limit set by the ratio of SRSET/VDAC. The

maximum allowable current limit is 100 mV across ACP – ACN (10 A for a 10-mΩ sense resistor).

The first 2 ms after the ACDRV signal begins to turn on, ACOC may limit the current; but the controller is not

allowed to latch off in order to allow a reasonable time for the system voltage to rise.

After 2 ms, ACOP is enabled. ACOP allows the ACFET to latch off before the ACFET can be damaged by

excessive thermal dissipation. The controller only latches if the ACOP pin voltage exceeds 2 V with respect to

AGND. In ACOP, a current source begins to charge the ACOP capacitor when the input current is being limited

by ACOC. This current source is proportional to the voltage across the source-drain of the ACFET (V_PVCC-ACP) by

an 18-µA/V ratio. This dependency allows faster capacitor charging if the voltage is larger (more power

dissipation). It allows the time to be programmed by the ACOP capacitor selected. If the controller is not limiting

current, a fixed 5-µA sink current into the ACOP pin to discharge the ACOP capacitor. This charge and discharge

effect depends on whether there is a current-limit condition, and has a memory effect that averages the power

over time, protecting the system from potentially hazardous repetitive faults. Whenever the ACOP threshold is

exceeded, the charge is disabled and the adapter is disconnected from the system to protect the ACFET and the

whole system. If the ACFET is latched off, the BATFET is turned on to connect the battery to the system.

The capacitor provides a predictable time to limit the power dissipation of the ACFET. Since the input current is

constant at the ACOC current limit, the designer can calculate the power dissipation on the ACFET.

Power = I_d× V_sd= I_{ACOC _ LIM}× V(PVCC - ACP)

The ACOC current Limit threshold is equal to

.

The time it takes to charge to 2V can be calculated from

C_ACOP× DV_ACOP

C

_ACOP× 2V

Dt =

=

i_ACOP

18mA/V × V(PVCC - ACP)

(6)

An ACOP fault latch off can only be cleared by bringing the ACDET pin voltage below 2.4 V, then above 2.4 V

(i.e. remove adapter and reinsert), or by reducing the PVCC voltage below the UVLO threshold and raising it.

Conditions for ACOP Latch Off:

702ms after ACDET (adapter detected), and

a. ACOP voltage > 2V. The ACOP pin charges the ceramic capacitor when in an ACOC current-limit condition.

The ACOP pin discharges the capacitor when not in ACOC current-limit.

b. ACOP protects from a single-pulse ACOC condition depending on duration and source-drain voltage of

ACFET. Larger voltage across ACFET creates more power dissipation so latch-off protection occurs faster,

by increasing the current source out of ACOP pin.

c. Memory effect (capacitor charging and discharging) allows protection from repetitive ACOC conditions,

depending on duration and frequency. (Figure 35)

d. In short conditions when the system is shorted to ground (ACN < 2.4 V)

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In all cases, after 700ms

delay, have input over-

current protection,

ACOC, by linearly limiting

input current.

Threshold is equal to the

lower of Idpm*1.5, or

10A.

ACOC, with ACOP Latch-off,

After Latch-Off, Latch

can only clear by:

Latch-off time accumulates

only when in current limit

1) bringing ACDET below

regulation, ACOC. The time

2.4V, then above 2.4V; or

before latch-off is

programmable with Cacop,

2) bringing PVCC below

and is inversely proportional to

UVLO, then above

source-drain voltage of

700ms delay after

ACDET, before allow

ACDRV to turn-on

UVLO.

ACFET (power). Cacop

charge/discharge per time

also provides memory for

power averaging over time.

ms

700

2ms

8ms

Allow Charge to Turn-on

Vin

Vadapter

ACDET

0V

ACGOOD

BATDRV

ACDRV

Vadapter

Vsystem

Vbattery

Ilim = 1.5xIdpm

(100 mV max

Across ACP_ACN)

Input Current

Allow Charge

Charge Current

V(ACOP)

A. ACFET overpower protection; initial current limit allows safe soft-start without system voltage droop.

Figure 34. ACOC Protection During Adapter Insertion

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Iin

Ilim = 1.5xIdpm

ACOC_REG

V(PVCC-ACP)

LATCH-OFF

Iacop_pin

LATCH-OFF

2V

Memory Effect

V(ACOP)

Averages Power

ON

OFF

ACDRV_ON

LATCH-OFF

Figure 35. ACOC Protection and ACOP Latch Off with Memory Effect Example

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ADAPTER+

R^AC

0.010 Ω

R10

2 Ω

P

ADAPTER-

Q1 (ACFET)

SI4435

Q2 (ACFET)

SI4435

C1

2.2 µF

C3

C2

0.1 µF

ACSET

0.1 µF

ACDRV_ON

ACOC ERROR

AMPLIFIER &

DRIVER

Regulation

Reference

Lowest of

1.5xIDPM_PRG

or

IDPM

Ratio-

/ACDRV

-

+

IDPM_PRG

metric

Program

ACOCREG =

REGULATING

10A (100mV)

(100mV_max)

IIN

Differential Amp

CSA

V(ACP-ACN)

-

ACN

ACP

+

IADAPT

-

+

PVCC

VDS

Differential Amp

V(PVCC-ACP)

C8

0.1 µF

Isrc=K*V(PVCC-ACP)

K=18 µA/V

REF=3.3V

ACOP Adaptor

Over Power

Comparator

ENA_SRC

ACOP

ACDRV

&

ACOPDET

ACOPDETDG

BATDRV

break-

1µs

Deglitch

+

-

ENA_SNK

Cacop

0.47 µF

before-make

logic

5 µA

S

R

Q

Rising-edge Set

& Reset inputs

+

2V

-

ACDET

Turn-off /ACDRV

700 ms

Delay

ACDET

PVCC_UVLO

To clear latch fault , user must remove

adapter and reinsert, or PVCC brought

below then above input UVLO threshold

Figure 36. ACOC / ACOP Circuit Functional Block Diagram

Table 2. Component List for Typical System Circuit of Figure 1

PART DESIGNATOR

QTY

3

DESCRIPTION

Q1, Q2, Q3

Q4, Q5

D1

P-channel MOSFET, –30 V, –6 A, SO-8, Vishay-Siliconix, Si4435

N-channel MOSFET, 30 V, 12.5 A, SO-8, Fairchild, FDS6680A

Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C

2

1

R_AC, R_SR

L1

2

Sense Resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F

Inductor, 8.2 µH, 8.5 A, 24.8 mΩ, Vishay-Dale, IHLP5050CE-01

Capacitor, Ceramic, 2.2 µF, 25 V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E225M

Capacitor, Ceramic, 10 µF, 35 V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M

Capacitor, Ceramic, 1 µF, 25 V, 10%, X7R, 2012, TDK, C2012X7R1E105K

Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU

Capacitor, Ceramic, 100 pF, 25 V, 10%, X7R, 0805, Kemet

Capacitor, Ceramic, 0.47 µF, 25 V, 10%, X7R, 0805, Kemet

Resistor, Chip, 10 kΩ, 1/16 W, 5%, 0402

1

C1

1

C6, C7, C11, C12

C4, C10

4

2

C2, C3, C8, C9, C13, C14, C15

7

C5

1

C16

R5, R6

R1

1

2

1

Resistor, Chip, 432 kΩ, 1/16 W, 1%, 0402

R2

1

Resistor, Chip, 66.5 kΩ, 1/16 W, 1%, 0402

R3

1

Resistor, Chip, 5.6 kΩ, 1/16 W, 1%, 0402

R4

1

Resistor, Chip, 118 kΩ, 1/16 W, 1%, 0402

R10

1

Resistor, Chip, 2 Ω, 1 W, 5%, 2010

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www.ti.com ....................................................................................................................................................................................................... SLUS834–JULY 2008

APPLICATION INFORMATION

Input Capacitance Calculation

During the adapter hot plug-in, the ACDRV has not been enabled. The AC switch is off and the simplified

equivalent circuit of the input is shown in Figure 37.

IIN

VIN

Li

Ri

Rc

Ci

Vi

Vc

Figure 37. Simplified Equivalent Circuit During Adapter Insertion

The voltage on the charger input side V_INis given by:

R

i

t

R_i* R_C

wL_i

V_IN(t) + I_IN(t) R_C) V_Ci(t) + V_ie ^2L

ƪ

_{sin wt ) cos wt}ƫ

i

(7)

in which,

R

æ _Rtö²

i

2L

t

V

1

i

R

= R + R w =

-

I

(t) =

e

sin wt

ç

÷

t

i

IN

C

L C

i

wL

è ^2L_iø

i

R

t

æ

ö

÷

ø

R

2L

t

i

V

(t) = V - Ve

s in wt + coswt

ç

Ci

i

è ^2wL

i

(8)

(9)

The damping conditions is:

L

i

_{R ) R u 2}Ǹ

c

i

C

i

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Figure 38 (a) demonstrates a higher Ci helps dampen the voltage spike. Figure 38 (b) demonstrates the effect of

the input stray inductance Li upon the input voltage spike. Figure 38 (c) shows how increased resistance helps to

suppress the input voltage spike.

35

30

25

20

15

10

5

35

30

25

20

15

10

5

C_i= 20 mF

C_i= 40 mF

L_i= 5 mH

C_i= 12 mH

R_i= 0.21 W

L_i= 9.3 mH

R_i= 0.15 W

C_i= 40 mF

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Time - ms

(a) V_cwith various C_ivalues

(b) V_cwith various L_ivalues

35

30

25

20

15

10

5

R_i= 0.15 W

L_i= 9.3 mH

C_i= 40 mF

R_i= 0.5 W

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Time - ms

(c) V_cwith various R_ivalues

Figure 38. Parametric Study Of The Input Voltage

As shown in Figure 38, minimizing the input stray inductance, increasing the input capacitance, and adding

resistance (including using higher ESR capacitors) helps suppress the input voltage spike. However, a user often

cannot control input stray inductance and increasing capacitance can increase costs. Therefore, the most

efficient and cost-effective approach is to add an external resistor.

Figure 39 depicts the recommended input filter design. The measured input voltage and current waveforms are

shown in Figure 40. The input voltage spike has been well damped by adding a 2Ω resistor, while keeping the

capacitance low.

V

PVCC

IN

2 W

(0.5 W, 1210 anti-surge)

Rext

C1

C2

0.1 mF

(50 V, 0805, very close to PVCC)

2.2 mF

(25 V, 1210)

Figure 39. Recommended Input Filter Design

30

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Figure 40. Adapter DC Side Hot Plug-in Test Waveforms

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PCB Layout Design Guideline

1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the

power ground are connected only at the power pad.

3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The

area of this loop must be minimized. An additional 0.1µF decoupling capacitor for ACN is required to further

reduce noise. The decoupling capacitors for these pins should be placed as close to the IC as possible.

4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact.

The area of this loop must be minimized. An additional 0.1µF decoupling capacitor for SRN is required to

further reduce noise. The decoupling capacitors for these pins should be placed as close to the IC as

possible.

5. Decoupling capacitors for PVCC (pin 28), VREF (pin 10), REGN (pin 24) should be placed underneath the IC

(on the bottom layer) with the interconnections to the IC as short as possible.

6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins

with the interconnections to the IC as short as possible.

7. Decoupling capacitor CX for the charger input must be placed very close to the Q4 drain and Q5 source.

Figure 41 shows the recommended component placement with trace and via locations.

For the QFN information, please refer to the following links: SCBA017 and SLUA271

(a) Top Layer

(b) Bottom Layer

Figure 41. Layout Example

32

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Nov-2008

PACKAGING INFORMATION

Orderable Device

BQ24750ARHDR

BQ24750ARHDT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RHD

28

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RHD

28

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Nov-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

BQ24750ARHDR

QFN

RHD

28

3000

330.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

18-Nov-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RHD 28

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

BQ24750ARHDR

3000

Pack Materials-Page 2

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Applications

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Medical

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amplifier.ti.com

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interface.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ24750A
厂家：	TEXAS INSTRUMENTS
描述：	Host-Controlled Multi-Chemistry Battery Charger with Low Iq and Integrated System Power Selector 主机控制的多化合物电池充电器低Iq和集成系统电源选择器电池
文件：	总39页 (文件大小：1744K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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