BQ25890HRTWR [TI]
具有 NVDC 电源路径和 HVDCP 的 I2C 单节 5A 降压电池充电器 | RTW | 24 | -40 to 85;
| 型号： | BQ25890HRTWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 NVDC 电源路径和 HVDCP 的 I2C 单节 5A 降压电池充电器 | RTW | 24 | -40 to 85 电池 |
| 文件： | 总67页 (文件大小：2136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
BQ25890H I2C 控制型单节电池 5A 快速充电器，采用 MaxChargeTM 技
术，支持高输入电压和可调电压 USB On-the-Go (OTG) 升压模式
1 特性
•
高精度
–
–
–
±0.5% 充电电压调节
1
•
高效率 5A 1.5MHz 开关模式降压充电
±5% 充电电流调节
±7.5% 输入电流调节
–
93% 的充电效率（充电电流为 2A）和 91% 的
充电效率（充电电流为 3A）
–
–
针对高电压输入 (9V/12V) 进行优化
低功耗 PFM 模式，适合轻载运行
•
安全
–
–
用于充电模式和升压模式的电池温度感测
热调节和热关断
•
USB On-the-Go (OTG) 以及 4.5V 至 5.5V 的可调
输出电压范围
2 应用
–
可选 500KHz/1.5MHz 升压转换器，输出电流高
达 2.4A
•
•
•
智能手机
–
–
–
–
5V/1A 输出时的升压效率为 93%
精确的断续模式过流保护
平板电脑
便携式网络设备
支持低至 2.5V 的电池
3 说明
针对轻载效率支持仅 PWM 或 PFM/PWM 控制
bq25890H 是一款适用于单节锂离子电池和锂聚合物电
池的高度集成型 5A 开关模式电池充电管理和系统电源
路径管理器件。此类器件支持高输入电压快速充电。低
阻抗电源路径对开关模式运行效率进行了优化、缩短了
电池充电时间并延长了放电阶段的电池使用寿命。
•
单个输入，支持 USB 输入和可调高电压适配器
–
–
支持 3.9V 至 14V 输入电压范围
输入电流限制（100mA 至 3.25A，分辨率为
50mA），支持 USB2.0、USB3.0 标准和高电
压适配器
–
–
通过输入电压限制（最高 14V）实现最大功率
跟踪，适用于各类适配器
器件信息(1)
器件型号
bq25890H
封装
封装尺寸（标称值）
自动检测 USB SDP、CDP、DCP 以及非标准
适配器
WQFN (24)
4.00mm x 4.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
输入电流优化器 (ICO)，无需过载适配器即可最大
限度提高输入功率
•
•
充电器输出与电池终端间的电阻补偿 (IRCOMP)
简化原理图
借助 11mΩ 电池放电 MOSFET 实现最高电池放电
效率，放电电流高达 9A
Input
3.9Vt14V at 3A
SYS 3.5Vt4.5V
•
•
集成 ADC，用于系统监视
（电压、温度和充电电流）
VBUS
SW
USB
OTG
5V at 2.4A
SYS
窄 VDC (NVDC) 电源路径管理
Ichg = 3A
BAT
–
–
无需电池或使用深度放电的电池即可瞬时接通
电池充电模式下实现理想的二极管运行
I2C Bus
QON
Host
REGN
•
BATFET 控制，支持运输模式、唤醒和完全系统复
位
灵活的自主和 I2C 模式，可实现最优系统性能
bq25890H
Optional
Host Control
TS
•
•
高集成度，包括所有 MOSFET、电流检测和环路补
偿
•
12μA 低电池泄漏电流，支持运输模式
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCC5
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
目录
8.4 Register Maps......................................................... 34
Application and Implementation ........................ 51
9.1 Application Information............................................ 51
9.2 Typical Application .................................................. 51
9.3 System Examples ................................................... 56
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 12
7.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 15
8.1 Functional Block Diagram ....................................... 15
8.2 Feature Description................................................. 16
8.3 Device Functional Modes........................................ 32
9
10 Power Supply Recommendations ..................... 57
11 Layout................................................................... 57
11.1 Layout Guidelines ................................................. 57
11.2 Layout Example .................................................... 57
12 器件和文档支持 ..................................................... 58
12.1 文档支持 ............................................................... 58
12.2 接收文档更新通知 ................................................. 58
12.3 社区资源................................................................ 58
12.4 商标....................................................................... 58
12.5 静电放电警告......................................................... 58
12.6 术语表 ................................................................... 58
13 机械、封装和可订购信息....................................... 58
8
4 修订历史记录
Changes from Original (September 2016) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
Added "SW (peak for 10 ns duration)" To the Absolute Maximum Ratings(1) ....................................................................... 6
Changed VSYS TYP value From: VBAT + 50 mV To: I(SYS) + 150 mV ...................................................................................... 7
Changed the title of 图 4 From: Charge Current Accuracy To: I2C Setting ......................................................................... 13
Changed axis title of 图 8 From: BAT Voltage (V) To: Input Current Limit (mA).................................................................. 13
Changed VVREF to VREGN in 公式 2........................................................................................................................................ 24
Changed VREF to VREGN in 图 16........................................................................................................................................... 25
Added sentence to the Battery Monitor secton "In battery only mode, .."............................................................................ 25
Changed the Description values of 表 26 From: mV To: mA ............................................................................................... 49
Changed the Type values of Bit 7 in 表 28 From: R To: R/W.............................................................................................. 50
Added VREF system pullup voltage to 表 29 ......................................................................................................................... 51
2
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
5 说明 （续）
具有充电和系统设置的 I2C 串行接口使得此器件成为一个真正的灵活解决方案。
bq25890H 是一款适用于单节锂离子电池和锂聚合物电池的高度集成型 5A 开关模式电池充电管理和系统电源路径
管理器件。该器件 支持 高输入电压快速充电，适用于各类智能手机、平板电脑和便携式设备。其低阻抗电源路径
对开关模式运行效率进行了优化、缩短了电池充电时间并延长了放电阶段的电池使用寿命。该器件还集成了输入电
流优化器 (ICO) 和电阻补偿 (IRCOMP)，从而为电池提供最大充电功率。该解决方案在系统和电池之间高度集成输
入反向阻断 FET（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以及电池
FET（BATFET，Q4）。它还集成了自举二极管以进行高侧栅极驱动和电池监视，从而简化系统设计。具有充电和
系统设置的 I2C 串行接口使得此器件成为一个真正的灵活解决方案。
该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口以及兼容 USB 的可调高电压适配器。为支持通
过可调高电压适配器进行快速充电，SN25890H 提供了 MaxChargeTM 握手支持（使用 D+/D- 引脚和 DSEL 引
脚）以进行 USB 开关控制。此外，该器件还提供有相应的接口，以支持采用输入电流脉冲协议的可调高电压适配
器。为设定默认输入电流限值，该器件使用内置 USB 接口，例如 USB PHY 器件。该器件符合 USB 2.0 和 USB
3.0 电源规范，具有输入电流和电压调节功能。此外，输入电流优化器 (ICO) 还能够检测输入源未发生过载时的最
大功率点。该器件还具有高达 2.4A 的限流能力，能够为 VBUS 提供 5V（4.5V-5.5V 可调节）电压，符合 USB
On-the-Go (OTG) 运行功率额定值规范。
电源路径管理将系统电压调节至稍高于电池电压的水平，但是不会下降至 3.5V 最小系统电压（可编程）以下。借
助于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流限值或电压限值
时，电源路径管理自动将充电电流减少为 0。随着系统负载持续增加，电源路径将使电池放电，直到满足系统电源
需求。这种补充模式 工作方式可防止输入源发生过载。
此器件在无需软件控制情况下启动并完成一个充电周期。它自动检测电池电压并通过三个阶段为电池充电：预充
电、恒定电流和恒定电压。在充电周期的末尾，当充电电流低于在恒定电压阶段中预设定的限值时，充电器自动终
止。当整个电池下降到低于再充电阈值时，充电器将自动启动另外一个充电周期。
此充电器提供针对电池充电和系统运行情况的多种安全 特性 ，其中包括电池负温度系数热敏电阻监视、充电安全
计时器和过压/过流保护。当结温超过 120°C（可编程）时，热调节会减小充电电流。STAT 输出报告充电状态和任
何故障状况。 当故障发生时，INT 会立即通知主机。
该器件还提供了一个 7 位模数转换器 (ADC)，用于监视充电电流和输入/电池/系统（VBUS、BAT、SYS、TS）电
压。QON 引脚提供 BATFET 使能/复位控制，以使器件退出低功耗出厂模式或完全系统复位功能。
该器件系列采用 24 引脚 4mm x 4mm2 x 0.75mm 薄型 WQFN 封装。
Copyright © 2016–2018, Texas Instruments Incorporated
3
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
6 Pin Configuration and Functions
BQ25890H
RTW (WQFN)
Top View
23
22
20
19
24
21
VBUS
D+
1
2
3
4
5
6
18
17
PGND
PGND
SYS
16
15
D–
STAT
SCL
SYS
14
BAT
BAT
13
SDA
7
8
9
10
11
12
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
No.
Charger Input Voltage.
VBUS
1
P
The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on
source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
Positive line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter. The pin can be configured as output
driver by DP_DAC register bits when input source is plugged-in or during OTG mode.
D+
D–
2
3
4
AIO
AIO
DO
Negative line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary
and secondary detection in BC1.2, and Adjustable high voltage adapter. The pin can be configured as output
driver by DM_DAC register bits when input source is plugged-in or during OTG mode.
Open drain charge status output to indicate various charger operation.
Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge
complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz.
The STAT pin function can be disabled when STAT_DIS bit is set.
STAT
I2C Interface clock.
Connect SCL to the logic rail through a 10-kΩ resistor.
SCL
SDA
5
6
DI
I2C Interface data.
Connect SDA to the logic rail through a 10-kΩ resistor.
DIO
Open-drain Interrupt Output.
INT
7
DO
Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report
charger device status and fault.
Active high enable pin during boost mode.
The boost mode is activated when OTG_CONFIG =1 and OTG pin is high
OTG
CE
8
9
DI
DI
Active low Charge Enable pin.
Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
4
Copyright © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
No.
Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected
from ILIM pin to ground to set the maximum limit as IINMAX = KILIM/RILIM . The actual input current limit is the
lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500
mA is not support on ILIM pin.
ILIM
10
AI
ILIM pin can also be used to monitor input current when the voltage is below 0.8V. The input current is
proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8)
The ILIM pin function can be disabled when EN_ILIM bit is 0.
Temperature qualification voltage input.
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider
from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2
thermistor.
TS
11
12
AI
DI
BATFET enable/reset control input.
When BATFET is in ship mode, a logic low of tSHIPMODE (typical 1sec) duration turns on BATFET to exit
shipping mode. .
When VBUS is not plugged-in, a logic low of tQON_RST (typical 15sec) duration resets SYS (system power) by
turning BATFET off for tBATFET_RST (typical 0.3sec) and then re-enable BATFET to provide full system power
reset.
QON
The pin contains an internal pull-up to maintain default high logic
Battery connection point to the positive terminal of the battery pack.
The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin.
BAT
SYS
13,14
15,16
P
P
System connection point.
The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system
voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20uF closely to the
SYS pin.
Power ground connection for high-current power converter node.
Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to
ground connection of input and output capacitors of the charger. A single point connection is recommended
between power PGND and the analog GND near the IC PGND pin.
PGND
17,18
P
Switching node connecting to output inductor.
SW
19,20
21
P
P
Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET.
Connect the 0.047µF bootstrap capacitor from SW to BTST.
PWM high side driver positive supply.
Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 µF bootstrap
capacitor from SW to BTST.
BTST
PWM low side driver positive supply output.
Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 µF (10 V rating) ceramic
capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as
bias rail of TS pin.
REGN
PMID
22
23
P
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.
Given the total input capacitance, put 1µF on VBUS to PGND, and the rest capacitance on PMID to PGND.
DO
Active high D+/D- multiplexer selection control.
Connect a 47-nF (6V rating) ceramic capacitor from DSEL to analog GND. The pin is normally low. During
input source type detection, the pin drives high to indicate the device D+/D- detection is in progress and needs
to take control of D+, D- signals. When detection is completed, the pin keeps high when DCP, MaxCharge or
HVDCP is detected. The pin returns to low when other input source type is detected.
DSEL
24
DO
P
Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on
the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.
PowerPAD™
Copyright © 2016–2018, Texas Instruments Incorporated
5
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–2
MAX
22
22
20
7
VALUE
VBUS (converter not switching)
V
V
PMID (converter not switching)
–0.3
–0.3
–0.3
–0.3
–2
STAT
DSEL
BTST
SW
V
V
20
16
16
6
V
V
Voltage range (with respect to GND)
SW (peak for 10 ns duration)
–3
V
BAT, SYS (converter not switching)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
SDA, SCL, INT, OTG, REGN, TS, CE, QON
7
V
D+, D–
7
V
BTST TO SW
PGND to GND
ILIM
7
V
0.3
5
V
V
INT, STAT
DSEL
6
mA
mA
°C
°C
Output sink current
2
Junction temperature
–40
–65
150
150
Storage temperature range, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
7.2 ESD Ratings
VALUE
UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
±2000
V
VESD
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
14(1)
UNIT
V
VIN
Input voltage
3.9
IIN
Input current (VBUS)
Output current (SW)
Battery voltage
3.25
A
ISYS
VBAT
5
A
4.608
5
V
Fast charging current
A
Up to 6 (continuos)
A
IBAT
Discharging current with internal MOSFET
Operating free-air temperature range
9 (peak)
(Up to 1 sec duration)
A
TA
–40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight
layout minimizes switching noise.
6
Copyright © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
7.4 Thermal Information
BQ25890H
THERMAL METRIC(1)
RTW (WQFN)
UNIT
24-PINS
31.8
27.9
8.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC((op)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.7
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VBAT = 4.2 V, V(VBUS) < V(UVLO), leakage
between BAT and VBUS
5
µA
µA
High-Z mode, no VBUS, BATFET disabled
(REG09[5]=1), battery monitor disabled, TJ
85°C
<
<
12
32
23
IBAT
Battery discharge current (BAT, SW, SYS) in buck mode
High-Z mode, no VBUS, BATFET enabled
(REG09[5]=0), battery monitor disabled, TJ
85°C
60
µA
V(VBUS)= 5 V, High-Z mode, no battery, battery
monitor disabled
15
25
1.5
3
35
50
3
µA
µA
Input supply current (VBUS) in buck mode when High-Z mode
is enabled
I(VBUS_HIZ)
V(VBUS)= 12 V, High-Z mode, no battery,
battery monitor disabled
VBUS > V(UVLO), VBUS > VBAT, converter not
switching
mA
mA
mA
mA
mA
VBUS > V(UVLO), VBUS > VBAT, converter
switching, VBAT = 3.2 V, ISYS = 0A
I(VBUS)
Input supply current (VBUS) in buck mode
Battery discharge current in boost mode
VBUS > V(UVLO), VBUS > VBAT, converter
switching, VBAT = 3.8 V, ISYS = 0 A
3
VBAT = 4.2 V, boost mode, I(VBUS)= 0 A,
converter switching, PFM_OTG_DIS=0
3
I(BOOST)
VBAT = 4.2 V, boost mode, I(VBUS)= 0 A,
converter switching, PFM_OTG_DIS=1
15
VBUS/BAT POWER UP
V(VBUS_OP)
VBUS operating range
3.9
3.6
14
V
V
VBUS for active I2C, no battery
Sleep mode falling threshold
V(VBUS_UVLOZ)
V(SLEEP)
25
130
14
65
120
370
14.6
14
mV
mV
V
V(SLEEPZ)
Sleep mode rising threshold
250
VBUS over-voltage rising threshold
VBUS over-voltage falling threshold
Battery for active I2C, no VBUS
Battery depletion falling threshold
Battery depletion rising threshold
Bad adapter detection threshold
Bad adapter detection current source
V(ACOV)
13.5
2.3
V
VBAT(UVLOZ)
VBAT(DPL)
VBAT(DPLZ)
V(VBUSMIN)
I(BADSRC)
V
2.15
2.35
2.5
2.7
V
V
3.8
30
V
mA
POWER-PATH MANAGEMENT
I(SYS) = 0 A, VBAT> VSYS(MIN), BATFET Disabled
(REG09[5]=1)
VBAT
50 mV
+
V
V
V
V
VSYS
Typical system regulation voltage
I(SYS) = 0 A, VBAT< VSYS(MIN), BATFET Disabled
(REG09[5]=1)
VSYS(MIN)
150 mV
+
VBAT< VSYS(MIN), SYS_MIN = 3.5 V
(REG03[3:1]=101), ISYS= 0 A
VSYS(MIN)
VSYS(MAX)
Minimum DC system voltage output
Maximum DC system voltage output
3.50
3.65
4.40
VBAT = 4.35 V, SYS_MIN = 3.5V
(REG03[3:1]=101), ISYS= 0 A
4.42
Copyright © 2016–2018, Texas Instruments Incorporated
7
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mV
V
TJ = –40°C to +85°C
27
38
Top reverse blocking MOSFET(RBFET) on-resistance
between VBUS and PMID
RON(RBFET)
RON(HSFET)
RON(LSFET)
TJ = –40°C to +125°C
TJ = –40°C to +85°C
TJ = –40°C to +125°C
TJ = –40°C to +85°C
TJ = –40°C to +125°C
BAT discharge current 10 mA
VBAT rising
27
44
27
39
Top switching MOSFET (HSFET) on-resistance between PMID
and SW
27
47
16
24
Bottom switching MOSFET (LSFET) on-resistance between
SW and GND
16
28
V(FWD)
BATFET forward voltage in supplement mode
Battery good comparator rising threshold
Battery good comparator falling threshold
30
VBAT(GD)
3.4
3.55
100
3.7
VBAT(GD_HYST)
BATTERY CHARGER
VBAT(REG_RANGE)
VBAT(REG_STEP)
VBAT falling
mV
Typical charge voltage range
Typical charge voltage step
3.840
4.608
V
16
64
mV
VBAT = 4.208 V (REG06[7:2]=010111) or
VBAT = 4.352 V (REG06[7:2]=100000)
TJ = –40°C to +85°C
VBAT(REG)
Charge voltage resolution accuracy
-0.5%
0
0.5%
5056
I(CHG_REG_RANGE)
I(CHG_REG_STEP)
Typical fast charge current regulation range
Typical fast charge current regulation step
mA
mA
VBAT = 3.1 V or 3.8 V, ICHG = 128 mA
TJ = –40°C to +85°C
-20%
-10%
-5%
20%
10%
5%
VBAT= 3.1 V or 3.8 V, ICHG = 256 mA
TJ = –40°C to +85°C
I(CHG_REG_ACC)
Fast charge current regulation accuracy
VBAT= 3.1 V or 3.8 V, ICHG=1792 mA
TJ = –40°C to +85°C
Battery LOWV falling threshold
Battery LOWV rising threshold
Fast charge to precharge, BATLOWV
(REG06[1]) = 1
2.6
2.8
3
2.9
V
V
VBAT(LOWV)
Precharge to fast charge, BATLOWV
(REG06[1])=1
(Typical 200-mV hysteresis)
2.8
64
3.1
I(PRECHG_RANGE)
I(PRECHG_STEP)
I(PRECHG_ACC)
I(TERM_RANGE)
I(TERM_STEP)
Precharge current range
1024
mA
mA
Typical precharge current step
Precharge current accuracy
Termination current range
Typical termination current step
64
64
VBAT=2.6 V, IPRECHG = 256 mA
–10%
64
+10%
1024
mA
mA
ITERM = 256 mA, ICHG<= 1344 mA
TJ = –20°C to +85°C
–12%
–20%
12%
20%
I(TERM_ACC)
Termination current accuracy
ITERM = 256 mA, ICHG> 1344 mA
TJ = –20°C to +85°C
V(SHORT)
Battery short voltage
VBAT falling
2
200
100
100
200
V
V(SHORT_HYST)
I(SHORT)
Battery short voltage hysteresis
Battery short current
VBAT rising
mV
mA
mV
mV
mA
mΩ
mΩ
VBAT < 2.2 V
VBAT falling, VRECHG (REG06[0]=0) = 0
VBAT falling, VRECHG (REG06[0]=0) = 1
VSYS = 4.2 V
V(RECHG)
Recharge threshold below VBATREG
System discharge load current
ISYS(LOAD)
RON(BATFET)
30
TJ = 25°C
11
11
13
19
SYS-BAT MOSFET (BATFET) on-resistance
TJ = –40°C to +125°C
INPUT VOLTAGE / CURRENT REGULATION
VIN(DPM_RANGE)
VIN(DPM_STEP)
VIN(DPM_ACC)
IIN(DPM_RANGE)
IIN(DPM_STEP)
IIN(DPM100_ACC)
Typical Input voltage regulation range
3.9
15.3
V
Typical Input voltage regulation step
Input voltage regulation accuracy
Typical Input current regulation range
Typical Input current regulation step
100
mV
VINDPM = 4.4 V, 9 V, TJ = –40°C to +105°C
IINLIM (REG00[5:0]) =100 mA
3%
3%
100
3250
mA
mA
50
90
Input current 100-mA regulation accuracy
VBAT = 5 V, current pulled from SW
85
100
mA
USB150, IINLIM (REG00[5:0]) = 150 mA
USB500, IINLIM (REG00[5:0]) = 500 mA
USB900, IINLIM (REG00[5:0]) = 900 mA
125
440
750
135
470
825
150
500
900
mA
mA
mA
Input current regulation accuracy
VBAT = 5 V, current pulled from SW
IIN(DPM_ACC)
Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500
mA
1300
1400
1500
mA
8
Copyright © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
IIN(START)
Input current regulation during system start up
IINMAX = KILIM/RILIM
VSYS = 2.2 V, IINLIM (REG00[5:0])> = 200 mA
Input current regulation by ILIM pin = 1.5 A
200
KILIM
315
350
385
A x Ω
D+/D- DETECTION
V(0P0_VSRC)
D+/D– voltage source (0 V)
D+/D– voltage source (0.6 V)
I(DP) < 1 mA; DP_DAC=001 or
DM_DAC=001
-0.15
0.5
0
0.15
0.7
V
V
V(0P6_VSRC)
V(1P2_VSRC)
V(2P0_VSRC)
V(2P7_VSRC)
V(3P3_VSRC)
I(DP) < 1 mA; DP_DAC=010
or
I(DM) < 1 m; ADM_DAC=010
0.6
D+/D– voltage source (1.2 V)
D+/D– voltage source (2.0 V)
D+/D– voltage source (2.7 V)
D+/D– voltage source (3.3 V)
I(DP) < 1 mA; DP_DAC=011
or
I(DM) < 1 m; DM_DAC=011
1.075
1.875
2.575
3.15
1.2
2.0
2.7
3.3
1.325
2.125
2.825
3.45
V
V
V
V
I(DP) < 1 mA; DP_DAC=100
or
I(DM) < 1 m; DM_DAC=100
I(DP) < 1 mA; DP_DAC=101
or
I(DM) < 1 m; DM_DAC=101
I(DP) < 1 mA; DP_DAC=110
or
I(DM) < 1 m; DM_DAC=110
V(3p45_VSRC)
I(10UA_ISRC)
I(100UA_ISINK)
I(DPDM_LKG)
D+/D– voltage source (3.45 V)
D+ connection check current source
D+/D– current sink (100 µA)
D+/D– leakage current
3.3
7
3.45
10
3.6
14
V
µA
µA
µA
µA
µA
mV
V
50
100
150
1
D–, switch open
D+, switch open
–1
–1
1
I(1P6MA_ISINK)
V(0P4_VTH)
V(0P8_VTH)
V(2P7_VTH)
D+/D– current sink (1.6 mA)
D+/D– low comparator threshold
D+ low comparator threshold
1.45
250
1.60
1.75
400
0.8
2.85
D+/D– comparator threshold for non-standard adapter
detection (divider 1, 3, or 4)
2.55
1.85
V
V(2P0_VTH)
V(1P2_VTH)
R(D–_DWN)
D+/D– comparator threshold for non-standard adapter
detection (divider 1, 3)
2.15
1.35
24.8
V
V
D+/D– comparator threshold for non-standard adapter
detection (divider 2)
1.05
D– pulldown for connection check
14.25
kΩ
BAT OVER-VOLTAGE/CURRENT PROTECTION
VBAT(OVP)
Battery over-voltage threshold
Battery over-voltage hysteresis
System over-current threshold
VBAT rising, as percentage of VBAT(REG)
VBAT falling, as percentage of VBAT(REG)
104%
2%
VBAT(OVP_HYST)
IBAT(FET_OCP)
9
A
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG
Junction temperature regulation accuracy
Thermal shutdown rising temperature
Thermal shutdown hysteresis
REG08[1:0] = 11
Temperature rising
Temperature falling
120
160
30
°C
°C
°C
TSHUT
TSHUT(HYS)
JEITA THERMISTOR COMPARATOR (BUCK MODE)
T1 (0°C) threshold, charge suspended T1 below this
temperature.
V(T1)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
As percentage to V(REGN)
72.75%
67.75%
44.25v
73.25%
1.4%
73.75%
68.75%
45.25%
34.875%
Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2])
above this temperature.
V(T1_HYS)
V(T2)
V(T2_HYS)
V(T3)
V(T3_HYS)
V(T5)
T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and
VREG (REG06[7:2]) below this temperature.
68.25%
1.4%
Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])
above this temperature.
T3 (45°C) threshold, charge back to ICHG (REG04[6:0]) and
VREG-200 mV (REG06[7:2]) above this temperature.
44.75%
1%
Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])
below this temperature.
T5 (60°C) threshold, charge suspended above this
temperature.
33.875%
34.375%
1.25%
Charge back to ICHG (REG04[6:0]) and VREG-200 mV
(REG06[7:2]) below this temperature.
V(T5_HYS)
COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)
Copyright © 2016–2018, Texas Instruments Incorporated
9
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
As percentage to VREGN REG01[5] = 1
(Approximately –20°C w/ 103AT)
V(BCOLD1)
Cold temperature threshold 1, TS pin voltage rising threshold
Cold temperature threshold 1, TS pin voltage falling threshold
Hot temperature threshold 2, TS pin voltage falling threshold
Hot temperature threshold 2, TS pin voltage rising threshold
79.5%
80%
80.5%
V(BCOLD1_HYS)
V(BHOT2)
As percentage to VREGN REG01[5] = 1
1%
As percentage to VREGN REG01[7:6] = 10
(Approx. 65°C w/ 103AT)
30.75%
1.32
31.25%
3%
31.75%
1.68
V(BHOT2_HYS)
PWM
As percentage to VREGN REG01[7:6] =10
FSW
PWM switching frequency, and digital clock
Maximum PWM duty cycle
Oscillator frequency
MHz
DMAX
97%
64
BOOST MODE OPERATION
V(OTG_REG_RANGE) Typical boost mode regulation voltage range
V(OTG_REG_STEP)
4.55
–3%
5.55
3%
V
Typical boost mode regulation voltage step
Boost mode regulation voltage accuracy
mV
I(VBUS) = 0 A, BOOSTV=4.998V
(REG0A[7:4] = 0111)
V(OTG_REG_ACC)
V(OTG_BAT1)
V(OTG_BAT2)
Minimum battery voltage to exit boost mode
Minimum battery voltage to exit boost mode
BAT falling, MIN_VBAT_SEL=0
BAT falling, MIN_VBAT_SEL=1
BAT rising, MIN_VBAT_SEL=0
BAT rising, MIN_VBAT_SEL=1
2.7
2.4
2.9
2.7
0.5
1.2
5.8
2.9
2.6
V
V
V
V
A
A
V
3.1
V(OTG_BAT_EN)
Minimum battery voltage to enter boost mode
2.9
I(OTG)
Typical boost mode output current range
Boost mode RBFET over-current protection accuracy
Boost mode over-voltage threshold
2.45
1.65
I(OTG_OCP_ACC)
V(OTG_OVP)
BOOST_LIM =1.2 A (REG0A[2:0]=010)
Rising threshold
6
10
Copyright © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to +125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
REGN LDO output voltage
REGN LDO current limit
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REGN LDO
V(REGN)
V(VBUS) = 9 V, I(REGN) = 40 mA
V(VBUS) = 5 V, I(REGN) = 20 mA
V(VBUS) = 9 V, V(REGN) = 3.8 V
5.6
4.7
50
6
6.4
V
V
4.8
I(REGN)
mA
ANALOG-TO-DIGITAL CONVERTER (ADC)
RES
Resolution
Rising threshold
7
bits
V
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
2.304
4.848
4.848
VBAT(RANGE)
V(BAT_RES)
V(SYS_RANGE)
Typical battery voltage range
Typical battery voltage resolution
Typical system voltage range
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
disabled
VSYS_MIN
V
mV
V
20
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
2.304
4.848
4.848
V(VBUS) < VBAT + V(SLEEP) and OTG mode is
disabled
VSYS_MIN
V
V(SYS_RES)
Typical system voltage resolution
Typical VVBUS voltage range
20
mV
V
V(VBUS) > VBAT + V(SLEEP) or OTG mode is
enabled
2.6
15.3
V(VBUS_RANGE)
V(VBUS_RES)
IBAT(RANGE)
Typical VVBUS voltage resolution
Typical battery charge current range
100
mV
A
V(VBUS) > VBAT + V(SLEEP) and VBAT
VBAT(SHORT)
>
0
6.4
IBAT(RES)
Typical battery charge current resolution
Typical TS voltage range
50
mA
V(TS_RANGE)
V(TS_RES)
21%
80%
Typical TS voltage resolution
0.47%
LOGIC I/O PIN (OTG, CE, QON)
VIH
Input high threshold level
1.3
VIL
Input low threshold level
0.4
1
V
µA
V
IIN(BIAS)
High Level Leakage Current
Pull-up rail 1.8 V
Battery only mode
V(VBUS) = 9 V
BAT
5.8
V(QON)
Internal /QON pull-up
V
V(VBUS) = 5 V
4.3
V
R(QON)
Internal /QON pull-up resistance
200
kΩ
LOGIC I/O PIN (DSEL)
VOL
Output low threshold level
Output high threshold level
IOL = 2 mA, CDSEL= 47 nF
0.4
V
V
IOH = 5 mA, CDSEL= 47 nF, non-switching,
I(REGN) = 30 mA
VOH
4.5
LOGIC I/O PIN (INT, STAT)
VOL
Output low threshold level
High level leakage current
Sink current = 5 mA, sink current
Pull-up rail 1.8 V
0.4
1
V
IOUT_BIAS
µA
I2C INTERFACE (SCL, SDA)
VIH
Input high threshold level, SCL and SDA
Pull-up rail 1.8 V
1.3
VIL
Input low threshold level
Output low threshold level
High level leakage current
Pull-up rail 1.8 V
0.4
0.4
1
V
V
VOL
IBIAS
Sink current = 5 mA, sink current
Pull-up rail 1.8 V
µA
Copyright © 2016–2018, Texas Instruments Incorporated
11
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
7.6 Timing Requirements
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
tBADSRC
BAT OVER-VOLTAGE PROTECTION
Battery over-voltage deglitch time to disable
charge
BATTERY CHARGER
Bad Adapter detection duration
30
msec
tBATOVP
1
µs
tRECHG
Recharge deglitch time
20
ms
CURRENT PULSE CONTROL
tPUMPX_STOP
tPUMPX_ON1
tPUMPX_ON2
tPUMPX_OFF
tPUMPX_DLY
Current pulse control stop pulse
430
240
70
570
360
130
130
225
ms
ms
ms
ms
ms
Current pulse control long on pulse
Current pulse control short on pulse
Current pulse control off pulse
70
Current pulse control stop start delay
80
BATTERY MONITOR
tCONV
Conversion time
CONV_RATE(REG02[6]) = 0
TJ = –10°C to +60°C
8
1000
ms
QON AND SHIPMODE TIMING
QON low time to turn on BATFET and exit ship
mode
tSHIPMODE
0.8
1.3
s
tQON_RST
QON low time to enable full system reset
BATFET off time during full system reset
Enter ship mode delay
TJ = –10°C to +60°C
TJ = –10°C to +60°C
TJ = –10°C to +60°C
15.5
250
10
23
400
15
s
ms
s
tBATFET_RST
tSM_DLY
I2C INTERFACE
fSCL
SCL clock frequency
400
kHz
DIGITAL CLOCK and WATCHDOG TIMER
fLPDIG
fDIG
Digital low power clock
Digital clock
REGN LDO disabled
REGN LDO enabled
18
30
45
kHz
kHz
1320
1500
1680
WATCHDOG
(REG07[5:4])=11, REGN LDO
disabled
100
136
160
160
s
s
tWDT
Watchdog reset time
WATCHDOG
(REG07[5:4])=11, REGN LDO
enabled
12
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
7.7 Typical Characteristics
95%
94%
93%
92%
91%
90%
89%
88%
87%
86%
85%
95%
93%
91%
89%
87%
85%
83%
81%
79%
77%
75%
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
VBUS = 5 V
VBUS = 9 V
VBUS = 12 V
0
1
2
3
4
5
0
0.5
1
1.5
2
Charge Current (A)
System Load Current (A)
D001
D002
VBAT = 3.8 V
DCR = 10 mΩ
图 1. Charge Efficiency vs Charge Current
图 2. System Light Load Efficiency vs System Light Load
Current
96%
94%
92%
90%
88%
86%
84%
82%
80%
6%
5%
4%
3%
2%
1%
0
-1%
-2%
-3%
-4%
VBUS = 3.2 V
VBUS = 3.8 V
VBAT = 3.1 V
VBAT = 3.8 V
-5%
-6%
0
0.5
1
1.5
VBUS (A)
2
2.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Charge Current (A)
D003
D005
VBUS = 9 V
图 3. Boost Mode Efficiency vs VBUS Load Current
图 4. Charge Current Accuracy vs Charge Current I2C
Setting
3.7
3.68
3.66
3.64
3.62
3.6
4.5
4.45
4.4
4.35
4.3
4.25
4.2
3.58
3.56
3.54
3.52
3.5
4.15
4.1
4.05
4
VBUS = 5 V
VBUS = 5 V
2.5
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
3
System Load Current (A)
System Load Current (A)
D006
D007
VBAT = 2.9 V
VBUS = 5 V
SYSMIN = 3.5 V
VBAT = 4.2 V
图 5. SYS Voltage Regulation vs System Load Current
图 6. SYS Voltage Regulation vs System Load Current
版权 © 2016–2018, Texas Instruments Incorporated
13
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
Typical Characteristics (接下页)
1600
1400
1200
1000
800
600
400
200
0
4.42
4.4
4.38
4.36
4.34
4.32
4.3
4.28
4.26
4.24
4.22
4.2
4.18
4.16
4.14
4.12
4.1
IINLM = 500 mA
IINLM = 900 mA
IINLIM = 1.5 A
VBUS = 5 V
VBUS = 12 V
-50
0
50
100
150
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
Temperature (èC)
D008
D009
图 7. BAT Voltage vs Temperature
图 8. Input Current Limit vs Temperature
14
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8 Detailed Description
The device is a highly integrated 5-A siwtch-mode battery charger for single cell Li-Ion and Li-polymer battery. It
is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side siwtching FET (HSFET, Q2) ,
low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap
diode for the high-side gate drive.
8.1 Functional Block Diagram
VBUS
RBFET
PMID
(Q1)
VVBUS_UVLOZ
UVLO
Q1 Gate
Control
V
BATZ +80mV
SLEEP
ACOV
REGN
BTST
REGN
LDO
EN_HIZ
V
ACOV
FBO
VBUS
VBUS_OVP_BOOST
Q2_UCP_BOOST
V OTG_OVP
IQ2
VINDPM
V OTG_HSZCP
SW
IQ3
VOTG_BAT
Q3_OCP_BOOST
HSFET (Q2)
REGN
CONVERTER
CONTROL
IINDPM
BAT
BATOVP
IC TJ
TREG
104%xVBAT_REG
BAT
I LSFET_UCP
LSFET (Q3)
V BAT_REG
PGND
UCP
IQ2
Q2_OCP
IQ3
SYS
I HSFET_OCP
VSYSMIN
EN_HIZ
EN_CHARGE
EN_BOOST
V BTST -VSW
ICHG_REG
REFRESH
VBTST_REFRESH
SYS
ICHG
REF
DAC
V BAT_REG
I CHG_REG
Q4 Gate
Control
IBADSRC
BATFET
(Q4)
BAD_SRC
IDC
ILIM
Converter
Control State
Machine
DSEL
IC TJ
DSEL
Driver
EN
TSHUT
TSHUT
BAT
VQON
BAT
BAT_GD
Input
Source
Detection
VBATGD
/QON
D+
USB
ICHG
ADC Control
Adapter
VBUS
BAT
SYS
TS
Dœ
-VRECHG
D+/D-
Output
Driver
VREG
BAT
RECHRG
ADC
ICHG
TERMINATION
BATLOWV
OTG
INT
CHARGE
CONTROL
STATE
ITERM
V BATLOWV
BAT
bq25890H
MACHINE
V SHORT
BAT
I2C
Interface
BATSHORT
SUSPEND
STAT
Battery
Sensing
TS
Thermistor
SCL SDA
CE
版权 © 2016–2018, Texas Instruments Incorporated
15
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.2 Feature Description
8.2.1 Device Power-On-Reset (POR)
The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above
VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET
driver are active. I2C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
8.2.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods describe in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.
8.2.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started when
AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:
1. Power Up REGN LDO
2. Poor Source Qualification
3. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINLIM) register and input
source type
4. Input Voltage Limit Threshold Setting (VINDPM threshold)
5. Converter Power-up
8.2.3.1 Power Up REGN Regulation (LDO)
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLOZ
2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
3. After 220 ms delay is completed
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device
is in HIZ.
8.2.3.2 Poor Source Qualification
After REGN LDO powers up, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the buck converter.
1. VBUS voltage below VACOV
2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)
Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT
pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification
every 2 seconds.
16
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
Feature Description (接下页)
8.2.3.3 Input Source Type Detection
After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection
when AUTO_DPDM_EN bit is set.
The bq25890H follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source
(SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it
initiates adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake
when MAXC_EN or HVDCP_EN is set.
After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin
are changed:
1. Input Current Limit (IINLIM) register is changed to set current limit
2. PG_STAT bit is set
The host can over-write IINLIM register to change the input current limit if needed. The charger input current is
always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO) is
enable or disabled.
When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit
(IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.
8.2.3.3.1 D+/D– Detection Sets Input Current Limit
The bq25890H contains a D+/D– based input source detection to set the input current limit automatically. The
D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter
detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2
is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated
Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard
adapter detection is applied to set the input current limit.
When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge™,
etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input
source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be
disabled by clearing MAXC_EN and/or HVDCP_EN bits .
Non-Standard Adapter
(Divider 1: 2.1A)
(Divider 2: 2A)
(Divider 3: 1A)
Non-Standard
Adapter
(Divider 4: 2.4A)
Adapter Plug-in
USB BC1.2
Detection
Ajustable High Voltage Adapter
Handshake
or
EN_DPDM
SDP (USB500)
(500mA)
CDP
(1.5A)
MaxCharge™ Apapter
(1.5A)
DCP
(3.25A)
图 9. USB D+/D- Detection
版权 © 2016–2018, Texas Instruments Incorporated
17
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
表 1. Non-Standard Adapter Detection
NON-STANDARD
ADAPTER
D+ THRESHOLD
D- THRESHOLD
INPUT CURRENT LIMIT
Divider 1
Divider 2
Divider 3
Divider 4
VD+ within V2P7_VTH
VD+ within V1P2_VTH
VD+ within V2P0_VTH
VD+ within V2P7_VTH
VD- within V2P0_VTH
VD- within V1P2_VTH
VD- within V2P7_VTH
VD- within V2P7_VTH
2.1A
2A
1A
2.4A
表 2. Adjustable High Voltage Adapter D+/D- Output Configurations
ADJUSTABLE HIGH VOLTAGE HANDSHAKE
MaxCharge (12V)
D+
D-
OUTPUT
12 V
I1P6MA_ISINK
V3p45_VSRC
V3p45_VSRC
I1P6MA_ISINK
MaxCharge (9V)
9 V
After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following
registers including Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:
表 3. bq25890H Result
INPUT CURRENT LIMIT
D+/D- DETECTION
SDP_STAT
VBUS_STAT
(IINLIM)
500 mA
1.5 A
USB SDP (USB500)
USB CDP
1
1
1
1
1
1
1
1
1
001
010
011
110
110
110
110
100
101
USB DCP
3.25 A
1 A
Divider 3
Divider 1
2.1 A
Divider 4
2.4 A
Divider 2
2 A
MaxCharge
Unknown Adapter
1.5 A
500 mA
18
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.2.3.3.2 Force Input Current Limit Detection
In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed,
FORCE_DPDM bit returns to 0 by itself and Input Result is updated.
8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two
methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.
1. Absolute VINDPM (FORCE_VINDPM=1)
By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM
is writable and allows host to set the absolute threshold of VINDPM function.
2. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)
When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM
register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The
algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.
After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.
8.2.3.5 Converter Power-Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input
current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the
device limits input current to the lower value of ILIM pin and IILIM register (ICO_EN = 0) or IDPM_LIM register
(ICO_EN = 1).
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-
tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp
height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS.
8.2.4 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without overload
the input source. The algorithm automatically identify maximum input current limit of power source without
entering VINDPM to avoid input source overload.
This feature is enabled by default (ICO_EN=1) and can be disabled by setting ICO_EN bit to 0. After DCP or
MaxCharge type input source is detected based on the procedures previously described (Input Source Type
Detection ). The algorithm runs automatically when ICO_EN bit is set. The algorithm can also be forced to
execute by setting FORCE_ICO bit regardless of input source type detected.
The actual input current limit used by the Dynamic Power Management is reported in IDPM_LIM register while
Input Current Optimizer is enabled (ICO_EN = 1) or set by IINLIM register when the algorithm is disabled
(ICO_EN = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin
function.
版权 © 2016–2018, Texas Instruments Incorporated
19
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.2.5 Boost Mode Operation from Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA (BOOST_LIM bits =
000) output requirement. The maximum output current is up to 2.4 A. The boost operation can be enabled if the
conditions are valid:
1. BAT above BATLOWV
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH and OTG_CONFIG bit =1)
4. Voltage at TS (thermistor) pin is within range configured by Boost Mode Temperature Monitor as configured
by BHOT and BCOLD bits
5. After 30 ms delay from boost mode enable
In boost mode, the device employs a 500 KHz or 1.5 MHz (selectable using BOOST_FREQ bit) step-up
switching regulator based on system requirements. To avoid frequency change during boost mode operations,
write to boost frequency configuration bit (BOOST_FREQ) is ignored when OTG_CONFIG is set.
During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5V by default
(selectable via BOOSTV register bits) and the output current can reach up to 2.4 A, selected via I2C
(BOOST_LIM bits). The boost output is maintained when BAT is above VOTG_BAT threshold
8.2.6 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.2.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage (default 3.5 V).
When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the
minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the
VDS of BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage
regulation.
4.4
Minimum System Voltage
SYS (Charge Disabled)
SYS (Charge Enabled)
4.2
4
3.8
3.6
3.4
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
BAT (V)
D011
图 10. V(SYS) vs V(BAT)
20
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.2.6.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below
the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below
the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement
Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high.
图 11 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum
system voltage setting.
Voltage
VBUS
SYS
BAT
3.6V
3.4V
3.2V
3.18V
Current
4A
ICHG
3.2A
2.8A
ISYS
1.2A
1.0A
IIN
0.5A
-0.6A
DPM
DPM
Supplement
图 11. DPM Response
8.2.6.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low.
This prevents oscillation from entering and exiting the Supplement Mode. As the discharge current increases, the
BATFET gate is regulated with a higher voltage to reduce RDS(ON) until the BATFET is in full conduction. At this
point onwards, the BATFET VDS linearly increases with discharge current. 图 12 shows the V-I curve of the
BATFET gate regulation operation. BATFET turns off to exit Supplement Mode when the battery is below battery
depletion threshold.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10 15 20 25 30 35 40 45 50 55
V(BAT_SYS) (mV)
D010
图 12. BATFET V-I Curve
版权 © 2016–2018, Texas Instruments Incorporated
21
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.2.7 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 5-A charge current for high capacity battery. The 11-mΩ
BATFET improves charging efficiency and minimize the voltage drop during discharging.
8.2.7.1 Autonomous Charging Cycle
With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is low), the device autonomously completes
a charging cycle without host involvement. The device default charging parameters are listed in 表 4. The host
can always control the charging operations and optimize the charging parameters by writing to the corresponding
registers through I2C.
表 4. Charging Parameter Default Setting
DEFAULT MODE
Charging Voltage
Charging Current
Pre-charge Current
Termination Current
Temperature Profile
Safety Timer
bq25890
4.208 V
2.048 A
128 mA
256 mA
JEITA
bq25892
4.208 V
2.048 A
128 mA
256 mA
JEITA
12 hour
12 hour
A new charge cycle starts when the following conditions are valid:
•
•
•
•
•
Converter starts
Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
No thermistor fault on TS pin
No safety timer fault
BATFET is not forced to turn off (BATFET_DIS bit = 0)
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When
a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device
automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit
can initiate a new charging cycle.
The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)
or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status
register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast
charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an
INT is asserted to notify the host.
8.2.7.2 Battery Charging Profile
The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the
beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.
表 5. Charging Current Setting
VBAT
< 2 V
CHARGING CURRENT
IBATSHORT
REG DEFAULT SETTING
CHRG_STAT
–
01
01
10
2 V – 3 V
> 3 V
IPRECHG
128 mA
2048 mA
ICHG
22
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less
than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is
counted at half the clock rate.
Regulation Voltage
(3.84V t 4.608V)
Battery Voltage
Fast Charge Current
(128mA-5056mA)
Charge Current
V
BAT_LOWV (2.8V/3V)
V
BAT_SHORT (2V)
I
PRECHARGE (64mA-1024mA)
TERMINATION (64mA-1024mA)
BATSHORT (100mA)
I
I
Fast Charge and Voltage Regulation
Trickle Charge
Pre-charge
Safety Timer
Expiration
图 13. Battery Charging Profile
8.2.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.
Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.
Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.
8.2.7.4 Resistance Compensation (IRCOMP)
For high current charging system, resistance between charger output and battery cell terminal such as board
routing, connector, MOSFETs and sense resistor can force the charging process to move from constant current
to constant voltage too early and increase charge time. To speed up the charging cycle, the device provides
resistance compensation (IRCOMP) feature which can extend the constant current charge time to delivery
maximum power to battery.
The device allows the host to compensate for the resistance by increasing the voltage regulation set point based
on actual charge current and the resistance as shown below. For safe operation, the host should set the
maximum allowed regulation voltage register (VCLAMP) and the minimum resistance compensation (BATCOMP).
VREG_ACTUAL = VREG + min(ICHRG_ACTUAL x BATCOMP, VCLAMP
)
(1)
8.2.7.5 Thermistor Qualification
8.2.7.5.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
版权 © 2016–2018, Texas Instruments Incorporated
23
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
The device continuously monitors battery temperature by measuring the voltage between the TS pins and
ground, typically determined by a negative temperature coefficient thermistor (NTC) and an external voltage
divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To
initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds the
T1–T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1–T2), JEITA recommends the charge current to be reduced to at least half of the
charge current or lower. At warm temperature (T3–T5), JEITA recommends charge voltage below nominal
charge voltage.
The device provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm
temperature (T3–T5) can be 200 mV below charge voltage (JEITA_VSET=0). The current setting at cool
temperature (T1–T2) can be further reduced to 20% or 50% of fast charge current (JEITA_ISET bit).
REGN
bq2589x
RT1
TS
RTH
RT2
103AT
图 14. TS Resistor Network
VREG
VREG - 200 mV
图 15. Charging Values
Assuming a 103AT NTC thermistor on the battery pack as shown in 图 14, the value RT1 and RT2 can be
determined by using 公式 2: :
1
1
æ
ö
VREGN ´RTHCOLD ´RTHHOT
´
-
VT1 VT5
ç
÷
è
ø
RT2 =
V
V
æ
ö
æ
ö
REGN
REGN
RTHHOT
´
-1 - RTHCOLD
´
ç
-1
÷
ç
÷
VT5
VT1
è
ø
è
ø
VREGN
VT1
-1
RT1=
1
1
+
RT2 RTHCOLD
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery,
RTHT1 = 27.28 kΩ
RTHT5 = 3.02 kΩ
RT1 = 5.24 kΩ
24
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
RT2 = 30.31 kΩ
8.2.7.5.2 Cold/Hot Temperature Window in Boost Mode
For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to
VBHOT2 thresholds unless boost mode temperature is disabled by setting BHOT bits to 11. When temperature is
outside of the temperature thresholds, the boost mode is suspended. Once temperature is within thresholds, the
boost mode is recovered.
Temperature Range to
Boost
VREGN
Boost Disable
V
BCOLDx
(-
10ºC / 20ºC)
Boost Enable
V
BHOTx
(55ºC / 60ºC / 65ºC)
Boost Disable
AGND
图 16. TS Pin Thermistor Sense Thresholds in Boost Mode
8.2.7.6 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety
timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to
11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will
expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.
8.2.8 Battery Monitor
The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system
voltage, thermistor ratio, and charging current, and charging current based on the device modes of operation.
The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be
configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second
continuous conversion.
For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the
conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The
conversion result is ready after tCONV (maximum 1 second).
For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During
active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides
conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when
CONV_RATE is cleared.
When battery monitor is active, the REGN power is enabled and can increase device quiescent current. In
battery only mode, the battery monitor is only active when V(BAT) > SYS_MIN setting in REG03.
版权 © 2016–2018, Texas Instruments Incorporated
25
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
表 6. Battery Monitor Modes of Operation
MODES OF OPERATION
PARAMETER
REGISTER
CHARGE
MODE
DISABLE CHARGE
MODE
BATTERY ONLY
MODE
BOOST MODE
Battery Voltage (VBAT
)
REG0E
REG0F
REG10
REG11
REG12
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA
Yes
Yes
Yes
Yes
NA
Yes
Yes
Yes
NA
System Voltage (VSYS
Temperature (TS) Voltage (VTS
VBUS Voltage (VVBUS
Charge Current (IBAT
)
)
)
)
NA
8.2.9 Status/Control Outputs (STAT, INT and DSEL)
8.2.9.1 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in 图
47. The STAT pin function can be disable by setting STAT_DIS bit.
表 7. STAT Pin State
CHARGING STATE
Charging in progress (including recharge)
STAT INDICATOR
LOW
HIGH
HIGH
Charging complete
Sleep mode, charge disable
Charge suspend (Input overvoltage, TS fault, timer fault, input or system overvoltage).
Boost Mode suspend (due to TS Fault)
blinking at 1 Hz
8.2.9.2 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT notifies the system on the
device operation. The following events will generate 256-µs INT pulse.
•
•
USB/adapter source identified (through PSEL or DPDM detection, with OTG pin)
Good input source detected
–
–
–
VBUS above battery (not in sleep)
VBUS below VACOV threshold
VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
•
•
•
Input removed
Charge Complete
Any FAULT event in REG0C
When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads
the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send
any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively.
The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.
8.2.9.3 D+/D- Multiplexer Selection Control
The DSEL pin is normally grounded and pulled-up by internally to 5V during input source type detection (when
AUTO_DPDM_EN=1 or FORCE_DPDM=1). The pin is normally low and drives high to indicate the D+/D-
detection is in progress. When detection is completed, the pin maintains high logic when DCP, MaxCharge or
HVDCP is detected. The pin returns to logic low when other input source type is detected. In addition, while input
source is plugged in or during OTG mode, the FORCE_DSEL bit can be set to force the DSEL pin to change
from low to high regardless of input source type detected. When in battery discharge mode (not in OTG), the
DSEL pin is always low.
26
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.2.10 BATET (Q4) Control
8.2.10.1 BATFET Disable Mode (Shipping Mode)
To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,
the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When
the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by tSM_DLY as configurated
by BATFET_DLY bit.
8.2.10.2 BATFET Enable (Exit Shipping Mode)
When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following
events can enable BATFET to restore system power:
1. Plug in adapter
2. Clear BATFET_DIS bit
3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)
4. A logic high to low transition on QON pin with tSHIPMODE deglitch time to enable BATFET to exit shipping
mode
8.2.10.3 BATFET Full System Reset
The BATFET functions as a load switch between battery and system when input source is not plugged-in. By
changing the state of BATFET from off to on, system connects to SYS can be effectively have a power-on-reset.
The QON pin supports push-button interface to reset system power without host by change the state of BATFET.
When the QON pin is driven to logic low for tQON_RST (typical 15 seconds) while input source is not plugged in
and BATFET is enabled (BATFET_DIS=0), the BATFET is turned off for tBATFET_RST and then it is re-enabled to
reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.
8.2.11 Current Pulse Control Protocol
The device provides the control to generate the VBUS current pulse protocol to communicate with adjustable
high voltage adapter in order to signal adapter to increase or decrease output voltage. To enable the interface,
the EN_PUMPX bit must be set. Then the host can select the increase/decrease voltage pulse by setting one of
the PUMPX_UP or PUMPX_DN bit (but not both) to start the VBUS current pulse sequence. During the current
pulse sequence, the PUMPX_UP and PUMPX_DN bits are set to indicate pulse sequence is in progress and the
device pulses the input current limit between current limit set forth by IINLIM or IDPM_LIM register and the
100mA current limit (IINDPM100_ACC). When the pulse sequence is completed, the input current limit is returned to
value set by IINLIM or IDPM_LIM register and the PUMPX_UP or PUMPX_DN bit is cleared. In addition, the
EN_PUMPX can be cleared during the current pulse sequence to terminate the sequence and force charger to
return to input current limit as set forth by the IINLIM or IDPM_LIM register immediately. When EN_PUMPX bit is
low, write to PUMPX_UP and PUMPX_DN bit would be ignored and have no effect on VBUS current limit.
8.2.12 D+/D- Output Driver
The device provides independent controlled voltage output drivers on D+ and D- pins to interface or emulate
non-standard adapters when input source is plugged-in or OTG mode is enabled. The D+/D- drivers are disabled
in high impedance mode (HiZ) by default or when DP_DAC or DM_DAC bits are set to 000. The drivers are
enabled and controlled independently with predefined voltage threshold when DP_DAC and DM_DAC bits are
set to values between 001 to 110.
When input source is plugged-in, the output drivers control (DP_DAC and DM_DAC) are reset to HiZ (000) to
execute USB BC1.2 and built-in handshake during the input source type detection. The host is recommended to
change DP_DAC and DM_DAC settings after input source type detection when VBUS_STAT/PG_STAT bits are
updated.
When OTG mode is enabled, the drivers can be enabled to provide electrical signature on D+/D- to emulate USB
non-standard adapters (Divider 1-4) as shown in 表 1.
8.2.13 Input Current Limit on ILIM
For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.
The input maximum current is set by a resistor from ILIM pin to ground as:
版权 © 2016–2018, Texas Instruments Incorporated
27
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
K
ILIM
I
=
INMAX
R
ILIM
(3)
The actual input current limit is the lower value between ILIM setting and register setting (IINLIM). For example, if
the register setting is 111111 for 3.25 A, and ILIM has a 260-Ω resistor (KILIM = 390 max.) to ground for 1.5 A,
the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings
when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters
input current regulation (Refer to Dynamic Power Management section).
The ILIM pin can also be used to monitor input current when EN_ILIM is enabled. The voltage on ILIM pin is
proportional to the input current. ILIM pin can be used to monitor the input current following 公式 4:
K
x V
ILIM
ILIM
I
=
IN
R
x 0.8 V
ILIM
(4)
For example, if ILIM pin is set with 260-Ω resistor, and the ILIM voltage is 0.4 V, the actual input current 0.615 A
- 0.75 A (based on KILM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage
floats above 0.8 V. If ILIM pin is short, the input current limit is set by the register.
The ILIM pin function can be disabled by setting EN_ILIM bit to 0. When the pin is disabled, both input current
limit function and monitoring function are not available.
8.2.14 Thermal Regulation and Thermal Shutdown
8.2.14.1 Thermal Protection in Buck Mode
The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface
temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit
(TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC
allows the user to optimize the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed battery charging current.
Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register
THERM_STAT bit goes high.
Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface
temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The
BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS
.
8.2.14.2 Thermal Protection in Boost Mode
The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
surface temperature exceeds TSHUT, the boost mode is disabled (converter is turned off) by setting
OTG_CONFIG bit low and BATFET is turned off. When IC surface temperature is below TSHUT_HYS, the BATFET
is enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.
8.2.15 Voltage and Current Monitoring in Buck and Boost Mode
8.2.15.1 Voltage and Current Monitoring in Buck Mode
The device closely monitors the input and system voltage, as well as HSFET current for safe buck and boost
mode operations.
8.2.15.1.1 Input Overvoltage (ACOV)
The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops
switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT
is asserted to the host..
8.2.15.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to
clamp the overshoot.
28
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.2.15.2 Voltage and Current Monitoring in Boost Mode
The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.
8.2.15.2.1 VBUS Overcurrent Protection
The charger device closely monitors the RBFET (Q1), and LSFET (Q3) current to ensure safe boost ode
operation. During overcurrent condition when output current exceed (IOTG_OCP) the device operates in hiccup
mode for protection. While in hiccup mode cycle, the device turns off RBFET for tOTG_OCP_OFF (30 ms typical) and
turns on RBFET for tOTG_OCP_ON (250 µs typical) in an attempt to restart. If the overcurrent condition is removed,
the boost converter returns to normal operation. When overcurrent condition continues to exist, the device
repeats the hiccup cycle until overcurrent condition is removed. When overcurrent condition is detected the fault
register bit BOOST_FAULT is set high to indicate fault in boost operation. An INT is also asserted to the host.
8.2.15.2.2 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. During the overvoltage
duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also
asserted to the host.
8.2.16 Battery Protection
8.2.16.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
8.2.16.2 Battery Over-Discharge Protection
When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To
recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the
BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or
precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV
.
8.2.16.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) so that its current exceeds the overcurrent
limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET
8.2.17 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6AH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
8.2.17.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
版权 © 2016–2018, Texas Instruments Incorporated
29
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
SDA
SCL
Change
of data
allowed
Data line stable;
Data valid
图 17. Bit Transfer on the I2C Bus
8.2.17.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
STOP (P)
START (S)
图 18. START and STOP conditions
8.2.17.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement
signal from revceiver
Acknowledgement
signal from slave
MSB
1
P or
Sr
S or Sr
2
7
8
9
ACK
1
2
8
9
ACK
START or
Repeated
START
STOP or
Repeated
START
图 19. Data Transfer on the I2C Bus
30
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.2.17.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.2.17.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
S
8
9
8
9
8
9
P
SCL
1-7
1-7
1-7
START
ADDRESS
R/W ACK
DATA
ACK
DATA
ACK
STOP
图 20. Complete Data Transfer
8.2.17.6 Single Read and Write
1
8
1
1
7
1
0
1
1
8
Slave Address
ACK
Reg Addr
ACK
P
S
ACK
Data Addr
图 21. Single Write
1
8
1
1
1
7
1
0
1
1
1
7
Slave Address
ACK
Reg Addr
ACK
S
S
ACK
Slave Address
1
1
8
P
Data
NCK
图 22. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
8.2.17.7 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.
图 23. Multi-Write
版权 © 2016–2018, Texas Instruments Incorporated
31
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
图 24. Multi-Read
REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For
example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the
fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault
information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT
which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and
multi-write.
8.3 Device Functional Modes
8.3.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,
WATCHDOG_FAULT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings.
In default mode, the device keeps charging the battery with 12-hour fast charging safety timer. At the end of the
12-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write
command to device transitions the charger from default mode to host mode. All the device parameters can be
programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1
to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by
setting WATCHDOG bits=00.
When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all
registers are reset to default values except IINLIM, VINDPM, VINDPM_OS, BATFET_RST_EN, BATFET_DLY,
and BATFET_DIS bits.
32
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
Device Functional Modes (接下页)
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset selective registers
Y
WD_RST bit = 1?
N
Y
N
I2C Write?
Y
N
Watchdog Timer
Expired?
图 25. Watchdog Timer Flow Chart
版权 © 2016–2018, Texas Instruments Incorporated
33
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4 Register Maps
I2C Slave Address: 6AH (1101010B + R/W)
8.4.1 REG00
图 26. REG00
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 8. REG00
Bit
Field
Type
Reset
Description
Enable HIZ Mode
0 – Disable (default)
1 – Enable
by REG_RST
by Watchdog
7
EN_HIZ
R/W
Enable ILIM Pin
0 – Disable
1 – Enable (default: Enable ILIM pin (1))
by REG_RST
by Watchdog
6
EN_ILIM
R/W
5
4
3
2
1
IINLIM[5]
IINLIM[4]
IINLIM[3]
IINLIM[2]
IINLIM[1]
R/W
R/W
R/W
R/W
R/W
by REG_RST
by REG_RST
by REG_RST
by REG_RST
by REG_RST
1600mA
800mA
400mA
200mA
100mA
Input Current Limit
Offset: 100mA
Range: 100mA (000000) – 3.25A (111111)
Default:0001000 (500mA)
(Actual input current limit is the lower of I2C or ILIM pin)
IINLIM bits are changed automaticallly after input source
type detection is completed
USB Host SDP = 500mA
USB CDP = 1.5A
USB DCP = 3.25A
Adjustable High Voltage (MaxCharge) DCP = 1.5A
Unknown Adapter = 500mA
0
IINLIM[0]
R/W
by REG_RST
50mA
Non-Standard Adapter = 1A/2A/2.1A/2.4A
34
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.2 REG01
图 27. REG01
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. REG01
Bit
7
Field
Type
R/W
R/W
Reset
Description
DP_DAC[2]
DP_DAC[1]
by REG_RST
by REG_RST
D+ Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V0P0_VSRC
6
)
010 – 0.6V (V0P6_VSRC
011 – 1.2V (V1P2_VSRC
100 – 2.0V (V2P0_VSRC
101 – 2.7V (V2P7_VSRC
110 – 3.3V (V3P3_VSRC
111 – Reserved
)
)
)
)
)
5
DP_DAC[0]
R/W
by REG_RST
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
4
3
DM_DAC[2]
DM_DAC[1]
R/W
R/W
by REG_RST
by REG_RST
D- Pin Output Driver
000 – HiZ mode (Default)
001 – 0V (V0P0_VSRC
)
010 – 0.6V (V0P6_VSRC
011 – 1.2V (V1P2_VSRC
100 – 2.0V (V2P0_VSRC
101 – 2.7V (V2P7_VSRC
110 – 3.3V (V3P3_VSRC
111 – Reserved
)
)
)
)
)
2
DM_DAC[0]
R/W
by REG_RST
Register bits are reset to default value when input source is plugged-in
and can be changed after D+/D- detection is completed.
Enable 12V detection for MaxCharge and HVDCP
0 – Disable 12V Detection (default)
1 – Enable 12V Detection
1
0
EN_12V
R/W
R/W
by REG_RST
by REG_RST
Input Voltage Limit Offset
0 – 400mV
VINDPM_OS
1 – 600mV (default)
版权 © 2016–2018, Texas Instruments Incorporated
35
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.3 REG02
图 28. REG02
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. REG02
Bit
Field
Type
Reset
Description
ADC Conversion Start Control
0 – ADC conversion not active (default).
1 – Start ADC Conversion
This bit is read-only when CONV_RATE = 1. The bit stays high during
ADC conversion and during input source detection.
by REG_RST
by Watchdog
7
CONV_START
R/W
ADC Conversion Rate Selection
0 – One shot ADC conversion (default)
1 – Start 1s Continuous Conversion
by REG_RST
by Watchdog
6
5
CONV_RATE
R/W
R/W
Boost Mode Frequency Selection
0 – 1.5MHz
1 – 500KHz
by REG_RST
by Watchdog
BOOST_FREQ
Note: Write to this bit is ignored when OTG_CONFIG is enabled.
Input Current Optimizer (ICO) Enable
0 – Disable ICO Algorithm
1 – Enable ICO Algorithm (default)
4
3
2
1
0
ICO_EN
R/W
R/W
R/W
R/W
R/W
by REG_RST
by REG_RST
by REG_RST
High Voltage DCP Enable
0 – Disable HVDCP handshake
1 – Enable HVDCP handshake (default)
HVDCP_EN
MAXC_EN
MaxCharge Adapter Enable
0 – Disable MaxCharge handshake
1 – Enable MaxCharge handshake (default)
Force D+/D- Detection
0 – Not in D+/D- or PSEL detection (default)
1 – Force D+/D- detection
by REG_RST
by Watchdog
FORCE_DPDM
AUTO_DPDM_EN
Automatic D+/D- Detection Enable
0 –Disable D+/D- or PSEL detection when VBUS is plugged-in
1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default)
by REG_RST
36
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.4 REG03
图 29. REG03
7
0
6
0
5
0
4
1
3
1
2
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. REG03
Bit
Field
Type
Reset
Description
DSEL Pin Control
7
FORCE_DSEL
R/W
by REG_RST
0 – Allow DSEL pin output to drive low (default)
1 – Force DSEL pin output to drive high
I2C Watchdog Timer Reset
0 – Normal (default)
1 – Reset (Back to 0 after timer reset)
by REG_RST
by Watchdog
6
5
4
WD_RST
R/W
R/W
R/W
Boost (OTG) Mode Configuration
0 – OTG Disable (default)
1 – OTG Enable
by REG_RST
by Watchdog
OTG_CONFIG
CHG_CONFIG
Charge Enable Configuration
0 - Charge Disable
1- Charge Enable (default)
by REG_RST
by Watchdog
3
2
1
SYS_MIN[2]
SYS_MIN[1]
SYS_MIN[02]
R/W
R/W
R/W
by REG_RST
by REG_RST
by REG_RST
0.4V
0.2V
0.1V
Minimum System Voltage Limit
Offset: 3.0V
Range 3.0V-3.7V
Default: 3.5V (101)
Minimum Battery Voltage (falling) to exit boost mode
0 - 2.9V (default)
1- 2.5V
by REG_RST
by Watchdog
0
MIN_VBAT_SEL
R/W
版权 © 2016–2018, Texas Instruments Incorporated
37
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.5 REG04
图 30. REG04
7
0
6
0
5
1
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. REG04
Bit
Field
Type
Reset
Description
Current pulse control Enable
0 - Disable Current pulse control (default)
1- Enable Current pulse control (PUMPX_UP and PUMPX_DN)
by Softwareby
by Watchdog
7
EN_PUMPX
R/W
by Softwareby
by Watchdog
6
5
4
3
2
1
0
ICHG[6]
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4096mA
by Softwareby
by Watchdog
2048mA
Fast Charge Current Limit
Offset: 0mA
by Softwareby
by Watchdog
1024mA
512mA
256mA
128mA
64mA
Range: 0mA (0000000) – 5056mA (1001111)
Default: 2048mA (0100000)
Note:
ICHG=000000 (0mA) disables charge
ICHG > 1001111 (5056mA) is clamped to register value
1001111 (5056mA)
by Softwareby
by Watchdog
by Softwareby
by Watchdog
by Softwareby
by Watchdog
by Softwareby
by Watchdog
38
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.6 REG05
图 31. REG05
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 13. REG05
Bit
Field
Type
Reset
Description
by Softwareby
by Watchdog
7
IPRECHG[3]
R/W
512mA
by Softwareby
by Watchdog
Precharge Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 128mA (0001)
6
5
4
3
2
1
0
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
256mA
128mA
64mA
by Softwareby
by Watchdog
by Softwareby
by Watchdog
by Softwareby
by Watchdog
512mA
256mA
128mA
64mA
by Softwareby
by Watchdog
Termination Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 256mA (0011)
ITERM[2]
by Softwareby
by Watchdog
ITERM[1]
by Softwareby
by Watchdog
ITERM[0]
版权 © 2016–2018, Texas Instruments Incorporated
39
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.7 REG06
图 32. REG06
7
0
6
1
5
0
4
1
3
1
2
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. REG06
Bit
Field
Type
Reset
Description
by Softwareby
by Watchdog
7
VREG[5]
R/W
512mV
by Softwareby
by Watchdog
6
5
4
3
2
VREG[4]
VREG[3]
VREG[2]
VREG[1]
VREG[0]
R/W
R/W
R/W
R/W
R/W
256mV
128mV
64mV
32mV
16mV
Charge Voltage Limit
Offset: 3.840V
Range: 3.840V – 4.608V (110000)
Default: 4.208V (010111)
Note:
by Softwareby
by Watchdog
by Softwareby
by Watchdog
VREG > 110000 (4.608V) is clamped to register value
110000 (4.608V)
by Softwareby
by Watchdog
by Softwareby
by Watchdog
Battery Precharge to Fast Charge Threshold
0 – 2.8V
1 – 3.0V (default)
by Softwareby
by Watchdog
1
0
BATLOWV
VRECHG
R/W
R/W
Battery Recharge Threshold Offset
by Softwareby (below Charge Voltage Limit)
by Watchdog 0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])
40
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.8 REG07
图 33. REG07
7
1
6
0
5
0
4
1
3
1
2
1
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 15. REG07
Bit
Field
Type
Reset
Description
Charging Termination Enable
0 – Disable
1 – Enable (default)
by Softwareby
by Watchdog
7
EN_TERM
R/W
STAT Pin Disable
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
by Softwareby
by Watchdog
6
STAT_DIS
R/W
by Softwareby I2C Watchdog Timer Setting
5
4
WATCHDOG[1]
WATCHDOG[0]
R/W
R/W
by Watchdog
00 – Disable watchdog timer
01 – 40s (default)
10 – 80s
by Softwareby
by Watchdog
11 – 160s
Charging Safety Timer Enable
0 – Disable
1 – Enable (default)
by Softwareby
by Watchdog
3
EN_TIMER
R/W
by Softwareby Fast Charge Timer Setting
2
1
CHG_TIMER[1]
CHG_TIMER[0]
R/W
R/W
by Watchdog
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (default)
11 – 20 hrs
by Softwareby
by Watchdog
JEITA Low Temperature Current Setting
0 – 50% of ICHG (REG04[6:0])
1 – 20% of ICHG (REG04[6:0]) (default)
by Software
by Watchdog
0
JEITA_ISET (0C-10C)
R/W
版权 © 2016–2018, Texas Instruments Incorporated
41
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.9 REG08
图 34. REG08
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. REG08
Bit
Field
Type
Reset
Description
by Softwareby
by Watchdog
7
BAT_COMP[2]
R/W
80mΩ
IR Compensation Resistor Setting
Range: 0 – 140mΩ
Default: 0Ω (000) (i.e. Disable IRComp)
by Softwareby
by Watchdog
6
5
4
3
2
1
BAT_COMP[1]
BAT_COMP[0]
VCLAMP[2]
VCLAMP[1]
VCLAMP[0]
TREG[1]
R/W
R/W
R/W
R/W
R/W
R/W
40mΩ
20mΩ
128mV
64mV
32mV
by Softwareby
by Watchdog
by Softwareby
by Watchdog
IR Compensation Voltage Clamp
above VREG (REG06[7:2])
Offset: 0mV
Range: 0-224mV
Default: 0mV (000)
by Softwareby
by Watchdog
by Softwareby
by Watchdog
by Softwareby Thermal Regulation Threshold
by Watchdog
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (default)
by Softwareby
by Watchdog
0
TREG[0]
R/W
42
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.10 REG09
图 35. REG09
7
0
6
1
5
0
4
0
3
0
2
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. REG09
Bit
Field
Type
Reset
Description
Force Start Input Current Optimizer (ICO)
0 – Do not force ICO (default)
1 – Force ICO
by Softwareby
by Watchdog
7
FORCE_ICO
R/W
Note:
This bit is can only be set only and always returns to 0 after ICO starts
Safety Timer Setting during DPM or Thermal Regulation
0 – Safety timer not slowed by 2X during input DPM or thermal
regulation
1 – Safety timer slowed by 2X during input DPM or thermal regulation
(default)
by Softwareby
by Watchdog
6
TMR2X_EN
R/W
Force BATFET off to enable ship mode
5
4
BATFET_DIS
R/W
R/W
by Softwareby 0 – Allow BATFET turn on (default)
1 – Force BATFET off
JEITA High Temperature Voltage Setting
by Software
0 – Set Charge Voltage to VREG-200mV during JEITA hig temperature
JEITA_VSET (45C-60C)
by Watchdog
(default)
1 – Set Charge Voltage to VREG during JEITA high temperature
BATFET turn off delay control
3
2
BATFET_DLY
R/W
R/W
by Softwareby 0 – BATFET turn off immediately when BATFET_DIS bit is set (default)
1 – BATFET turn off delay by tSM_DLY when BATFET_DIS bit is set
BATFET full system reset enable
by Softwareby 0 – Disable BATFET full system reset
1 – Enable BATFET full system reset (default)
BATFET_RST_EN
Current pulse control voltage up enable
0 – Disable (default)
by Softwareby 1 – Enable
1
0
PUMPX_UP
PUMPX_DN
R/W
R/W
by Watchdog
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed
Current pulse control voltage down enable
0 – Disable (default)
by Softwareby 1 – Enable
by Watchdog
Note:
This bit is can only be set when EN_PUMPX bit is set and returns to 0
after current pulse control sequence is completed
版权 © 2016–2018, Texas Instruments Incorporated
43
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.11 REG0A
图 36. REG0A
7
0
6
1
5
1
4
1
3
0
2
0
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. REG0A
Bit
Field
Type
Reset
Description
by Softwareby
by Watchdog
7
BOOSTV[3]
R/W
512mV
Boost Mode Voltage Regulation
Offset: 4.55V
Range: 4.55V – 5.51V
Default:4.998V(0111)
by Softwareby
by Watchdog
6
5
4
BOOSTV[2]
BOOSTV[1]
BOOSTV[0]
R/W
R/W
R/W
256mV
by Softwareby 128mV
by Softwareby
64mV
by Watchdog
PFM mode allowed in boost mode
0 – Allow PFM in boost mode (default)
3
PFM_OTG_DIS
R/W
by Software
1 – Disable PFM in boost mode
by Software
by Watchdog
000: 0.5A
001: 0.75A
010: 1.2A
2
1
BOOST_LIM[2]
BOOST_LIM[1]
R/W
R/W
by Software
by Watchdog
011: 1.4A
Boost Mode Current Limit
Default: 1.4A (011)
100: 1.65A
101: 1.875A
110: 2.15A
111: 2.45A
by Software
by Watchdog
0
BOOST_LIM[0]
R/W
44
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.12 REG0B
图 37. REG0B
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. REG0B
Bit
7
Field
Type
R
Reset
N/A
Description
VBUS_STAT[2]
VBUS_STAT[1]
VBUS Status register
000: No Input 001: USB Host SDP
010: USB CDP (1.5A)
6
R
N/A
011: USB DCP (3.25A)
100: Adjustable High Voltage DCP (MaxCharge) (1.5A)
101: Unknown Adapter (500mA)
5
VBUS_STAT[0]
R
N/A
110: Non-Standard Adapter (1A/2A/2.1A/2.4A)
111: OTG Note: Software current limit is reported in IINLIM register
4
3
CHRG_STAT[1]
CHRG_STAT[0]
R
R
N/A
N/A
Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV
10 – Fast Charging
)
11 – Charge Termination Done
Power Good Status
0 – Not Power Good
1 – Power Good
2
1
0
PG_STAT
Reserved
R
R
N/A
N/A
Reserved: Always reads 0
VSYS Regulation Status
0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)
VSYS_STAT
版权 © 2016–2018, Texas Instruments Incorporated
45
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.13 REG0C
图 38. REG0C
7
x
6
x
5
x
4
x
3
x
2
x
1
x
0
x
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. REG0C
Bit
Field
Type
Reset
Description
Watchdog Fault Status
Status 0 – Normal
7
WATCHDOG_FAULT
R
N/A
1- Watchdog timer expiration
Boost Mode Fault Status
0 – Normal
1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low in
boost mode
6
5
BOOST_FAULT
CHRG_FAULT[1]
R
R
N/A
N/A
Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V)
)
4
CHRG_FAULT[0]
R
N/A
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
Battery Fault Status
0 – Normal
3
BAT_FAULT
R
N/A
1 – BATOVP (VBAT > VBATOVP
)
2
1
NTC_FAULT[2]
NTC_FAULT[1]
R
R
N/A
N/A
NTC Fault Status
Buck Mode:
000 – Normal
010 – TS Warm
011 – TS Cool
101 – TS Cold
110 – TS Hot
Boost Mode:
0
NTC_FAULT[0]
R
N/A
000 – Normal
101 – TS Cold
110 – TS Hot
46
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.14 REG0D
图 39. REG0D
7
0
6
0
5
0
4
1
3
0
2
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. REG0D
Bit
Field
Type
Reset
Description
VINDPM Threshold Setting Method
0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
7
FORCE_VINDPM
R/W
by Softwareby
Note: Register is reset to default value when input source is plugged-in
6
5
4
3
2
1
VINDPM[6]
VINDPM[5]
VINDPM[4]
VINDPM[3]
VINDPM[2]
VINDPM[1]
R/W
R/W
R/W
R/W
R/W
R/W
by Softwareby 6400mV
by Softwareby 3200mV
by Softwareby 1600mV
by Softwareby 800mV
by Softwareby 400mV
by Softwareby 200mV
Absolute VINDPM Threshold
Offset: 2.6V
Range: 3.9V (0001101) – 15.3V (1111111)
Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
Register is read only when FORCE_VINDPM=0 and can
be written by internal control based on relative VINDPM
threshold setting
Register can be read/write when FORCE_VINDPM = 1
Note: Register is reset to default value when input source
is plugged-in
0
VINDPM[0]
R/W
by Softwareby 100mV
8.4.15 REG0E
图 40. REG0E
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. REG0E
Bit
Field
Type
Reset
Description
Thermal Regulation Status
0 – Normal
7
THERM_STAT
R
N/A
1 – In Thermal Regulation
6
5
4
3
2
1
0
BATV[6]
BATV[5]
BATV[4]
BATV[3]
BATV[2]
BATV[1]
BATV[0]
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1280mV
640mV
320mV
160mV
80mV
40mV
20mV
ADC conversion of Battery Voltage (VBAT
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
)
版权 © 2016–2018, Texas Instruments Incorporated
47
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.16 REG0F
图 41. REG0F
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. REG0F
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
SYSV[6]
SYSV[5]
SYSV[4]
SYSV[3]
SYSV[2]
SYSV[1]
SYSV[0]
Reserved: Always reads 0
1280mV
6
R
5
R
640mV
4
R
320mV
160mV
80mV
40mV
20mV
ADDC conversion of System Voltage (VSYS
Offset: 2.304V
Range: 2.304V (0000000) – 4.848V (1111111)
Default: 2.304V (0000000)
)
3
R
2
R
1
R
0
R
8.4.17 REG10
图 42. REG10
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. REG10
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Reserved
TSPCT[6]
TSPCT[5]
TSPCT[4]
TSPCT[3]
TSPCT[2]
TSPCT[1]
TSPCT[0]
Reserved: Always reads 0
29.76%
6
R
5
R
14.88%
4
R
7.44%
3.72%
1.86%
0.93%
0.465%
ADC conversion of TS Voltage (TS) as percentage of REGN
Offset: 21%
Range 21% (0000000) – 80% (1111111)
Default: 21% (0000000)
3
R
2
R
1
R
0
R
48
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
8.4.18 REG11
图 43. REG11
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. REG11
Bit
Field
Type
Reset
Description
VBUS Good Status
0 – Not VBUS attached
1 – VBUS Attached
7
VBUS_GD
R
N/A
6
5
4
3
2
1
0
VBUSV[6]
VBUSV[5]
VBUSV[4]
VBUSV[3]
VBUSV[2]
VBUSV[1]
VBUSV[0]
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6400mV
3200mV
1600mV
800mV
400mV
200mV
100mV
ADC conversion of VBUS voltage (VBUS
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
Default: 2.6V (0000000)
)
8.4.19 REG12
图 44. REG12
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 26. REG12
Bit
7
Field
Type
R
Reset
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Always reads 0
3200mA
Unused
6
ICHGR[6]
ICHGR[5]
ICHGR[4]
ICHGR[3]
ICHGR[2]
ICHGR[1]
ICHGR[0]
R
5
R
1600mA
800mA
400mA
200mA
100mA
50mA
ADC conversion of Charge Current (IBAT) when VBAT
VBATSHORT
Offset: 0mA
Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
>
4
R
3
R
2
R
Note:
This register returns 0000000 for VBAT < VBATSHORT
1
R
0
R
版权 © 2016–2018, Texas Instruments Incorporated
49
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
8.4.20 REG13
图 45. REG13
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 27. REG13
Bit
Field
Type
Reset
Description
VINDPM Status
0 – Not in VINDPM
1 – VINDPM
7
VDPM_STAT
R
N/A
IINDPM Status
0 – Not in IINDPM
1 – IINDPM
6
IDPM_STAT
R
N/A
5
4
3
2
1
0
IDPM_LIM[5]
IDPM_LIM[4]
IDPM_LIM[3]
IDPM_LIM[2]
IDPM_LIM[1]
IDPM_LIM[0]
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
1600mA
800mA
Input Current Limit in effect while Input Current Optimizer
(ICO) is enabled
Offset: 100mA (default)
400mA
200mA
100mA
50mA
Range 100mA (0000000) – 3.25mA (1111111)
8.4.21 REG14
图 46. REG14
7
0
6
0
5
0
4
1
3
1
2
1
1
1
0
1
R/W
R/W
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 28. REG14
Bit
Field
Type
Reset
Description
Register Reset
0 – Keep current register setting (default)
7
REG_RST
R/W
N/A
1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
Input Current Optimizer (ICO) Status
0 – Optimization is in progress
6
ICO_OPTIMIZED
R
N/A
1 – Maximum Input Current Detected
5
4
3
PN[2]
PN[1]
PN[0]
R
R
R
N/A
N/A
N/A
Device Configuration
011: bq25890H
Temperature Profile
1- JEITA
2
TS_PROFILE
R
N/A
1
0
DEV_REV[1]
DEV_REV[0]
R
R
N/A
N/A
Device Revision: 11
50
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also
integrates a bootstrap diode for the high-side gate drive.
9.2 Typical Application
Input
OTG
3.9Vt14V at 3A
5V at 2.4A
VBUS
PMID
1ꢀH
SYS 3.5Vt4.5V
10ꢀF 10ꢀF
1ꢀF
C1
SW
47nF
USB
47nF
BTST
REGN
Optional
DSEL
D+
4.7ꢀF
D-
1ꢀF
PGND
SYS
260Q
SYS
ILIM
Ichg = 5A
10ꢀF
BAT
VREF
QON
2.2YQ
STAT
SDA
10YQ 10YQ 10YQ
Host
Optional
REGN
SCL
INT
OTG
5.23YQ
TS
/CE
30.1YQ
10YQ
bq25890H
Copyright © 2016, Texas Instruments Incorporated
Recommended C1 = 8.2 μF (OTG ≤ 1.8 A) or 20 μF (OTG ≤ 2.4 A)
图 47. bq25890 with D+/D- Interface and USB On-The-Go (OTG)
9.2.1 Design Requirements
For this design example, use the parameters shown in 表 29.
表 29. Design Parameter
PARAMETERS
Input voltage range
Input current limit
VALUES
3.9 V to 14 V
1.5 A
Fast charge current
Output voltage
5000 mA
4.352 V
VREF system pullup voltage
1.8 V - 3.3 V
版权 © 2016–2018, Texas Instruments Incorporated
51
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
I
³ I
+ (1/2) I
BAT
CHG
RIPPLE
(5)
The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs)
and inductance (L):
V
x D x (1-D)
BUS
I
=
RIPPLE
f s x L
(6)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a
practical design.
9.2.2.2 Buck Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50%
and can be estimated by 公式 7:
I
= I x D x (1 - D)
CHG
PMID
(7)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred
for up to 14-V input voltage. 8.2-μF capacitance is suggested for typical of 3 A – 5 A charging current.
52
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
9.2.2.3 System Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
RIPPLE
I
=
» 0.29 x I
RIPPLE
CSYS
2 x
3
(8)
The output capacitor voltage ripple can be calculated as follows:
æ
ö
÷
÷
÷
V
V
SYS
SYS
ç
DV
=
ç1-
O
ç
ç
è
2
÷
ø
V
BUS
8 LC
SYS
f s
(9)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum
of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.
版权 © 2016–2018, Texas Instruments Incorporated
53
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
9.2.3 Application Curves
VBAT = 3.2 V
图 48. Power Up with Charge Disabled
图 49. Power Up with Charge Enabled
VBUS = 5 V
VBUS = 12 V
图 50. Charge Enable
图 51. Charge Disable
VBUS = 5 V
IIN = 3 A
Charge Disable
VBUS = 9 V
ICHG = 2 A
IIN = 1.5 A
VBAT = 3.8 V
ISYS = 0 A - 4 A
图 52. Input Current DPM Response without Battery
图 53. Load Transient During Supplement Mode
54
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
VBUS = 12 V
VBAT = 3.8 V
ICHG = 3 A
VBUS = 9V
No Battery
ISYS = 10 mA,
Charge Disable
图 54. PWM Switching Waveform
图 55. PFM Switching Waveform
VBAT = 3.8 V
ILOAD = 1 A
VBAT = 3.8 V
ILOAD = 0 A - 1 A
图 56. Boost Mode Switching Waveform
图 57. Boost Mode Load Transient
版权 © 2016–2018, Texas Instruments Incorporated
55
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
9.3 System Examples
Input
OTG
3.9Vœ14V at 3A
5V at 2.4A
VBUS
PMID
1ꢀH
SYS 3.5Vœ4.5V
1ꢀF
C1
SW
47nF
10ꢀF
10ꢀF
USB
47nF
BTST
Optional
DSEL
D+
REGN
4.7ꢀF
D-
1ꢀF
PGND
SYS
260
Ω
ILIM
SYS
Ichg=5A
10uF
BAT
VREF
QON
2.2K
Ω
STAT
SDA
10KΩ 10KΩ 10KΩ
Optiona
l
Host
REGN
SCL
INT
5.23K
Ω
TS
OTG
/CE
10KΩ
bq25890H
Copyright © 2016, Texas Instruments Incorporated
Recommended C1 = 8.2 μF (OTG ≤ 1.8 A) or 20 μF (OTG ≤ 2.4 A)
图 58. bq25890H with D+/D- Interface, USB On-The-Go (OTG) and no Thermistor Connections
56
版权 © 2016–2018, Texas Instruments Incorporated
BQ25890H
www.ti.com.cn
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 14 V input
with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage > VBATUVLO
connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the
charger to provide maximum output power to SYS.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 59) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground
with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or using a 0Ω resistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.
Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the VQFN
information, refer to SCBA017 and SLUA271.
11.2 Layout Example
图 59. High Frequency Current Path
版权 © 2016–2018, Texas Instruments Incorporated
57
BQ25890H
ZHCSI54A –SEPTEMBER 2016–REVISED MAY 2018
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
《四方扁平无引线逻辑封装》应用报告 SCBA017
《QFN/SON PCB 连接》应用报告 SLUA271
《半导体和 IC 封装热指标》应用报告 SPRA953
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
58
版权 © 2016–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25890HRTWR
BQ25890HRTWT
ACTIVE
WQFN
WQFN
RTW
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ
25890H
ACTIVE
RTW
NIPDAU
BQ
25890H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25890HRTWR
BQ25890HRTWT
WQFN
WQFN
RTW
RTW
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25890HRTWR
BQ25890HRTWT
WQFN
WQFN
RTW
RTW
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
BQ25890_15
bq25890/2 I2C Controlled Single Cell 5-A Fast Charger with MaxChargeTM Technology for High Input Voltage and Adjustable Voltage USB On-the-Go Boost Mode
TI
BQ25892_15
bq25890/2 I2C Controlled Single Cell 5-A Fast Charger with MaxChargeTM Technology for High Input Voltage and Adjustable Voltage USB On-the-Go Boost Mode
TI
BQ25895M
bq25895M I2C Controlled Single Cell Fast Charger with MaxChargeTM Technology for High Input Voltage
TI
BQ25895MRTWR
bq25895M I2C Controlled Single Cell Fast Charger with MaxChargeTM Technology for High Input Voltage
TI
BQ25895MRTWT
bq25895M I2C Controlled Single Cell Fast Charger with MaxChargeTM Technology for High Input Voltage
TI
©2020 ICPDF网 联系我们和版权申明