BQ25968 [TI]
I2C 控制的单节电池高效率 ADC、6A 开关电容快速充电器;
| 型号： | BQ25968 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | I2C 控制的单节电池高效率 ADC、6A 开关电容快速充电器 电池 开关 |
| 文件： | 总88页 (文件大小：2359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25968
ZHCSNA1A –APRIL 2020 –REVISED FEBRUARY 2021
BQ25968 具有ADC 的I2C 控制型单节电池高效率6A 开关电容快速充电器
– ADC 读数和配置
• 集成式16 位有效模数转换器(ADC)
1 特性
• 97% 高效功率级可实现6A 快速充电
• 正在申请专利的开关电容充电器架构经过优化，可
实现50% 的占空比
– ±0.5% 总线电压
– ±0.5% VOUT 电压
– –0.4% 至0.2% 电池电压（使用差分检测）
– 输入电压为电池电压的2 倍（3.5 V 至4.65 V）
– 输出电流为输入电流的2 倍
– ±1.5% 电池电流（6A，使用外部RSENSE
– ±1% 电池温度
）
（高达4.5A）
– 降低电缆的功率损耗
– ±1% 总线温度
– ±4°C 裸片温度
• 可实现安全运行的集成可编程保护功能
– 输入过压保护(BUS_OVP)
2 应用
– 具有可调警报的输入过流保护(BUS_OCP)
– 使用外部OVP FET 实现输入过压保护
（VAC_OVP 高达17V）
• 智能手机
• 平板电脑
3 说明
– 具有可调警报的电池过压保护(BAT_OVP)
BQ25968 是使用开关电容器架构且效率达 97% 的高
效 6A 电池充电解决方案。该架构和集成式 FET 经过
优化，可实现 50% 占空比，这就允许电缆电流为向电
池提供的电流的一半，从而降低充电电缆上的损耗并限
制应用中的温度升高。
– 输出过压保护(VOUT_OVP)
– 具有可调警报的输入过流保护(BUS_OCP)
– 具有可调警报的IBAT 过流保护(BAT_OCP)
– 开关MOSFET 逐周期电流限制
– 电池温度监测
– 连接器温度监控
• 用于系统优化的可编程设置
器件信息(1)
封装尺寸（标称值）
器件型号
BQ25968
封装
– 为中断提供了STAT、FLAG 和MASK 选项
DSBGA (56)
3.00mm x 3.20mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
Phone
BQ25968
VOUT
SC
Phase #1
SC
Phase #2
Adaptor
BQ2589x
SW
VBUS
AC/DC
SYSTEM
Converter
SYS
D+/D-
D+/D-
BAT
Host + PD Controller
(MSP430 + TPS25740)
CC1/ CC2
PD Controller
(TUSB422)
I2C
AP
(MSP430)
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSE31
BQ25968
www.ti.com.cn
ZHCSNA1A –APRIL 2020 –REVISED FEBRUARY 2021
Table of Contents
9.5 Programming............................................................ 28
9.6 Register Maps...........................................................30
10 Application and Implementation................................72
10.1 Application Information........................................... 72
10.2 Typical Application.................................................. 72
11 Power Supply Recommendations..............................77
12 Layout...........................................................................78
12.1 Layout Guidelines................................................... 78
12.2 Layout Example...................................................... 78
13 Device and Documentation Support..........................82
13.1 Device Support....................................................... 82
13.2 Documentation Support.......................................... 82
13.3 接收文档更新通知................................................... 82
13.4 支持资源..................................................................82
13.5 Trademarks.............................................................82
13.6 静电放电警告.......................................................... 82
13.7 术语表..................................................................... 83
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................8
8.6 Typical Characteristics..............................................13
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................25
Information.................................................................... 83
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (April 2020) to Revision A (February 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 在“特性”中将“开关电容充电器架构经过优化，可实现50% 的占空比”更改为“正在申请专利的开关电容
充电器架构经过优化，可实现 50% 的占空比”................................................................................................. 1
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English Data Sheet: SLUSE31
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ZHCSNA1A –APRIL 2020 –REVISED FEBRUARY 2021
5 说明（续）
两相架构可提高充电效率并降低输入和输出电容要求。当与BQ25790 等主充电器配合使用时，该系统能够通过预
充电（通过CC、CV 和终端进行）以最低的功耗实现最快的充电速度。
两相架构可降低输入电容器要求并减少输出电压纹波。当与BQ2589x 等标准充电器配合使用时，该系统能够通过
预充电（通过CC、CV 和终端进行）以最低的功耗实现最快的充电速度。
该器件集成了确保安全充电的所有必要保护特性，包括输入过压和过流保护、输出过压和过流保护、电池和电缆
温度检测以及裸片温度监测。
该器件包含一个 12 位有效模数转换器 (ADC)，以通过智能壁式适配器或移动电源提供总线电压、总线电流、输出
电压、电池电压、电池电流、总线温度、电池温度、裸片温度和管理电池充电所需的其他计算测量值。
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ZHCSNA1A –APRIL 2020 –REVISED FEBRUARY 2021
6 Device Comparison Table
FUNCTION
Device ID
BQ25970
BQ25971
0001
No
BQ25968
0000
0110
Yes. VAC up to 40 V
No
External OVPFET Control
IBAT, VBAT regulation
Yes. VAC up to 40 V
Yes, through external OVPFET
No
VDROP OVP protection during
regulation
Yes
8A
No
8A
No
6A
Recommended charging current
7 Pin Configuration and Functions
1
2
3
4
5
6
7
CDRVL
_ADDRMS
H
G
F
GND
CFL1
VOUT
CFH1
TSBUS
CDRVH
GND
GND
GND
GND
GND
GND
GND
CFL1
CFL1
CFL1
CFL2
CFL2
CFL2
CFL2
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
CFH1
CFH1
CFH1
CFH2
CFH2
CFH2
CFH2
PMID
PMID
PMID
PMID
PMID
PMID
REGN
VBUS
VBUS
VBUS
VBUS
SRN
SDA
SCL
VAC
E
D
C
B
A
OVPGATE
/INT
BATN
TSBAT
_SYNCOUT
BATP
_SYNCIN
SRP
Not to scale
图7-1. YFF Package 56-Pin DSBGA Bottom View
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表7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A1, B1,
C1, D1,
E1, F1,
G1, H1
GND
P
P
P
Power ground.
A2, B2,
C2, D2
Switched cap flying cap connection. Connect three 22-µF capacitors in parallel between
this pin and CFH2.
CFL2
A3, B3,
C3, D3,
E3, F3,
G3, H3
VOUT
Device power output. Connect a 22-µF capacitor between this pin and GND.
Switched cap flying cap connection. Connect a three 22-µF capacitors in parallel
between this pin and CFL2. Other capacitor values and number can be used, and will
affect VOUT ripple and efficiency.
A4, B4,
C4, D4
CFH2
P
Battery temperature voltage input and Master Mode SYNCOUT. Requires external
resistor divider, NTC, and voltage reference. See the TSBAT section for choosing the
resister divider values. If the device is in Master Mode, connect this pin to SYNCIN of
the Slave device.
A5
A6
A7
TSBAT_SYNCOUT
AIO
Positive input for low side battery current sensing. Place a 2-mΩor 5-mΩRSENSE
between SRN and SRP. Short to SRN and SRP together and GND if not used. Since
the device senses the current by measuring the voltage drop across RSENSE, if other
than 2-mΩor 5-mΩRSENSE is used, the host device will have to scale the IBAT_ADC
reading appropriately.
SRP
AI
Positive input for battery voltage sensing. Connect to positive terminal of battery pack.
Place 100-Ωto 1-kΩseries resistance between pin and positive terminal. If configured
as a Slave for parallel configuration, this pin functions as SYNCIN, and connect to
SYNCOUT of Master, and connect a 1-kΩpullup resistor to REGN.
BATP_SYNCIN
PMID
AI
P
B5, C5,
D5, E5,
F5, G5
PMID is the input to the switched cap power stage. Connect 10-µF cap to PMID.
Negative input for low side battery current sensing. Place a 2-mΩor 5-mΩRSENSE
between SRN and SRP. Short to SRP and SRN together and to GND if not used.
B6
B7
SRN
BATN
AI
AI
Negative input for batter voltage sensing. Connect to negative terminal of battery pack.
Place 100-Ω/1-k series resistance between pin and negative terminal.
C6, D6,
E6, F6
Device power input. Place a 1-µF bypass cap to GND as close as possible to these
pins.
VBUS
P
Open drain, active low interrupt output. Pull up to voltage with 10-kΩresistor. Normally
C7
D7
INT
DO
AO
high, the device asserts low to report status and faults. INT is pulsed low for tINT
.
External OVP FET N-channel gate drive pin. A minimum of 8-nC of capacitance is
required from the OVP FET Gate to Source. Float if not in use.
OVPGATE
Switched cap flying cap connection. Connect three 22-µF caps in parallel between this
pin an CFH1. Other capacitor values and number can be used, and will affect VOUT
ripple and efficiency.
E2, F2,
G2, H2
CFL1
CFH1
P
P
Switched cap flying cap connection. Connect three 22-µF caps in parallel between this
pin and CFL1. Other capacitor values and number can be used, and will affect VOUT
ripple and efficiency.
E4, F4,
G4, H4
E7
F7
G6
G7
VAC
SCL
AI
DIO
AO
DI
Device power input. Tie to VBUS if BQ25971 (no external OVP FET).
I2C interface data. Pull up to voltage with 1-kΩresistor.
LDO output. Connect a 4.7-µF cap between this pin and GND.
I2C interface clock. Pull up to voltage with 1-kΩresistor.
REGN
SDA
BUS temperature voltage input. Requires external resistor divider, NTC, and voltage
reference.
H5
H6
TSBUS
CDRVH
AI
AIO
Charge pump for gate drive. Connect a 0.22-µF cap between CDRVH and CDRVL.
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表7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Charge pump for gate drive. Connect a 0.22-µF cap between CDRVH and CDRVL.
During POR, this pin is used to assign the address of the device and the mode of the
device as Standalone, Master, or Slave. See 表9-2 in 节9.3.10 for a table of
functionality.
H7
CDRVL_ADDRMS
AIO
(1) Type: P = Power , AIO = Analog Input/Output , AI = Analog Input, DO = Digital Output, AO = Analog Output, DIO = Digital Input/Output
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
40
20
20
7
UNIT
V
Voltage
VAC
VBUS
V
–2
PMID
V
–0.3
–1.4
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
CFL1, CFL2, VOUT
SRP, SRN
V
1.8
6
V
Voltage
BATP_SYNCIN, BATN
OVPGATE - VBUS
INT, SDA, SCL, CDRVL_ADDRMS, REGN
CDRVH
V
14
6
V
V
20
6
V
TSBUS, TSBAT_SYNCOUT
V
CFH1, CFH2, while maintaining CFH-VOUT
= 7VMAX
Voltage
0
14
V
SRP-SRN
VOUT - VBUS
INT
0.5
6
V
V
–0.5
–16
Maximum Voltage Difference
Output Sink Current
6
mA
°C
°C
Junction Temperature, TJ
Storage Temperature, TSTG
150
150
–40
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VAC
12
12
6
V
V
V
V
V
V
V
V
V
VBUS
VOUT
3
CFH1-VOUT, CFL1, CFH2-VOUT, CFL2
BATP_SYNCIN, BATN
7
0
–0.05
–0.1
0
6
Voltage
SRP-SRN
0.05
SRN
TSBAT_SYNCOUT, TSBUS
SDA, SCL, CDRVL_ADDRMS, INT, CHGSTAT
3
5
0
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MAX UNIT
ZHCSNA1A –APRIL 2020 –REVISED FEBRUARY 2021
8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
IVOUT
Current
0
8
A
8.4 Thermal Information
BQ25968
THERMAL METRIC
YFF (DSBGA)
56 PIN
47.6
UNIT
RθJA
RθJC(top)
RθJB
ωJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
10.3
0.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
10.4
ωJB
8.5 Electrical Characteristics
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
ADC Disabled, Charge Disabled,
OVPGATE not used
285
345
400
385
8
µA
µA
µA
µA
µA
µA
µA
ADC Disabled, Charge Disabled,
OVPGATE used
IQ_VBUS
VBUS Operating Quiescent Current
ADC Enabled (fastest mode), Charge
Disabled
ADC Enabled (slowest mode), Charge
Disabled
ADC Disabled, Charge Disabled, VIN Not
Present
18
ADC Enabled (slowest mode), Charge
Disabled, VBUS Not Present
IQ_BAT
Battery Only Quiescent Current
385
385
ADC Enabled (fastest mode), Charge
Disabled, VBUS Not Present
RESISTANCES
RQB_ON
VBUS to PMID On Resistance
VBUS = 9 V
6
22
10
7
8
27
16
14
14
27
16
14
14
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
kΩ
RQCH1_ON
RQDH1_ON
RQCL1_ON
RQDL1_ON
RQCH2_ON
RQDH2_ON
RQCL2_ON
RQDL2_ON
RVBUS_PD
RVAC_PD
On resistance of QCH1
On resistance of QDH1
On resistance of QCL1
On resistance of QDL1
On resistance of QCH2
On resistance of QDH2
On resistance of QCL2
On resistance of QDL2
VBUS pull-down resistance
VAC pull-down resistance
VPMID = 9 V
CFLY = 4.5 V
VOUT = 4.5 V
CFLY = 4.5 V
VPMID = 9 V
CFLY = 4.5 V
VOUT = 4.5 V
CFLY = 4.5 V
8
22
10
7
8
6
130
Ω
INTERNAL THRESHOLDS
VBUSUVLO Rising
VBUS Rising
3.3
V
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8.5 Electrical Characteristics (continued)
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Rising
VAC Rising
3.3
VACUVLO
VOVPGATE
VOUTUVLO
Falling Hysteresis
300
10
mV
External FET Gate Drive Voltage,
Measured from Gate to Source, with
minimum 8 nF CGS
VAC = 8 V
V
Rising
2.3
3.5
V
mV
V
Falling Hysteresis
Rising
100
300
VACPRESEN
T
Falling Hysteresis
Rising
mV
V
2.85
2.85
VBUSPRESE
NT
Falling Hysteresis
Rising
500
2.3
100
150
30
mV
V
VOUTPRESE
NT
Falling Hysteresis
Rising Internal (TJ) Shutdown
Falling Hysteresis
mV
°C
°C
TSHUT
PROTECTION and ALARMS THRESHOLD AND ACCURACY
VOUTOVP
VDROP
VOUT OVP rising threshold
VDROP rising threshold
VDROP rising threshold
VBAT Over-Voltage Range
VBAT Over-Voltage Step Size
VBAT Over-Voltage Accuracy
VBAT Alarm Range
4.8
4.2
4.9
300
400
5
V
Adjustable in Register 0x05h, bit 4 = 0
Adjustable in Register 0x05h, bit 4 = 1
mV
mV
V
VDROP
4.65
10
mV
VBATOVP
Adjustable in Register 0x00h
1%
–1%
4.2
4.65
V
Adjustable in Register 0x01h
VBAT Alarm Step Size
25
50
mV
mV
VBAT_ALM
VBAT Alarm Hysteresis
VBAT Alarm Comparator Accuracy
IBAT_OCP Range
Falling
From VBAT = 3.5 V to 4.4 V
Adjustable in Register 0x02h
0.4%
10
–0.4%
0
A
IBAT_OCP Step Size
50
mA
IBAT_OCP
IBAT_OCP Comparator Accuracy
IBATOCP_ALM Range
IBAT = 6 A
5%
10
–5%
Adjustable in Register 0x03h
0
A
IBATOCP_ALM Step Size
IBATOCP_ALM Hysteresis
50
50
mA
mA
IBATOCP_ALM
Falling
IBATOCP_ALM Comparator Accuracy IBAT = 6 A and 9 A
1%
10
–1%
IBATUCP_ALM Range
Adjustable in Register 0x04h
0
A
IBATUCP_ALM Step Size
IBAT_UCP_ALM Hysteresis
50
50
mA
mA
IBATUCP_ALM
Rising
IBATUCP_ALM Comparator Accuracy IBAT = 3 A
2%
17
–2%
VAC_OVP Range
Adjustable in Register 0x05h
6.5
V
V
VAC_OVP Step Size
Step size valid for 11 V through 17 V only
Accuracy for 6.5 V
1
VVAC_OVP
VAC_OVP Comparator Accuracy
VAC_OVP Comparator Accuracy
2%
2%
–2%
–2%
Accuracy for 11 V through 17 V
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8.5 Electrical Characteristics (continued)
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Adjustable in Register 0x06h, 250 mV
typical hysteresis
VBUS_OVP Range
6
12.35
VBUS_OVP
VBUS_OVP Step Size
50
mV
VBUS_OVP Comparator Accuracy
VBUSOVP_ALM Range
VBUS = 10 V
1%
–1%
Adjustable in Register 0x07h
6
12.35
mV
mV
mV
VBUSOVP_ALM Step Size
VBUSOVP_ALM Hysteresis
VBUSOVP_ALM Comparator Accuracy
IBUS_OCP Range
50
50
VBUSOVP_AL
M
Falling
0.5%
4.75
–0.5%
Adjustable in Register 0x08h
3 A
0
A
IBUS_OCP Step Size
50
300
500
mA
IBUS_OCP
IBUS_UCP
IBUS_UCP
IBUS_OCP Comparator Accuracy
5%
–5%
IBUS_UCP Rising, IBAT must reach
this value before the SS timeout or
Switching Stops, Protection disabled
until IBUS Current Reaches this Value
Adjustable in Register 0x2Bh, bit 2 = 0
375
mA
mA
IBUS_UCP Rising, IBAT must reach
this value before the SS timeout or
Switching Stops, Protection disabled
until IBUS Current Reaches this Value
Adjustable in Register 0x2Bh, bit 2 = 1
Adjustable in Register 0x2Bh, bit 2 = 0
575
IBUS_UCP Falling, Switching stops
when IBUS current reaches this value
10
150
250
mA
mA
IBUS_UCP
IBUS_UCP Falling, Switching stops
when IBUS current reaches this value
Adjustable in Register 0x2Bh, bit 2 = 1
Adjustable in Register 0x09h
100
0
IBUSOCP_ALM Range
IBUSOCP_ALM Step Size
IBUSOCP_ALM Hysteresis
4.95
A
50
50
mA
mA
IBUSOCP_AL
M
Falling
IBUSOCP_ALM Comparator Accuracy IBUS = 3 A (0°C to 85°C)
TSBUS and TSBAT voltage range
4%
–4%
0%
75%
TSBUS and TSBAT Threshold Step
Size
0%
0.1953%
1%
TSBAT_FLT
TSBUS_FLT
TSBUS and TSBAT Comparator
Accuracy
–1%
TSBUS and TSBAT Falling Hysteresis
4%
TIMINGS
fSW
Switching Frequency
VAC OVP reaction time
VAC OVP reaction time
VAC Pulldown duration
Register set to 500 kHz in Register 0x0Bh
500
0.1
5.5
400
kHz
µs
tVAC_OVP
tVOUT_OVP
tVAC_PD
µs
ms
VBUS OVP reaction time (Note: The
deglitch time is increased during
regulation)
tVBUS_OVP
tIBUS_OCP
tIBUS_UCP
Not in regulation
Not in regulation
1
75
10
µs
µs
µs
IBUS OCP reaction time (Note: The
deglitch time is increased during
regulation)
IBUS UCP falling reaction time (Note:
The deglitch time is increased during
regulation)
Not in regulation. Adjustable in Register
0x2Eh, bit 4 = 0
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8.5 Electrical Characteristics (continued)
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IBUS UCP falling reaction time (Note:
The deglitch time is increased during
regulation)
Not in regulation. Adjustable in Register
0x2Eh, bit 4 = 1
tIBUS_UCP
10
ms
VDROP rising threshold deglitch (Note:
The deglitch time is increased during
regulation)
Not in regulation. Adjustable in Register
0x2Eh, bit 3 = 0
tVDROP
10
5
µs
VDROP rising threshold deglitch (Note:
The deglitch time is increased during
regulation)
Not in regulation. Adjustable in Register
0x2Eh, bit 3 = 1
tVDROP
ms
0
5
µs
ms
µs
tVBAT_OVP
tVOUT_OVP
tIBAT_OCP
VBAT OVP reaction time
VOUT OVP reaction time
IBAT OCP reaction time
Deglitch during regulation
Deglitch during regulation
4
500
5
µs
ms
Duration that INT is pulled low when an
event occurs
tINT
256
650
µs
If the part is in regulation, but below
VDROP_OVP for this amount of time, the
part will stop switching.
tREG_TIMEOU
ms
T
Rising
Falling
100
5
ms
ms
tINT_REG_DG Deglitch when INT is pulled low after
an event occurs
L
TALM_DEBOU Time between consecutive faults for
120
1
ms
µs
ALM indication
NCE
tBUS_DETACH IBUS threshold reaction time
ADC MEASUREMENT ACCURACY AND PERFORMANCE
ADC_SAMPLE[1:0] = 00
24
12
6
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
ADC_SAMPLE[1:0] = 00
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
tADC_CONV Conversion Time, Each Measurement
ms
3
14
13
12
11
ADCRES
Effective Resolution (0°C to 85°C)
bits
ADC MEASUREMENT RANGES AND LSB
Range
0
5
A
ADC Bus Current Readable in
IBUS_ADC
Registers 0x16h and 0x17h
LSB
1
1
mA
IBUS_ADC ADC Accuracy
IBUS_ADC ADC Accuracy
1.5 A (0°C to 85°C)
3 A (0°C to 85°C)
Range
5%
5%
14
–5%
–5%
0
V
VBUS_AD ADC Bus Voltage Readable in
C
Registers 0x18h and 0x19h
LSB
mV
VBUS_AD ADC Bus Voltage
C
Accuracy for 8V, ADC_RATE = 00
0.5%
14
–0.%5
Range
0
V
ADC VAC Voltage Readable in
Registers 0x1Ah and 0x1Bh
VAC_ADC
LSB
1
1
mV
VAC_ADC ADC VAC Voltage
Accuracy for 8 V, ADC_RATE = 00
0.5%
5
–0.5%
Range
LSB
0
V
VOUT_AD ADC Output Voltage Readable in
C
Registers 0x1Ch and 0x1Dh
mV
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8.5 Electrical Characteristics (continued)
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT_AD ADC Output Voltage
C
Accuracy for 4 V, ADC_RATE = 00
0.5%
–0.5%
Range
LSB
0
5
V
ADC Battery Voltage Readable in
Registers 0x1Eh and 0x1Fh
VBAT_ADC
1
mV
VBAT_ADC ADC Battery Voltage
Accuracy for 3.5 V through 4.4 V,
ADC_RATE = 00
0.2%
10
–0.4%
Range
0
A
ADC Battery Current Readable in
Registers 0x20h and 0x21h
IBAT_ADC
1
mA
LSB with 2 mΩRSENSE
IBAT_ADC ADC Battery Current
IBAT_ADC ADC Battery Current
IBAT_ADC ADC Battery Current
3 A
6 A
9 A
2%
1.5%
1.5%
–2%
–1.5%
–1.5%
TSBUS_AD
ADC TSBUS pin voltage
C
Range
0.2
0%
2.7
V
Range
50%
TSBUS_AD ADC TSBUS % of VOUT Readable in
C
0.09766
%
Registers 0x22h and 0x23h
LSB
TSBUS_AD ADC TSBUS Accuracy
C
TSBUS pin voltage 2 V
1%
–1%
TSBAT_AD
ADC TSBAT pin voltage
C
Range
0.2
0%
2.7
V
Range
50%
TSBAT_AD ADC TSBAT pin voltage Readable in
C
0.09766
%
Registers 0x24h and 0x25h
LSB
TSBAT_AD ADC TSBAT pin voltage
C
TSBAT pin voltage 2 V
1%
–1%
–40
Range
LSB
150
°C
°C
°C
ADC Die Temperature Readable in
Registers 0x26h and 0x27h
TDIE_ADC
0.5
±4
TDIE_ADC ADC Die Temperature (Typ over temp)
REGN LDO
VREGN
IREGN
REGN LDO Output Voltage
REGN LDO Current Limit
VBUS = 8 V
5
V
VBUS = 8 V, VREGN = 4.5 V
50
1.3
1.3
mA
LOGIC I/O THRESHOLDS ( INT, BATP_SYNCIN)
VIL
Input Low Threshold
ISINK = 5 mA
0.4
1
V
V
VIH
Input High Threshold
ISINK = 5 mA
ILEAK
High Level Leakage Current
VPULL-UP = 3.3 V
µA
LOGIC I/O THRESHOLDS (TSBAT_SYNCOUT)
VOH
VOL
Output High Threshold
Output Low Threshold
VPULL-UP = 1.8V
VPULL-UP = 1.8V
0.4
0.4
I2C LEVELS and TIMINGS
VIL
Input Low Threshold
VPULL-UP = 1.8 V, SDA and SCL
VPULL-UP = 1.8 V, SDA and SCL
IOL = 20 mA
V
V
VIH
Input High Threshold
Output Low Threshold
High Level Leakage Current
SCL Clock Frequency
Data Set-Up Time
1.3
VOL
0.4
1
V
IBIAS
fSCL
tSU_STA
tHD_DAT
VPULL-UP = 1.8 V, SDA and SCL
µA
MHz
ns
ns
1
10
0
Data Hold Time
70
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8.5 Electrical Characteristics (continued)
over operating free-air temperature range of –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Cbus = 100 pF max
Cbus = 100 pF max
MIN
10
TYP
MAX
80
UNIT
ns
trDA
tfDA
Rise Time of SDA Signal
Fall Time of SDA Signal
10
80
ns
8.6 Typical Characteristics
Typical characteristics are taken with test equipment for nonswitching tests, and with the EVM-893 for switching tests.
98
97.5
97
1.4
1.2
1
96.5
96
0.8
0.6
0.4
0.2
0
95.5
95
187.5kHz
250kHz
300kHz
375kHz
500kHz
750kHz
187.5kHz
250kHz
300kHz
375kHz
500kHz
750kHz
94.5
94
93.5
93
0.5
1.5
2.5
3.5
Charging Current (A)
4.5
5.5
6.5
7
0.5
1.5
2.5
3.5
Charging Current (A)
4.5
5.5
6.5
7
图8-1. BQ25968 Device Efficiency, 3 x 22-µF Caps Per Phase
图8-2. BQ25968 Device Power Loss, 4 x 20-µF Caps Per Phase
98
1.2
97.5
97
1
0.8
96.5
0.6
187.5kHz
187.5kHz
250kHz
300kHz
375kHz
500kHz
750kHz
250kHz
300kHz
375kHz
500kHz
750kHz
96
95.5
95
0.4
0.2
0
1
2
3
4
Charging Current (A)
5
6
7
0.5
1.5
2.5
3.5
Charging Current (A)
4.5
5.5
6.5
7
图8-3. BQ25968 Device Efficiency, 4 x 22-µF Caps Per Phase
图8-4. BQ25968 Device Power Loss, 4 x 22-µF Caps Per Phase
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8.6 Typical Characteristics (continued)
Typical characteristics are taken with test equipment for nonswitching tests, and with the EVM-893 for switching tests.
98
97.5
97
56
55
54
53
52
51
50
49
48
47
46
45
44
96.5
96
187.5 kHz
250 kHz
300 kHz
375 kHz
500 kHz
187.5 kHz - M_IBUS_%
187.5 kHz - S_IBUS_%
250 kHz - M_IBUS_%
250 kHz - S_IBUS_%
300 kHz - M_IBUS_%
300 kHz - S_IBUS_%
375 kHz - M_IBUS_%
375 kHz - S_IBUS_%
500 kHz - M_IBUS_%
95.5
95
2
2.5
3
3.5
4
4.5
5 5.5
IBAT (A)
6
6.5
7
7.5
8
8.5
9
2
2.5
3
3.5
4
4.5
5
5.5
IBAT (A)
6
6.5
7
7.5
8
8.5
9
D030
D031
A1 BV L13 4*20-µF caps per phase, 2-mΩIBAT sense
A1 BV L13 4*20-µF caps per phase, 2-mΩIBAT sense
resistor
resistor
图8-5. BQ25968 Parallel Efficiency
图8-6. BQ25968 Parallel Current Sharing
1.2
200
180
160
140
120
100
80
1
0.8
0.6
0.4
187.5 kHz
250 kHz
60
40
300 kHz
375 kHz
500 kHz
0.2
0
2 Caps/Phase
3 Caps/Phase
4 Caps/Phase
20
0
2
2.5
3
3.5
4
4.5
5
5.5 6 6.5 7 7.5 8 8.5 9
0
1
2
3
4
5
Charge Current (A)
6
7
8
IBAT (A)
D032
D024
A1 BV L13 4*20-µF caps per phase, 2-mΩIBAT sense
图8-8. VBAT Ripple at 500 kHz
resistor
图8-7. BQ25968 Parallel Power Loss
0.035
0
VOUT Error
25 - 0
25 - 1
25 - 10
25 - 11
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
0.03
0.025
0.02
0.015
0.01
0.005
0
0
0.5
1
1.5
2
2.5
VBAT (V)
3
3.5
4
4.5
5
3.5
3.75
4
4.25 4.5
VBAT_OVP Target (V)
4.75
5
D027
D028
图8-9. VOUT_ADC Error
图8-10. VBAT_OVP Error
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8.6 Typical Characteristics (continued)
Typical characteristics are taken with test equipment for nonswitching tests, and with the EVM-893 for switching tests.
2
1.5
1
0.2
0.15
0.1
25 - 0 - 3.5
25 - 0 - 3.8
25 - 0 - 4.2
0 - 500 kHz - 3.8 - No
25 - 500 kHz - 3.8 - No
85 - 500 kHz - 3.8 - No
0.5
0
0.05
0
-0.5
-1
-0.05
-0.1
-0.15
-0.2
-1.5
-2
0
0.5
1
1.5
TS_BAT (V)
2
2.5
3
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9
IBUS (A)
D033
D039
图8-11. TS_BAT Error
图8-12. IBUS_ADC Error
5
4
0.1
0.08
0.06
0.04
0.02
0
3
2
1
0
-0.02
-0.04
-0.06
-0.08
-0.1
-1
-2
-3
-4
-5
1
2
3
4
5
IBAT (A)
6
7
8
9
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
IBAT (A)
D037
D038
图8-13. IBAT_ADC Error
图8-14. IBAT_ADC Error
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9 Detailed Description
9.1 Overview
The BQ25968 is a 97% efficient, 6-A battery charging solution using a switched cap architecture. This
architecture and the integrated FETs are optimized to enable a 50% duty cycle, allowing the cable current to be
half the current delivered to the battery, reducing the losses over the charging cable as well as limiting the
temperature rise in the application. The dual-phase architecture reduces the input cap requirements as well as
reducing the output voltage ripple. When used with a standard charger such as the BQ2589x, the system
enables the fastest charging at the lowest power loss from precharge through CC, CV, and termination.
The device integrates all the necessary protection features to ensure safe charging, including input overvoltage
and overcurrent protection, output overvoltage and overcurrent protection, temperature sensing for the battery
and cable, and monitoring the die temperature.
The device includes a 16-bit (minimum 12-bit effective) ADC to provide bus voltage, bus current, output voltage,
battery voltage, battery current, bus temperature, bat temperature, die temperature, and other calculated
measurements needed to manage the charging of the battery from the smart wall adapter or power bank.
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9.2 Functional Block Diagram
BQ25968
CDRVH
CDRVL_ADDRMS
REGN
QB
VBUS
PMID
D
QCH2
G
D
QCH1
QDH1
QCL1
QDL1
G
G
G
G
Switched
Cap
Control
OVP, REG, and ILIM
Control
CFH2
OVPGATE
S
S
D
D
CFH1
VAC
QDH2
G
S
D
S
D
VOUT
QCL2
G
SDA
S
D
S
Digital Core
SCL
D
CFL1
QDL2
G
/INT
CFL2
S
S
BATP_SYNCIN
VBUS_ADC
VBAT_ADC
IBAT_ADC
BATN
TBUS_ADC
VAC_ADC
IBUS_ADC
TBAT_ADC
ADC
VOUT_ADC
+
-
DIE_TEMP_ADC
SRP
TSBUS_FLT
TSBUS
VBUS
VBUS_OVP
+
-
SRN
+
-
+
-
VBAT_OVP
VAC
VAC_OVP
+
-
Protection
TSBAT_
SYNCOUT
+
-
+
-
IBAT_OCP
+
-
TSBAT_FLT
GND
9.3 Feature Description
9.3.1 Charging System
The BQ25968 is a slave charger used with a fast charging switching charger such as the BQ25890. A host must
set up the protections and alarms on the BQ25968 prior to disabling the SW charger and enabling the BQ25968
charger. The host must monitor the alarms generated by the BQ25968 and communicate with the smart adapter
to control the current delivered to the charger.
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Phone
BQ25968
VOUT
SC
Phase #1
SC
Phase #2
Adaptor
BQ2589x
SW
VBUS
AC/DC
SYSTEM
Converter
SYS
D+/D-
D+/D-
BAT
Host + PD Controller
(MSP430 + TPS25740)
CC1/ CC2
PD Controller
(TUSB422)
I2C
AP
(MSP430)
图9-1. BQ25968 System Diagram
9.3.2 Battery Charging Profile
The system will have a specific battery charging profile that is unique due to the switched cap architecture.
During the trickle charge and precharge of the battery up to 3.5 V, the charging will be controlled by the primary
charger (BQ25890 in 图9-1). Once the battery voltage reaches 3.5 V, the adapter can negotiate for a higher bus
voltage, enable the BQ25968 charging, and regulate the current on VBUS to charge the battery. In the CC
phase, the protection in the BQ25968 will not regulate the battery voltage, but will provide feedback to the
system to increase/decrease current as needed, as well as disable the output if the voltage is exceeded. Once
the CV point is reached, the BQ25968 will provide feedback to the adapter to reduce the current, effectively
tapering the current until a point where the primary charger takes over again. This charging profile is shown in 图
9-2.
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8A
7A
Note: Current and Voltage steps are exagerated for
example only œ actual current steps are much
smaller
BAT_OVP
BAT_OVP_ALM
6A
5A
4A
Battery Current
Battery Voltage
Cable Current
3.5V
3A
3.5
2A
1A
3.0
3.0V
Pre-Charge
Pre-Charge
bq25890
CC
bq25890 bq25970
T2 T3
CC
CV
bq25970
CV
bq25890
T1
T4
T5
图9-2. BQ25968 System Charging Profile
9.3.3 Control State Diagram for System Implementation
The device being charged will need to communicate with the adapter to control the current being delivered to the
BQ25968. This is accomplished by using the adjustable protection and alarm settings in the BQ25968, and
communicating to the wall charger (or power bank or car charge adapter) as shown in 图 9-3. The availability of
the alarms are dependant on the presence of the input supply and the charge state, which is shown in 表9-1.
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Connection and
Cable
Smart Adapter With CC/CV control
Device with PD Controller, Host, Switching Charger and bq2597x
USB Plug In Event
PD Controller Startup
Enable SW Mode Charger and Provide Sys
Power;
Set Charge Disable;
Disable DPDM Detection
PD Controller run PD
Protocol on CC1/2;
Check VDM
Type-C bq2597x
Adapter?
N
Y
N
Y
Disable Doubler Charger;
Enable SW mode charger;
Monitor VBAT with bq2597x ADC
HVDCP Adapter?
N
Has VBAT
reached 3.5V?
Start HV SW mode
charging process
Y
Set initial bq2597x settings;
BUS Current Limit set to 0A
BUS Voltage Limit set to 5V
Set VBAT_ALM below VBATREG
Set VBAT_OVP to VBATREG
Set BAT_OCP to 8A (or desired level)
Set BUS_OCP to 4A (or desired level)
Disable the SW charger;
Start 5V SW mode
charging process
Enable the bq2597x
Increase BUS Voltage Limit to 2xVBATREG
(e.g. 8.7V for a 4.35V battery);
Increase BUS Current Limit to 4A (ramp)
Measure VOUT, calculate the cable and
connection voltage drop;
Send data to Adapter
Increase the BUS voltage OR BUS Current
(Preferred to be voltage limited current
source for best operation)
N
N
VBAT >
VBAT_ALM?
IBAT <
IBAT_UCP_ALM?
Y
Y
Reduce BUS Current Limit or BUS Voltage
Disable bq2597x;
Enable SW Charger;
Complete charge through Termination
图9-3. System Control State Diagram
表9-1. ALM/FLT Function Activity
VAC PRESENT
CHG_EN = 0
VAC PRESENT
CHG_EN = 1
ALM/FLT FUNCTION
BATTERY ONLY
Not Active
BAT_OVP_ALM
Not Active
Active
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表9-1. ALM/FLT Function Activity (continued)
VAC PRESENT
CHG_EN = 0
VAC PRESENT
CHG_EN = 1
ALM/FLT FUNCTION
BATTERY ONLY
BAT_OCP_ALM
BAT_UCP_ALM
BUS_OVP_ALM
BUS_OCP_ALM
TSBUS_FLT
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Not Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
TSBAT_FLT
Active
TDIE_ALM
Active
TSBUS_TSBAT_ALM
Active
9.3.4 Device Power Up
The device is powered from the greater of either VBUS or VOUT (battery). The voltage must be greater than the
VBUSPRESENT or VOUTPRESENT threshold to be a valid supply. However, the device will start drawing power
once the voltage rises above the VBUSUVLO or VOUTUVLO threshold.
The device has a watchdog timer, which is enabled by default. If the device is not read from or written to before
the watchdog expires, the part will stop switching. The first read of the watchdog timer flag will always read
‘1’. During initial power up of the device, upon completion of pin detection for address, an INT pulse will be
triggered to show a watchdog timeout. The host should not attempt to read or write before this initial INT signal.
The device will not charge when first powered up, as the default charge state is always not enabled. The ADC is
available prior to enabling charge so the system parameters are known to the host before enabling charge. If the
VOUT voltage is not greater than 3 V, the charger cannot be enabled. The lowest charge voltage allowed on
VOUT is 2.8 V falling.
Although the device will depend on the smart adapter to ramp the charging current, the device implements a soft
start through QB that limits the ramp current. If the current through QB is greater than the programmed VBUS_OCP
the FET is disabled. The output voltage ramps as the current is increased.
,
9.3.5 Switched Cap Function
The power stage used in the device is a parallel-series switched cap architecture with two phases. The output
voltage of the power stage is half of the input voltage. The output current of the power stage is twice the input
current. By controlling the constant current source input to the power stage, the CC and CV charging phases can
be achieved with the protections and alarms implemented in the device.
9.3.5.1 Theory of Operation
The power stage of the device is shown in the block diagram, and a simplified single phase circuit is shown in 图
9-4. When operating, the device switches at a 50% duty cycle with Q1 and Q3 turned on and off at the same
time, while Q2 and Q4 are turned on and off simultaneously. This results in the following equivalent circuits.
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I:
VIN
CPMID
Q1
Q2
Q3
Q4
VOUT
COUT
CFLY
图9-4. BQ25968 Simplified Switched Cap Architecture (single phase)
Q2 and Q4 turned on
Q1 and Q3 turned off
Q1 and Q3 turned on
Q2 and Q4 turned off
t2=
t1=
R1
R3
R4
R2
I:
I:
VOUT
COUT
VIN
VOUT
VIN
+
-
+
-
CFLY
CFLY
CPMID
CPMID
COUT
图9-5. BQ25968 Equivalent Circuits During Operation
t1
t2
t1
t2
t1
Gate Signal
t
V1
V2
Flying cap voltage
Flying cap current
t
t
I1
I3
I2
图9-6. BQ25968 Switching Waveforms
9.3.6 Charging Start-Up
Prior to enabling charging, set all the protections to the desired thresholds. Protections available are BAT_OVP,
BAT_OVP_ALM, BAT_OCP, BAT_OCP_ALM, BAT_UCP_ALM, AC_PROTECTION, BUS_OVP,
BUS_OVP_ALM, BUS_OCP_UCP, and BUS_OCP_ALM. These can be found in registers 0x0h through 0x9h.
The *_OVP and *_OCP registers set the thresholds where if these conditions are met, the charger stops
switching. The *_ALM registers set the thresholds where an interrupt is sent to the host to take actions to avoid
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reaching the *_OVP or *_OCP thresholds. The settings for the *_ALM registers will depend on the response time
required from the host and the operating conditions of the system.
Once the protections have been set, the BUS voltage must be between VBUS_ERROR_LO and
VBUS_ERROR_HI in order for the part to start switching. Register 0x0Ah contains the registers to check if these
conditions have been met. Typically VBUS_ERROR_LO is 2.05 times VBAT. It is recommended to start with
VBUS near this voltage when enabling charge. Once charge has been enabled, the CONV_SWITCHING_STAT
bit should be '1', and current will start to flow to the battery. Raising the BUS voltage will increase the current to
the battery. If using a current limited source, the voltage can be raised until reaching the current limit. The battery
current, IBAT, must reach the IBUS_UCP_THRESHOLD rise threshold within the SS_TIMEOUT_SET time.
These parameters can be set in register 0x2Bh. If the IBUS_UCP_THRESHOLD is not met within
SS_TIMEOUT_SET, switching stops and the startup sequence must be done again.
9.3.7 Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
The integrated 16-bit ADC of the device allows the user to get critical system information for optimizing the
behavior of the charger control. The control of the ADC is done through the ADC_CTRL register. The ADC_EN
bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous
conversion or one-shot behavior. The ADC_AVG_DIS bit enbles or disables averaging
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the
VVBUS>VBUSPRESENT or VVOUT>VOUTPRESENT is valid. If ADC_EN is set to ‘1’ before VBUS or VOUT reach
their respective PRESENT threshold, then the ADC conversion will be postponed until one of the power supplies
reaches the threshold.
The ADC_SAMPLE bits control the sample speed of the ADC, with conversion times of tADC_CONV. The
integrated ADC has two rate conversion options: a 1-Shot Mode and a Continuous Conversion Mode set by the
ADC_RATE bit. By default, all ADC parameters will be converted in 1-Shot or Continuous Conversion Mode
unless disabled in the ADC_FN_DIS register. If an ADC parameter is disabled by setting the correcsponding bit
in the ADC_FN_DIS register, then the value in that register will be from the last valid ADC conversion or the
default POR value (all zeros if no conversions have taken place). If an ADC parameter is disabled in the middle
of an ADC measurement cycle, the device will finish the conversion of that parameter, but will not convert the
parameter starting the next conversion cycle. Even though no conversion takes place when all ADC
measurement parameters are disabled, the ADC circuitry is active and ready to begin conversion as soon as one
of the bits in the ADC_FN_DIS register is set to ‘0’.
The ADC_DONE_* bits signal when a conversion is complete in 1-Shot Mode only. During Continuous
Conversion Mode, the ADC_DONE_* bits have no meaning and will be ‘0’.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set
ADC_EN = ‘0’ to disable the ADC. ADC readings are only valid for DC states and not for transients. When
the host writes ADC_EN = ‘0’, the ADC stops immediately. If the host wants to exit ADC more gracefully, it is
possible to do either of the following:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Write all the DIS bits low, and the ADC will stop at the end of the current measurement.
9.3.8 Device Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
The device has three temperature sensing mechanisms to protect the device and system during charging:
TSBUS for monitoring the cable connector temperature, TSBAT for monitoring the battery temperature, and
TDIE for monitoring the internal junction temperature of the device. TSBUS and TSBAT only operate when there
is a valid input supply. The TSBUS and TSBAT both rely on a resistor divider that has an external pullup voltage
to VOUT. Place a negative coefficient thermistor in parallel to the low-side resistor. A fault on the TSBUS and
TSBAT pin is triggered on the falling edge of the voltage threshold, signifying a “hot” temperature. The
threshold is adjusted using the TSBUS_FLT and TSBAT_FLT registers. A warning TSBUS_TSBAT_ALM
interrupt will be sent if the percentage reached within 5% of the FLT setting. If the TSBUS_FLT or TSBAT_FLT is
disabled, it will not trigger a TSBUS_TSBAT_ALM interrupt. The RLO and RHI resistors should be chosen
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depending on the NTC used. If a 10-kΩ NTC is used, use 10-kΩ resistors for RLO and RHI. If a 100-kΩ NTC is
used, use 100-kΩ resistors for RLO and RHI. The ratio of VTS/VOUT can be from 0% to 50%, and the voltage at
the TS pin is determined by the following equation.
1
1
1
≈
’
+
∆
«
÷
◊
RNTC RLO
1
VTSBUS or VTSBAT (V) =
ì VOUT
RHI +
1
1
≈
’
+
∆
«
÷
◊
RNTC RLO
(1)
The percentage of the TS pin voltage is determined by the following equation.
1
1
1
≈
’
+
∆
«
÷
◊
RNTC RLO
1
TSBUS or TSBAT (%) =
RHI +
1
1
≈
’
+
∆
«
÷
◊
RNTC RLO
(2)
Additionally, the device has an internal die temperature measurement, with adjustable threshold TDIE_FLT.
If TSBUS, TSBAT, or TDIE protections are not used, the functions can be disabled in the CHRG_CTRL register
by setting the TSBUS_DIS, TSBAT_DIS, or TDIE_DIS bit to ‘1’. If the TSBUS_FLT, TSBAT_FLT, thresholds
are reached, the CHG_EN bit is set to ‘0’, and the start-up sequence must be followed to resume charging.
Using the TDIE_ALM register, an alarm can be set to notify the host when the device die temperature exceeds a
threshold. The device will not automatically stop switching when reaching the alarm threshold, and the host may
decide on the steps to take to lower the temperature, such as reducing the charge current. The device will
automatically stop switching when it reaches the TSHUT threshold.
9.3.9 INT Pin, STAT, FLAG, and MASK Registers
The INT pin is an open drain pin that needs to be pulled up to a voltage with a pullup resistor. INT is normally
high and will assert low for tINT when the device needs to alert the host of a fault or status change. The behavior
of the INT pin is determined by six registers: INT_STAT, INT_FLAG, INT_MASK, FLT_STAT, FLT_FLAG, and
FLT_MASK.
The fields in the STAT registers show the current status of the device, and are updated as the status changes.
The fields in the FLAG registers indicate that the event has occurred, and the field is cleared when read. If the
event persists after the FLAG register has been read and cleared, another INT signal is not sent. The fields in
the MASK registers allow the user to disable the interrupt on the INT pin, but the STAT and FLAG registers are
still updated even though INT is not pulled low.
9.3.10 CDRVH and CDRVL_ADDRMS Functions
The device requires a cap between the CDRVH and CDRVL_ADDRMS pins to operate correctly. The
CDRVL_ADDRMS pin also allows setting the default I2C address and power-up AC_OVP threshold for external
OVP FET control. Pull to GND with a resistor for the desired setting shown in 表 9-2. Once I2C communication
begins with the device, the register sets the AC_OVP threshold.
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表9-2. BQ25968 I2C Address and Mode Selection
RESISTOR VALUE
TO GND ON
CDRVL_ADDRMS
I2C ADDR
I2C ADDR
(NVM_I2CADDR_ALT = 0)
MASTER, SLAVE, OR
STANDALONE OPERATION
(NVM_I2CADDR_ALT = AC_OVP SETTING
1)
0×65
0×66
0×65
0×66
0×66
0×67
0×67
0×67
6.5 V
(Disabled)
11 V
Master
Slave
18 KΩ
39 KΩ
Standalone
Standalone
75 KΩ
6.5 V
Open (>150 KΩ)
If a standalone device is needed with the AC_OVP function disabled, use the BQ25971.
9.3.11 Parallel Operation Using Master and Slave Modes
For higher power systems, it is possible to use two BQ25968 devices in parallel. This has the effect of reducing
the adapter power requirements, reducing the cable losses, and reducing the losses in the device. The parallel
system is shown in the figure below. The CDRVL_ADDRMS pin is used to configure the functionality of the
device as Master or Slave. Refer to 节9.3.10 for proper setting.
When configured as a Master, the TSBAT_SYNCOUT pin functions as SYNCOUT, and the BATP_SYNCIN pin
functions as BATP. When configured as a Slave, the TSBAT_SYNCOUT pin functions as TSBAT, and the
BATP_SYNCIN pin functions as SYNCIN. OVPGATE is controlled by the Master, and the OVPGATE pin on the
slave should be left floating. Pull the SYNCIN/SYNCOUT pins to REGN through a 1-kΩresistor.
VBUS
SW
SYSTEM LOAD
SYS
GND
BAT
BQ2589x
SDA/SCL
Ext.
OVPFET
Host
BQ25968_Slave
BQ25968_Master
VBUS
VBUS
SDA/
SCL
SDA/
SCL
Digital Core
Digital Core
QB
QB
OVPGATE
PMID
PMID
CFH1
CFH1
VOUT
VOUT
BATP
SC Phase
#1
SC Phase
#1
CFLY
CFLY
CFL1
CFH2
CFL2
CFL1
CFH2
PMID
PMID
BATN
SRP
SC Phase
#2
SC Phase
#2
CFL2
BATN
SRP
CDRVH
CDRVH
SRN
Protection
12-Bit ADC
12-Bit ADC
Protection
CDRVL_
ADDRMS
SRN
CDRVL_
ADDRMS
TSBAT_SYNCOUT
BATP_SYNCIN
图9-7. Parallel BQ25968 System
9.4 Device Functional Modes
9.4.1 Device Modes and Protection Status
表9-3 shows the features and modes of the device depending on the conditions of the device.
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表9-3. Device Modes and Protection Status
STATE
BATT-ONLY (VAC <
VACpres)
VAC > VACpresent
VAC > VACpresent
VAC > VACpresent
VAC > VACpresent
FUNCTIONS AVAILABLE
(REGARDLESS OF
VOUTpres)
DURING CHARGE
SOFTSTART
CHARGE DISABLED CHARGE DISABLED
CHARGING
(REGARDLESS OF
ADC)
(ADC NOT
(REGARDLESS OF
ADC)
ADC ENABLED
ENABLED)
(REGARDLESS OF ADC)
I2C allowed
Allow user ADC request
VAC FET gate drive
VAC OVP protection
TS_BUS ALM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TS_BAT ALM
DIE TMP ALM
VBUS OVP ALM
VBAT OVP ALM
VBAT OCP ALM
VOUT_OVP
X
VBUS OCP ALM
VBUS UCP ALM
VBUS In-range (slow UVP/OVP)
TS_BUS FLT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TS_BAT FLT
DIE TMP FLT
VBUS OVP FLT
VBAT OVP FLT
VBAT OCP FLT
VBUS OCP FLT
VBUS UCP FLT
Cycle by Cycle Current Limit
X
Tripping any of these protection faults will cause QB to be off. Masking the fault or alarm does NOT disable the
protection, but only keeps an INT from being triggered by the event. Disabling the fault or alarm will hold that stat
and flag bits in reset, and also prevent an interrupt from occurring.
9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection
The device integrates the functionality of an input overvoltage protector. The device can be paired with an
external N-channel FET to block input voltages higher than the setting programmed by the ADDR_MS pin. The
device senses the input through the VAC pin and turns the external N-channel FET on or off through the
OVPGATE pin. This eliminates the need for a separate OVP device to protect the overall system. The integrated
VAC_OVP feature has a reaction time of tVAC_OVP. The VAC OVP setting is adjustable in the
VAC_PROTECTION register.
The integrated OVP feature has a reaction time of tVAC_OVP (the actual time to turn off OVP FET will be longer
and depends upon the FET gate capacitance) and the feature is always active as long as VVAC > VACPRESENT).
The default VAC OVP threshold is set by CDRVL_ADDRMS and can be changed with the VAC_PROTECTION
register bits. VAC OVP bits are only reset by a REG_RST or a POR event where the CDRVL_ADDRMS value is
used.
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tON_VBUS
tVAC_OVP
tOFF_PRESENT
90%
tDEB
tDEB
VGS = 0 V
OVPGATE
10%
VACOVP (rising)
VACOVP (falling)
VAC
VACPRESENT (rising)
VACPRESENT (falling)
图9-8. OVPGATE Timing
The device has an integrated blocking FET (QB), with a reaction time of tVBUS_OVP. The BUS OVP threshold is
adjustable in the BUS_OVP register.
Overcurrent protection monitors the current flow into VBUS. The overcurrent protection threshold is adjustable in
the BUS_OCP register through the BUS_OCP bits, with a reaction time of tIBUS_OCP
.
When any input OVP, UVP, or OCP event is triggered, the CHG_EN bit is set to ‘0’ to disable charging, and
the start-up protocol must be followed to begin charging again.
When the BAT_UCP_ALM is triggered, the host is notified and the CHG_EN bit is not set to ‘0’ to disable
charging. The host must disable charging after this event and determine when to switch back to the primary
switching charger. This alarm is blanked during start up for proper operation. When the device starts switching,
the IBUS_UCP protection is disabled until the BUS current rises above IBUS_UCP rising threshold. After that, if
the BUS current falls below IBUS_UCP falling, the device will stop switching. IBUS_UCP falling threshold cannot
be masked or disabled.
9.4.1.2 Battery Overvoltage and Overcurrent Protection
The device integrates both overcurrent and overvoltage protection for the battery. The device monitors the
battery voltage on BATP and BATN. In order to reduce the possibility of battery terminal shorts during
manufacturing, series resistors on BATP and BATN are required. VBAT measurement accuracy must be met
with a 100-Ω series resistor, but the device must still be operational with a 1-kΩ resistor. The device is intended
to be operated within the window formed by the BAT_OVP and BAT_OVP_ALM. When the BAT_OVP_ALM is
reached, an interrupt is sent to the host to reduce the charge current and thereby reaching the BAT_OVP
threshold. If BAT_OVP is reached, charging stops, the CHG_EN bit is set to ‘0’, and the start-up sequence
must be followed to resume charging.
A fixed VOUT_OVP threshold is implemented to protect the device if the battery is removed.
The device monitors current through the battery by monitoring the voltage across the external series battery
sense resistor. The differential voltage of this sense resistor is measured on SRP and SRN. The device is
intended to be operated within the window formed by the BAT_OCP and BAT_OCP_ALM. When the
BAT_OCP_ALM is reached, an interrupt is sent to the host to reduce the charge current from reaching the
BAT_OCP threshold. If BAT_OCP is reached, charging stops, the CHG_EN bit is set to ‘0’, and the start-up
sequence must be followed to resume charging.
Comparator based for all battery overvoltage alarms and protections.
9.4.1.3 Cycle-by-Cycle Current Limit
The device monitors the outer switching FET current on a cycle-by-cycle basis. If an overcurrent is triggered for
16 cycles, the device responds by stopping switching and setting CHG_EN=0. When device triggered cycle-by-
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cycle protection, CONV_OCP_FLAG is set to ‘1’and INT is asserted low to alert host. The start-up sequence
must be followed to resume charging. It is recommended to limit the charging current of BQ25968 to 6 A without
triggering the cycle-by-cycle protection.
9.5 Programming
The BQ25968 uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial
interface developed by NXP (formerly Philips Seminconductor, see I2C BUS Specification, Version 5, October
2012). The BUS consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the BUS is
idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C BUS through
open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal processor,
controls the BUS. The master is responsible for generating the SCL signal and device addresses. The master
also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives
and/or transmits data on the BUS under control of the master device.
The BQ25968 device works as a slave and supports the following data transfer modes, as defined in the I2C
BUS™ Specification: Standard Mode (100 kbps) and Fast Mode (400 kbps). The interface adds flexibility to the
battery management solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from the battery in Active Battery Mode.
The battery voltage must stay above VBATUVLO when no VIN is present to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-Mode in this document. The BQ25968 device only supports 7-bit addressing. The device 7-bit address is
determined by the ADDR pin on the device.
To avoid I2C hang-ups, a timer (TI2CRESET) runs during I2C transactions. If the transaction takes longer than
TI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
9.5.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in the figure below. All I2C-compatible devices
should recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图9-9. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 9-10). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see 图 9-11) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
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DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
图9-10. Bit Transfer on the Serial Interface
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
8
SCL From
Master
9
1
2
Clock Pulse for
Acknowledgement
START
Condition
图9-11. Acknowledge on the I2C BUS
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see 图 9-12). This releases the BUS and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the BUS is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
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Recognize STOP or
REPEATED START
Condition
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Recognize START or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
图9-12. BUS Protocol
9.6 Register Maps
9.6.1 Customer Registers
表 9-4 can be accesses using I2C using the address programmed by the CDRVH_ADDRMS pin, and the value
can be found in 表9-2.
表9-4. CUSTOMER Registers
ADDRESS ACRONYM
REGISTER NAME
Battery Voltage Limit
Battery Voltage Alarm
Charge Current Limit
Charge Current Alarm
Charge Under Current Alarm
Input Voltage Limit
Bus Over Voltage Protection
Input Voltage Alarm
Input Current Limit
Input Current Alarm
Converter State
SECTION
Go
0h
1h
BAT_OVP
BAT_OVP_ALM
BAT_OCP
Go
2h
Go
3h
BAT_OCP_ALM
BAT_UCP_ALM
AC_PROTECTION
BUS_OVP
Go
4h
Go
5h
Go
6h
Go
7h
BUS_OVP_ALM
BUS_OCP_UCP
BUS_OCP_ALM
CONVERTER_STATE
CONTROL
Go
8h
Go
9h
Go
Ah
Bh
Ch
Dh
Eh
Fh
Go
Control Register
Charger Control 1
INT STAT
Go
CHRG_CTRL
INT_STAT
Go
Go
INT_FLAG
INT Flag
Go
INT_MASK
INT Mask
Go
10h
11h
12h
13h
14h
15h
FLT_STAT
FAULT STAT
Go
FLT_FLAG
FAULT FLAG
Go
FLT_MASK
FAULT MASK
Go
PART_INFO
ADC_CTRL
Part Information
Go
ADC Control
Go
ADC_FN_DIS
ADC Function Disable
Go
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表9-4. CUSTOMER Registers (continued)
ADDRESS ACRONYM
REGISTER NAME
SECTION
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
IBUS_ADC1
IBUS_ADC0
VBUS_ADC1
VBUS_ADC0
VAC_ADC1
ADC BUS Current Measurement
ADC BUS Current Measurement
ADC BUS Voltage Measurement
ADC BUS Voltage Measurement
ADC VAC Voltage Measurement
ADC VAC Voltage Measurement
ADC OUT Voltage Measurement
ADC OUT Voltage Measurement
ADC BAT Voltage Measurement
ADC BAT Voltage Measurement
ADC BAT Current Measurement
ADC BAT Current Measurement
ADC TSBUS Pin Voltage Measurement
ADC TSBUS Pin Voltage Measurement
ADC TSBAT Pin Voltage Measurement
ADC TSBAT Pin Voltage Measurement
ADC Die Temperature Measurement
ADC Die Temperature Measurement
TSBUS Pin Voltage Fault Setting
TSBAT Pin Voltage Fault Setting
Die Temp Fault Setting
VAC_ADC0
VOUT_ADC1
VOUT_ADC0
VBAT_ADC1
VBAT_ADC0
IBAT_ADC1
IBAT_ADC0
TSBUS_ADC1
TSBUS_ADC0
TSBAT_ADC1
TSBAT_ADC0
TDIE_ADC1
TDIE_ADC0
TSBUS_FLT1
TSBAT_FLT0
TDIE_ALM
CHG_CTRL
Charger Control
VOUT_OVP_STAT
VOUT_OVP_FLAG_MASK
DEGLITCH
VOUT_OVP status
VOUT_OVP FLAG and MASK
Deglitch Settings
Complex bit access types are encoded to fit into small table cells. 表 9-5 shows the codes that are used for
access types in this section.
表9-5. CUSTOMER Access Type Codes
ACCESS TYPE CODE
DESCRIPTION
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
x may be 0 or 1
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9.6.1.1 BAT_OVP Register (Address = 0h) [reset = 22h]
BAT_OVP is shown in 图9-13 and described in 表9-6.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-13. BAT_OVP Register
7
6
RESERVED
0h
5
4
3
2
1
0
BAT_OVP_DIS
R/W-0h
BAT_OVP[5]
R/W-1h
BAT_OVP[4]
R/W-0h
BAT_OVP[3]
R/W-0h
BAT_OVP[2]
R/W-0h
BAT_OVP[1]
R/W-1h
BAT_OVP[0]
R/W-0h
表9-6. BAT_OVP Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default Reg_RST WATCH Value
DOG
Description
7
BAT_OVP_DIS
R/W
0h
Y
N
N/A
Disable BAT_OVP
6
5
4
3
2
1
0
RESERVED
BAT_OVP[5]
BAT_OVP[4]
BAT_OVP[3]
BAT_OVP[2]
BAT_OVP[1]
BAT_OVP[0]
0h
1h
0h
0h
0h
1h
0h
R/W
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
800 mV Battery Overvoltage Protection Setting. When the
battery voltage goes above the programmed
threshold, and INT is sent, the output is disabled
400 mV
200 mV
100 mV
50 mV
25 mV
and CHG_EN is set to 0.
The host controller should monitor the battery
voltage to ensure that the adapter keeps the voltage
under this threshold for proper operation.
The setting is determined by BAT_OVP = 3.475 V +
BAT_OVP[5:0]*25 mV Default: 4.35 V (b 10 0010)
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9.6.1.2 BAT_OVP_ALM Register (Address = 1h) [reset = 1Ch]
BAT_OVP_ALM is shown in 图9-14 and described in 表9-7.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-14. BAT_OVP_ALM Register
7
6
5
4
3
2
1
0
BAT_OVP_ALM RESERVED
_DIS
BAT_OVP_AL BAT_OVP_AL BAT_OVP_AL BAT_OVP_AL BAT_OVP_AL BAT_OVP_AL
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
R/W-0h
0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
表9-7. BAT_OVP_ALM Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset
Reg_RST by
WATCH
Bit
Value
Description
DOG
7
BAT_OVP_ALM_DIS
R/W
0h
Y
N
N/A
Disable BAT_OVP_ALM
6
5
4
3
2
1
0
RESERVED
0h
0h
1h
1h
1h
0h
0h
BAT_OVP_ALM[5]
BAT_OVP_ALM[4]
BAT_OVP_ALM[3]
BAT_OVP_ALM[2]
BAT_OVP_ALM[1]
BAT_OVP_ALM[0]
R/W
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
800 mV Battery Overvoltage Alarm Setting. When the
battery voltage goes above the programmed
threshold an INT is sent.
400 mV
200 mV
100 mV
50 mV
25 mV
The BAT_OVP_ALM should be set lower than
BAT_OVP and the host controller should monitor
the battery voltage to ensure that the adapter
keeps the voltage under the BAT_OVP threshold
for proper operation.
The setting is determined by BAT_OVP_ALM =
3.5 V + BAT_OVP_ALM[5:0]*25 mV Default: 4.2
V (b01 1100)
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9.6.1.3 BAT_OCP Register (Address = 2h) [reset = 3Dh]
BAT_OCP is shown in 图9-15 and described in 表9-8.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-15. BAT_OCP Register
7
6
5
4
3
2
1
0
BAT_OCP_DIS
R/W-0h
BAT_OCP[6]
R/W-0h
BAT_OCP[5]
R/W-1h
BAT_OCP[4]
R/W-1h
BAT_OCP[3]
R/W-1h
BAT_OCP[2]
R/W-1h
BAT_OCP[1]
R/W-0h
BAT_OCP[0]
R/W-1h
表9-8. BAT_OCP Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset
Reg_RST by
WATCH
Bit
Value
Description
DOG
7
6
BAT_OCP_DIS
BAT_OCP[6]
R/W
R/W
0h
0h
Y
Y
N
N
N/A
Disable BAT_OCP
6400
mA
Battery Overcurrent Protection Setting. Any
setting over 10 A is set to 10 A.
When the battery current goes above the
programmed threshold, the output is disabled.
The host controller should monitor the battery
current to ensure that the adapter keeps the
current under this threshold for proper operation.
The setting is determined by BAT_OCP = 2 A +
BAT_OCP[6:0]*100 mA Default: 8.1 A (b 011
1101)
5
4
BAT_OCP[5]
BAT_OCP[4]
R/W
R/W
1h
1h
Y
Y
N
N
3200
mA
1600
mA
3
2
1
0
BAT_OCP[3]
BAT_OCP[2]
BAT_OCP[1]
BAT_OCP[0]
R/W
R/W
R/W
R/W
1h
1h
0h
1h
Y
Y
Y
Y
N
N
N
N
800 mA
400 mA
200 mA
100 mA
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9.6.1.4 BAT_OCP_ALM Register (Address = 3h) [reset = 3Ch]
BAT_OCP_ALM is shown in 图9-16 and described in 表9-9.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-16. BAT_OCP_ALM Register
7
6
5
4
3
2
1
0
BAT_OCP_ALM BAT_OCP_AL BAT_OCP_AL BAT_OCP_AL BAT_OCP_AL BAT_OCP_AL BAT_OCP_AL BAT_OCP_AL
_DIS
M[6]
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
表9-9. BAT_OCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
BAT_OCP_ALM_DIS
BAT_OCP_ALM[6]
R/W
R/W
0h
0h
Y
Y
N
N
N/A
Disable BAT_OCP_ALM
6400
mA
Battery Overcurrent Alarm Setting. When the
battery current goes above the programmed
threshold an INT is sent.
The BAT_OCP_ALM should be set lower than
the BAT_OCP and the host controller should
monitor the battery current to ensure that the
adapter keeps the current under the BAT_OCP
threshold for proper operation.
5
4
BAT_OCP_ALM[5]
BAT_OCP_ALM[4]
R/W
R/W
1h
1h
Y
Y
N
N
3200
mA
1600
mA
3
2
1
0
BAT_OCP_ALM[3]
BAT_OCP_ALM[2]
BAT_OCP_ALM[1]
BAT_OVP_ALM[0]
R/W
R/W
R/W
R/W
1h
1h
0h
0h
Y
Y
Y
Y
N
N
N
N
800 mA
400 mA
200 mA
100 mA
The setting is determined by BAT_OCP_ALM =
2 A + BAT_OCP_ALM[6:0]*100 mA Default: 8 A
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9.6.1.5 BAT_UCP_ALM Register (Address = 4h) [reset = 28h]
BAT_UCP_ALM is shown in 图9-17 and described in 表9-10.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-17. BAT_UCP_ALM Register
7
6
5
4
3
2
1
0
BAT_UCP_ALM BAT_UCP_AL BAT_UCP_AL BAT_UCP_AL BAT_UCP_AL BAT_UCP_AL BAT_UCP_AL BAT_UCP_AL
_DIS
M[6]
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
表9-10. BAT_UCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
BAT_UCP_ALM_DIS
BAT_UCP_ALM[6]
R/W
R/W
0h
0h
Y
Y
N
N
N/A
Disable BAT_UCP_ALM
3200
mA
Battery Undercurrent Alarm Setting. When the
battery current falls below the programmed
threshold, an INT is sent.
The host controller should monitor the battery
current to determine when to disable the
BQ25968 and hand overcharging to the
switching charger.
The setting is determined by BAT_UCP_ALM =
BAT_UCP_ALM[7:0]*50 mA Default: 2 A
(b0101000)
5
BAT_UCP_ALM[5]
R/W
1h
Y
N
1600
mA
4
3
2
1
0
BAT_UCP_ALM[4]
BAT_UCP_ALM[3]
BAT_UCP_ALM[2]
BAT_UCP_ALM[1]
BAT_UCP_ALM[0]
R/W
R/W
R/W
R/W
R/W
0h
1h
0h
0h
0h
Y
Y
Y
Y
Y
N
N
N
N
N
800 mA
400 mA
200 mA
100 mA
50 mA
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9.6.1.6 AC_PROTECTION Register (Address = 5h) [reset = 3h]
AC_PROTECTION is shown in 图9-18 and described in 表9-11.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-18. AC_PROTECTION Register
7
6
5
4
3
2
1
0
AC_OVP_STAT AC_OVP_FLAG AC_OVP_MAS
K
RESERVED
R-x
AC_OVP[2]
AC_OVP[1]
AC_OVP[0]
R-0h
R-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
表9-11. AC_PROTECTION Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
5
AC_OVP_STAT
AC_OVP_FLAG
AC_OVP_MASK
R
0h
0h
0h
Y
Y
Y
N/A
N/A
N
N/A
N/A
N/A
Status of AC_OVP. Persists until condition is no
longer valid.
R
Set when an AC_OVP event occurs. Cleared
upon read.
R/W
Masks an AC_OVP event from sending an INT.
RESERVED
4-3
2
RESERVED
AC_OVP[2]
AC_OVP[1]
AC_OVP[0]
R
x
N
Y
Y
Y
N
N
N
N
N/A
4 V
2 V
1 V
R/W
R/W
R/W
0h
1h
1h
Bus Overvoltage Protection Setting. When the
bus voltage reaches the programmed
threshold, OVPGATE turns off the OVP FET.
The host controller should monitor the bus
voltage to ensure that the adapter keeps the
voltage under this threshold for proper
operation.
1
0
The setting is determined by AC_OVP = 11 V +
AC_OVP[3:0]*1 V
Writing all 1s to these bits sets the AC_OVP to
6.5 V
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9.6.1.7 BUS_OVP Register (Address = 6h) [reset = 3Ah]
BUS_OVP is shown in 图9-19 and described in 表9-12.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-19. BUS_OVP Register
7
6
5
4
3
2
1
0
VBUS_PD_EN
R/W-0h
BUS_OVP[6]
R/W-0h
BUS_OVP[5]
R/W-1h
BUS_OVP[4]
R/W-1h
BUS_OVP[3]
R/W-1h
BUS_OVP[2]
R/W-0h
BUS_OVP[1]
R/W-1h
BUS_OVP[0]
R/W-0h
表9-12. BUS_OVP Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
VBUS_PD_EN
R/W
0h
Y
N
N/A
0: Pulldown disabled, 1: Pulldown enabled
Enabling this will turn off the external OVPFET,
and conduct current from VBUS to GND
through an internal diode. Any time the
OVPFET charge pump is not running, this
pulldown device will be active to help discharge
VBUS after a hot-plug event.
6
5
BUS_OVP[6]
BUS_OVP[5]
R/W
R/W
0h
1h
Y
Y
N
N
3200
mV
Bus Overvoltage Setting. When the bus voltage
reaches the programmed threshold, QB is
turned off and CH_EN is set to 0.
The host controller should monitor the bus
voltage to ensure that the adapter keeps the
voltage under the BUS_OVP threshold for
proper operation.
The setting is determined by BUS_OVP = 5.95
V + BUS_OVP[6:0]*50 mV Default: 8.9 V (b011
1010)
1600
mV
4
3
2
1
0
BUS_OVP[4]
BUS_OVP[3]
BUS_OVP[2]
BUS_OVP[1]
BUS_OVP[0]
R/W
R/W
R/W
R/W
R/W
1h
1h
0h
1h
0h
Y
Y
Y
Y
Y
N
N
N
N
N
800 mV
400 mV
200 mV
100 mV
50 mV
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9.6.1.8 BUS_OVP_ALM Register (Address = 7h) [reset = 38h]
BUS_OVP_ALM is shown in 图9-20 and described in 表9-13.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-20. BUS_OVP_ALM Register
7
6
5
4
3
2
1
0
BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL BUS_OVP_AL
M_DIS
M[6]
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
表9-13. BUS_OVP_ALM Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
BUS_OVP_ALM_DIS
BUS_OVP_ALM[6]
R/W
R/W
0h
0h
Y
Y
N
N
N/A
Disable BUS_OVP_ALM
3200
mV
Bus Overvoltage Alarm Setting. When the bus
voltage reaches the programmed threshold, an
INT is sent.
The host controller should monitor the bus
voltage to ensure that the adapter keeps the
voltage under the BUS_OVP threshold for
proper operation.
The setting is determined by BUS_OVP_ALM =
6 V + BUS_OVP_ALM[6:0]*50 mV Default: 8.8
V (b011 1000)
5
BUS_OVP_ALM[5]
R/W
1h
Y
N
1600
mV
4
3
2
1
0
BUS_OVP_ALM[4]
BUS_OVP_ALM[3]
BUS_OVP_ALM[2]
BUS_OVP_ALM[1]
BUS_OVP_ALM[0]
R/W
R/W
R/W
R/W
R/W
1h
1h
0h
0h
0h
Y
Y
Y
Y
Y
N
N
N
N
N
800 mV
400 mV
200 mV
100 mV
50 mV
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9.6.1.9 BUS_OCP_UCP Register (Address = 8h) [reset = Dh]
BUS_OCP_UCP is shown in 图9-21 and described in 表9-14.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-21. BUS_OCP_UCP Register
7
6
5
4
3
2
1
0
BUS_OCP_DIS IBUS_UCP_RIS IBUS_UCP_RIS IBUS_UCP_FA BUS_OCP[3]
BUS_OCP[2]
BUS_OCP[1]
BUS_OCP[0]
E_FLAG
E_MASK
LL_FLAG
R/W-0h
R-0h
R/W-0h
R-0h
R/W-1h
R/W-1h
R/W-0h
R/W-1h
表9-14. BUS_OCP_UCP Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
BUS_OCP_DIS
R/W
R
0h
0h
Y
Y
N
N/A
N/A
BUS_OCP Disable
IBUS_UCP_RISE_FLAG
N/A
Bus Undercurrent Threshold Rising Flag. An
INT is sent when this occurs, and is cleared
upon read.
5
4
IBUS_UCP_RISE_MASK
IBUS_UCP_FALL_FLAG
R/W
R
0h
0h
Y
Y
N
N/A
N/A
Bus Undercurrent Threshold Rising INT Mask.
0: Not Masked, 1: Masked
N/A
Bus Undercurrent Threshold Falling Flag. An
INT is sent when this occurs, and is cleared
upon read.
3
2
1
0
BUS_OCP[3]
BUS_OCP[2]
BUS_OCP[1]
BUS_OCP[0]
R/W
R/W
R/W
R/W
1h
1h
0h
1h
Y
Y
Y
Y
N
N
N
N
2 A
Bus Overcurrent Protection Setting. When the
bus current reaches the programmed threshold,
the output is disabled.
1 A
500 mA
250 mA
The host controller should monitor the bus
current to ensure that the adapter keeps the
current under this threshold for proper
operation.
The setting is determined by BUS_OCP = 1 A +
BUS_OCP[6:0]*250 mA Default: 4.25 A (b1101)
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9.6.1.10 BUS_OCP_ALM Register (Address = 9h) [reset = 50h]
BUS_OCP_ALM is shown in 图9-22 and described in 表9-15.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-22. BUS_OCP_ALM Register
7
6
5
4
3
2
1
0
BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL BUS_OCP_AL
M_DIS
M[6]
M[5]
M[4]
M[3]
M[2]
M[1]
M[0]
R/W-0h
R/W-1h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表9-15. BUS_OCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
Reg_RST WATCH Value
DOG
Description
7
6
BUS_OCP_ALM_DIS
BUS_OCP_ALM[6]
R/W
R/W
0h
1h
Y
Y
N
N
N/A
BUS_OCP_ALM Disable
3200
mA
Bus Overcurrent Alarm Setting. When the bus
current reaches the programmed threshold, an
INT is sent.
The host controller should monitor the bus
current to ensure that the adapter keeps the
current under BUS_OCP for proper operation.
The setting is determined by BUS_OCP_ALM =
BUS_OCP_ALM[6:0]*50 mA - 50 mA
Writing all 0s is 0 A
5
BUS_OCP_ALM[5]
R/W
0h
Y
N
1600
mA
4
3
2
1
0
BUS_OCP_ALM[4]
BUS_OCP_ALM[3]
BUS_OCP_ALM[2]
BUS_OCP_ALM[1]
BUS_OCP_ALM[0]
R/W
R/W
R/W
R/W
R/W
1h
0h
0h
0h
0h
Y
Y
Y
Y
Y
N
N
N
N
N
800 mA
400 mA
200 mA
100 mA
50 mA
Default: 4 A (b1010000)
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9.6.1.11 CONVERTER_STATE Register (Address = Ah) [reset = 0h]
CONVERTER_STATE is shown in 图9-23 and described in 表9-16.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-23. CONVERTER_STATE Register
7
6
5
4
3
2
1
0
TSHUT_FLAG TSHUT_STAT
VBUS_
ERRORLO_
STAT
VBUS_
ERRORHI_
STAT
SS_TIMEOUT_ CONV_SWITC CONV_OCP_
FLYCAP_
SHORT_FLAG
FLAG
HING_STAT
FLAG
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表9-16. CONVERTER_STATE Register Field Descriptions
Bit
Field
Type
Reset Reset by Reset by Bit
Description
or
Default
Reg_RST WATCHD Value
OG
7
TSHUT_FLAG
R
0h
Y
N/A
N/A
Thermal Shutdown Flag. An INT is sent when
this event happens, and is cleared when
read.
6
5
TSHUT_STAT
R
R
0h
0h
Y
Y
N/A
N/A
N/A
N/A
Thermal Shutdown Status. This register is 1
until the event no longer persists.
VBUS_ERRORLO_STAT
VBUS is too low for the converter to start
switching. This bit shows the current status,
and is 0 only when the event is not
happening.
4
3
VBUS_ERRORHI_STAT
SS_TIMEOUT_FLAG
R
R
0h
0h
Y
N
N/A
N/A
N/A
N/A
VBUS is too high for the converter to start
switching. This bit shows the current status,
and is 0 only when the event is not
happening.
Soft-Start Timeout Flag. If the current is not
ramped to the proper level in
SS_TIMEOUT_SET[1:0] time, the converter
will stop switching. An INT is sent when this
event happens, and is cleared when read.
2
CONV_SWITCHING_STAT
R
0h
N
N/A
N/A
An interrupt is sent when the converter starts
switching and the SS timer starts. The
adapter current must be ramped to the
IBUS_UCP_RISE threshold SS_TIMEOUT or
switching will stop. This bit is not maskable.
Only one INT is set when switching starts.
The bit can be read at any time to determine
if the part is switching or not.
1
CONV_OCP_FLAG
R
0h
N
N/A
N/A
Converter Overcurrent Flag. When any
internal switching FET reaches current limit,
an INT is sent when this event happens, and
is cleared when read.
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表9-16. CONVERTER_STATE Register Field Descriptions (continued)
Bit
Field
Type
Reset Reset by Reset by Bit
Description
or
Default
Reg_RST WATCHD Value
OG
0
PIN_DIAG_FAIL_FLAG
R
0h
Y
N/A
N/A
Pin Diagnostic Fail Flag. When CHG_EN is
set to '1', several fault conditions are checked
on the CFLY and VOUT pins to ensure
proper operation. If a diagnostic fails, an INT
is sent when this event happens, and is
cleared when read.
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9.6.1.12 CONTROL Register (Address = Bh) [reset = 40h]
CONTROL is shown in 图9-24 and described in 表9-17.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-24. CONTROL Register
7
6
5
4
3
2
1
0
REG_RST
FSW_SET[2:0]
WD_TIMEOUT WATCHDOG_D
WATCHDOG[1:0]
_FLAG
IS
R/W-0h
R/W-4h
R-0h
R/W-0h
R/W-0h
表9-17. CONTROL Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default Reg_RST WATCH Value
DOG
Description
7
REG_RST
R/W
0h
Y
N
N/A
0 = No Register Reset
1 = Reset Registers to their Default Values
Always reads 0
6
5
4
FSW_SET[2]
FSW_SET[1]
FSW_SET[0]
R/W
R/W
R/W
1h
0h
0h
N
N
N
N
N
N
N/A
N/A
N/A
Set the Switching Frequency
000: Slowest (187.5 kHz)
001: 250 kHz
010: 300 kHz
011: 375 kHz
100: 500 kHz (default)
101-111: Fastest (750 kHz)
If master or slave, max frequency is 500 kHz
3
2
WD_TIMEOUT_FL
AG
R
0h
0h
Y
Y
N/A
N
N/A
N/A
Watchdog Timeout Flag. An INT is sent when this
event happens, and is cleared when read.
WATCHDOG_DIS R/W
0 = Watchdog Enabled
1 = Watchdog Disabled
1
0
WATCHDOG[1]
WATCHDOG[0]
R/W
R/W
0h
0h
Y
Y
N
N
N/A
N/A
Watchdog Timing, (Cleared by any completed read
or write I2C transaction)
00 = 0.5 s (default)
01 = 1 s
10 = 5 s
11 = 30 s
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9.6.1.13 CHRG_CTRL Register (Address = Ch) [reset = 0h]
CHRG_CTRL is shown in 图9-25 and described in 表9-18.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-25. CHRG_CTRL Register
7
6
5
4
3
2
1
0
CHG_EN
R/W-0h
MS[1:0]
R-0h
FREQ_SHIFT[1:0]
R/W-0h
TSBUS_DIS
R/W-0h
TSBAT_DIS
R/W-0h
TDIE_DIS
R/W-0h
表9-18. CHRG_CTRL Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default Reg_RST WATCH Value
DOG
Description
7
CHG_EN
MS[1:0]
R/W
R
0h
Y
Y
N/A
0 = Charge disabled
1 = Charge enabled
6-5
0h
Y
N/A
N/A
Master, Slave, or Standalone Operation.
00 = Standalone
01 = Slave
1X = Master
4-3
FREQ_SHIFT[1:0] R/W
0h
Y
N
N/A
Adjust Fsw for EMI.
00 = Nominal Frequency
01 = +10%
10 = –10%
11 = Spread Spectrum varies frequency ±10%
2
1
0
TSBUS_DIS
TSBAT_DIS
TDIE_DIS
R/W
R/W
R/W
0h
0h
0h
Y
Y
Y
N
N
N
N/A
N/A
N/A
Disable TSBUS protection function.
0 = Enabled
1 = Disable
Disable TSBAT protection function.
0 = Enabled
1 = Disable
Disable TDIE protection function.
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9.6.1.14 INT_STAT Register (Address = Dh) [reset = xh]
INT_STAT is shown in 图9-26 and described in 表9-19.
Return to Summary Table.
Shows current status. All bits are RESET BY REG_RST.
图9-26. INT_STAT Register
7
6
5
4
3
2
1
0
BAT_OVP_
ALM_STAT
BAT_OCP_
ALM_STAT
BUS_OVP_
ALM_STAT
BUS_OCP_
ALM_STAT
BAT_UCP_
ALM_STAT
ADAPTER_
INSERT_STAT
VBAT_INSERT ADC_DONE_
_STAT
STAT
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
表9-19. INT_STAT Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset
REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
5
4
3
2
BAT_OVP_ALM_STAT
BAT_OCP_ALM_STAT
BUS_OVP_ALM_STAT
BUS_OCP_ALM_STAT
BAT_UCP_ALM_STAT
ADAPTER_INSERT_STAT
R
R
R
R
R
R
x
x
x
x
x
x
N
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BAT_OVP_ALM threshold is exceeded.
BAT_OCP_ALM threshold is exceeded.
BUS_OVP_ALM threshold is exceeded.
BUS_OCP_ALM threshold is exceeded.
BAT_UCP_ALM is below the threshold.
BUS voltage is present and above the VBUS
UVLO threshold.
1
0
VBAT_INSERT_STAT
ADC_DONE_STAT
R
R
x
x
N
N
N/A
N/A
N/A
N/A
BAT voltage is present.
Indicates if the ADC conversion is complete for
the requested parameters in 1-Shot Mode only.
This bit will change to '0' when an ADC
conversion is requested in 1-Shot Mode, and it
will change back to '1' when the conversion is
complete. During continuous conversion mode,
this bit will be 0.
0 = Conversion not complete
1 = Conversion complete
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9.6.1.15 INT_FLAG Register (Address = Eh) [reset = xh]
INT_FLAG is shown in 图9-27 and described in 表9-20.
Return to Summary Table.
Only clears upon read. All bits are RESET BY REG_RST.
图9-27. INT_FLAG Register
7
6
5
4
3
2
1
0
BAT_OVP_
ALM_FLAG
BAT_OCP_
ALM_FLAG
BUS_OVP_
ALM_FLAG
BUS_OCP_
ALM_FLAG
BAT_UCP_
ALM_FLAG
ADAPTER_
INSERT_FLAG
VBAT_INSERT ADC_DONE_
_FLAG
FLAG
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
表9-20. INT_FLAG Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
BAT_OVP_ALM_FLAG
BAT_OCP_ALM_FLAG
BUS_OVP_ALM_FLAG
BUS_OCP_ALM_FLAG
BAT_UCP_ALM_FLAG
ADAPTER_INSERT_FLAG
R
R
R
R
R
R
x
x
x
x
x
x
N
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BAT_OVP_ALM threshold has been exceeded.
BAT_OCP_ALM threshold has been exceeded.
BUS_OVP_ALM threshold has been exceeded.
BUS_OCP_ALM threshold has been exceeded.
BAT_UCP_ALM has fallen below the threshold.
BUS voltage has been present and above the
VBUS UVLO threshold.
1
0
VBAT_INSERT_FLAG
ADC_DONE_FLAG
R
R
x
x
N
N
N/A
N/A
N/A
N/A
BAT votlage has been present.
0 = Conversion not complete
1 = Conversion complete
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9.6.1.16 INT_MASK Register (Address = Fh) [reset = 0h]
INT_MASK is shown in 图9-28 and described in 表9-21.
Return to Summary Table.
INT will not assert low if enabled. All bits are RESET BY REG_RST.
图9-28. INT_MASK Register
7
6
5
4
3
2
1
0
BAT_OVP_
ALM_MASK
BAT_OCP_
ALM_MASK
BUS_OVP_
ALM_MASK
BUS_OCP_
ALM_MASK
BAT_UCP_
ALM_MASK
ADAPTER_
INSERT_MASK
VBAT_INSERT ADC_DONE_
_MASK
MASK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表9-21. INT_MASK Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset by Bit
REG_RST WATCH Value
DOG
Description
7
BAT_OVP_ALM_MASK
BAT_OCP_ALM_MASK
BUS_OVP_ALM_MASK
BUS_OCP_ALM_MASK
BAT_UCP_ALM_MASK
R/W
0h
0h
0h
0h
0h
0h
0h
0h
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Masks BAT Overvoltage Alarm Event.
0 = Not Masked
1 = Masked
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
Masks BAT Overcurrent Alarm Event.
0 = Not Masked
1 = Masked
Masks BUS Overvoltage Alarm Event.
0 = Not Masked
1 = Masked
Masks BUS Overcurrent Alarm Event.
0 = Not Masked
1 = Masked
Masks BAT_UCP Alarm Event.
0 = Not Masked
1 = Masked
ADAPTER_INSERT_MASK R/W
Masks a ADAPTER_INSERT Event.
0 = Not Masked
1 = Masked
VBAT_INSERT_MASK
ADC_DONE_MASK
R/W
R/W
Masks a VBAT INSERT EVENT.
0 = Not Masked
1 = Masked
Masks a ADC DONE Event.
0 = Not Masked
1 = Masked
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9.6.1.17 FLT_STAT Register (Address = 10h) [reset = xh]
FLT_STAT is shown in 图9-29 and described in 表9-22.
Return to Summary Table.
Shows current status. All bits are RESET BY REG_RST.
图9-29. FLT_STAT Register
7
6
5
4
3
2
1
0
BAT_OVP_FLT BAT_OCP_FLT BUS_OVP_FLT BUS_OCP_FLT TSBUS_TSBAT TSBAT_FLT_ST TSBUS_FLT_S TDIE_ALM_ST
_STAT
_STAT
_STAT
_STAT
_ALM_STAT
AT
TAT
AT
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
表9-22. FLT_STAT Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset
Bit
Description
Default
REG_RST by
WATCH
Value
DOG
7
6
5
4
3
BAT_OVP_FLT_STAT
BAT_OCP_FLT_STAT
BUS_OVP_FLT_STAT
BUS_OCP_FLT_STAT
R
R
R
R
x
x
x
x
x
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
Indicates a BAT Overvoltage Event is
occurring.
N/A
N/A
N/A
N/A
Indicates a BAT Overcurrent Event is
occurring.
Indicates a BUS Overvoltage Event is
occurring.
Indicates a BUS Overcurrent Event is
occurring.
TSBUS_TSBAT_ALM_STA R
T
Indicates that the TSBUS or TSBAT threshold
is within 5% of the TSBUS_FLT or TSBAT_FLT
set threshold.
2
1
0
TSBAT_FLT_STAT
TSBUS_FLT_STAT
TDIE_ALM_STAT
R
R
R
x
x
x
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
Indicates a BAT Over Temp Fault has
Occurred TSBAT voltage falls below
TSBAT_FLT setting.
Indicates a BUS Over Temp Fault has
Occurred TSBUS votlage falls below
TSBUS_FLT setting.
Indicates a DIE Over Temp Fault has Occurred
TDIE_ALM temp has been exceeded.
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9.6.1.18 FLT_FLAG Register (Address = 11h) [reset = xh]
FLT_FLAG is shown in 图9-30 and described in 表9-23.
Return to Summary Table.
Only clears upon read. All bits are RESET BY REG_RST.
图9-30. FLT_FLAG Register
7
6
5
4
3
2
1
0
BAT_OVP_FLT BAT_OCP_FLT BUS_OVP_FLT BUS_OCP_FLT TSBUS_TSBAT TSBAT_FLT_FL TSBUS_FLT_F TDIE_ALM_FL
_FLAG
_FLAG
_FLAG
_FLAG
_ALM_FLAG
AG
LAG
AG
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
表9-23. FLT_FLAG Register Field Descriptions
Bit
Field
Type Reset
or
Reset By Reset
REG_RST by
WATCH
Bit
Value
Description
Default
DOG
7
6
5
4
3
BAT_OVP_FLT_FLAG
BAT_OCP_FLT_FLAG
BUS_OVP_FLT_FLAG
BUS_OCP_FLT_FLAG
TSBUS_TSBAT_ALM_FLAG
R
R
R
R
R
x
x
x
x
x
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Indicates a BAT Overvoltage Event has
occurred.
Indicates a BAT Overcurrent Event has
occurred.
Indicates a BUS Overvoltage Event has
occurred.
Indicates a BUS Overcurrent Event has
occurred.
Indicates that the TSBUS or TSBAT threshold
has been within 5% of the TSBUS_FLT or
TSBAT_FLT set threshold.
2
1
0
TSBAT_FLT_FLAG
TSBUS_FLT_FLAG
TDIE_ALM_FLAG
R
R
R
x
x
x
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
Indicates a BAT Temp Fault has Occurred.
Indicates a BUS Temp Fault has Occurred.
Indicates a DIE Temp Fault has Occurred.
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9.6.1.19 FLT_MASK Register (Address = 12h) [reset = 0h]
FLT_MASK is shown in 图9-31 and described in 表9-24.
Return to Summary Table.
INT will not assert if enabled. All bits are RESET BY REG_RST.
图9-31. FLT_MASK Register
7
6
5
4
3
2
1
0
BAT_OVP_FLT BAT_OCP_FLT BUS_OVP_FLT BUS_OCP_FLT TSBUS_TSBAT TSBAT_FLT_M TSBUS_FLT_M TDIE_ALM_MA
_MASK
_MASK
_MASK
_MASK
_ALM_MASK
ASK
ASK
SK
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表9-24. FLT_MASK Register Field Descriptions
Bit
Field
Type Reset
or
Reset by
REG_RST WATCH Value
DOG
Reset by Bit
Description
Default
7
BAT_OVP_FLT_MASK
BAT_OCP_FLT_MASK
BUS_OVP_FLT_MASK
BUS_OCP_FLT_MASK
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Masks BAT Overvoltage Event.
0 = Not Masked
1 = Masked
6
5
4
3
2
1
0
Masks BAT Overcurrent Event.
0 = Not Masked
1 = Masked
Masks BUS Overvoltage Event.
0 = Not Masked
1 = Masked
Masks BUS Overcurrent Event.
0 = Not Masked
1 = Masked
TSBUS_TSBAT_ALM_MAS R/W 0h
K
Masks TSBUS_TSBAT_ALM Event.
0 = Not Masked
1 = Masked
TSBAT_FLT_MASK
TSBUS_FLT_MASK
TDIE_ALM_MASK
R/W 0h
R/W 0h
R/W 0h
Masks a BAT Temp Fault.
0 = Not Masked
1 = Masked
Masks a BUS Temp Fault.
0 = Not Masked
1 = Masked
Masks a DIE Temp Fault.
0 = Not Masked
1 = Masked
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9.6.1.20 PART_INFO Register (Address = 13h) [reset = xh]
PART_INFO is shown in 图9-32 and described in 表9-25.
Return to Summary Table.
图9-32. PART_INFO Register
7
6
5
4
3
2
1
0
RESERVED[7:4]
R-x
DEVICE_ID[3:0]
R-x
表9-25. PART_INFO Register Field Descriptions
Bit
Field
Type Reset
Reset by
Reset By Bit
Description
or
Default
REG_RST WATCHD Value
OG
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
DEVICE_ID[3]
DEVICE_ID[2]
DEVICE_ID[1]
DEVICE_ID[0]
0
0
0
1
x
x
x
x
R
R
R
R
x
x
x
x
N/A
N/A
N/A
N/A
x
x
x
x
Device ID
0000 = BQ25970
0001= BQ25971
0110= BQ25968
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9.6.1.21 ADC_CTRL Register (Address = 14h) [reset = xh]
ADC_CTRL is shown in 图9-33 and described in 表9-26.
Return to Summary Table.
Bits 7-3 and bit 0 are RESET BY REG_RST.
图9-33. ADC_CTRL Register
7
6
5
4
3
2
1
0
ADC_EN
R/W-0h
ADC_RATE
R/W-0h
ADC_AVG
R/W-0h
ADC_AVG_INIT
R/W-0h
ADC_SAMPLE[1:0]
R/W-0h
RESERVED IBUS_ADC_DIS
R/W-0h
0
表9-26. ADC_CTRL Register Field Descriptions
Bit
Field
Type
Reset or Reset By Reset
Default REG_RST By
WATCH
Bit
Value
Description
DOG
7
ADC_EN
R/W
0h
Y
Y
N/A
Enable ADC
0 = Disabled
1 = Enabled
6
5
ADC_RATE
ADC_AVG
R/W
R/W
R/W
0h
0h
0h
0h
Y
Y
Y
Y
N
N
N
N
N/A
N/A
N/A
N/A
0 = Continuous Conversion
1 = One-shot
0 = Single Value
1 = Running Average
4
ADC_AVG_INIT
0 = Start averaging using the existing register value
1 = Start averaging using a new ADC conversion
3-2
ADC_SAMPLE[1:0] R/W
Sample speed of the ADC.
00 = 15-bit effective resolution
01 = 14-bit effective resolution
10 = 13-bit effective resolution
11 = 12-bit effective resolution
1
0
RESERVED
IBUS_ADC_DIS
0
R/W
0h
Y
N
N/A
0 = Enable Conversion
1 = Disable Conversion
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9.6.1.22 ADC_FN_DISABLE Register (Address = 15h) [reset = 0h]
ADC_FN_DIS is shown in 图9-34 and described in 表9-27.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-34. ADC_FN_DISABLE Register
7
6
5
4
3
2
1
0
VBUS_ADC_DI VAC_ADC_DIS VOUT_ADC_DI VBAT_ADC_DI IBAT_ADC_DIS TSBUS_ADC_ TSBAT_ADC_D TDIE_ADC_DIS
S
S
S
DIS
IS
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表9-27. ADC_FN_DISABLE Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset
REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
5
4
3
2
1
0
VBUS_ADC_DIS
VAC_ADC_DIS
VOUT_ADC_DIS
VBAT_ADC_DIS
IBAT_ADC_DIS
TSBUS_ADC_DIS
TSBAT_ADC_DIS
TDIE_ADC_DIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0 = Enable Conversion
1 = Disable Conversion
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9.6.1.23 IBUS_ADC1 Register (Address = 16h) [reset = xh]
IBUS_ADC1 is shown in 图9-35 and described in 表9-28.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-35. IBUS_ADC1 Register
7
6
5
4
3
IBUS_ADC[14:8]
R-x
2
1
0
IBUS_POL
R-x
表9-28. IBUS_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset By Reset
Default REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
IBUS_POL
R
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
IBUS_ADC[14]
x
Y
N/A
16384
mA
Current of IBUS
5
4
3
2
1
0
IBUS_ADC[13]
IBUS_ADC[12]
IBUS_ADC[11]
IBUS_ADC[10]
IBUS_ADC[9]
IBUS_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mA
4096 mA
2048 mA
1024 mA
512 mA
256 mA
9.6.1.24 IBUS_ADC0 Register (Address = 17h) [reset = xh]
IBUS_ADC0 is shown in 图9-36 and described in 表9-29.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-36. IBUS_ADC0 Register
7
6
5
4
3
2
1
0
IBUS_ADC[7:0]
R-x
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表9-29. IBUS_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset By Reset
Default REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
5
4
3
2
1
0
IBUS_ADC[7]
IBUS_ADC[6]
IBUS_ADC[5]
IBUS_ADC[4]
IBUS_ADC[3]
IBUS_ADC[2]
IBUS_ADC[1]
IBUS_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mA
64 mA
32 mA
16 mA
8 mA
4 mA
2 mA
1 mA
9.6.1.25 VBUS_ADC1 Register (Address = 18h) [reset = xh]
VBUS_ADC1 is shown in 图9-37 and described in 表9-30.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-37. VBUS_ADC1 Register
7
6
5
4
3
VBUS_ADC[14:8]
R-x
2
1
0
VBUS_POL
R-x
表9-30. VBUS_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset By Reset
Default REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
VBUS_POL
R
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
VBUS_ADC[14]
x
Y
N/A
16384
mV
Voltage of VBUS
5
4
3
2
1
0
VBUS_ADC[13]
VBUS_ADC[12]
VBUS_ADC[11]
VBUS_ADC[10]
VBUS_ADC[9]
VBUS_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
256 mV
9.6.1.26 VBUS_ADC0 Register (Address = 19h) [reset = xh]
VBUS_ADC0 is shown in 图9-38 and described in 表9-31.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-38. VBUS_ADC0 Register
7
6
5
4
3
2
1
0
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图9-38. VBUS_ADC0 Register (continued)
VBUS_ADC[7:0]
R-x
表9-31. VBUS_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset By Reset
Default REG_RST By
WATCH
Bit
Value
Description
DOG
7
6
5
4
3
2
1
0
VBUS_ADC[7]
VBUS_ADC[6]
VBUS_ADC[5]
VBUS_ADC[4]
VBUS_ADC[3]
VBUS_ADC[2]
VBUS_ADC[1]
VBUS_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mV
64 mV
32 mV
16 mV
8 mV
4 mV
2 mV
1 mV
9.6.1.27 VAC_ADC1 Register (Address = 1Ah) [reset = xh]
VAC_ADC1 is shown in 图9-39 and described in 表9-32.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-39. VAC_ADC1 Register
7
6
5
4
3
VAC_ADC[14:8]
R-x
2
1
0
VAC_POL
R-x
表9-32. VAC_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
VAC_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
6
VAC_ADC[14]
R
x
Y
N/A
16384
mV
Voltage of VAC
5
4
3
2
1
0
VAC_ADC[13]
VAC_ADC[12]
VAC_ADC[11]
VAC_ADC[10]
VAC_ADC[9]
VAC_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
256 mV
9.6.1.28 VAC_ADC0 Register (Address = 1Bh) [reset = xh]
VAC_ADC0 is shown in 图9-40 and described in 表9-33.
Return to Summary Table.
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All bits are RESET BY REG_RST.
图9-40. VAC_ADC0 Register
7
6
5
4
3
2
1
0
VAC_ADC[7:0]
R-x
表9-33. VAC_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
1
0
VAC_ADC[7]
VAC_ADC[6]
VAC_ADC[5]
VAC_ADC[4]
VAC_ADC[3]
VAC_ADC[2]
VAC_ADC[1]
VAC_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mV
64 mV
32 mV
16 mV
8 mV
4 mV
2 mV
1 mV
9.6.1.29 VOUT_ADC1 Register (Address = 1Ch) [reset = xh]
VOUT_ADC1 is shown in 图9-41 and described in 表9-34.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-41. VOUT_ADC1 Register
7
6
5
4
3
VOUT_ADC[14:8]
R-x
2
1
0
VOUT_POL
R-x
表9-34. VOUT_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
VOUT_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
6
VOUT_ADC[14]
R
x
Y
N/A
16384
mV
Voltage of VOUT
5
4
3
2
1
0
VOUT_ADC[13]
VOUT_ADC[12]
VOUT_ADC[11]
VOUT_ADC[10]
VOUT_ADC[9]
VOUT_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
256 mV
9.6.1.30 VOUT_ADC0 Register (Address = 1Dh) [reset = xh]
VOUT_ADC0 is shown in 图9-42 and described in 表9-35.
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Return to Summary Table.
All bits are RESET BY REG_RST.
图9-42. VOUT_ADC0 Register
7
6
5
4
3
2
1
0
VOUT_ADC[7:0]
R-x
表9-35. VOUT_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
1
0
VOUT_ADC[7]
VOUT_ADC[6]
VOUT_ADC[5]
VOUT_ADC[4]
VOUT_ADC[3]
VOUT_ADC[2]
VOUT_ADC[1]
VOUT_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mV
64 mV
32 mV
16 mV
8 mV
4 mV
2 mV
1 mV
9.6.1.31 VBAT_ADC1 Register (Address = 1Eh) [reset = xh]
VBAT_ADC1 is shown in 图9-43 and described in 表9-36.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-43. VBAT_ADC1 Register
7
6
5
4
3
VBAT_ADC[14:8]
R-x
2
1
0
VBAT_POL
R-x
表9-36. VBAT_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
VBAT_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
6
VBAT_ADC[14]
R
x
Y
N/A
16384
mV
Voltage of VBAT
5
4
3
2
1
0
VBAT_ADC[13]
VBAT_ADC[12]
VBAT_ADC[11]
VBAT_ADC[10]
VBAT_ADC[9]
VBAT_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
256 mV
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9.6.1.32 VBAT_ADC0 Register (Address = 1Fh) [reset = xh]
VBAT_ADC0 is shown in 图9-44 and described in 表9-37.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-44. VBAT_ADC0 Register
7
6
5
4
3
2
1
0
VBAT_ADC[7:0]
R-x
表9-37. VBAT_ADC0 Register Field Descriptions
Bit
Field
Type
Reset
Reset by Reset by Bit
REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
1
0
VBAT_ADC[7]
VBAT_ADC[6]
VBAT_ADC[5]
VBAT_ADC[4]
VBAT_ADC[3]
VBAT_ADC[2]
VBAT_ADC[1]
VBAT_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mV
64 mV
32 mV
16 mV
8 mV
4 mV
2 mV
1 mV
9.6.1.33 IBAT_ADC1 Register (Address = 20h) [reset = xh]
IBAT_ADC1 is shown in 图9-45 and described in 表9-38.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-45. IBAT_ADC1 Register
7
6
5
4
3
IBAT_ADC[14:8]
R-x
2
1
0
IBAT_POL
R-x
表9-38. IBAT_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
IBAT_POL
R
x
Y
N/A
N/A
Positive is charging and negative is discharging.
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
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表9-38. IBAT_ADC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
6
IBAT_ADC[14]
R
x
Y
N/A
16384
mA
Current of IBAT
5
4
3
2
1
0
IBAT_ADC[13]
IBAT_ADC[12]
IBAT_ADC[11]
IBAT_ADC[10]
IBAT_ADC[9]
IBAT_ADC[8]
R
R
R
R
R
R
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
8192 mA
4096 mA
2048 mA
1024 mA
512 mA
256 mA
9.6.1.34 IBAT_ADC0 Register (Address = 21h) [reset = xh]
IBAT_ADC0 is shown in 图9-46 and described in 表9-39.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-46. IBAT_ADC0 Register
7
6
5
4
3
2
1
0
IBAT_ADC[7:0]
R-x
表9-39. IBAT_ADC0 Register Field Descriptions
Bit
Field
Type
Reset
or
Default
Reset by Reset
REG_RST by
WATCH
Bit
Value
Description
DOG
7
6
5
4
3
2
1
0
IBAT_ADC[7]
IBAT_ADC[6]
IBAT_ADC[5]
IBAT_ADC[4]
IBAT_ADC[3]
IBAT_ADC[2]
IBAT_ADC[1]
IBAT_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
128 mA
64 mA
32 mA
16 mA
8 mA
4 mA
2 mA
1 mA
9.6.1.35 TSBUS_ADC1 Register (Address = 22h) [reset = xh]
TSBUS_ADC1 is shown in 图9-47 and described in 表9-40.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-47. TSBUS_ADC1 Register
7
6
5
4
3
TSBUS_ADC[14:8]
R-x
2
1
0
TSBUS_POL
R-x
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表9-40. TSBUS_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset
Default REG_RST by
WATCH
Bit
Value
Description
DOG
7
TSBUS_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
6
5
4
3
2
1
0
TSBUS_ADC[14]
TSBUS_ADC[13]
TSBUS_ADC[12]
TSBUS_ADC[11]
TSBUS_ADC[10]
TSBUS_ADC[9]
TSBUS_ADC[8]
R
R
R
R
R
R
R
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
TSBUS Pin Voltage as a Percentage of VOUT
TSBUS Percentage = TSBUS_ADC[8:0] x
0.09766%
50%
25%
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9.6.1.36 TSBUS_ADC0 Register (Address = 23h) [reset = xh]
TSBUS_ADC0 is shown in 图9-48 and described in 表9-41.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-48. TSBUS_ADC0 Register
7
6
5
4
3
2
1
0
TSBUS_ADC[7:0]
R-x
表9-41. TSBUS_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
TSBUS_ADC[7]
TSBUS_ADC[6]
TSBUS_ADC[5]
TSBUS_ADC[4]
TSBUS_ADC[3]
R
R
R
R
R
x
x
x
x
x
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
12.5%
6.25%
3.125%
1.5625%
0.78125
%
2
1
0
TSBUS_ADC[2]
TSBUS_ADC[1]
TSBUS_ADC[0]
R
R
R
x
x
x
Y
Y
Y
N/A
N/A
N/A
0.39063
%
0.19531
%
0.09766
%
9.6.1.37 TSBAT_ADC1 Register (Address = 24h) [reset = xh]
TSBAT_ADC1 is shown in 图9-49 and described in 表9-42.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-49. TSBAT_ADC1 Register
7
6
5
4
3
TSBAT_ADC[14:8]
R-x
2
1
0
TSBAT_POL
R-x
表9-42. TSBAT_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
TSBAT_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0b = Result is positive
1b = Result is negative
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表9-42. TSBAT_ADC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
6
5
4
3
2
1
0
TSBAT_ADC[14]
TSBAT_ADC[13]
TSBAT_ADC[12]
TSBAT_ADC[11]
TSBAT_ADC[10]
TSBAT_ADC[9]
TSBAT_ADC[8]
R
R
R
R
R
R
R
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
50%
25%
9.6.1.38 TSBAT_ADC0 Register (Address = 25h) [reset = xh]
TSBAT_ADC0 is shown in 图9-50 and described in 表9-43.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-50. TSBAT_ADC0 Register
7
6
5
4
3
2
1
0
TSBAT_ADC[7:0]
R-x
表9-43. TSBAT_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
TSBAT_ADC[7]
TSBAT_ADC[6]
TSBAT_ADC[5]
TSBAT_ADC[4]
TSBAT_ADC[3]
R
R
R
R
R
x
x
x
x
x
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
12.5%
TSBAT Pin Voltage as a Percentage of VOUT
TSBAT Percentage = TSBAT_ADC[8:0] x 0.09766%
6.25%
3.125%
1.5625%
0.78125
%
2
1
0
TSBAT_ADC[2]
TSBAT_ADC[1]
TSBAT_ADC[0]
R
R
R
x
x
x
Y
Y
Y
N/A
N/A
N/A
0.39063
%
0.19531
%
0.09766
%
9.6.1.39 TDIE_ADC1 Register (Address = 26h) [reset = xh]
TDIE_ADC1 is shown in 图9-51 and described in 表9-44.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-51. TDIE_ADC1 Register
7
6
5
4
3
TDIE_ADC[14:8]
R-x
2
1
0
TDIE_POL
R-x
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图9-51. TDIE_ADC1 Register (continued)
表9-44. TDIE_ADC1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
TDIE_POL
R
x
Y
N/A
N/A
Reported in Two's Complement.
0 = Result is positive
1 = Result is negative
6
5
4
3
2
1
0
TDIE_ADC[14]
TDIE_ADC[13]
TDIE_ADC[12]
TDIE_ADC[11]
TDIE_ADC[10]
TDIE_ADC[9]
TDIE_ADC[8]
R
R
R
R
R
R
R
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DIE Temperature = 5°C + TDIE_ADC[8:0] * 0.5°C
128°C
9.6.1.40 TDIE_ADC0 Register (Address = 27h) [reset = xh]
TDIE_ADC0 is shown in 图9-52 and described in 表9-45.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-52. TDIE_ADC0 Register
7
6
5
4
3
2
1
0
TDIE_ADC[7:0]
R-x
表9-45. TDIE_ADC0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
1
0
TDIE_ADC[7]
TDIE_ADC[6]
TDIE_ADC[5]
TDIE_ADC[4]
TDIE_ADC[3]
TDIE_ADC[2]
TDIE_ADC[1]
TDIE_ADC[0]
R
R
R
R
R
R
R
R
x
x
x
x
x
x
x
x
Y
Y
Y
Y
Y
Y
Y
Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
64°C
32°C
16°C
8°C
4°C
2°C
1°C
0.5°C
9.6.1.41 TSBUS_FLT1 Register (Address = 28h) [reset = 15h]
TSBUS_FLT1 is shown in 图9-53 and described in 表9-46.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-53. TSBUS_FLT1 Register
7
6
5
4
3
2
1
0
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图9-53. TSBUS_FLT1 Register (continued)
TSBUS_FLT[7:0]
R/W-75h
表9-46. TSBUS_FLT1 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
TSBUS_FLT[7]
TSBUS_FLT[6]
TSBUS_FLT[5]
TSBUS_FLT[4]
TSBUS_FLT[3]
TSBUS_FLT[2]
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
1h
0h
1h
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
25.00%
12.5%
TSBUS Percentage Fault Threshold
A TSBUS_TSBAT_ALM interrupt will be sent when
TSBUS is within 5% of the value set in this register
TSBUS_FLT = TSBUS_FLT[7:0] x 0.19531%
Default: 4.1% (b00010101)
6.25%
3.125%
1.5625%
0.78125
%
1
0
TSBUS_FLT[1]
TSBUS_FLT[0]
R/W
R/W
0h
1h
Y
Y
N
N
0.39063
%
0.19531
%
9.6.1.42 TSBAT_FLT0 Register (Address = 29h) [reset = 15h]
TSBAT_FLT0 is shown in 图9-54 and described in 表9-47.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-54. TSBAT_FLT0 Register
7
6
5
4
3
2
1
0
TSBAT_FLT[7:0]
R/W-75h
表9-47. TSBAT_FLT0 Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
TSBAT_FLT[7]
TSBAT_FLT[6]
TSBAT_FLT[5]
TSBAT_FLT[4]
TSBAT_FLT[3]
TSBAT_FLT[2]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
1
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
25.00%
12.5%
TSBAT Percentage Fault Threshold
A TSBUS_TSBAT_ALM interrupt will be sent when
TSBAT is within 5% of the value set in this register.
TSBAT_FLT = TSBAT_FLT[7:0] x 0.19531%
Default: 4.1% (b00010101)
6.25%
3.125%
1.5625%
0.78125
%
1
0
TSBAT_FLT[1]
TSBAT_FLT[0]
R/W
R/W
0
1
Y
Y
N
N
0.39063
%
0.19531
%
9.6.1.43 TDIE_ALM Register (Address = 2Ah) [reset = C8h]
TDIE_ALM is shown in 图9-55 and described in 表9-48.
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Return to Summary Table.
All bits are RESET BY REG_RST.
图9-55. TDIE_ALM Register
7
6
5
4
3
2
1
0
TDIE_ALM[7:0]
R/W-A8h
表9-48. TDIE_ALM Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
4
3
2
1
0
TDIE_ALM[7]
TDIE_ALM[6]
TDIE_ALM[5]
TDIE_ALM[4]
TDIE_ALM[3]
TDIE_ALM[2]
TDIE_ALM[1]
TDIE_ALM[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
0h
0h
1h
0h
0h
0h
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
64°C
32°C
16°C
8°C
TDIE Voltage Fault Threshold
If the value written to the register is greater than the
max or less than the min defined value, the register
will be set to the maximum or minimum as
necessary.
4°C
TDIE_ALM = 30 + TDIE_FLT[7:0] x 0.5°C
Default: 125C (b11001000)
2°C
1°C
0.5°C
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9.6.1.44 CHG_CTRL Register (Address = 2Bh) [reset = 0h]
图9-56. CHG_CTRL Register
7
6
5
4
3
2
1
0
SS_TIMEOUT_ SS_TIMEOUT_ SS_TIMEOUT_
RESERVED
VOUT_OVP_DI IBUS_UCP_RIS SET_IBAT_SN
E_THRE S_RES
VAC_PD_EN
SET2
SET1
SET0
S
R/W - 0h
R-x
R/W - 0h
表9-49. CHG_CTRL Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7
6
5
SS_TIMEOUT_SET R/W
2
0h
0h
0h
N
N
N
N
N
N
N/A
N/A
N/A
Adjustable timeout for IBUS to rise to
IBUS_UCP_RISE_THRESH
000: Timeout Disabled
001: 12.5 ms
SS_TIMEOUT_SET R/W
1
SS_TIMEOUT_SET R/W
0
010: 25 ms
011: 50 ms
100: 100 ms
101: 400 ms
110: 1.5 s
111: 100 s
4
3
2
RESERVED
R
x
N
N
Y
N
N
N
N/A
N/A
N/A
RESERVED
VOUT_OVP_DIS
R/W
0h
0h
This register disables the VOUT_OVP function.
IBUS_UCP_RISE_ R/W
THRESH
This is the threshold above which the BUS current
must rise to within the SS_TIMEOUT. The value can
only be changed prior to enabling switching.0: 300
mA rising, 150 mA falling (typ)1: 500 mA rising, 250
mA falling (typ)
1
0
SET_IBAT_SNS_R R/W
ES
0h
0h
N
Y
N
N
N/A
N/A
This bit selects the external BAT_SNS resistor
value.
0: 2 mΩ
1: 5 mΩ
VAC_PD_EN
R/W
When this bit is enabled, it pulls down the VAC for
tVAC_PD to discharge any bulk input cap on VAC.
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9.6.1.45 VOUT_OVP_STAT Register (Address = 2Ch) [reset = 0h]
图9-57. VOUT_OVP_STAT Register
7
6
5
4
3
2
1
0
RESERVED
VOUT_OVP_S
TAT
R-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-50. VOUT_OVP_STAT Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset by Bit
Default REG_RST WATCH Value
DOG
Description
7-1
0
RESERVED
R
R
x
x
N
N
N
N
N/A
N/A
RESERVED
VOUT_OVP_STAT
Ths bit is set when VOUT_OVP is active. It is
cleared when VOUT_OVP is no longer active.
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9.6.1.46 VOUT_FLAG_MASK Register (Address = 2Dh) [reset = 0h]
图9-58. VOUT_FLAG_MASK Register
7
6
5
4
3
2
1
0
RESERVED
VOUT_OVP_FL
AG
RESERVED
VOUT_OVP_M
ASK
R-X
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-51. VOUT_FLAG_MASK Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset
Default REG_RST by
WATCH
Bit Value Description
DOG
7-5
4
RESERVED
R
R
x
x
N
N
N
N
N/A
N/A
RESERVED
VOUT_OVP_FLAG
This bit is set when VOUT_OVP has been active. It
is cleared by a read and VOUT_OVP is no longer
active.
3-1
0
RESERVED
R
x
N
Y
N
N
N/A
N/A
RESERVED
VOUT_OVP_MASK R/W
0h
This register masks the interrupt when the part
enters exceeds the VOUT_OVP threshold000REG.
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9.6.1.47 DEGLITCH Register (Address = 2Eh) [reset = 0h]
PULSE_MODE is shown in 图9-59 and described in 表9-52.
Return to Summary Table.
All bits are RESET BY REG_RST.
图9-59. Deglitch Register
7
6
5
4
3
2
1
0
RESERVED
VBUS_ERROR IBUS_LOW_DG
RESERVED
_LO_DG_SET
_SET
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表9-52. Deglitch Register Field Descriptions
Bit
Field
Type
Reset or Reset by Reset
Default REG_RST by
WATCH
Bit
Value
Description
DOG
7
6
5
4
RESERVED
0h
0h
0h
VBUS_ERROR_LO_D R/W
G_SET
0h
Y
Y
N
N
N/A
N/A
This bit sets the deglitch time for
VBUS_ERROR_LO0: 10 µs, 1: 10 ms
3
IBUS_LOW_DG_SET R/W
0h
Ths bit sets the deglitch time for
IBUS_LOW_DG_SET0: 10 µs, 1: 5 ms
2
1
0
RESERVED
0h
0h
0h
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
A typical application consists of the device configured as an I2C controlled parallel charger along with a standard
switching charger, however, it can also be used with a linear charger or PMIC with integrated charger as well.
For simplicity, it is called the primary charger. As shown in 图 9-2 the device can start fast charging after the
primary charger completes precharging, where the BQ25890 is used as the primary charger. The device will then
hand back charging to the primary charger when final current tapering is desired. This point is usually where the
efficiency of the primary charger is acceptable for the application. The device can be used to charge Li-ion and
Li-polymer batteries used in a wide range of smartphones and other portable devices. To take advantage of the
high charge current capabilities of the BQ25968, it may be necessary to charge in excess of 1C. In this case, be
sure to follow the battery manufacturers recommendations closely.
10.2 Typical Application
The BQ25968 system implementation on the charging device can be very small. A typical schematic is shown
below with all the optional and required components shown.
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10.2.1 Standalone Application Information (for use with switching charger)
BQ25968
CDRVH
CDRV
CDRVL_ADDRMS
REGN
RADDRMS
CREGN
VBUS
CIN
PMID
CPMID
CFH2
CFH1
OVPGATE
VAC
CF1
CF2
VREF
VOUT
SDA
VREF
COUT
SCL
VREF
CFL1
CFL2
INT
Battery
Pack
BATP_SYNCIN
VBAT
RSENSE
BATN
SRP
TSBUS
VBAT
RNTC
SRN
RNTC
TSBAT_
SYNCOUT
GND
图10-1. Typical Schematic for BQ25968
10.2.1.1 Design Requirements
The design requires a smart wall adapter to provide the proper input voltage and input current to the BQ25968,
following the USB_PD Programmable Power Supply (PPS) voltage steps and current steps. The design shown
is capable of charging up to 6 A, although this may not be practical for some applications due to the total power
loss at this operating point. Careful consideration of the thermal constraints, space constraints, and operating
conditions should be done to ensure acceptable performance.
10.2.1.2 Detailed Design Procedure
The first step is the determine if an external OVP FET is required in the application. Choosing to include the
external OVP FET allows protection of the device if an over-voltage event occurs. If not using the external OVP
FET capable part (BQ25970 or BQ25968), it is recommended to have some other TVS mechanism to protect the
device.
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The next step is to determine the number of CFLY caps to put on each phase of the design. It is important to
consider the current rating of the caps, their ESR, and the capacitance rating. Be sure to consider the bias
voltage derating for the caps, as the CFLY caps are biased to half of the input voltage, and this will affect their
effective capacitance. An optimal system will have four 22-µF caps per phase, for a total of 8 caps per device.
The recommended parts for this configuration are shown below, and result in the lowest cost, acceptable
efficiency, and acceptable voltage and current ripple. It is possible to use fewer caps, with a minimum
recommendation of 3. Using fewer caps will result in higher voltage and current ripple on the output, as well as
lower efficiency. Using more than 4 caps per phase will not significantly improve the output voltage or current
ripple, or efficiency.
The default switching frequency, fSW, for the power stage is 500 kHz. The switching frequency can be adjusted in
register 0x0Bh using the FSW_SET bits. Using a lower switching frequency will increase the efficiency, but also
increase the voltage and current ripple. If using 3 22-µF caps per phase, it is recommended to use the default
fSW of 500 kHz. If using 4 22-µF caps per phase, either 500 kHz or 300 kHz is recommended.
表10-1. BQ25968 Capacitors
CAPACITANCE
(µF)
SIZE, VOLTAGE RATING, TEMP
CHAR
CAPACITOR TYPE
SUPPLIER(1)
COMMENT
Lowest ESR (high efficiency)
when using four caps
20
22
0704, 16 V, X5R
0603, 10 V, X5R
GRMJN7R61C206ME05
Murata
Lowest Cost and Smallest Size
(Recommended) when using
four caps
GRM188R61A226ME15
Murata
(1) See Third-party Products Disclaimer
10.2.1.3 Application Curves
图10-2. Power Up
图10-3. Disable Charge
图10-4. VBUS_OVP
图10-5. IBAT_OCP
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图10-6. IBUS_OCP
图10-7. VBAT_OVP
10.2.2 Parallel BQ25968 for Higher Power Applications
VBUS
SW
SYSTEM LOAD
SYS
GND
BAT
BQ2589x
SDA/SCL
Ext.
OVPFET
Host
BQ25968_Slave
BQ25968_Master
VBUS
VBUS
SDA/
SCL
SDA/
Digital Core
Digital Core
SCL
QB
QB
OVPGATE
PMID
PMID
CFH1
CFH1
VOUT
VOUT
BATP
SC Phase
#1
SC Phase
#1
CFLY
CFLY
CFL1
CFL1
CFH2
PMID
PMID
CFH2
BATN
SC Phase
#2
SC Phase
#2
CFL2
BATN
SRP
CFL2
SRP
CDRVH
CDRVH
SRN
Protection
12-Bit ADC
12-Bit ADC
Protection
CDRVL_
ADDRMS
SRN
CDRVL_
ADDRMS
TSBAT_SYNCOUT
BATP_SYNCIN
图10-8. Parallel BQ25968 System
10.2.2.1 Design Requirements
For design requirements refer to 节10.2.1.1.
10.2.2.2 Detailed Design Procedure
If the total loss is greater than desired for a single BQ25968 at the fast charge current, two devices can be used
in parallel to reduce losses. The same design procedure is applied for the master and slave devices, with a few
additional steps for parallel operation.
The master device is used for BAT current sensing, so the slave device should short SRN and SRP to GND.
The master device supplies the SYNCOUT signal to the slave, so connect pin A5 of the master to pin A7 of the
slave device.
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The master device controls the OVP FET (if used), so the slave device should connect VAC to VBUS.
10.2.2.3 Application Curve
图10-9. Parallel Switching Waveform
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11 Power Supply Recommendations
The BQ25968 can be powered by a standard power supply capable of meeting the input voltage and current
requirements for evaluation. In the actual application, it must be used with a wall adapter that supports USB
Power Delivery (PD) Programmable Power Supply (PPS) specifications.
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12 Layout
12.1 Layout Guidelines
Layout is very important to maximize the electrical and thermal performance of the total system. General
guidelines are provided, but the form factor, board stack-up, and proximity of other components also need to be
considered to maximize the performance. The parasitics in the board layout impacts the switching current in the
MOSFETs and the output current of the device.
• VBUS traces should be as short and wide as possible to accommodate for high current.
• Minimize losses through connectors wherever possible, as the losses in these connectors will contribute a
significant amount to the total power loss.
• Use vias under the exposed thermal pad for thermal relief.
• Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be placed as
close to the device pins as possible.
• The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the
device, as these are switching pins and this will help reduce EMI.
• Connect all quiet signals to the AGND pins.
• Connect all power signals to the PGND pins.
• Do not route so the power planes are interrupted by signal traces.
12.2 Layout Example
图12-1. BQ25968 Layout Example - Top Layer
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图12-2. BQ25968 Layout Example - Bottom Layer
图12-3. BQ25968 Layout Example - Signal Layer 1
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图12-4. BQ25968 Layout Example - Signal Layer 2
图12-5. BQ25968Layout Example - Signal Layer 3
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图12-6. BQ25968 Layout Example - Signal Layer 4
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.1.2 Device Nomenclature
IADAPT (A)
VADAPT (V)
Output current of adapter
Output voltage of adapter
VCONADROP (V) Voltage drop across the adapter connector
VCONA (V)
Output voltage after adapter connector (same as the voltage at the beginning of the cable)
VCABLEDROP (V) Voltage drop
VCABLED (V)
VCOND (V)
VDEVCON (V)
IIN (A)
Voltage at the cable, going into the device
Output voltage after the device connector
Output voltage after the device control FETs (controlled by the PD controller)
Input current to the BQ25968
VIN (V)
Input voltage to the BQ25968
VOUT (V)
Output voltage of the BQ25968
VCONBDROP (V) Voltage drop across the battery connector and sense resistor
VBAT (V)
IBAT (A)
Voltage at the battery
Current at the battery
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ2597xEVM-xxx User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
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13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25968YFFR
ACTIVE
DSBGA
YFF
56
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25968
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
YFF0056
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
2
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
2.4 TYP
SYMM
H
G
D: Max = 3.361 mm, Min =3.301 mm
E: Max = 2.813 mm, Min =2.753 mm
F
E
D
C
SYMM
2.8
TYP
0.3
0.2
56X
B
A
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
7
0.4 TYP
4219481/A 10/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
56X ( 0.23)
(0.4) TYP
2
4
5
6
7
1
A
B
C
D
E
F
SYMM
G
H
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219481/A 10/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0056
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
56X ( 0.25)
(R0.05) TYP
1
2
3
4
5
6
7
A
(0.4)
TYP
B
METAL
TYP
C
D
E
F
SYMM
G
H
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4219481/A 10/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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