BQ27Z746 [TI]
具有集成保护器、采用 Impedance Track™ 技术的电池包侧单节电池电量监测计;
| 型号： | BQ27Z746 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成保护器、采用 Impedance Track™ 技术的电池包侧单节电池电量监测计 电池 |
| 文件： | 总31页 (文件大小：1535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ27Z746
ZHCSP94A –NOVEMBER 2021 –REVISED FEBRUARY 2022
适用于单芯锂离子电池组的BQ27Z746 Impedance Track™ 技术电池电量
监测计和保护解决方案
1 特性
3 说明
• 集成电池电量监测计和保护器
• 闪存可编程定制BQBMP RISC CPU
德州仪器 (TI) BQ27Z746 Impedance Track™ 电量监测
计解决方案是高度集成的高精度单芯电池电量监测计和
保护解决方案。
– 安全散列算法(SHA-256) 认证
– 400kHz I2C 总线通信接口
• 低电压(2.0 V) 运行
BQ27Z746 器件提供了一套基于电池组的完全集成式
解决方案，该解决方案具备闪存可编程的定制精简指令
集 CPU (RISC)、安全保护、电池电量变化检测模拟输
出以及身份验证功能，适用于单芯锂离子和锂聚合物电
池组。
• 2 个16 位独立高精度ADC
– 带有低至1mΩ的电流感测电阻的库仑计数
ADC
– 用于电池电压和外部及内部温度传感器的电压
BQ27Z746 电量监测计通过一个与 I2C 兼容的接口进
行通信，并将超低功耗的 TI BQBMP 处理器、高精度
模拟测量功能、集成式闪存、N 沟道高侧 FET 驱动器
以及 SHA-2 身份验证变换响应器融合为一个完整的高
性能电池管理解决方案。
ADC
• 基于获得专利的Impedance Track™（阻抗跟踪）
技术的电池电量监测
– 用于电池续航能力精确预测的电池放电模拟曲线
– 针对电池老化、温度以及额定引入效应进行自动
调节
器件信息
封装1
• 带有内置保护功能的电池开尔文检测差动模拟输出
引脚
• 高侧或低侧电流感测
封装尺寸（标称值）
器件型号
BQ27Z746
YAH (15)
1.7mm × 2.6mm
• 基于硬件的可编程保护
PACK+
S2
S1
– 高侧FET 栅极驱动器
G2
G1
RDSG
– 过压和欠压（OVP 和UVP）
– 放电过流保护和充电过流保护（OCD 和OCC）
– 放电短路(SCD)
CHG
DSG
RPACK
VDD
BAT
TS
1.8V
LDO
CVDD
1uF
SRP
SRN
Battery
Protection
BAT
– 基于固件的过热(OT)
• 典型功率降低模式
PACK
Li-Ion
Cell
BAT_SP
BAT_SN
BAT
VSS
Cell
Sensing
Buffer
NTC
– 睡眠模式：20μA
– 运输模式：10μA
– 货架模式5μA
VSS
SRP
VSS
GPO/TS1
SRP
ENAB
SCL
Fuel
Gauge
RSNS
1m
SRN
SRN
– 关断模式：0.2μA
SDA
• 超紧凑15 焊球NanoFree™ DSBGA
PACK–
2 应用
BQ27Z746 简化版原理图
• 带1 芯可充电电池的任何终端设备
– 智能手机
– 平板电脑
– 摄像头
– 便携式可穿戴设备/医疗设备
– 工业手持设备
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDW2
BQ27Z746
www.ti.com.cn
ZHCSP94A –NOVEMBER 2021 –REVISED FEBRUARY 2022
Table of Contents
7.4 Device Functional Modes..........................................20
8 Applications and Implementation................................21
8.1 Application Information............................................. 22
8.2 Typical Applications.................................................. 22
9 Power Supply Requirements........................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 第三方产品免责声明................................................27
11.2 Documentation Support.......................................... 27
11.3 接收文档更新通知................................................... 27
11.4 支持资源..................................................................27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 术语表..................................................................... 27
12 Mechanical, Orderable, and Packaging
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Digital I/O: DC Characteristics.................................. 12
6.7 Digital I/O: Timing Characteristics.............................13
6.8 Typical Characteristics..............................................15
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................17
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2021) to Revision A (February 2022)
Page
• Updated C2 pin name to GPO/TS1 Pin Configurations and Functions ............................................................. 3
• Updated Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE) ...............................................................6
• Updated Gauge Measurements (ADC, CC, Temperature) ...............................................................................11
• Updated Digital I/O: DC Characteristics .......................................................................................................... 12
• Updated Typical Characteristics ...................................................................................................................... 15
• Updated Battery Sensing .................................................................................................................................19
• Updated Typical Applications ...........................................................................................................................22
• Updated Layout Guidelines ............................................................................................................................. 25
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ZHCSP94A –NOVEMBER 2021 –REVISED FEBRUARY 2022
5 Pin Configurations and Functions
Bottom View
Top View
1
2
3
1
2
3
SRP
SRN
SCL
CHG
DSG
PACK
E
D
C
B
A
A
B
C
D
E
VSS
TS
ENAB
SDA
VDD
TS
BAT
BAT_SP
BAT_SN
SDA
GPO/
TS1
GPO/
TS1
BAT_SN
BAT_SP
PACK
VDD
CHG
BAT
VSS
SRP
ENAB
SRN
DSG
SCL
0.5 mm
(typ)
0.2 mm
(typ)
0.4 mm
(max)
1.7 mm (typ)
图5-1. Pinout Diagram
表5-1. Pin Functions
PIN
NO.
A1
DESCRIPTION
NAME
TYPE(1)
CHG
AO
Charge FET (CHG) driver
Discharge FET (DSG) driver. Connect a series 10-MΩtypical resistor (RDSG) between DSG pin
and PACK+ positive terminal.
DSG
PACK
VDD
A2
A3
B1
AO
IA
P
Pack input voltage sensing pin. Connect a series 5-kΩtypical resistor (RPACK) between PACK
pin and PACK+ positive terminal.
LDO regulator input. Connect a 1-µF typical capacitor (CVDD) between VDD and VSS. Place the
capacitor close to the gauge.
BAT
BAT_SP
BAT_SN
TS
B2
B3
C3
C1
IA
OA
OA
IA
Battery voltage measurement sense input
Cell sense output, positive
Cell sense output, negative
Thermistor input to ADC with internal 18-kΩpullup resistor
General purpose output.
Optional TS1 ADC input channel with internal 18-kΩpullup resistor
GPO/TS1
VSS
C2
D1
D2
D3
I/O
P
Device ground
Active low digital input with weak internal pullup to VDD. If enabled for ultra-low power SHIP
mode, driving this signal to the PACK–negative terminal will enable the device to wake up.
ENAB
SDA
I
Digital input, open drain output for I2C serial data. Use with a typical 10-kΩpullup resistor.
I/O
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表5-1. Pin Functions (continued)
PIN
NO.
DESCRIPTION
NAME
TYPE(1)
Digital input, open drain output for I2C serial clock. Use with a typical 10-kΩpullup resistor.
SCL
E3
E1
I/O
This is the positive analog input pin connected to the internal coulomb-counter peripheral for
integrating a small voltage between SRP (positive side) and SRN (negative side).
SRP
SRN
IA
IA
This is the negative analog input pin connected to the internal coulomb-counter peripheral for
integrating a small voltage between SRP (positive side) and SRN (negative side).
E2
(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
Supply voltage range
VDD
6
8
V
PACK (limited to 4 mA max)
PACK+ external battery pack input terminal with 5 kΩ
24
24
–0.3
–12
resistor in series to device PACK input pin
PACK+ external battery pack input terminal with a 5 kΩ
resistor (RPACK) in series to device PACK pin and a 10
MΩ resistor (RDSG) to device DSG pin
Input voltage range
V
BAT
6
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–65
SDA, SCL, ENAB
TS
6
2
SRP, SRN
BAT_SP, BAT_SN
CHG, DSG
VBAT + 0.3
6
12
Output voltage range
V
Operating junction temperature, TJ
Storage temperature, Tstg
85
°C
°C
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM) on all pins, per ANSI/ESDA/
JEDEC JS-001(1)
±2000
V(ESD) Electrostatic discharge
V
Charged-device model (CDM) on all pins, per ANSI/ESDA/
JEDEC JS-002(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage
range
VDD
2.0
5.5
V
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ZHCSP94A –NOVEMBER 2021 –REVISED FEBRUARY 2022
6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
0
12
5.5
PACK (with 5 kΩ RPACK current limit)
PACK (no RPACK current limit)
0
BAT
1.5
–0.3
5.5
Input voltage
range
V
SDA, SCL, ENAB
TS
VDD
VSS
1.8
SRN, SRP
VCC_CM + 0.1
VDD +VOFFS
1.8
V
CC_CM –0.1
2
BAT_SP, BAT_SN
Output voltage GPO
range
VSS
V
VDD+ (VDD ×
CHG, DSG
VSS
1
AFETON
)
External Decoupling Capacitor on VDD pin, CVDD
External Decoupling Capacitor on TS pin, CTS
µF
µF
0.01
External Sense Resistor from PACK+ terminal to device PACK pin,
RPACK
5
kΩ
External Sense Resistor from PACK+ terminal to device DSG pin,
RDSG
10
MΩ
External Sense Resistor from SRN to SRP pins, RSNS
Operating Temperature, TA
1
20
85
mΩ
-40
℃
6.4 Thermal Information
Over-operating free-air temperature range (unless otherwise noted)
YAH (DSBGA)
THERMAL METRIC(1)
UNIT
(15 PINS)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
70
17
20
1
RθJC(top)
RθJB
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
18
NA
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
6.5.1 Supply Current
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃, no host communications, PROT On(1)
,
VCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA), VDD = 4 V, Average current over 30 s with default firmware settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INORMAL
ISLEEP
Standard operating conditions
57
µA
µA
20
Measured current ≤sleep current threshold
VBAT = 3.0 V, Firmware SHIP mode enabled. 60 s
average
ISHIP
10
5
µA
µA
VBAT = 3.0 V, Firmware SHELF mode enabled. PROT
Off . 60 s average
ISHELF
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6.5.1 Supply Current (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃, no host communications, PROT On(1)
,
VCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA), VDD = 4 V, Average current over 30 s with default firmware settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Firmware SHUTDOWN mode enabled OR VBAT
VSHUT, PROT Off
≤
ISHUT
0.2
1
µA
(1) PROT On/Off. Protector block enabled with both DSG and CHG pins On or Off.
6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal 1.8-V LDO (REG18)
VREG18
Regulator output voltage
1.6
1.8
2.0
V
Regulator output change with
temperature
+1.2%
ΔVREG18TEMP
ΔVBAT/ΔTA, IREG18 = 10 mA
–1.2%
Line regulation
0.8%
1.5%
60
ΔVREG18LINE
ΔVREG18LOAD
ISHORT
–0.8%
–1.5%
18
Load regulation
IREG18 = 16 mA
VREG18 = 0 V
Short Circuit Current Limit
mA
dB
ΔVBAT/ΔVREG18, IREG18 = 10 mA,
VBAT > 2.5 V, f = 10 Hz
PSRRREG18
Power Supply Rejection Ratio
50
VPORth
VPORhy
POR threshold
POR hysteresis
Rising Threshold
1.55
0.7
1.65
0.1
1.75
V
V
ENAB turn-on voltage for
LDO (1)
VENAB
Active low falling threshold
0.4
1.3
V
RENAB
ENAB pin pullup resistance (1) Internal pull-up to VDD
1
65.536
32.768
MΩ
Low Frequency Internal Oscillator (LFO)
fLFO
LFO Operating frequency
LFO Frequency error
LFO operating frequency
LFO frequency error
kHz
kHz
Normal operating mode
Low power mode
fLFO(ERR)
fLFO32
+2.5%
+5%
–2.5%
–5%
fLFO32(ERR)
High Frequency Internal Oscillator (HFO)
fHFO
HFO operating frequency
16.78
MHz
2.5%
3.5%
TA = –20°C to 70°C
TA = –40°C to 85°C
–2.5%
–3.5%
fHFO(ERR)
HFO frequency error
TA = –40°C to 85°C,
CLKCTL[HFRAMP] = 1, oscillator
frequency within +/- 3% of nominal
frequency or a power-on reset
tHFOSTART
HFO start-up time
4
ms
V
Voltage Reference1 (VREF1)
VREF1
Internal reference voltage
1.195
1.21
1.21
1.227
REF1 is for protection circuits, LDO,
and CC
Internal Reference Voltage
Drift
VREF1_DRIFT
+80 PPM/°C
–80
Voltage Reference2 (VREF2)
VREF2
Internal Reference Voltage
1.2
1.22
V
REF2 is for the ADC
Internal Reference Voltage
Drift
VREF2_DRIFT
+20 PPM/°C
–20
Wake-Up Comparator (I-WAKE)
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6.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE) (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sense resistor voltage
threshold range to wake-up
500 µV step. Data Flash firmware
VWAKE
mV
–1.5
–2.0
–2.5
gauge from low-power states default is 2 mV typical
(2)
Ideal RSNS = 1 mΩ
–1000
–500
–200
–3000
–1500
–600
Effective wake-up current
Ideal RSNS = 2 mΩ
threshold range
IWAKE
mA
Ideal RSNS = 5 mΩ
Wake-up detection accuracy
VWAKE_ACC
250
µV
ms
–250
(2)
Configurable with two delay options.
Data Flash firmware default is 12 ms
typical
9.6
12
24
14.4
28.8
I-WAKE detection delay
options (1)
tWAKE
19.2
(1) Specified by design
(2) Data flash is configurable in FULL ACCESS mode and locked in SEALED. Accuracy is assured by factory trim at specified default
threshold. A change in the factory threshold requires device calibration in the field.
6.5.3 Battery Protection (CHG, DSG)
Protection hardware circuits operating over free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
N-CH FET DRIVER, CHG AND DSG
VDRIVER
Gate Driver Voltage, VCHG or VDSG
CLOAD = 8 nF
2 × VDD
1.0
V
FET driver gain factor, Vgs voltage to
FET
AFETON = (Vdriver –VDD)/VDD,
CLOAD = 8 nF, UVP < VDD < 3.8 V
AFETON
0.9
1.2
V/V
VDSGOFF
VCHGOFF
DSG FET driver off output voltage
CHG FET driver off output voltage
0.2
0.2
V
V
VDSGOFF = VDSG –PACK, CL= 8 nF
VCHGOFF = VCHG –VSS , CL= 8 nF
CL = 8 nF, (Vdriver –VDD)/VDD = 1x
VFETON changes from VDD to 2×VDD
trise
FET driver rise time (1)
FET driver fall time (1)
400
50
800
200
us
us
CL = 8 nF, VFETON changes from
VFETMAX to VFETOFF
tfall
Firmware FET driver shut down
voltage (2) (4)
VFET_SHUT
2000
2000
2100
2300
5000
mV
Configurable with 1-mV steps
VFET_SHUT_RE Firmware FET driver shut down
5000
10
mV
uA
release (2) (4)
L
ILOAD
FET driver maximum loading
VOLTAGE PROTECTION
Hardware overvoltage protection
3500
5000
(OVP) detection range (3)
Recommended threshold range.
Factory trimmed in 50-mV steps
VOVP
mV
Factory default trimmed threshold(3)
4525
TA = 25oC,
CLOAD at CHG/DSG < 1 μA
15
25
50
mV
mV
mV
–15
–25
–50
TA = 0oC to 60oC,
CLOAD at CHG/DSG < 1 μA
VOVP_ACC
Hardware OVP detection accuracy (3)
Firmware OVP detection range (4)
TA = –40oC to 85oC,
CLOAD at CHG/DSG < 1 μA
VFW_OVP
2000
2000
4490
4290
5000
5000
mV
mV
Configurable with 1-mV steps
VFW_OVP_REL Firmware OVP release range (4)
Hardware undervoltage (UVP)
2000
4000
detection range (3)
VUVP
Recommended threshold range.
Factory trimmed in 50-mV steps
mV
Factory default trimmed threshold(3)
2300
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6.5.3 Battery Protection (CHG, DSG) (continued)
Protection hardware circuits operating over free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25oC,
MIN
TYP
MAX
UNIT
20
mV
–20
CLOAD at CHG/DSG < 1 μA
TA = 0oC to 60oC,
CLOAD at CHG/DSG < 1uA
VUVP_ACC
Hardware UVP detection accuracy (3)
30
50
mV
mV
–30
–50
TA = –40oC to 85oC,
CLOAD at CHG/DSG < 1uA
VFW_UVP
Firmware UVP detection range (4)
2000
2000
100
2500
2900
300
5000
5000
550
Configurable with 1 mV steps
SHUTDOWN mode only
VFW_UVP_REL Firmware UVP release range (4)
mV
RPACK-VSS
VRCP
Resistance between PACK and VSS
Reverse Charge Protection limit
kΩ
–10V Continuous Operating, –12 V
ABS MAX
V
–10
CURRENT PROTECTION
Sense voltage threshold range for
1
100
Recommended threshold range.
Factory trimmed in 1-mV steps
Overcurrent in Charge (OCC) (3) (4)
Factory default trimmed threshold(3)
OCC 2-mV step design option
VOCC
mV
mV
14
VOCC
2 mV step configuration option
Ideal RSNS = 1 mΩ
2
4
256
100
50
14
7
Effective OCC current threshold range
from VOCC
IOCC
2
A
Ideal RSNS = 2 mΩ
(1) (4)
0.8
0
2.8
20
Ideal RSNS = 5 mΩ
IFW_OCC
Firmware OCC detection range (4)
Configurable with 1 mA steps
12000 +ICC_IN
mA
mV
mV
Sense voltage threshold range for
Overcurrent in discharge (OCD) (3) (4)
–4
–100
Recommended threshold range.
Factory trimmed in 1-mV steps
VOCD
Factory default trimmed threshold(3)
–16
VOCD
OCD 2-mV step design option
±2 mV step configuration option
Ideal RSNS = 1 mΩ
–2
–4
–256
–16
–8
–100
–50
–20
Effective OCD current threshold range
IOCD
A
Ideal RSNS = 2 mΩ
–2
(1) (4)
from VOCD
Ideal RSNS = 5 mΩ
–0.8
–3.2
IFW_OCD
Firmware OCD detection range (4)
Configurable with 1-mA steps
mA
–ICC_IN –7000
0
Sense voltage threshold range for
Short circuit current in discharge
(SCD) (3) (4)
–5
–120
Threshold factory trimmed with 1-mV
steps
VSCD
mV
A
Factory default trimmed threshold(3)
–20
Ideal RSNS = 1 mΩ
Ideal RSNS = 2 mΩ
Ideal RSNS = 5 mΩ
<20 mV, TA = –25°C to 60oC
<20 mV
–5
–2.5
–1
–20
–10
–4
–120
–60
–24
2.1
2.1
3
Effective SCD current threshold range
ISCD
(1) (4)
from VSCD
-2.1
–2.1
–3
Overcurrent (OCC, OCD, SCD)
detection accuracy (3)
VOC_ACC
mV
20 mV–55 mV
56 mV–100 mV
>100 mV
5
–5
12
–12
Current sink between PACK and VDD
during current fault
IPACK-VDD
Load removal detection in firmware
15
μA
OCC fault release threshold
100
mV
mV
VOC_REL
(VPACK –VBAT
)
OCD, SCD fault release threshold
–400
OVERTEMPERATURE PROTECTION
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6.5.3 Battery Protection (CHG, DSG) (continued)
Protection hardware circuits operating over free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–40.0
–40.0
–40.0
–40.0
–40.0
–40.0
–40.0
–40.0
TYP
55.0
50.0
60.0
55.0
0.0
MAX
150.0
150.0
150.0
150.0
150.0
150.0
150.0
150.0
UNIT
°C
TOTC_TRIP
TOTC_REL
TOTD_TRIP
TOTD_REL
TUTC_TRIP
TUTC_REL
TUTD_TRIP
TUTD_REL
OTC trip/release threshold (2) (4)
°C
°C
OTD trip/release threshold (2) (4)
UTC trip/release threshold (2) (4)
UTD trip/release threshold (2) (4)
°C
Firmware-based and configurable in
0.1°C steps
°C
5.0
°C
0.0
°C
5.0
°C
PROTECTION DELAY(1)
Configurable with 4095 delay options
in 1.953-ms steps. Factory default =
1000 ms (512 counts) typical
OVP detection delay (debounce)
tOVP
tUVP
tOCD
tOCC
tSCD
1.953
1.953
1.953
0.244
122
1000
127
7.8
7998
248
ms
ms
ms
ms
µs
options (1) (4)
Configurable with 127-delay options in
1.953-ms steps. Factory default = 127
ms (65 counts) typical
UVP detection delay (debounce)
options (1) (4)
Configurable with 31 delay options in
1.953-ms steps. Factory default = 7.8
ms (4 counts) typical
OCD detection delay (debounce)
options (1) (4)
60.5
62.3
854
Configurable with 255 delay options in
0.244-ms steps. Factory default = 15.9
ms (65 counts) typical
OCC detection delay (debounce)
options (1) (4)
15.9
244
Configurable with seven delay options
in 122-µs steps. Factory default = 244-
µs (2 counts) typical
SCD detection delay (debounce)
options (1) (4)
TOTC_DLY
TOTD_DLY
TUTC_DLY
TUTD_DLY
OTC trip delay(2) (4)
OTD trip delay(2) (4)
UTC trip delay(2) (4)
UTD trip delay(2) (4)
0
0
0
0
2
2
2
2
255
255
255
255
s
s
s
s
Firmware-based and configurable in 1-
s steps.
The typical value is the data flash
factory default.
ZERO VOLT (LOW VOLTAGE) CHARGING
Charger voltage requires to start zero-
volt charging
V0CHGR
1.6
V
V
V
PACK –VSS
Battery voltage that inhibits zero-volt
charging
V0INH
1.0
1.1
VDD –VSS
(1) Specified by design. Not production tested.
(2) Firmware-based parameter. Not production tested.
(3) Accuracy assured by factory trim at specified default threshold. A change from the default threshold requires device calibration in the
field. Refer to the BQ27Z746 Technical Reference Manual.
(4) Specified typical value is the factory default. Not production tested. The data flash configuration value can be changed in FULL
ACCESS mode and is locked in SEALED mode. Refer to the BQ27Z746 Technical Reference Manual.
6.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Response
VBAT @ 1500 mV and 2400 mV DC,
PACK-BAT_SP ≥200 mV,
BAT_SP load: Hi-Z to 1 kΩ,
BAT_SN load: 1 kΩ to 10 kΩ
1450
2350
1500
2400
1550
2450
Buffer accuracy
(BAT_SP –BAT_SN)
VBUFACC
mV
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6.5.4 Cell Sensing Output (BAT_SP, BAT_SN) (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
370
TYP
400
200
0
MAX
UNIT
400-mV option, VBAT = 1.5 V to 2.5 V
200-mV option, VBAT = 2.0 V to 2.5 V
0-mV option, VBAT = 2.0 V to 2.5 V
600-mV option, VBAT = 2.0 to 2.5 V
430
230
30
170
BAT_SN common mode shift
(BAT_SN –VSS)
VBUFOFFS
mV
–30
550
600
650
VBAT = 1.5 to 2.5 V, no load, BAT_SP
–BAT_SN, VPACK –VBAT = 1.0 V
Buffer line regulation
Buffer load regulation
10
mV
mV
ΔVBUF_LINE
ΔVBUF_LOAD
VRLOACC
VBAT = 2.4 V, load = 1 mA, BAT_SP –
BAT_SN, VPACK - VBAT = 1.0 V
1.2
RLO mode accuracy
(BAT_SP –BAT_SN)
+7
+5
+5
–7
–5
–5
VBAT = 3000-mV to 5000-mV DC,
For stability, 0-mV buffer option
enabled
BAT_SP load: Hi-Z to 1 kΩ
BAT_SN load: 1 kΩ to 10 kΩ
RLO mode accuracy
(BAT_SP –VSS)
VRLOACCP
VRLOACCN
mV
RLO mode accuracy
(BAT_SN –VSS)
160
459
160
459
200
510
200
510
260
561
260
561
200-Ω option, DSG FET = ON
510-Ω option, DSG FET = ON
200-Ω option, DSG FET = ON
510-Ω option, DSG FET = ON
BAT_SP low resistance
mode
RLO_SP
Ω
Ω
BAT_SN low resistance
mode
RLO_SN
BAT_SP high impedance
mode
RHIZ_SP
RHIZ_SN
tBUF_OFF
0.6
0.6
1.0
1.0
1.3
1.3
CHG FET = OFF
MΩ
BAT_SN high impedance
mode
Buffer disable timing respect to DSG
FET turn-on
Buffer turn-off timing (1)
500
us
pF
CBUF_SP
CBUF_SN
150
150
BAT_SP to SRN (PACK–)
BAT_SN to SRN (PACK–)
Max external capacitance for
stable operation (1)
Buffer unity gain bandwidth
BBUF_BW
Buffer enabled
30
kHz
(1)
BAT_SP –BAT +Fault
+100
+250
(BCP) Threshold Range(1)
Recommended threshold range.
VBCP
Factory default trimmed
threshold(3)
Factory trimmed in ≈2-mV steps
+200
mV
RLO mode enabled,
Step size 10 mV
BAT_SP –BAT +Fault
VBCP_ACC
+10
–10
Accuracy (3)
BAT_SP –BAT –Fault
–250
–100
(BDP) Threshold Range(1)
Recommended threshold range.
VBDP
Factory trimmed in ≈2-mV steps
Factory default trimmed
threshold(3)
mV
mV
–200
RLO mode enabled,
Step size 10 mV
BAT_SP –BAT –Fault
VBDP_ACC
+10
–10
Accuracy (3)
BAT_SN –VSS +Fault
+100
+250
(BCN) Threshold Range(1)
Recommended threshold range.
Factory trimmed in ≈2-mV steps
VBCN
Factory default trimmed
threshold(3)
+200
RLO mode enabled,
Step size 10 mV
BAT_SN –VSS +Fault
VBCN_ACC
+10
–10
Accuracy (3)
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6.5.4 Cell Sensing Output (BAT_SP, BAT_SN) (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BAT_SN –VSS –Fault
–250
–100
(BDN) Threshold Range(1)
Recommended threshold range.
VBDN
Factory trimmed in ≈2-mV steps
Factory default trimmed
threshold(3)
mV
–200
RLO mode enabled,
Step size 10 mV
BAT_SN –VSS –Fault
VBDN_ACC
+10
–10
Accuracy (3)
8-ms delay
8
ms
ms
BAT_SP / BAT_SN
tLO_FAULT_DLY
fault comparator delay(1)
100-ms delay
100
BAT_SP / BAT_SN
tLO_FAULT_STRT
1000
ms
fault restart time (1) (2)
Transient Response
VLOAD_SP
BAT_SP load transient (1)
VLOAD_SN
300
200
mV
mV
–300
–200
No load ≥1 KΩ ≥No load,
Transition time 1 μs
BAT_SN load transient (1)
BAT_SN line transient (1)
VBAT = 1.5 V ≥2.4 V ≥1.5 V,
Transition slope 500 mV / 10 us
VLINE_SN
VTRANS
30
50
mV
mV
–30
Firmware commanded transition from
BUF mode to RLO mode
(BAT_SP –BAT_SN)
–700
transition transient (1)
(1) Specified by Design. Not production tested.
(2) Firmware-based parameter. Not production tested.
(3) Accuracy assured by factory trim at specified default threshold. A change from the default threshold requires device calibration in the
field. Refer to the BQ27Z746 Technical Reference Manual.
6.5.5 Gauge Measurements (ADC, CC, Temperature)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Digital Converter (ADC)
Battery Voltage ADC
VBAT_RES
Signed data format, ±15 bits
16
bits
V
Resolution (bits)
Battery Measurement Full
VBAT_FS
5.5
–0.2
Scale Range
±1
±2
TA = +25℃, VBAT = 4.0 VDC
VBAT_ERR
Battery Voltage ADC Error
mV
VBAT = 2.5 to 5.0 VDC
RBAT
Effective input resistance
8
MΩ
ms
Battery Voltage Conversion
Time
tBAT
11.7
15
VADC_RES
Effective Resolution
VBAT
14
bits
Coulomb Counter (CC)
Common mode voltage
VCC_CM
VSS
VBAT
V
V
VSS = 0V, 2V ≤VBAT ≤5V
range
VCC_IN
Input voltage range
VCC_CM+0.1
V
CC_CM–0.1
Ideal RSNS = 1 mΩ (16-bit data
limited)
±32,768
Effective input current sense
range (1) (2)
ICC_IN
mA
Ideal RSNS = 2 mΩ (16-bit data
limited)
±20,000
1000
16
Ideal RSNS = 5 mΩ
tCC_CONV
Conversion time
Single conversion
ms
bits
µV
CCADC_RES
Effective Resolution
1 LSB = VREF1/10/(±215
)
±3.7
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6.5.5 Gauge Measurements (ADC, CC, Temperature) (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
Ideal RSNS = 1.0 mΩ, 10.0 A, TA =
25 ℃
26
Effective current
measurement error
ICC_ERR
Ideal RSNS = 1.0 mΩ, –10.0 A, TA
= 25 ℃
29
CCOSE
Offset error
16- bit Post-Calibration
-2.6
1.3
+2.6
LSB
CCOSE_DRIFT
Offset error drift
15-bit + sign, Post Calibration
0.04
0.07 LSB/°C
15-bit + sign, Over input voltage
range
CCGE
Gain Error
-492
7
131
+492
LSB
RCC_IN
Effective input resistance
MΩ
NTC Thermistor Measurement
Factory Trimmed, Firmware
compensated
RNTC(PU)
Internal Pullup Resistance
14.4
–250
–2
18
–120
±1
21.6
0
kΩ
Resistance drift over
temperature
RNTC(DRIFT)
Firmware compensated
PPM/°C
Ideal 10KΩ 103AT NTC, TA = –10
to 70℃
+2
External NTC Thermistor
Temperature Measurement
Error with Linearization
RNTC_ERR
℃
Ideal 10KΩ 103AT NTC, TA = –40
to 85℃
±2
+3
–3
Internal Temperature Sensor
Internal Temperature sensor
V(TEMP)
VTEMPP
1.65
0.17
1.73
0.18
1.8 mV/°C
0.19 mV/°C
voltage drift
Internal Temperature sensor
voltage drift
V
TEMPP –VTEMPN (specified by
V(TEMP)
design)
(1) Firmware-based parameter. Not production tested.
(2) Limited by 16-bit twos-complement numeric format
6.5.6 Flash Memory
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETER
TEST CONDITIONS
MIN
10
TYP
100
MAX
UNIT
Years
Cycles
Cycles
µs
Data retention
Data Flash
20000
1000
Flash programming write
cycles
Instruction Flash
t(ROWPROG)
t(MASSERASE)
t(PAGEERASE)
IFLASHREAD
IFLASHWRTIE
IFLASHERASE
Row programming time
Mass-erase time
40
40
40
1
ms
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
Page-erase time
ms
Flash Read Current
Flash Write Current
Flash Erase Current
mA
5
mA
15
mA
6.6 Digital I/O: DC Characteristics
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃, VREG18 = 1.8 V
PARAMETER
I2C Pins (SCL, SDA/HDQ)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
High-level input voltage
Low-level input voltage low
Low-level output voltage
SCL, SDA pins
1.26
V
V
V
SCL, SDA pins
0.54
0.36
VOL
SCL, SDA pins, IOL = 1 mA
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6.6 Digital I/O: DC Characteristics (continued)
Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃, VREG18 = 1.8 V
PARAMETER
Input capacitance
Input leakage current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
pF
CI
SCL, SDA pins
10
Ilkg
SCL, SDA pins
1
µA
Push-Pull Pins (GPO)
VIH
VIL
VOH
VOL
CI
High-level input voltage
Push-Pull pins
1.15
1.08
V
V
Low-level input voltage low
Output voltage high
Output voltage low
Push-Pull pins
0.54
Push-Pull pins, IOH = -1 mA
Push-Pull pins, IOL = 1 mA
Push-Pull pins
V
0.36
10
V
Input capacitance
pF
µA
Ilkg
Input leakage current
Push-Pull pins
1
6.7 Digital I/O: Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
I2C Timing —100 kHz
fSCL
Clock Operating Frequency SCL duty cycle = 50%
100
kHz
µs
µs
µs
µs
ns
ns
ns
ns
µs
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
START Condition Hold Time
Low period of the SCL Clock
High period of the SCL Clock
Setup repeated START
Data hold time (SDA input)
Data setup time (SDA input)
Clock Rise Time
4.0
4.7
4.0
4.7
0
250
10% to 90%
90% to 10%
1000
300
tf
Clock Fall Time
tSU:STO
Setup time STOP Condition
4.0
4.7
Bus free time STOP to
START
tBUF
µs
I2C Timing —400 kHz
fSCL
Clock Operating Frequency SCL duty cycle = 50%
START Condition Hold Time
Low period of the SCL Clock
High period of the SCL Clock
Setup repeated START
400
kHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
0.6
1.3
600
600
0
Data hold time (SDA input)
Data setup time (SDA input)
100
Clock Rise Time
10% to 90%
90% to 10%
300
300
tf
Clock Fall Time
tSU:STO
Setup time STOP Condition
0.6
1.3
Bus free time STOP to
START
tBUF
µs
HDQ Timing
tB
Break Time
190
40
µs
µs
µs
µs
µs
tBR
Break Recovery Time
Host Write 1 Time
Host Write 0 Time
Cycle Time, Host to device
tHW1
tHW0
tCYCH
Host drives HDQ
Host drives HDQ
device drives HDQ
0.5
86
50
145
190
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6.7 Digital I/O: Timing Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
190
32
NOM
MAX
UNIT
µs
tCYCD
tDW1
Cycle Time, device to Host
Device Write 1 Time
Device Write 0 Time
Device Response Time
device drives HDQ
device drives HDQ
device drives HDQ
device drives HDQ
205
250
50
µs
tDW0
80
145
950
µs
tRSPS
190
µs
Host drives HDQ after device drives
HDQ
tTRND
tRISE
tRST
Host Turn Around Time
250
2.2
µs
µs
s
HDQ Line Rising Time to
Logic 1
1.8
Host drives HDQ low before device
reset
HDQ Reset
SDA
t
BUF
t
t
LOW
t
f
HD;STA
t
r
t
t
SP
t
r
f
SCL
t
t
SU;STA
t
SU;STO
HD;STA
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
图6-1. I2C Timing
1.2V
t
t
(R ISE)
(BR )
t
(B)
(b) H D Q line rise tim e
(a) Break and Break R ecovery
t
(D W 1)
t
(H W 1)
t
(D W 0)
(C YC D )
t
(H W 0)
(C YC H )
t
t
(d) Gauge Transm itted Bit
(c) H ost Transm itted Bit
7-bit address
1-bit
R/W
8-bit data
Break
t
(R SPS)
(e) Gauge to Host Response
t
(R ST )
(f) H D Q R eset
a . H D Q Bre a kin g
b . R ise tim e o f H D Q lin e
c. H D Q H o st to fu e l g a u g e co m m u n ica tio n
d . Fu e l g a u g e to H o st co m m u n ica tio n
e . Fu e l g a u g e to H o st re sp o n se fo rm a t
f. H D Q H o st to fu e l g a u g e
图6-2. HDQ Timing
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6.8 Typical Characteristics
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
30 A
10 A
2 A
30 A
10 A
2 A
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
Temperature (èC)
D003
D002
图6-3. Charge Current Error vs Temperature and
图6-4. Discharge Current Error vs Temperature
Charger Current with 1-mΩsense, No Calibration and Load Current with 1mΩSense, No Calibration
1
0.8
0.6
0.4
0.2
0
2
0
2.5-V Common Mode
4.0-V Common Mode
5.5 V Common Mode
-2
-4
-0.2
-0.4
-0.6
-0.8
-1
-6
2.0 V
3.6 V
5.0 V
-8
-10
-50 -40 -30 -20 -10
0
10 20 30 40 50 60
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (C)
Temperature (èC)
D001
图6-5. 2.2A Current Error vs CC ADC Input
Common Mode Voltage and Temperature, No
Calibration
图6-6. Cell Voltage Error vs Battery Voltage and
Temperature
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7 Detailed Description
7.1 Overview
The BQ27Z746 gas gauge is a fully integrated battery manager that employs flash-based firmware to provide a
complete solution for battery-stack architectures composed of 1-series cells. The BQ27Z746 device interfaces
with a host system through an I2C or HDQ protocol. High-performance, integrated analog peripherals enable
support for a sense resistor down to 1 mΩ, and simultaneous current/voltage data conversion for instant power
calculations. The following sections detail all of the major component blocks included as part of the BQ27Z746
device.
7.2 Functional Block Diagram
Updated:21 Feb 2019
PACK+
S1
S2
R
DSG
10Mꢀ
G2
G1
CHG
DSG
R
PACK
5Kꢀ
REF1
VDD
PACK
DSG Load
Detection
REF1
Charge Pump and
nFET Driver
PACK
VREG
VDD
I
PACK-VDD
1.8V
LDO
Super
Comparator
C
BAT
BAT
1uF
(OV, UV, OCC,
OCD, SCD)
Protection
Logic
SRP-SRN
PACK
Pack
Detection
POR
ENAB
PACK
BAT_SP
BAT_SN
BAT
VSS
BAT
TS
Pack
Divider
Direct Battery
Sensing Output
VREG
18kꢀ
NTC
Bias
+
Internal Die
Temp Sensor
Li-Ion
Cell
VDD
Weak PU
ADC MUX
REF1
REF1
NTC
-
VSS
ENAB
ENAB
16-bit
CC
16-bit
ADC
REF2
HFO
LFO
R
SNP
100ꢀ
SRP
SRN
Test
Interface
IO and
Interrupt
Controller
R
SNS
Data Flash
4-kBytes
Data SRAM
2-kBytes
CC/ADC
Digital Filter
0.1uF
≥ 1mꢀ
R
SNN
100ꢀ
DMData (8b)
DMAddr (16b)
GPO
bqBMP
CPU
Push Pull
PMData (8b)
SDA
SCL
Open Drain
Open Drain
PMAddr (16b)
Timers
COMM
Engine
Program Flash
32-kBytes
ROM
20-kBytes
PACKœ
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7.3 Feature Description
7.3.1 BQ27Z746 Processor
The BQ27Z746 device uses a custom TI-proprietary processor design that features a Harvard architecture and
operates at frequencies up to 4.2 MHz. Using an adaptive, three-stage instruction pipeline, the BQ27Z746
processor supports variable instruction lengths of 8, 16, or 24 bits.
7.3.2 Battery Parameter Measurements
The BQ27Z746 device measures cell voltage and current simultaneously, and also measures temperature to
calculate the information related to remaining capacity, full charge capacity, state-of-health, and other gauging
parameters.
7.3.2.1 Coulomb Counter (CC) and Digital Filter
The first ADC is an integrating analog-to-digital converter designed specifically for tracking charge and discharge
activity, or coulomb counting, of a rechargeable battery. It features a single-channel differential input that
converts the voltage difference across a sense resistor between the SRP and SRN terminals with a resolution of
3.74 µV. The differential input common mode voltage range is from VSS to VBAT and supports a 1-series cell
high-side or low-side sensing option with ±0.1-V input range. The CC digital filter generates a 16-bit conversion
value from the delta-sigma CC front-end. New conversions are available every 1 s.
7.3.2.2 ADC Multiplexer
The ADC multiplexer provides selectable connections to the external pins, BAT and TS, as well as the internal
temperature sensor. In addition, the multiplexer can independently enable the TS input connection to the internal
thermistor biasing circuitry, and enables the user to short the multiplexer inputs for test and calibration purposes.
7.3.2.3 Analog-to-Digital Converter (ADC)
The second ADC is a 16-bit delta-sigma converter designed for general-purpose measurements. The ADC
automatically scales the input voltage range during sampling based on channel selection. The converter
resolution is a function of its full-scale range and number of bits, yielding a 38-µV resolution.
7.3.2.4 Internal Temperature Sensor
An internal temperature sensor is available on the BQ27Z746 device to reduce the cost, power, and size of the
external components necessary to measure temperature. It is available for connection to the ADC using the
multiplexer, and is ideal for quickly determining pack temperature under a variety of operating conditions.
7.3.2.5 External Temperature Sensor Support
The TS input is enabled with an internal 18-kΩ(Typ.) linearization pull-up resistor to support the use of a 10-kΩ
(25°C) NTC external thermistor, such as the Semitec 103AT-2. The NTC thermistor should be connected
between VSS and the individual TS pin. The analog measurement is then taken by the ADC through its input
multiplexer. If a different thermistor type is required, then changes to configurations may be required.
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REG18
TS
ADC
NTC
图7-1. External Thermistor Biasing
7.3.3 Power Supply Control
The BQ27Z746 device uses the VDD pin as its power source. VDD powers the internal voltage sources that
supply references for the device. The BAT pin is a non-current carrying path and used as a Kelvin sense
connection to the battery cell.
7.3.4 Bus Communication Interface
The BQ27Z746 device has an I2C bus communication interface. Alternatively, the device can be configured to
communicate through the HDQ pin (shared with SDA).
备注
Once the device is switched to the HDQ protocol, it is not reversible.
7.3.5 Low Frequency Oscillator
The BQ27Z746 device includes a low frequency oscillator (LFO) running at 65.536 kHz.
7.3.6 High Frequency Oscillator
The BQ27Z746 includes a high frequency oscillator (HFO) running at 16.78 MHz. It is frequency locked to the
LFO output and scaled down to 8.388 MHz with a 50% duty cycle.
7.3.7 1.8-V Low Dropout Regulator
The BQ27Z746 device contains an integrated capacitor-less 1.8-V LDO (REG18) that provides regulated supply
voltage for the device CPU and internal digital logic.
7.3.8 Internal Voltage References
The BQ27Z746 device provides two internal voltage references. REF1 is used by REG18, oscillators, and CC.
REF2 is used by the ADC.
7.3.9 Overcurrent in Discharge Protection
The overcurrent in discharge (OCD) function detects abnormally high current in the discharge direction. The
overload in discharge threshold and delay time are configurable through the firmware register. The thresholds
and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider tolerance
through calibration. When an OCD event occurs, the Safety Status flag is set to 1 and is latched until it is
cleared and the fault condition his removed.
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7.3.10 Overcurrent in Charge Protection
The short-circuit current in charge (OCC) function detects catastrophic current conditions in the charge direction.
The short-circuit in charge threshold and delay time are configurable through the firmware register. The
thresholds and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider
tolerance through calibration. The detection circuit also incorporates a blanking delay before disabling the CHG
and DSG FETs. When an OCC event occurs, the Safety Status flag bit is set to 1 and is latched until it is
cleared and the fault condition is removed.
7.3.11 Short-Circuit Current in Discharge Protection
The short-circuit current in discharge (SCD) function detects catastrophic current conditions in the discharge
direction. The short-circuit in discharge thresholds and delay times are configurable through the firmware
register. The thresholds and timing can be fine-tuned even further based on a sense resistor with lower
resistance or wider tolerance with calibration. The detection circuit also incorporates a delay before disabling the
CHG and DSG FETs. When an SCD event occurs, the Safety Status flag bit is set to 1 and is latched until it is
cleared and the fault condition is removed.
7.3.12 Primary Protection Features
The BQ27Z746 gas gauge supports the following battery and system level protection features, which can be
configured using firmware:
• Cell Undervoltage Protection
• Cell Overvoltage Protection
• Overcurrent in CHARGE Mode
• Overcurrent in DISCHARGE Mode
• Overload in DISCHARGE Mode
• Short Circuit in DISCHARGE Mode
• Overtemperature in CHARGE Mode
• Overtemperature in DISCHARGE Mode
• Precharge Timeout
• Fast Charge Timeout
7.3.13 Battery Sensing
The BQ27Z746 offers direct battery sensing through differential battery sensing pins BAT_SP and BAT_SN for
accurate battery voltage measurement and detection. BQ27Z746 battery sensing path includes protection and
isolation to minimize any leakage and coupling issue. The cell isolation includes a combination of buffered and
resistive options. Firmware configuration allows seamless auto-transition between the two sensing schemes.
The battery sensing buffer is powered from the PACK pin.
For accurate battery voltage sensing when using the sensing buffer, the PACK pin must be powered and VPACK
> VBAT + 0.7 V. The sensing protection thresholds (BCP, BCN, BDP, and BDN) provide short detection for the
battery sensing output pins, and places the battery sensing output pins in a high impedance state when
triggered. The BQ27Z746 battery sensing has firmware programmable offset options for applications where
differential output voltage needs to be shifted to overcome an input range limitation. The offset voltage selected
should never exceed the sensing protection thresholds, because this causes false battery sensing faults.
7.3.14 Gas Gauging
This device uses the Impedance Track™ technology to measure and determine the available charge in battery
cells. See the Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm Application
Report for further details.
7.3.15 Zero Volt Charging (ZVCHG)
ZVCHG (0-V charging) is a special function that allows charging a severely depleted battery that is below the
FET driver charge pump shutdown voltage (VFET_SHUT). The BQ27Z746 has ZVCHG enabled. If VBAT > V0INH
and VBAT < VFET_SHUT and the charger voltage at PACK+ is > V0CHGR, then the CHG output will be driven to the
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voltage of the PACK pin, allowing charging. ZVCHG mode in the BQ27Z746 is exited when VBAT
>
VFET_SHUT_REL, at which point the charge pump is enabled, and CHG transitions to being driven by the charge
pump. For BQ27Z746, when the voltage on VDD is below V0INH, the CHG output becomes high impedance, and
any leakage current flowing through the CHG FET may cause this voltage to rise and reenable charging. If this is
undesired, a high impedance resistor can be included between the CHG FET gate and source to overcome any
leakage and ensure the FET remains disabled in this case. This resistance should be as high as possible while
still ensuring the FET is disabled, since it will increase the device operating current when the CHG driver is
enabled. Because gate leakage is typically extremely low, a gate-source resistance of 50 MΩto 100 MΩmay
be sufficient to overcome the leakage.
7.3.16 Charge Control Features
This device supports charge control features, such as:
• Reports charging voltage and charging current based on the active temperature range—JEITA temperature
ranges T1, T2, T3, T4, T5, and T6
• Provides more complex charging profiles, including sub-ranges within a standard temperature range
• Reports the appropriate charging current required for constant current charging, and the appropriate charging
voltage needed for constant voltage charging to a smart charger, using the bus communication interface
• Selects the chemical state-of-charge of each battery cell using the Impedance Track method
• Provides pre-charging/zero-volt charging
• Employs charge inhibit and charge suspend if battery pack temperature is out of programmed range
• Activates charge and discharge alarms to report charging faults and to indicate charge status
7.3.17 Authentication
This device supports security with the following features, which can be enabled if desired:
• Authentication by the host using the SHA-256 method
• The gas gauge requires SHA-256 authentication before the device can be unsealed or allow full access.
7.4 Device Functional Modes
This device supports five modes, but the current consumption varies, based on firmware control of certain
functions and modes of operation:
• NORMAL mode: In this mode, the device performs measurements, calculations, protections, and data
updates every 250-ms intervals. Between these intervals, the device operates in a reduced power state to
minimize total average current consumption. Battery protections are continuously monitored and both
protection NFETs are typically on.
• SLEEP mode: In this mode, the device performs measurements, calculations, and data updates in adjustable
time intervals. Between these intervals, the device operates in a reduced power stage to minimize total
average current consumption. Battery protections are continuously monitored and both protection NFETs are
typically on.
• SHIP mode: In this mode, the device measures voltage and temperature very infrequently and at shorter
ADC conversion times, and current is not measured or coulomb counted. Current is assumed to be, and
reported as, 0 mA. Therefore, the device tracks the battery's state-of-charge from OCVs. The measurements
performed each interval are cell voltage, temperature, and PACK voltage (every fourth interval). Processing is
minimized by reducing the number of calculations. Some calculations are performed less frequently: only
after voltage and temperature are measured. These less frequent calculations include updating firmware-
based protections, lifetime data, and the voltage and temperature ranges of the advanced charge algorithm.
Other calculations, such as updating RemainingCapacity() and FullChargeCapacity(), are not performed at all
with the assumption the system is off and will not communicate with the gauge. Battery protections are
continuously monitored and both protection NFETs remain on, typically.
• SHELF mode: In this mode, power consumption is reduced even further from SHIP mode by turning off the
CHG and DSG NFETs and all hardware-based protections. Due to this, no external power is available to the
system in SHELF mode. The device measures voltage and temperature very infrequently and at shorter ADC
conversion times, and current is not measured or coulomb counted. Current is assumed to be, and reported
as, 0 mA. Therefore, the device tracks the battery's state-of-charge from voltage measurements. The
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measurements performed each interval are cell voltage, temperature and PACK voltage (every fourth
interval). Processing is minimized by reducing the number of calculations. Some calculations are performed
less frequently: only after voltage and temperature are measured. These less frequent calculations include
updating firmware-based protections, lifetime data, and the voltage and temperature ranges of the advanced
charge algorithm. Other calculations, such as updating RemainingCapacity() and FullChargeCapacity(), are
not performed at all with the assumption the system is off and will not communicate with the gauge.
• SHUTDOWN mode: In this mode, the device is completely disabled to minimize power consumption and to
avoid depleting the battery.
7.4.1 Lifetime Logging Features
The device supports data logging of several key parameters for warranty and analysis:
• Maximum and minimum cell temperature
• Maximum current in CHARGE or DISCHARGE mode
• Maximum and minimum cell voltages
• Safety events and number of occurrences
7.4.2 Configuration
The device supports accurate data measurements and data logging of several key parameters.
7.4.2.1 Coulomb Counting
The device uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement. The ADC
measures charge/discharge flow of the battery by measuring the voltage across a very small external sense
resistor. The integrating ADC measures a bipolar signal from a range of –100 mV to 100 mV, with a positive
value when V(SRP) –V(SRN), indicating charge current and a negative value indicating discharge current.
The current measurement is performed by measuring the voltage drop across the external sense resistor, which
can be as low as 1 mΩ, and the polarity of the differential voltage determines if the cell is in the CHARGE or
DISCHARGE mode.
7.4.2.2 Cell Voltage Measurements
The BQ27Z746 gas gauge measures the cell voltage at 1-s intervals using the ADC. This measured value is
internally scaled for the ADC and is calibrated to reduce any errors due to offsets. This data is also used for
calculating the impedance of the cell for Impedance Track gas gauging.
7.4.2.3 Auto Calibration
The auto-calibration feature helps to cancel any voltage offset across the SRP and SRN pins for accurate
measurement of the cell voltage, charge/discharge current, and thermistor temperature. The auto-calibration is
performed when there is no communication activity for a minimum of 5 s on the bus lines.
7.4.2.4 Temperature Measurements
This device has an internal sensor for on-die temperature measurements, and the ability to support an external
temperature measurement through the external NTC on the TS pin. These two measurements are individually
enabled and configured.
8 Applications and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
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8.1 Application Information
The BQ27Z476 can be used with a 1-series Li-ion/Li polymer battery pack. To implement and design a
comprehensive set of parameters for a specific battery pack, the user needs Battery Management Studio
(BQStudio), which is a graphical user-interface tool installed on a PC during development. The firmware installed
in the product has default values, which are summarized in the associated BQ27Z476 Technical Reference
Manual (SLUUCA6). Using the BQStudio tool, these default values can be changed to cater to specific
application requirements during development once the system parameters, such as enable or disable certain
features for operation, cell configuration, chemistry that best matches the cell used, and more. The final flash
image, which is extracted once configuration and testing are complete, is used for mass production and is
referred to as the "golden image."
8.2 Typical Applications
The following is an example BQ27Z476 application schematic for a single-cell battery pack.
C7
F
C6
0.1
1
0.1
F
= Recommended for IEC ESD
1
PACKP
C5
0.1
R7
10 M
F
F
1
C4
0.1
R6
5 k
DSG
R1
10
CHG
1
PACKN
VDD
C1
1.0 uF
PACK
BQ27Z746
1
BAT_SP
BAT_SN
BAT_SP
BAT_SN
BAT
TS
CELLP
R2
1
1 K
Li-Ion
Cell
C2
GPO/TS1
ENAB
0.01
RT1
103AT
F
CELLN
VSS
SRP
R9
100
SCL
SCL
SDA
R4
100
R3
2 m
SDA/HDQ
C3
F
R8
100
0.1
SRN
R5
100
PACKN
图8-1. BQ27Z746 1-Series Cell Low Side Current Sensing Typical Implementation
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C7
F
C6
0.1
1
0.1
F
= Recommended for IEC ESD
1
PACKP
C5
R7
10 M
0.1
F
F
1
C4
0.1
R6
5 k
DSG
R1
10
CHG
1
PACKN
VDD
C1
1.0 uF
PACK
R3
2 m
BQ27Z746
1
BAT_SP
BAT_SN
BAT_SP
BAT_SN
BAT
TS
CELLP
R2
1
1 K
Li-Ion
Cell
C2
GPO/TS1
ENAB
0.01
F
CELLN
RT1
103AT
VSS
SRP
R9
R4
100
100
SCL
SCL
SDA
C3
F
SDA/HDQ
0.1
R8
100
SRN
R5
100
PACKN
图8-2. BQ27Z746 1-Series Cell High Side Current Sensing Typical Implementation
8.2.1 Design Requirements (Default)
Design Parameter
Example
1s1p (1 series with 1 parallel)
5300 mAh
Cell Configuration
Design Capacity
Device Chemistry
Design Voltage
Li-Ion
4000 mV
Cell Low Voltage
2500 mV
8.2.2 Detailed Design Procedure
8.2.2.1 Changing Design Parameters
For the firmware settings needed for the design requirements, refer to the BQ27Z746 Technical Reference
Manual (SLUUCA6).
• To change design capacity, set the data flash value (in mAh) in the Gas Gauging: Design: Design Capacity
register.
• To set device chemistry, go to the data flash I2C Configuration: Data: Device Chemistry. The BQStudio
software automatically populates the correct chemistry identification. This selection is derived from using the
BQCHEM feature in the tools and choosing the option that matches the device chemistry from the list.
• To set the design voltage, go to Gas Gauging: Design: Design Voltage register.
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• To set the cell Low Voltage or clear the cell Low Voltage, use Settings: Configuration: Init Voltage Low
Set or Clear. This is used to set the cell voltage level that will set (clear) the [VOLT_LO] bit in the Interrupt
Status register.
• To enable the internal temperature and the external temperature sensors: Set Settings:Configuration:
Temperature Enable: Bit 0 (TSInt) = 1 for the internal sensor; set Bit 1 (TS1) = 1 for the external sensor.
8.2.3 Calibration Process
The calibration of current, voltage, and temperature readings is accessible by writing 0xF081 or 0xF082 to
ManufacturerAccess(). A detailed procedure is included in the BQ27Z746 Technical Reference Manual
(SLUUCA6) in the Calibration section. The description allows for calibration of cell voltage measurement offset,
battery voltage, current calibration, coulomb counter offset, PCB offset, CC gain/capacity gain, and temperature
measurement for both internal and external sensors.
8.2.4 Gauging Data Updates
When a battery pack enabled with the BQ27Z746 gas gauge is cycled, the value of FullChargeCapacity()
updates several times, including the onset of charge or discharge, charge termination, temperature delta,
resistance updates during discharge, and relaxation. 图 8-3 shows actual battery voltage, load current, and
FullChargeCapacity() when some of those updates occur during a single application cycle.
Update points from the plot include:
• Charge termination at 7900 s
• Relaxation at 9900 s
• Resistance update at 11500 s
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8.2.4.1 Application Curve
图8-3. Full Charge Capacity Tracking (X-Axis Is Seconds)
9 Power Supply Requirements
The BQ27Z746 device uses the VDD pin as its power source. VDD pin powers the internal voltage sources that
supply references for the device. The VDD pin connects to 1-series battery cells' positive terminal and supports
a minimum of 2 V to a maximum of 5 V. The BAT pin is a noncurrent carrying path and is used as a battery
voltage Kelvin sense connection to the 1-series battery cells' positive terminal.
10 Layout
10.1 Layout Guidelines
• The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a
temperature coefficient no greater than 50 ppm to minimize current measurement drift with temperature.
Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit ranges of
the BQ27Z746 gas gauge. Select the smallest value possible to minimize thermal dissipation and still
maintain required measurement accuracy. The value of the sense resistor impacts the differential voltage
generated across the BQ27Z746 SRP and SRN nodes during a short circuit. These pins have a differential
voltage should not exceed VCC_IN of ± 0.1 V for normal operation. Parallel sense resistors can be used as
long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩto 20-mΩsense resistor.
• BAT should be tied directly to the positive connection of the battery with a series 1-kΩresistor. It should not
share a path with the VDD pin and its 10-Ωseries resistor.
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• In reference to the gas gauge circuit, the following features require attention for component placement and
layout: VDD bypass capacitor, SRN and SRP differential low-pass filter, and I2C communication ESD external
protection.
• The BQ27Z746 gas gauge uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω
resistor from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-μF filter capacitor
across the SRP and SRN inputs. Place all filter components as close as possible to the device. Route the
traces from the sense resistor as differential pairs to the filter circuit. Adding a ground plane around the filter
network can provide additional noise immunity.
• The BQ27Z746 has an internal LDO that is internally compensated and does not require an external
decoupling capacitor.
• The I2C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener
diode and series resistor provides more robust ESD performance. The I2C clock and data lines have an
internal pulldown. When the gas gauge senses that both lines are low (such as during removal of the pack),
the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.
10.2 Layout Example
RPACK
RDSG
RSRN
RSNS
CSNS
S1
RSRP
DSG G1
CHG G2
CTS
Common
Drain
NFET
Pair
S2
CVDD
RBAT
RVDD
NTC
Weld
Tab
Weld
Tab
CELL+
CELL-
Battery
图10-1. BQ27Z746 Key Trace Board Layout
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11 Device and Documentation Support
11.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 Documentation Support
11.2.1 Related Documentation
• BQ27Z746 Technical Reference Manual
• Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm Application Report
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
Impedance Track™, NanoFree™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Orderable, and Packaging Information
The following pages include mechanical, orderable, and packaging information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ27Z746YAHR
ACTIVE
DSBGA
YAH
15
3000 RoHS & Green
SAC396
Level-1-260C-UNLIM
-40 to 85
BQ27Z746
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ27Z746YAHR
DSBGA
YAH
15
3000
180.0
12.4
1.88
2.76
0.55
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YAH 15
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
BQ27Z746YAHR
3000
Pack Materials-Page 2
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