BQ29209-Q1 [TI]
具有自动电池均衡功能的汽车电压保护，用于 2 节锂离子电池，OVP=4.30V;
| 型号： | BQ29209-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有自动电池均衡功能的汽车电压保护，用于 2 节锂离子电池，OVP=4.30V 电池 |
| 文件： | 总24页 (文件大小：1506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ29209-Q1
ZHCSDT4D –JUNE 2015 –REVISED SEPTEMBER 2020
适用于2 节串联锂离子电池且具有自动电池平衡功能的BQ29209-Q1
电压保护
1 特性
3 说明
• 2 节串联电池二级保护
BQ29209-Q1 器件是一款用于 2 节串联锂离子电池组
的二级过压保护 IC，具有高精度精密过压检测电路和
自动电量失衡校正功能。
• 带外部使能控制的自动电量失衡校正
– ±30mV 使能阈值，0mV 禁用阈值（典型值）
• 外部电容控制的延迟计时器
该 IC 将 2 节串联电池组中每节电池的电压与出厂设定
的内部参考电压进行比较。如果任一电池达到过压状
态，OUT 引脚由低电平转换为高电平状态。
• 外部电阻控制的电量平衡电流
• 低功耗ICC < 3µA（典型值）（VCELL（总电压）<
VPROTECT
）
BQ29209-Q1 可执行基于电压的自动电量失衡校正。
当电池电压与内部参考电压相差 30mV 或以上时，启
动电量平衡；当电池电压与内部参考电压相差 0mV
时，停止电量平衡。电量平衡功能由CB_EN 引脚启用
和禁用。
• 内部电量平衡功能可处理
高达15mA 的电流
• 支持外部电量平衡模式
• 高精度过压保护：
– ±25mV（TA = 0°C 至60°C）
• 固定过压保护阈值：
器件信息
4.30V
器件型号(1)
BQ29209-Q1
封装尺寸（标称值）
封装
• 小型8 引脚DRB 封装
• 提供功能安全型
VSON (8)
3.00mm × 3.00mm
– 可帮助进行功能安全系统设计的文档
• 符合汽车类AEC Q100 2 级标准
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
PACK+
2 应用
RIN2
• 锂离子电池组二级保护
RVD
VC2
VC1
OUT
VDD
1
2
3
8
7
6
5
CELL2
CELL1
CIN
CIN
– 紧急呼叫(eCall)
– 笔记本电脑
– 电动工具
– 便携式设备和仪器
– 备用电池系统
RIN1
VC1_CB CB_EN
4 CD
GND
PWR PAD
CVD
RCBext
CCD
PACK-
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSC62
BQ29209-Q1
ZHCSDT4D –JUNE 2015 –REVISED SEPTEMBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Applications.................................................. 12
9.3 System Example.......................................................13
10 Power Supply Recommendations..............................14
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 接收文档更新通知................................................... 15
12.3 支持资源..................................................................15
12.4 Trademarks.............................................................15
12.5 静电放电警告.......................................................... 15
12.6 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
7 Specifications.................................................................. 3
7.1 Absolute Maximum Ratings........................................ 3
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................4
7.6 Recommended Cell Balancing Configurations........... 6
7.7 Typical Characteristics................................................6
8 Detailed Description........................................................7
8.1 Overview.....................................................................7
8.2 Functional Block Diagram...........................................7
8.3 Feature Description.....................................................7
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2018) to Revision D (September 2020)
Page
• 添加了“提供功能安全型”信息......................................................................................................................... 1
Changes from Revision B (November 2018) to Revision C (December 2018)
Page
• Added a clarification regarding operation if GND is not connected first in sequence.........................................8
Changes from Revision A (March 2016) to Revision B (November 2018)
Page
• 更改了简化版原理图中的元件名称....................................................................................................................1
• Changed a component name in Recommended Operating Conditions ............................................................ 4
• Added the value of internal cell balancing switch resistances to Electrical Characteristics ...............................4
• Changed resistor names ....................................................................................................................................6
• Added 图8-2 to clarify the cell balancing description; updated the equations .................................................. 9
• Changed values and component names in 图9-1 ...........................................................................................12
• Changed component names and values used in the design example ............................................................ 12
• Changed external cell balancing figure, equations, and description.................................................................13
Changes from Revision * (June 2015) to Revision A (March 2016)
Page
• 更改了电阻器RVD 位置，在简化版原理图中添加了PACK+ 和PACK–........................................................... 1
• Deleted the Lead Temperature (soldering) from the 节7.1 table .......................................................................3
• Changed resistor RVD location in 图9-1 ..........................................................................................................12
• Added title to 表9-1 .........................................................................................................................................12
• Changed resistor RVD location, added PACK+ and PACK–in 图9-3 ............................................................ 13
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5 Device Options
TA
PART NUMBER
OVP
BQ29209-Q1
4.3 V
–40°C to +105°C
6 Pin Configuration and Functions
1
2
3
4
8
7
6
5
VC2
VC1
OUT
VDD
PWR PAD
VC1_CB
CD
CB_EN
GND
图6-1. DRB Package 8-Pin VSON Top View
Pin Functions
PIN
DESCRIPTION
NAME
CB_EN
CD
NO.
6
Cell balance enable
4
Connection to external capacitor for programmable delay time
GND
5
Ground pin
Output
OUT
8
Thermal Pad
VC1
PWR PAD GND pin to be connected to the PWRPAD on the printed circuit board for proper operation
2
3
1
7
Sense voltage input for bottom cell
Cell balance input for bottom cell
Sense voltage input for top cell
Power supply
VC1_CB
VC2
VDD
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage range, VMAX
16
V
V
V
V
V
VDD–GND
–0.3
–0.3
–0.3
–0.3
–0.3
16
VC2–GND, VC1–GND
Input voltage range, VIN
8
16
VC2–VC1, CD–GND
CB_EN–GND
Output voltage range, VOUT
16
OUT–GND
Continuous total power dissipation, PTOT
Storage temperature , Tstg
See 节7.4.
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
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7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (VC2, CD,
OUT, and GND)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
4
NOM
MAX UNIT
Supply voltage, VDD
10
5
V
V
Input voltage range
0
VC2–VC1, VC1–GND
CCD (See 图9-1.)
Delay time capacitance, td(CD)
Voltage monitor filter resistance
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
Cell balance resistance
0.1
1K
µF
100
RIN (See 图9-1.)
Ω
0.01
0.1
100
0.1
µF
CIN (See 图9-1.)
1K
RVD (See 图9-1.)
Ω
µF
CVD (See 图9-1.)
100
4.7K
105
RCBext (See 图9-1 and 节8.3.1.)
Ω
Operating ambient temperature range, TA
°C
–40
7.4 Thermal Information
BQ29209-Q1
DRB
THERMAL METRIC(1)
UNIT
8 PINS
50.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
25.1
19.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.7
ψJT
18.9
ψJB
RθJC(bot)
5.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 105°C
and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
Overvoltage detection
voltage
VPROTECT
VHYS
4.3
V
Overvoltage detection
hysteresis
200 300 400
mV
mV
Overvoltage detection
accuracy
VOA
TA = 25°C
10
–10
TA = 0°C to 60°C
0.4
0.6
–0.4
–0.6
Overvoltage threshold
temperature drift
VOA_DRIFT
mV°/C
TA = –40°C to 110°C
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Typical values stated where TA = 25°C and VDD = 7.2 V. Minimum and maximum values stated where TA = –40°C to 105°C
and VDD = 4 V to 10 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
TA = 0°C to 60°C
Note: Does not include external capacitor variation.
6
9
9
12
Overvoltage delay time
scale factor
XDELAY
s/µF
TA = –40°C to 110°C
Note: Does not include external capacitor variation.
5.5
13.5
Overvoltage delay time
scale factor in Customer
Test Mode
(1)
XDELAY_CTM
0.08
s/µF
Overvoltage detection
charging current
ICD(CHG)
ICD(DSG)
150
60
nA
µA
Overvoltage detection
discharging current
Overvoltage detection
external capacitor
comparator threshold
VCD
ICC
1.2
V
Supply current
3
6
µA
V
(VC2–VC1) = (VC1–GND) = 3.5 V (See 图8-5.)
(VC2–VC1) or (VC1–GND) > VPROTECT
,
6
8.25
9.5
VDD = 10 V, IOH = 0
(VC2–VC1) or (VC1–GND) = VPROTECT, VDD = VPROTECT
IOH = –100 µA, TA = 0°C to 60°C
,
1.75
2.5
0
V
VOUT
OUT pin drive voltage
(VC2–VC1) and (VC1–GND) < VPROTECT
,
200
mV
IOL = 100 µA, TA = 25°C
(VC2–VC1) and (VC1–GND) < VPROTECT
,
10
mV
mV
µA
IOL = 0 µA, TA = 25°C
VC2 = VC1 = VDD = 4 V, IOL = 100 µA
200
OUT = 1.75 V, (VC2–VC1) or (VC1–GND) = VPROTECT
VDD = VPROTECT to 10 V, TA = 0°C to 60°C
,
,
IOH
High-level output current
Low-level output current
–100
OUT = 0.05 V, (VC2–VC1) or (VC1–GND) < VPROTECT
IOL
30
85
–8
0.2
µA
mA
µA
µA
VDD = VPROTECT to 10 V, TA = 0°C to 60°C
High-level short-circuit
output current
OUT = 0 V, (VC2–VC1) = (VC1–GND) = VPROTECT
VDD = 4 to 10 V
IOH_ZV
Measured at VC1, (VC2–VC1) = (VC1–GND) = 3.5 V,
TA = 0°C to 60°C (See 图8-5.)
–0.2
IIN
Input current at VCx pins
Measured at VC2, (VC2–VC1) = (VC1–GND) = 3.5 V,
TA = 0°C to 60°C (See 图8-5.)
2.5
45
9
Cell mismatch detection
threshold for turning ON
(VC2–VC1) versus (VC1–GND) and vice-versa when cell
balancing is enabled. VC2 = VDD = 7.6 V
VMM_DET_ON
17
30
0
mV
mV
V
Cell mismatch detection
threshold for turning OFF
Delta between (VC2–VC1) and (VC1–GND) when cell
balancing is disabled. VC2 = VDD = 7.6 V
VMM_DET_OFF
VCB_EN_ON
VCB_EN_OFF
ICB_EN
–9
Cell balance enable ON
threshold
Active LOW pin at CB_EN
Active HIGH at CB_EN
CB_EN = GND (See 图8-6.)
CB_EN = GND
1
Cell balance enable OFF
threshold
2.2
V
Cell balance enable ON
input current
0.2
µA
Ω
Ω
Internal cell balance
switch resistance
RCB1int
300
235
Internal cell balance
switch resistance
RCB2int
CB_EN = GND
(1) Specified by design. Not 100% tested in production.
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7.6 Recommended Cell Balancing Configurations
Typical values stated where TA = 25°C and (VC2–VC1), (VC1–GND) = 3.8 V. Minimum and maximum values stated where
TA = –40°C to 105°C, VDD = 4 V to 10 V, and (VC2–VC1), (VC1–GND) = 3 V to 4.2 V. All values assume recommended
supply voltage filter resistance RVD of 100 Ωand 5% accurate or better cell balance resistor RCBext
.
MIN NOM MAX
UNIT
0.5 0.75
1
2
RCBext = 4700 Ω
RCBext = 2200 Ω
RCBext = 910 Ω
1
2
1.5
3
4
3
4.5
6
6
ICB
Cell balance input current
mA
RCBext = 560 Ω
RCBext = 360 Ω
RCBext = 240 Ω
RCBext = 120 Ω
3.5
4
8.5
11
15
7.5
10
5
7.7 Typical Characteristics
图7-1. ICD Charge Current
图7-2. ICD Discharge Current
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
-40
0
25
60
110
Operating Temperature (°C)
C002
图7-3. Average ICC During Normal Operation Across Operational Temperature
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8 Detailed Description
8.1 Overview
The BQ29209-Q1 provides overvoltage protection and cell balancing for 2-series cell lithium-ion battery packs.
8.1.1 Voltage Protection
Each cell voltage is continuously compared to a factory configured internal reference threshold. If either cell
reaches an overvoltage condition, the BQ29209-Q1 device starts a timer that provides a delay proportional to
the capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from a low to high
state.
8.1.2 Cell Balancing
If enabled, the BQ29209-Q1 performs automatic cell-balance correction where the two cells are automatically
corrected for voltage imbalance by loading the cell with the higher voltage with a small balancing current. When
the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied if the
imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the CB_EN pin
low, and disabled when CB_EN is pulled to greater than 2.2 V, for example, VDD.
If the internal cell balancing current of up to 15 mA is insufficient, the BQ29209-Q1 may be configured via
external circuitry to support much higher external cell balancing current.
8.2 Functional Block Diagram
VDD
5-V LDO
and POR
VC2
CTRL
+
–
Hys.
CB2_EN
CB1 _EN
CB
Logic
ICD =
150 nA
VC1
VC1_CB
+
–
OUT
GND
CB_EN
CD
0.1 µF
8.3 Feature Description
8.3.1 Protection (OUT) Timing
Sizing the external capacitor is based on the desired delay time as follows:
td
CCD
=
XDELAY
Where td is the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds
per microfarad. XDELAY is nominally 9 s/µF. For example, if a nominal delay of 3 seconds is desired, use a CCD
capacitor that is 3 s / 9 s/µF = 0.33 µF.
The delay time is calculated as follows:
td = CCD ´ XDELAY
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If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the
internal current source is disabled and an internal discharge block is employed to discharge the external
capacitor down to 0 V. In this instance, the OUT pin remains in a low state.
8.3.2 Cell Voltage > VPROTECT
When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay
begins to count to td. If the input remains above VPROTECT for the duration of td, the BQ29209-Q1 output changes
from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V
when IOH = 0 mA.
The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V
typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.
VPROTECT
-
VPROTECT VHYS
Cell Voltage
VC2 1,
VC1 GND
VC
t
d
L
H
OUT
图8-1. Timing for Overvoltage Sensing
8.3.3 Cell Connection Sequence
Note
Before connecting the cells, populate the overvoltage delay timing capacitor, CCD
.
The recommended cell connection sequence begins from the bottom of the stack, as follows:
1. GND
2. VC1
3. VC2
While not advised, connecting the cells in a sequence other than that described above does not result in errant
activity on the OUT pin. For example:
1. GND
2. VC2 or VC1
3. Remaining VCx pin
Note
Using any cell connection sequence that does not connect GND first may result in increased leakage
current drawn by the VDD pin.
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8.3.4 Cell Balance Enable Control
To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance
Enable Control pin at lower state-of-charge (SOC) levels.
8.3.5 Cell Balance Configuration
The following cell balancing details relate to 图8-2.
PACK+
RIN2
RVDD
VC2
OUT
VDD
1
2
3
4
8
7
6
5
+
CIN2
CIN1
RCB2int
VCELL2
-
VC1
RIN1
VC1_CB
CB_EN
RCB1int
GND
CD
CVDD
+
RCBext
VCELL1
PWR PAD
-
CCD
PACK-
图8-2. Simplified Schematic for Cell Balancing Description
The cell balancing current may be calculated as follows:
For Cell 1 balancing current, ICB1
:
VCELL1
ICB1
=
RCBext + RCB1int
(1)
For Cell 2 balancing current, ICB2
:
VCELL2
ICB2
=
RCBext + RCB2int + RVDD
(2)
Where:
RCBext = resistor connected between the top of Cell 1 and the VC1_CB pin
RIN1 = resistor connected between the top of Cell 1 and the VC1 pin
RIN2 = resistor connected between the top of Cell 2 and the VC2 pin
RVDD = resistor connected between the top of Cell 2 and the VDD pin
8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage)
The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The
recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3 V and 4.2
V. Below VDD = 6 V, it is recommended to pull CB_EN high to disable the cell balancing function.
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111%
100%
79%
VC2
8.4 V
7.6 V
6 V
图8-3. VMM_DET_ON and VMM_DET_OFF Threshold
8.3.7 Customer Test Mode
Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker
customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such,
individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate
overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use.
To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device
switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of
approximately 0.08, thereby reducing the delay time during an overvoltage condition.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also,
avoid exceeding absolute maximum voltages for the individual cell voltages (VC1–GND) and
(VC2–VC1). Stressing the pins beyond the rated limits may cause permanent damage to the
device.
To exit CTM, power off the device and then power it back on.
15 V
VDD
Test Mode Entered
VC2
> 10 ms
4.5 V
V
PROTECT
(VC2–VC1)
or
(VC1–GND)
V
V
PROTECT – HYST
4 V
<<t
OUT
d
图8-4. Voltage Test Limits
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8.3.8 Test Conditions
IIN
VC2
OUT
8
1
IIN
2 VC1
VDD 7
______
CB_EN
Icc
3
6
VC1_CB
4 CD
GND 5
图8-5. ICC, IIN Measurement
VCELL
VC2
OUT
VDD
1
2
3
8
VC1
7
6
5
ICB
______
CB_EN
ICB
VC1_CB
ICB_EN
VCELL VCB
4 CD
GND
图8-6. ICB Measurement
8.4 Device Functional Modes
This device monitors the voltage of the cells connected to the VCx pins and depending on these voltages and
the overall battery voltage at VDD the device enters different operating modes.
8.4.1 NORMAL Mode
The device is operating in NORMAL mode when the cell voltage range is between the over-charge detection
threshold (VPROTECT) and the minimum supply voltage.
If this condition is satisfied, the device turns OFF the OUT pin.
8.4.2 PROTECTION Mode
The device is operating in PROTECTION mode when the cell over voltage protection feature has been triggered.
See 节8.3.2 for more details on this feature.
If this condition is satisfied, the device turns ON the OUT pin.
9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The BQ29209-Q1 is designed to be used in 2-series Li-Ion battery packs and with the option to include voltage-
based cell balancing. The number of parallel cells or the overall capacity of the battery only affects the cell
balancing circuit due to the level of potential imbalance that needs to be corrected.
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9.2 Typical Applications
9.2.1 Battery Connection
图9-1 shows the configuration for the 2-series cell battery connection with cell balancing enabled.
FUSE
PACK+
100Ω
260 Ω
1 kΩ
Si1406
1
2
3
4
VC2
OUT
VDD
8
7
6
5
CELL2
CELL1
0.1 μF
0.1 μF
VC1
260Ω
440Ω
VC1_CB
CB_ EN
GND
CD
0.1 μF
PWR PAD
PACK–
0.33 μF
图9-1. 2-Series Cell Configuration
9.2.1.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE at TA = 25°C
Input voltage range
4 V to 10 V
4.3 V
Overvoltage Protection (OVT)
Overvoltage detection delay time
Overvoltage detection delay timer capacitor
Cell Balancing Enabled
3 s
0.33 µF
Yes
Cell Balancing Current, ICB1 and ICB2
Cell Balancing Resistors, RCBext, RIN1, RIN2 and RVD
5 mA (targeted at a nominal cell voltage of 3.8 V)
RCBext = 440 Ω, RIN1 = 260 Ω, RIN2 = 260 Ω, RVD = 100 Ω
9.2.1.2 Detailed Design Procedure
The BQ29209-Q1 has limited features but there are some key calculations to be made when selecting external
component values.
• Calculate the required CCD capacitor value for the voltage protection delay time. Care should be taken to
evaluate the tolerances of the capacitor and the BQ29209-Q1 to ensure system specifications are met.
• Calculate the cell balancing resistor values to provide a suitable level of balancing current that will, at a
minimum, counter act an increase in imbalance during normal operation of the battery. Care should be taken
to ensure any connectivity resistance is also considered as this will also reduce the balancing current level.
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9.2.1.3 Application Curve
2
1
0
œ1
œ2
œ3
œ4
œ5
œ6
VC1 V(PROTECT)
VC2 V(PROTECT)
-40
0
25
60
110
Operating Temperature (°C)
C001
图9-2. Average VPROTECT Accuracy (VOA) Across Operation Temperature
9.3 System Example
9.3.1 External Cell Balancing
Higher cell balancing currents can be supported by means of a simple external network, as shown in 图9-3.
PACK+
RVD
1
2
8
OUT
VC2
RIN2
RIN1
CIN
CIN
VCELL2
VC1
VDD 7
CB_ EN 6
GND 5
3
VC1_CB
CD
VCELL1
RCBext
Q1
Q2
4
PWR PAD
RCLAMP
CVD
CCD
PACK–
图9-3. External Cell Balancing Configuration
The VC1_CB pin is tri-stated when cell balancing is disabled, is driven low by the internal logic to enable
balancing on CELL1, and is driven high by the internal logic to enable balancing on CELL2. RCLAMP ensures that
both Q1 and Q2 remain off when balancing is disabled, and should be sized above 2 kΩ to prevent excessive
internal device current when the balancing network is activated. If RCLAMP is too small, then the gate-source
voltage required to enable the external FETs cannot be achieved. RCBext determines the value of the balancing
current, and is dependent on the voltage of the balanced cell and the specific Q1 and Q2 transistors used in the
design (due to the transistors operating in saturation mode during balancing). The balancing currents (assuming
the current through RCLAMP is not significant) are given as follows:
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( VCELL1 - VSG_Q2
)
ICB1
=
=
RCBext
(3)
( VCELL2 - VGS_Q1
RCBext
)
ICB2
(4)
10 Power Supply Recommendations
The recommended power supply for this device is a maximum 10-V operation on the VDD input pin.
11 Layout
11.1 Layout Guidelines
The following are the recommended layout guidelines:
1. Ensure the input filters to the VC1 and VC2 pins are as close to the IC as possible to improve noise
immunity.
2. If the OUT pin is used to control a high current path, for example: to blow a chemical fuse, then care should
be taken to ensure the high current path creates minimal interference of the BQ29209-Q1 voltage sense
inputs.
3. The input RC filter on the VDD pin should be close to the terminal of the IC.
11.2 Layout Example
Additional circuitry required based on usage of the OUT pin
1
Via connects between two layers
8
VC2
VC1
OUT
VDD
1
2
1
PWRPAD
PACK +
PACK -
7
CB_EN
GND
6
5
3
4
VC1_CB
CD
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12 Device and Documentation Support
12.1 Documentation Support
For additional information, see the following related document:
• BQ29209-Q1 Functional Safety FIT Rate, FMD, and Pin FMA Application Report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ29209TDRBRQ1
BQ29209TDRBTQ1
ACTIVE
ACTIVE
SON
SON
DRB
DRB
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
209Q1
209Q1
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ29209TDRBRQ1
BQ29209TDRBTQ1
SON
SON
DRB
DRB
8
8
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ29209TDRBRQ1
BQ29209TDRBTQ1
SON
SON
DRB
DRB
8
8
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
BQ29312A
TWO-CELL, THREE-CELL, AND FOUR-CELL LITHIUM-ION OR LITHIUM-POLYMER BATTERY PROTECTION AFE
TI
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