BQ294506DRVT [TI]
BQ2945xy Overvoltage Protection For 2-Series and 3-Series Cell Li-Ion Batteries;
| 型号： | BQ294506DRVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BQ2945xy Overvoltage Protection For 2-Series and 3-Series Cell Li-Ion Batteries |
| 文件： | 总24页 (文件大小：2130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
SLUSAJ3I – SEPTEMBER 2011 – REVISED MAY 2021
BQ2945xy Overvoltage Protection For 2-Series and 3-Series Cell Li-Ion Batteries
1 Features
3 Description
•
2-series and 3-series cell overvoltage monitor for
secondary protection
Fixed programmable delay timer
Fixed OVP threshold
– Available range from 3.85 V to 4.6 V
Fixed OVP delay option: 4 s or 6.5 s
High-accuracy overvoltage protection:
±10 mV
The BQ2945xy family of products is a secondary-level
voltage monitor and protector for Li-ion battery pack
systems. Each cell is monitored independently for
an overvoltage condition. Based on the configuration,
an output is triggered after a fixed delay if any of
the two or three cells has an overvoltage condition.
This output is triggered into a high state after an
overvoltage condition satisfies the specified delay
timer.
•
•
•
•
•
Low power consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT
Low leakage current per cell input < 100 nA
Small package footprint
)
Device Information
•
•
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
BQ2945xy
SON (6)
2.00 mm × 2.00 mm
– 6-pin SON
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Second-Level Protection in Li-Ion Battery Packs in:
– Tablets
– Slates
– Power Tools
– Notebook Computers
– Portable Equipment and Instrumentation
Pack +
R
VD
RIN
V3
OUT
VDD
V1
C
IN
VCELL3
VCELL2
VCELL1
R
IN
V2
C
IN
R
IN
CVD
VSS
PWRPAD
C
IN
Pack–
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
SLUSAJ3I – SEPTEMBER 2011 – REVISED MAY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Layout.............................................................................13
9.1 Layout Guidelines..................................................... 13
9.2 Layout Example........................................................ 13
10 Device and Documentation Support..........................14
10.1 Device Support....................................................... 14
10.2 Receiving Notification of Documentation Updates..14
10.3 Support Resources................................................. 14
10.4 Trademarks.............................................................14
10.5 Electrostatic Discharge Caution..............................14
10.6 Glossary..................................................................14
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (December 2017) to Revision I (May 2021)
Page
•
Changed the BQ294506 device to Production Data...........................................................................................3
Changes from Revision G (November 2017) to Revision H (December 2017)
Page
•
•
Added the BQ294506 device..............................................................................................................................3
Added the BQ294506 device to the Electrical Characteristics .......................................................................... 6
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BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
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5 Device Comparison Table
TA
PART NUMBER
OVP (V)
DELAY TIME (s)
BQ294502
BQ294504
BQ294506
BQ294512
BQ294522
BQ294524
BQ294532
BQ294533
BQ294582
BQ294592
4.35
4.35
4.38
4.4
4
6.5
4
4
4.45
4.45
4.5
4
–40°C to +110°C
6.5
4
4.5
6.5
4
4.225
4.3
4
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BQ294533 BQ294582 BQ294592
BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
SLUSAJ3I – SEPTEMBER 2011 – REVISED MAY 2021
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6 Pin Configuration and Functions
V3
1
2
3
6
5
4
OUT
VDD
V1
Thermal
Pad
V2
VSS
Not to scale
Figure 6-1. DRV Package 6-Pin SON Top View
Table 6-1. Pin Functions
NUMBER
NAME
V3
I/O(1)
IA
DESCRIPTION
1
2
3
4
5
6
Sense input for positive voltage of the third cell from the bottom of the stack.
Sense input for positive voltage of the second cell from the bottom of the stack.
V2
IA
VSS
V1
P
Electrically connected to IC ground and negative terminal of the lowest cell in the stack.
Sense input for positive voltage of the lowest cell in the stack.
Power supply
IA
VDD
OUT
P
OA1
Output drive for external N-channel FET.
VSS pin to be connected to the PWRPAD on the printed-circuit-board (PCB) for proper
operation.
—
PWRPAD
—
(1) IA = Input Analog, OA = Output Analog, P = Power Connection
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BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
30
30
8
UNIT
Supply voltage
Input voltage
VDD–VSS
V
V
V
V
V1–VSS or V2–VSS or V3–VSS+
V3–V2 or V2–V1
OUT–VSS
Output voltage
30
Continuous total power dissipation, PTOT
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
See Section 7.4
300
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) See Figure 8-3.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
25
UNIT
V
(1)
Supply voltage, VDD
Input voltage
3
0
V3–V2 or V2–V1 or V1–VSS
5
V
Operating ambient temperature, TA
–40
110
°C
(1) See Section 9.2.
7.4 Thermal Information
BQ2945xy
DRV (SON)
6 PINS
186.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
90.4
110.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
96.7
ψJB
90
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 10.8 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD
3 V to 15 V (unless otherwise noted).
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE PROTECTION THRESHOLD VCx
BQ294502, fixed delay 4 s
4.35
4.35
4.38
4.4
BQ294504, fixed delay 6.5 s
BQ294506, fixed delay 4 s
BQ294512, fixed delay 4 s
BQ294522, fixed delay 4 s
BQ294524, fixed delay 6.5 s
BQ294532, fixed delay 4 s
BQ294533, fixed delay 6.5 s
BQ294582, fixed delay 4 s
BQ294592, fixed delay 4 s
4.45
4.45
4.5
V(PROTECT)
Overvoltage Detection
–
VOV
V
4.5
4.225
4.3
Overvoltage Detection
Hysteresis
VHYS
VHYS
250
300
400
mV
TA = 25°C, BQ2945xy
–10
–7
10
7
mV
mV
VOA
OV Detection Accuracy
TA = 25°C, BQ294506 only
TA = –40°C
TA = 0°C
TA = 60°C
TA = 110°C
–40
–20
–24
–54
44
20
24
54
mV
mV
OV Detection Accuracy
due to Temperature
VOA –DRIFT
TA = 10°C to 45°C, BQ294506 only
–15
15
SUPPLY AND LEAKAGE CURRENT
(V3–V2) = (V2–V1) = (V1–VSS) = 4 V (See Figure 8-3
for reference.)
1
2
ICC
Supply Current
µA
µA
(V3–V2) = (V2–V1) = (V1–VSS) = 2.8 V with TA
–40°C to 60°C
=
1.25
Measured at V3, V2, and V1 = 4 V
(V2–V1) = (V1–VSS) = 4 V
TA = 0°C to 60°C (See Figure 8-3 for reference.)
Input Current at Vx
Pins
IIN
–0.1
6
0.1
OUTPUT DRIVE OUT
(V3–V2) or (V2–V1) or (V1–VSS) > VOV
VDD = 7.2 V, IOH = 100 µA, TA = –40°C to +110°C
V
V
Two of the three cells are short circuit and only one
cell is powered
(V3–V2) or (V2–V1) or (V1–VSS) > VOV
VDD = Vx (Cell voltage), IOH = 100 µA, TA = –40°C to
+110°C
VDD – 0.2
250
VOUT
Output Drive Voltage
(V3–V2), (V2–V1), and (V1–VSS) < VOV, IOL = 100
µA, TA = 25°C
TA = –40°C to +110°C
400
4.5
mV
mA
OUT Short Circuit
Current
IOUT(Short)
OUT = 0 V (V3–V2) or (V2–V1) or (V1–VSS) > VOV
CL = 1 nF, VOH(OUT) = 0 V to 5 V(1)
tR
Output Rise Time
Output Impedance
5
2
µs
ZO
5
kΩ
FIXED DELAY TIMER
Fixed Delay, BQ2945xy with delay set to 4s typ
Fixed Delay, BQ2945xy with delay set to 6.5 s
3.2
5.2
4
4.8
7.8
Fault Detection Delay
Time
tDELAY
s
6.5
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7.5 Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 10.8 V, MIN/MAX values stated where TA = –40°C to +110°C and VDD
=
3 V to 15 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fault Detection Delay
tDELAY_CTM
Fixed Delay (Internal settings)
15
ms
Time in Test Mode
(1) Specified by design. Not 100% tested in production.
7.6 Typical Characteristics
1.3
1.2
1.1
1
4.38
Min
Max
Mean
4.37
4.36
4.35
4.34
4.33
4.32
4.31
0.9
0.8
0.7
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D002
Temperature (èC)
D001
Figure 7-2. BQ294502 Overvoltage Threshold
(OVT) vs Temperature
Figure 7-1. ICC Current Consumption vs
Temperature
325
-3.85
-3.9
-3.95
-4
324
323
322
321
320
319
318
317
316
315
-4.05
-4.1
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D004
D003
Figure 7-4. Output Current IOUT vs Temperature
Figure 7-3. Hysteresis VHYS vs Temperature
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8
7.5
7
3-Cell Data
2-Cell Data
6.5
6
5.5
5
4.5
4
0
100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
D005
Figure 7-5. Output Voltage vs Output Current
8 Detailed Description
8.1 Overview
The BQ2945xy is a second-level overvoltage (OV) protector. Each cell is monitored independently by comparing
the actual cell voltage to a protection voltage threshold, VOV. The protection threshold is preprogrammed at the
factory with a range from 3.85 V to 4.65 V.
8.2 Functional Block Diagram
PACK+
RVD
CVD
VDD
REG
R
IN
V3
V2
INT_EN
VOV
Delay
Timer
C
IN
R
IN
OUT
C
IN
V1
R
IN
OSC
C
IN
VSS
PWRPAD
PACK–
Copyright © 2017, Texas Instruments Incorporated
8.3 Feature Description
The voltage sensing for each cell is done independently using a multiplexer. The method of overvoltage
detection is comparing the voltage to an overvoltage protection voltage VOV. Once the voltage exceeds the
programmed fixed value, the delay timer circuit is activated. This delay (tDELAY) is fixed for either a 4-s or 6.5-s
delay. When these conditions are satisfied, the OUT terminal is transitioned to a high level. This output (OUT) is
released to a low condition if all of the cell inputs (Vx) are below the OVP threshold minus the Vhys.
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VOV
VOV–VHYS
tDELAY
OUT (V)
Figure 8-1. Timing for Overvoltage Sensing
8.3.1 Sense Positive Input for VX
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
8.3.2 Output Drive, OUT
The gate of an external N-channel MOSFET is connected to this terminal. This output transitions to a high level
when an overvoltage condition is detected and after the programmed delay timer. OUT will reset to a low level if
the cell voltage falls below the VOV threshold before the fixed delay timer expires.
8.3.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.4 Thermal Pad, PWRPAD
For correct operation, the power pad (PWRPAD) is connected to the VSS terminal on the PCB.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1) and (V3–V2). The OUT
pin is inactive in this mode.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceeds the overvoltage threshold, VOV for the
configured OV delay time, tDELAY. The OUT pin will pull high internally. An external FET ihen turns on, shorting
the fuse to ground, which allows the battery or charger power to blow the fuse. When all of the cell voltages fall
below (VOV–VHYS), the device returns to NORMAL mode.
8.4.3 Customer Test Mode
Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay timer parameter once
the circuit is implemented in the battery pack. To enter CTM, VDD should be set to at least 10 V higher than V3
(see Figure 8-2). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal
operation. To exit CTM, remove the VDD to VC3 voltage differential of 10 V so that the decrease in this value
automatically causes an exit.
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BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
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CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also
avoid exceeding Absolute Maximum Voltages for the individual cell voltages (V3–V2), (V2–V1), and
(V1–VSS). Stressing the pins beyond the rated limits may cause permanent damage to the device.
Figure 8-2 shows the timing for CTM.
10 V
V
OV
V
–V
HYS
OV
t
10 ms
>
DELAY
OUT (V)
Figure 8-2. Timing for Customer Test Mode
Figure 8-3 shows the measurement for current consumption for the product for both VDD and Vx.
bq2945xx
IIN
1
2
3
V3
OUT
VDD
V1
6
5
4
3.6 V
3.6 V
3.6 V
ICC
IIN
V2
IIN
VSS
PWRPAD
Figure 8-3. Configuration for IC Current Consumption Test
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The BQ2945xy devices are a family of second-level protectors used for overvoltage protection of the battery
pack in the application. The device, when configuring the OUT pin with active high, drives a NMOS FET that
connects the fuse to ground in the event of a fault condition. This provides a shorted path to use the battery or
charger power to blow the fuse and cut the power path.
9.2 Typical Application
Pack +
R
VD
RIN
V3
OUT
VDD
V1
C
IN
VCELL3
VCELL2
VCELL1
R
IN
V2
C
IN
R
IN
CVD
VSS
PWRPAD
C
IN
Pack–
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Figure 9-1. Application Configuration Schematic
9.2.1 Design Requirements
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements. Figure 9-1 shows
each external component.
Table 9-1. Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
100
0.1
TYP
MAX UNIT
Voltage monitor filter resistance
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
RIN
CIN
1000
4700
1
Ω
µF
Ω
RVD
CVD
100
1K
0.1
µF
9.2.2 Detailed Design Procedure
1. Determine the overvoltage threshold and delay time. Select the proper device from the table in Section 5, or
contact TI for a different configuration.
2. Determine the number of cell in series. The device supports 2-S to 3-S cell configuration. For 2-S
configuration, V3 pin should be shorted to V2.
3. Follow the application configuration schematic (see Figure 9-1) to connect the device.
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BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
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9.2.3 Application Curves
4.38
Min
Max
325
324
323
322
321
320
319
318
317
316
315
4.37
Mean
4.36
4.35
4.34
4.33
4.32
4.31
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D002
D003
Figure 9-2. OVT vs Temperature
Figure 9-3. VHYS vs Temperature
9.3 System Examples
Pack +
100
1k
bq2945xx
V3
OUT
VDD
V1
VCELL3
VCELL2
VCELL1
0.1µF
1k
1k
V2
0.1µF
VSS
0.1 µF
PWRPAD
0.1µF
Pack –
Figure 9-4. 3-Series Cell Configuration with Fixed Delay
Pack +
100
bq2945xx
OUT
VDD
V1
V3
1k
1k
V2
VCELL2
VCELL1
0.1µF
VSS
0.1µF
PWRPAD
0.1µF
Pack –
Figure 9-5. 2-Series Cell Configuration with Internal Fixed Delay
Copyright © 2021 Texas Instruments Incorporated
12
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Product Folder Links: BQ294502 BQ294504 BQ294506 BQ294512 BQ294522 BQ294524 BQ294532
BQ294533 BQ294582 BQ294592
BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
SLUSAJ3I – SEPTEMBER 2011 – REVISED MAY 2021
www.ti.com
Power Supply Recommendations
The maximum power of this device is 25 V on VDD.
9 Layout
9.1 Layout Guidelines
•
Ensure the RC filters for the V1 and VDD pins are placed as close as possible to the target terminal, reducing
the tracing loop area.
•
•
The VSS pin should be routed to the CELL– terminal.
Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand
the current during a fuse blown event.
9.2 Layout Example
Place the RC filters close to the
device terminals
Power Trace Line
Pack +
NC
V2
OUT
VDD
Pack œ
PWPD
VCELL
VSS
VSS
Ensure trace can support sufficient current
flow for fuse blow
Connect the VSS pins to the CELL- side
Figure 9-1. Layout Schematic
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: BQ294502 BQ294504 BQ294506 BQ294512 BQ294522 BQ294524 BQ294532
BQ294533 BQ294582 BQ294592
BQ294502, BQ294504, BQ294506, BQ294512
BQ294522, BQ294524, BQ294532, BQ294533
BQ294582, BQ294592
SLUSAJ3I – SEPTEMBER 2011 – REVISED MAY 2021
www.ti.com
10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
14
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Product Folder Links: BQ294502 BQ294504 BQ294506 BQ294512 BQ294522 BQ294524 BQ294532
BQ294533 BQ294582 BQ294592
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ294502DRVR
BQ294502DRVT
BQ294504DRVR
BQ294504DRVT
BQ294506DRVR
BQ294506DRVT
BQ294512DRVR
BQ294512DRVT
BQ294522DRVR
BQ294522DRVT
BQ294524DRVR
BQ294524DRVT
BQ294532DRVR
BQ294532DRVT
BQ294533DRVR
BQ294533DRVT
BQ294582DRVR
BQ294582DRVT
BQ294592DRVR
BQ294592DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
4502
4502
4504
4504
4506
4506
4512
4512
4522
4522
4524
4524
4532
4532
4533
4533
4582
4582
4592
4592
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ294502DRVR
BQ294502DRVR
BQ294502DRVT
BQ294502DRVT
BQ294504DRVR
BQ294504DRVR
BQ294504DRVT
BQ294504DRVT
BQ294506DRVR
BQ294506DRVR
BQ294506DRVT
BQ294506DRVT
BQ294512DRVR
BQ294512DRVT
BQ294522DRVR
BQ294522DRVT
BQ294524DRVR
BQ294524DRVR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ294524DRVT
BQ294524DRVT
BQ294532DRVR
BQ294532DRVR
BQ294532DRVT
BQ294532DRVT
BQ294533DRVR
BQ294533DRVT
BQ294582DRVR
BQ294582DRVR
BQ294582DRVT
BQ294582DRVT
BQ294592DRVR
BQ294592DRVR
BQ294592DRVT
BQ294592DRVT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
250
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
250
3000
250
3000
3000
250
250
3000
3000
250
250
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DRV
SPQ
3000
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
BQ294502DRVR
6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ294502DRVR
BQ294502DRVT
BQ294502DRVT
BQ294504DRVR
BQ294504DRVR
BQ294504DRVT
BQ294504DRVT
BQ294506DRVR
BQ294506DRVR
BQ294506DRVT
BQ294506DRVT
BQ294512DRVR
BQ294512DRVT
BQ294522DRVR
BQ294522DRVT
BQ294524DRVR
BQ294524DRVR
BQ294524DRVT
BQ294524DRVT
BQ294532DRVR
BQ294532DRVR
BQ294532DRVT
BQ294532DRVT
BQ294533DRVR
BQ294533DRVT
BQ294582DRVR
BQ294582DRVR
BQ294582DRVT
BQ294582DRVT
BQ294592DRVR
BQ294592DRVR
BQ294592DRVT
BQ294592DRVT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
3000
250
250
3000
3000
250
250
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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