BQ294704 [TI]
Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries with External Delay Capacitor; 过压保护2系列至4节串联锂离子电池，外置延迟电容
| 型号： | BQ294704 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries with External Delay Capacitor |
| 文件： | 总19页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 –SEPTEMBER 2012
Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
Check for Samples: bq294700, bq294701, bq294702, bq294703, bq294704, bq294705
1
FEATURES
APPLICATIONS
•
•
•
2-, 3-, and 4-Series Cell Overvoltage Protection
External Capacitor-Programmed Delay Timer
•
•
Notebook
UPS Battery Backup
Factory Programmed OVP Threshold
(Threshold Range 3.85 V to 4.6 V)
•
•
•
Output Options: Active High or Open Drain
Active Low
High-Accuracy Overvoltage Protection:
±10 mV
Low Power Consumption ICC ≈ 1 µA
(VCELL(ALL) < VPROTECT
)
•
•
Low Leakage Current Per Cell Input < 100 nA
Small Package Footprint
–
8-Pin SON (2 mm x 2 mm)
DESCRIPTION
The bq2947xy family of products is an overvoltage monitor and protector for Li-Ion battery pack systems. Each
cell is monitored independently for an overvoltage condition.
In the bq2947xy device, an external delay timer is initiated upon detection of an overvoltage condition on any
cell. Upon expiration of the delay timer, the output is triggered into its active state (either high or low, depending
on the configuration). The external delay timer feature also includes the ability to detect an open or shorted delay
capacitor on the CD pin, which will similarly trigger the output driver in an overvoltage condition.
For quicker production-line testing, the bq2947xy device provides a Customer Test Mode with reduced delay
time.
1
8
VDD
V4
OUT
CD
2
3
4
7
6
5
V3
V2
VSS
V1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
SLUSB15 –SEPTEMBER 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
Package
Designator
OV Hysteresis
(V)
Tape and Reel
(Large)
TA
Part Number
Package
OVP (V)
Output Drive
bq294700
bq294701
bq294702
bq294703
bq294704
bq294705
4.350
4.250
4.300
4.325
4.400
4.450
0.300
0.300
0.300
0.300
0.300
0.300
CMOS Active High bq294700DSGR
CMOS Active High bq294701DSGR
CMOS Active High bq294702DSGR
CMOS Active High bq294703DSGR
CMOS Active High bq294704DSGR
CMOS Active High bq294705DSGR
CMOS Active High
–40°C to
110°C
8-pin
SON
DSG
bq2947xy(1)
3.850–4.600
0–0.300
or Open Drain
Active Low
bq2947xyTBD
(1) Future option, contact TI.
THERMAL INFORMATION
bq2947xy
SON
8 PINS
62
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance
θJC(top)
θJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
72
32.5
1.6
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
33
θJC(bottom)
10
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 –SEPTEMBER 2012
PIN FUNCTIONS
bq2947xy
Pin Name
Type I/O
Description
1
2
3
4
5
6
7
8
9
VDD
V4
P
IA
IA
IA
IA
P
Power supply input
Sense input for positive voltage of the fourth cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the lowest cell in the stack
V3
V2
V1
VSS
CD
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
External capacitor connection for delay timer
OA
OA
P
OUT
PWPD
Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low
TI recommends connecting the exposed pad to VSS on PCB.
PIN DETAILS
In the bq2947xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed
current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes
from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin
successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is
detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 2 for details on CD
and OUT pin behavior during an overvoltage event.
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present) and
is high impedance when inactive (no OV).
VOV
VOV–VHYS
tCD
OUT (V)
Figure 1. Timing for Overvoltage Sensing
Copyright © 2012, Texas Instruments Incorporated
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SLUSB15 –SEPTEMBER 2012
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Figure 2 shows the behavior of CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
tCHGDELAY
tCD
V
OUT1
V(OUT)
Note: Active High OUT version shown
Figure 2. CD Pin Mechanism
NOTE
In the case of an Open Drain Active Low version, the VOUT signal will be high and
transition to low state when the voltage on the VCD capacitor discharges to the set level
based on the tCD timer.
Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active
Low options.
Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
External Delay Capacitor, CD
This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV
threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
4
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Product Folder Links: bq294700 bq294701 bq294702 bq294703 bq294704 bq294705
bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 –SEPTEMBER 2012
To calculate the delay, use the following equation:
tCD (sec) = K * CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (sec) = 10 * 0.1 = 1 s (Minimum)
tCD (sec) = 20 * 0.1 = 2 s (Maximum)
NOTE
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
FUNCTIONAL BLOCK DIAGRAM
Figure 3 shows a CMOS Active High configuration.
PACK+
R
VD
C
VD
VDD
1
R
R
R
R
V4
V3
V2
IN
IN
IN
IN
2
3
4
5
6
C
IN
V
OV
C
IN
Enable
OUT
Active
Delay Charge
/
Discharge Circuit
8
C
IN
V1
C
IN
VSS
9
7
PWPD
CD
C
CD
PACK–
Figure 3. Block Diagram
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Copyright © 2012, Texas Instruments Incorporated
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SLUSB15 –SEPTEMBER 2012
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ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
Supply voltage range
CONDITION
VDD–VSS
VALUE/UNIT
–0.3 to 30 V
–0.3 to 30 V
–0.3 to 30 V
Input voltage range
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
OUT–VSS
Output voltage range
Continuous total power dissipation, PTOT
Storage temperature range, TSTG
See package dissipation rating.
–65 to 150°C
Lead temperature (soldering, 10 s),
TSOLDER
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
(1)
Supply voltage, VDD
Input voltage
range
3
20
V
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
0
5
V
Operating ambient temperature range, TA
(1) See APPLICATION SCHEMATIC.
–40
110
°C
DC CHARACTERISTICS
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V
to 20 V (unless otherwise noted).
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Voltage Protection Thresholds
bq294700, RIN = 1 kΩ
bq294701, RIN = 1 kΩ
bq294702, RIN = 1 kΩ
bq294703, RIN = 1 kΩ
bq294704, RIN = 1 kΩ
bq294705, RIN = 1 kΩ
bq2947xy(1)
4.350
4.250
4.300
4.325
4.400
4.450
300
V
V
V
V(PROTECT) Overvoltage
Detection
VOV
V
V
V
VHYS
VOA
OV Detection Hysteresis
OV Detection Accuracy
250
–10
–40
–20
–24
–54
400
10
40
20
24
54
mV
mV
mV
mV
mV
mV
TA = 25°C
TA = –40°C
TA = 0°C
OV Detection Accuracy
Across Temperature
VOADRIFT
TA = 60°C
TA = 110°C
Supply and Leakage Current
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 14.)
IDD
IIN
Supply Current
1
2
µA
µA
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 14.)
Input Current at Vx Pins
–0.1
0.1
Current Consumption at Power down, (V4–V3) =
Input Current (ALL Vx
and VDD Input Pins)
ICELL
(V3–V2) = (V2–V1) = (V1–VSS) = 2.30 V at TA
25°C
=
1.1
µA
Output Drive OUT, CMOS Active High Versions Only
(1) Future option, contact TI.
6
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bq294700, bq294701, bq294702
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www.ti.com
SLUSB15 –SEPTEMBER 2012
DC CHARACTERISTICS (continued)
Typical values stated where TA = 25°C and VDD = 14.4 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V
to 20 V (unless otherwise noted).
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV
VDD = 14.4 V, IOH = 100 µA
,
6
V
If three of four cells are short circuited, only one
cell remains powered and > VOV, VDD = Vx (cell
voltage), IOH = 100 µA
VDD –
0.3
Output Drive Voltage,
Active High
V
VOUT
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
,
,
250
400
4.5
mV
mA
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV
VDD = 14.4 V,
,
OUT Source Current
(during OV)
IOUTH
OUT = 0 V, measured out of OUT pin.
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
OUT = VDD, measured into OUT pin .Pull resistor
OUT Sink Current (no
OV)
IOUTL
0.5
14
mA
RPU = 5 kΩ to VDD = 14.4 V
Output Drive OUT, CMOS Open Drain Active Low Versions Only
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
,
,
Output Drive Voltage,
Active High
VOUT
250
400
14
mV
mA
nA
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
OUT = VDD, measured into OUT pin. Pull resistor
OUT Sink Current (no
OV)
IOUTL
0.5
RPU = 5 kΩ to VDD = 14.4 V
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
,
IOUTLK
OUT pin leakage
100
OUT = VDD, measured into OUT pin.
Delay Timer
tCD
OV Delay Time
CCD = 0.1 µF (see Equation 1)
1
1.5
2
s
OV Delay Time with CD Delay due to CCD capacitor shorted to ground for
pin = 0 V Customer Test Mode
tCD_GND
20
170
ms
Copyright © 2012, Texas Instruments Incorporated
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SLUSB15 –SEPTEMBER 2012
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TYPICAL CHARACTERISTICS
4.40
0.316
0.315
0.314
0.313
0.312
Mean
Min
Max
4.39
4.38
4.37
4.36
4.35
4.34
4.33
4.32
4.31
4.30
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
G001
G002
Figure 4. Overvoltage Threshold (OVT) vs.
Temperature
Figure 5. Hysteresis VHYS vs. Temperature
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
G003
G004
Figure 6. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 7. ICELL vs. Temperature
at VCELL= 9.2 V
−3.68
8
7
6
5
4
3
2
1
0
−3.70
−3.72
−3.74
−3.76
−3.78
−3.80
−3.82
−3.84
−3.86
−3.88
−50
−25
0
25
50
75
100
125
0
5
10
15
20
25
30
Temperature (°C)
VDD (V)
G005
G006
Figure 8. Output Current IOUT vs.
Temperature
Figure 9. VOUT vs. VDD
8
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bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
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SLUSB15 –SEPTEMBER 2012
APPLICATION INFORMATION
Figure 10 shows the recommended reference design components.
Pack
+
100 Ω
OUT
CD
VDD
V4
1k
1k
1k
1k
VCELL4
VCELL3
VCELL2
VCELL1
0.1µF
0.1µF
V3
V2
VSS
V1
0.1µF
PWPD
0.1 µF
0.1 µF
0.1µF
–
Pack
Figure 10. Application Configuration for Active High
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Changes to the ranges stated in Table 1 will impact the accuracy of the cell
measurements.
Table 1. Parameters
PARAMETER
EXTERNAL COMPONENT
MIN
900
0.01
100
NOM
1000
0.1
MAX
4700
1.0
1
UNIT
Ω
Voltage monitor filter resistance
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
CD external delay capacitance
RIN
CIN
µF
RVD
CVD
CCD
KΩ
µF
0.1
0.1
1.0
1.0
µF
NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
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SLUSB15 –SEPTEMBER 2012
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APPLICATION SCHEMATIC
Pack
+
Pack
+
100 Ω
100 Ω
VDD
V4
OUT
CD
OUT
CD
VDD
V4
1k
V3
V2
VSS
V1
V3
V2
VSS
V1
0.1µF
0.1µF
VCELL3
1k
1k
1k
1k
VCELL2
VCELL1
0.1µF
0.1µF
VCELL2
VCELL1
PWPD
PWPD
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
–
Pack
Pack–
Figure 11. 2-Series Cell Configuration Active High
with Capacitor-Programmed Delay
Figure 12. 3-Series Cell Configuration Active High
with Capacitor-Programmed Delay
NOTE
In these application examples of 2s and 3s, an external pull-up resistor is required on the
OUT terminal to configure for an Open Drain Active Low operation.
10
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bq294700, bq294701, bq294702
bq294703, bq294704, bq294705
www.ti.com
SLUSB15 –SEPTEMBER 2012
CUSTOMER TEST MODE
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of
170 ms.
Figure 13 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(OUT)
CD pin held low
V(CD)
Figure 13. Timing for Customer Test Mode
Figure 14 shows the measurement for current consumption of the product for both VDD and Vx.
IDD
1
2
3
4
8
7
6
5
VDD
V4
OUT
CD
IIN4
IIN3
VSS
V3
V2
ICELL
IIN2
V1
IIN1
ICELL = IDD + IIN1 + IIN2 + IIN3 + IIN4
Figure 14. Configuration for IC Current Consumption Test
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
700
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
Green (RoHS
& no Sb/Br)
700
701
701
702
702
703
703
704
704
705
705
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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