BQ32002D [TI]
可自动切换到备用电源的实时时钟 (RTC)
| D | 8 | -40 to 85;
| 型号： | BQ32002D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可自动切换到备用电源的实时时钟 (RTC) | D | 8 | -40 to 85 时钟 |
| 文件： | 总31页 (文件大小：1882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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BQ32002
SLUSA96B –AUGUST 2010–REVISED APRIL 2016
BQ32002 Real-Time Clock (RTC)
1 Features
3 Description
The BQ32002 device is a compatible replacement for
industry standard real-time clocks.
1
•
•
Automatic Switchover to Backup Supply
I2C Interface Supports Serial Clock
up to 400 kHz
The BQ32002 features an automatic backup supply
that can be implemented using a capacitor or non-
rechargeable battery. The BQ32002 has
•
Uses 32.768-kHz Crystal With
a
–63-ppm to +126-ppm Adjustment
programmable calibration adjustment from –63 ppm
to +126 ppm. The BQ32002 registers include an OF
(oscillator fail) flag indicating the status of the RTC
oscillator, as well as a STOP bit that allows the host
processor to disable the oscillator. The time registers
are normally updated once per second, and all the
registers are updated at the same time to prevent a
timekeeping glitch. The BQ32002 includes automatic
leap-year compensation.
•
•
•
Integrated Oscillator-Fail Detection
8-Pin SOIC Package
–40°C to +85°C Ambient Operating Temperature
2 Applications
General Consumer Electronics
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
BQ32002
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
VCC
Simplified Schematic
3.0 to 3.6 V
Place supply-decoupling
1 µF
capacitor near supply pin
BQ32002
SCL
VCC
VCC
VBACK
Automatic
Backup
Switch
Real-Time
SDA
Clock
4.7 kW
4.7 kW 4.7 kW
VCORE
____
IRQ
IRQ
Interrupt
Generator
OSCI
32-kHz
Oscillator
SCL
SDA
Copyright © 2016, Texas Instruments Incorporated
I2C Register
OSCO
Interface With
Undervoltage
Lockout
Registers
GND
Copyright © 2016, Texas Instruments Incorporated
NOTE: All pullup resistors should be connected to
VCC such that no pullup is applied during
backup supply operation.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ32002
SLUSA96B –AUGUST 2010–REVISED APRIL 2016
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Table of Contents
7.4 Device Functional Modes........................................ 10
7.5 Programming........................................................... 10
7.6 Register Maps......................................................... 12
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
Power Supply Recommendations...................... 21
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1 Community Resources.......................................... 22
11.2 Trademarks........................................................... 22
11.3 Electrostatic Discharge Caution............................ 22
11.4 Glossary................................................................ 22
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision A (December 2010) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings section, Thermal Information section, Detailed
Description section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
•
•
•
Deleted Trickle Charge Pump from Functional Block Diagram/Application Circuit ............................................................... 1
Changed Crystal series resistance maximum from 40 kΩ to 70 kΩ in Recommended Operating Conditions ...................... 4
Added Recommended Operating Conditions table note (1) Crystal load capacitance ±10% is allowed. ............................. 4
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
1
2
3
4
8
OSCI
VCC
7
6
5
OSCO
VBACK
IRQ
SCL
SDA
GND
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
POWER AND GROUND
VCC
8
4
3
—
—
—
Main device power
GND
VBACK
Ground
Backup device power
SERIAL INTERFACE
SCL
6
I
I2C serial interface clock
I2C serial data
SDA
5
7
I/O
INTERRUPT
IRQ
O
Configurable interrupt output. Open-drain output.
OSCILLATOR
OSCI
1
2
—
—
Oscillator input
Oscillator output
OSCO
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–40
–60
MAX
4
UNIT
VCC to GND
VIN
Input voltage
V
All other pins to GND
VCC + 0.3
150
TJ
Operating junction temperature
Storage temperature after reflow
°C
°C
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
VCC
TA
fo
Supply voltage, VCC to GND
Operating free-air temperature
Crystal resonant frequency
Crystal series resistance
3
3.6
85
V
°C
–40
32.768
12
kHz
kΩ
pF
RS
CL
70
Crystal load capacitance(1)
(1) Crystal load capacitance ±10% is allowed.
6.4 Thermal Information
BQ32002
D (SOIC)
8 PINS
114.8
59.1
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
55.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
11.9
ψJB
55
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
POWER SUPPLY
ICC VCC supply current
TEST CONDITION
MIN
TYP
MAX UNIT
65
200
VCC
VCC
1.5
μA
V
Operating
1.4
2
VBACK Backup supply voltage
IBACK Backup supply current
Switchover
VCC = 0 V, VBAT = 3 V, Oscillator on, TA = 25°C
Operating → Backup
Backup → Operating
0.9(1)
1.8
μA
V
VSO
Switchover voltage
2.4
LOGIC LEVEL INPUTS
VIL
VIH
IIN
Input low voltage
Input high voltage
Input current
0.3 × VCC
V
V
0.7 × VCC
–1
0 V ≤ VIN ≤ VCC
1
μA
LOGIC LEVEL OUTPUTS
VOL
IL
Output low voltage
Leakage current
IOL = 3 mA
0.4
1
V
–1
μA
REAL-TIME CLOCK CHARACTERISTICS
Pre-calibration accuracy
VCC = 3.3 V, VBAT = 3 V, Oscillator on, TA = 25°C
±35(2)
ppm
(1) The backup supply current is measured only after an initial power up. The device behavior is not ensured before the first power up.
(2) Typical accuracy is measured using reference board design and KDS DMX-26S surface-mount 32.768-kHz crystal. Variation in board
design and crystal section results in different typical accuracy.
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UNIT
6.6 Timing Requirements
STANDARD MODE
FAST MODE
PARAMETER
MIN NOM
MAX
MIN NOM
MAX
fscl
I2C clock frequency
I2C clock high time
I2C clock low time
0
4
100
0
0.6
1.3
0
400 kHz
tsch
tscl
μs
μs
4.7
0
tsp
I2C spike time
50
50
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
tsds
tsdh
ticr
I2C serial data setup time
I2C serial data hold time
I2C input rise time
I2C input fall time
I2C output fall time
I2C bus free time
I2C Start setup time
I2C Start hold time
250
0
100
0
(1)
1000
300
20 + 0.1Cb
300
300
300
(1)
(1)
ticf
20 + 0.1Cb
20 + 0.1Cb
tocf
300
tbuf
tsts
4.7
4.7
4
1.3
0.6
0.6
0.6
tsth
tsps
tvd (data)
I2C Stop setup time
4
Valid data time (SCL low to SDA valid)
1
1
1
1
Valid data time of ACK
(ACK signal from SCL low to SDA low)
tvd (ack)
μs
(1) Cb = total capacitance of one bus line in pF
6.7 Typical Characteristics
50
100
90
80
70
60
50
40
30
20
10
0
20
Icc (uA)
107.5
106
VCC = 3.3 V
VCC = 2 V
Iback (uA)
45
40
35
30
25
20
15
10
5
104.5
103
0
101.5
100
-5
-10
Icc (uA)
Iback (uA)
-10
0.5
1.0
1.5
2.0
2.5
3.0
2.4
2.9
3.4
3.9
Vbackup (V)
Vbackup (V)
C001
C002
Figure 1. Current Consumption vs Backup Supply Voltage
Figure 2. Current Consumption vs Backup Supply Voltage
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7 Detailed Description
7.1 Overview
The BQ32002 is a real-time clock that features an automatic backup supply with integrated oscillator-fail
detection.
7.2 Functional Block Diagram
V
CC
Place supply-decoupling
capacitor near supply pin
1 µF
V
CC
Automatic
Backup
Switch
V
BACK
Use only
super-capacitor
or battery, not
both
V
CC
.22 F
VCORE
4.7 kΩ
4.7 kΩ
4.7 kΩ
IRQ
Interrupt
Generator
OSCI
I2C Register
Interface With
Undervoltage
Lockout
SCL
SDA
32-kHz
Oscillator
OSCO
Registers
GND
Copyright © 2016, Texas Instruments Incorporated
NOTE: All pullup resistors should be connected to VCC such that no pullup is applied during backup supply operation.
7.3 Feature Description
7.3.1 IRQ Function
The IRQ pin of the BQ32002 functions as a general-purpose output or a frequency test output. The function of
IRQ is configurable in the device register space by setting the FT, FTF, and OUT bits. On initial power cycles,
the OUT bit is set to one, and the FTF and FT bits are set to zero. On subsequent power-ups, with backup
supply present, the OUT bit remains unchanged, and the FTF and FT bits are set to zero. When operating on
backup supply, the IRQ pin function is unused. IRQ pullup resistor must be tied to VCC to prevent IRQ operation
when operating on backup supply. The effect of the calibration logic is not normally observable when IRQ is
configured to output 1 Hz. The calibration logic functions by periodically adjusting the width of the 1-Hz clock.
The calibration effect is observable only every eight or sixteen minutes, depending on the sign of the calibration.
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Feature Description (continued)
Figure 3. IRQ Pin Functional Diagram
Table 1. IRQ Function
FT
1
OUT
FTF
1
IRQ STATE
X
X
1
0
1 Hz
1
0
512 Hz
0
X
1
0
0
X
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7.3.2 VBACK Switchover
The BQ32002 has an internal switchover circuit that causes the device to switch from main power supply to
backup power supply when the voltage of the main supply pin VCC drops below a minimum threshold. The VBACK
switchover circuit uses an internal reference voltage VREF derived from the on-chip bandgap reference; VREF is
approximately 1.8 V. The device switches to the VBACK supply when VCC is less than the lesser of VBACK or VREF
.
Similarly, the device switches to the VCC supply when VCC is greater than either VBACK or VREF
.
Some registers are reset to default values when the RTC switches from main power supply to backup power
supply. See the register definitions to determine what register bits are effected by a backup switchover (effected
bits have their reset value (1/0) shown for Cycle, bits that are unchanged by backup are marked UC).
The time-keeping registers can take up to 1 second to update after the RTC switches from backup power supply
to main power supply.
VBACK > VREF
VBACK > VREF
3.3V
VBACK
VRE F
3.3V
VBACK
VRE F
VCC
VCC
–5 V/ms (max)
Time
Time
On VCC
On VBACK
On VBACK
OnVCC
VREF > VBACK
VREF > VBACK
3.3V
3.3V
VRE F
VRE F
VBACK
VBACK
VCC
–5 V/ms (max)
VCC
Time
Time
On VCC
On VBACK
On VBACK
OnVCC
Figure 4. Switchover Diagram
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7.4 Device Functional Modes
When the device switches from the main power supply to backup supply, the time-keeping registers [0- 9] cannot
be accessed through the I2C. The access to these registers are only when VCC > VREF. The time-keeping
registers can take up to 1 second to update after the device switches from backup power supply to main power
supply.
7.5 Programming
7.5.1 I2C Serial Interface
The I2C interface allows control and monitoring of the RTC by a microcontroller. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000).
The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pullup resistors. When the bus is idle,
both SDA and SCL lines are pulled high.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer.
A slave device receives and/or transmits data on the bus under control of the master device. This device
operates only as a slave device.
I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while
SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first,
including the data direction bit (R/W). After receiving a valid address byte, this device responds with an
acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. This device
responds to the I2C slave address 11010000b for write commands and slave address 11010001b for read
commands.
This device does not respond to the general call address.
A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W
bit is high, the data from this device are the values read from the register previously selected by a write to the
subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if
complete bytes are received and acknowledged.
A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the
master to terminate the transfer. A master device must wait at least 60 μs after the RTC exits backup mode to
generate a START condition.
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Programming (continued)
ticf
ticr
tsdh
tvd
0.7 VCC
SDA
0.3 VCC
Start Condition
ticf
ticr
tsds
tsch
3
0.7 VCC
1
2
4
SCL
0.3 VCC
tscl
tsth
1/fscl
Stop Condition
tvd
tbuf
0.7 VCC
D7/A
SDA
0.3 VCC
Start Condition
tsds
0.7 VCC
8
9
SCL
0.3 VCC
tsps
Figure 5. I2C Timing Diagram
1 1
1
1 1
1
R
S
(AN)
Sub
S
(DN)
(DN+1)
0
0 0 0 W
0
0 0 0
DataN+1
Slave
Address
Slave
Address
DataN
Address
Figure 6. I2C Read Mode
Figure 7. I2C Write Mode
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7.6 Register Maps
Table 2. Normal Registers
ADDRESS
REGISTER
(HEX)
REGISTER NAME
DESCRIPTION
0
1
2
3
4
5
6
7
9
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x09
SECONDS
MINUTES
CENT_HOURS
DAY
Clock seconds and STOP bit
Clock minutes
Clock hours, century, and CENT_EN bit
Clock day
DATE
Clock date
MONTH
Clock month
YEARS
Clock years
CAL_CFG1
CFG2
Calibration and configuration
Configuration 2
Table 3. Special Function Registers
ADDRESS
(HEX)
REGISTER
REGISTER NAME
DESCRIPTION
32
33
34
0x20
0x21
0x22
SF KEY 1
SF KEY 2
SFR
Special function key 1
Special function key 2
Special function register
7.6.1 I2C Read After Backup Mode
The time-keeping registers can take up to 1 second to update after the RTC switches from backup power supply
to main power supply. An I2C read of the RTC that starts before the update has completed will return the time
when the RTC enters backup mode. To ensure that the correct time is read after backup mode, the host should
wait longer than 1 second after the main supply is greater than 2.8 V and VBACK
.
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7.6.2 Normal Register Descriptions
Table 4. SECONDS Register
Address
0x00
Name
SECONDS
Initial Value
Description
0XXXXXXb
Clock seconds and STOP bit
D7
STOP
r/w
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
10_SECOND
1_SECOND
r/w
r/w
X
Read/Write
Initial
0
X
X
X
X
X
X
UC
UC
UC
UC
UC
UC
UC
UC
Cycle
STOP
Oscillator stop. The STOP bit is used to force the oscillator to stop oscillating. STOP is set to 0 on initial application of
power, on all subsequent power cycles STOP remains unchanged. On initial power application STOP can be written to 1
and then written to 0 to force start the oscillator.
0
1
Normal
Stop
10_SECOND
1_SECOND
BCD of tens of seconds. The 10_SECOND bits are the BCD representation of the number of tens of seconds on the
clock. Valid values are 0 to 5. If invalid data is written to 10_SECOND, the clock will update with invalid data in
10_SECOND until the counter rolls over; thereafter, the data in 10_SECOND is valid. Time keeping registers can take up
to 1 second to update after the RTC switches from backup power supply to main power supply.
BCD of seconds. The 1_SECOND bits are the BCD representation of the number of seconds on the clock. Valid values
are 0 to 9. If invalid data is written to 1_SECOND, the clock will update with invalid data in 1_SECOND until the counter
rolls over; thereafter, the data in 1_SECOND is valid. Time keeping registers can take up to 1 second to update after the
RTC switches from backup power supply to main power supply.
Table 5. MINUTES Register
Address
0x01
Name
MINUTES
1XXXXXXb
Clock minutes
Initial Value
Description
D7
OF
r/w
1
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
10_MINUTE
1_MINUTE
r/w
r/w
X
Read/Write
Initial
X
X
X
X
X
X
0
UC
UC
UC
UC
UC
UC
UC
Cycle
OF
Oscillator fail flag. The OF bit is a latched flag indicating when the 32.768-kHz oscillator has dropped at least four
consecutive pulses. The OF flag is always set on initial power-up, and it can be cleared through the serial interface.
When OF is 0, no oscillator failure has been detected. When OF is 1, the oscillator fail detect circuit has detected at least
four consecutive dropped pulses.
0
1
No failure detected
Failure detected
10_MINUTE
1_MINUTE
BCD of tens of minutes. The 10_MINUTE bits are the BCD representation of the number of tens of minutes on the clock.
Valid values are 0 to 5. If invalid data is written to 10_MINUTE, the clock will update with invalid data in 10_MINUTE until
the counter rolls over; thereafter, the data in 10_MINUTE is valid. Time keeping registers can take up to 1 second to
update after the RTC switches from backup power supply to main power supply.
BCD of minutes. The 1_MINUTE bits are the BCD representation of the number of minutes on the clock. Valid values are
0 to 9. If invalid data is written to 1_MINUTE, the clock will update with invalid data in 1_MINUTE until the counter rolls
over; thereafter, the data in 1_MINUTE is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
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Table 6. CENT_HOURS Register
Address
0x02
Name
CENT_HOURS
XXXXXXXXb
Initial Value
Description
Clock hours, century, and CENT_EN bit
D7
CENT_EN
r/w
D6
CENT
r/w
D5
D4
D3
D2
D1
D0
BIT(S)
Name
10_HOUR
r/w
1_HOUR
r/w
Read/Write
Initial
X
X
X
X
X
X
X
X
UC
UC
UC
UC
UC
UC
UC
UC
Cycle
CENT_EN
Century enable. The CENT_EN bit enables the century timekeeping feature. If CENT_EN is set to 1, then the clock
tracks the century using the CENT bit. If CENT_EN is set to 0, the clock ignores the CENT bit.
0
1
Century disabled
Century enabled
CENT
Century. The CENT bit tracks the century when century timekeeping is enabled. The clock toggles the CENT bit when
the year count rolls from 99 to 00. Because the clock compliments the CENT bit, the user can define the meaning of
CENT (1 for current century and 0 for next century, or 0 for current century and 1 for next century).
10_HOUR
BCD of tens of hours (24-hour format). The 10_HOUR bits are the BCD representation of the number of tens of hours on
the clock, in 24-hour format. Valid values are 0 to 2. If invalid data is written to 10_HOUR, the clock will update with
invalid data in 10_HOUR until the counter rolls over; thereafter, the data in 10_HOUR is valid. Time keeping registers can
take up to 1 second to update after the RTC switches from backup power supply to main power supply.
1_HOUR
BCD of hours (24-hour format). The 1_HOUR bits are the BCD representation of the number of hours on the clock, in 24-
hour format. Valid values are 0 to 9. If invalid data is written to 1_HOUR, the clock will update with invalid data in
1_HOUR until the counter rolls over; thereafter, the data in 1_HOUR is valid. Time keeping registers can take up to 1
second to update after the RTC switches from backup power supply to main power supply.
Table 7. DAY Register
Address
0x03
Name
DAY
Initial Value
Description
00000XXXb
Clock day
D7
D6
D5
RSVD
r/w
0
D4
D3
D2
D1
DAY
r/w
X
D0
BIT(S)
Name
Read/Write
Initial
0
0
0
0
0
0
0
0
X
X
0
UC
UC
UC
Cycle
RSVD
DAY
Reserved. The RSVD bits should always be written as 0.
BCD of the day of the week. The DAY bits are the BCD representation of the day of the week. Valid values are 1 to 7
and represent the days from Sunday to Saturday. DAY updates if set to 0 until the counter rolls over; thereafter, the data
in DAY is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power
supply to main power supply.
1
2
3
4
5
6
7
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
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Table 8. DATE Register
Address
0x04
Name
DATE
Initial Value
Description
00XXXXXXb
Clock date
D7
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
RSVD
r/w
10_DATE
r/w
1_DATE
r/w
Read/Write
Initial
0
0
0
0
X
X
X
X
X
X
UC
UC
UC
UC
UC
UC
Cycle
RSVD
Reserved. The RSVD bits should always be written as 0.
10_DATE
BCD of tens of date. The 10_DATE bits are the BCD representation of the tens of date on the clock. Valid values are 0 to
3(1). If invalid data is written to 10_DATE, the clock will update with invalid data in 10_DATE until the counter rolls over;
thereafter, the data in 10_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
1_DATE
BCD of date. The 1_DATE bits are the BCD representation of the date on the clock. Valid values are 0 to 9(1). If invalid
data is written to 1_DATE, the clock will update with invalid data in 1_DATE until the counter rolls over; thereafter, the
data in 1_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup
power supply to main power supply.
(1) 10_DATE and 1_DATE must form a valid date, 01 to 31, dependent on month and year.
Table 9. MONTH Register
Address
0x05
Name
MONTH
Initial Value
Description
000XXXXXb
Clock month
D7
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
RSVD
10_MONTH
1_MONTH
r/w
r/w
0
r/w
X
Read/Write
Initial
0
0
0
0
X
X
X
X
0
UC
UC
UC
UC
UC
Cycle
RSVD
Reserved. The RSVD bits should always be written as 0.
10_MONTH
BCD of tens of month. The 10_MONTH bits are the BCD representation of the tens of month on the clock. Valid values
are 0 to 1(1). If invalid data is written to 10_MONTH, the clock will update with invalid data in 10_MONTH until the
counter rolls over; thereafter, the data in 10_MONTH is valid.
1_MONTH
BCD of month. The 1_MONTH bits are the BCD representation of the month on the clock. Valid values are 0 to 9(1). If
invalid data is written to 1_MONTH, the clock will update with invalid data in 1_MONTH until the counter rolls over;
thereafter, the data in 1_MONTH is valid.
(1) 10_MONTH and 1_MONTH must form a valid date, 01 to 12.
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Table 10. YEARS Register
Address
0x06
Name
YEARS
Initial Value
Description
XXXXXXXXb
Clock year
D7
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
10_YEAR
r/w
1_YEAR
r/w
Read/Write
Initial
X
X
X
X
X
X
X
X
UC
UC
UC
UC
UC
UC
UC
UC
Cycle
10_YEAR
BCD of tens of years. The 10_YEAR bits are the BCD representation of the tens of years on the clock. Valid values are 0
to 9. If invalid data is written to 10_YEAR, the clock will update with invalid data in 10_YEAR until the counter rolls over;
thereafter, the data in 10_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC
switches from backup power supply to main power supply.
1_YEAR
BCD of year. The 1_YEAR bits are the BCD representation of the years on the clock. Valid values are 0 to 9. If invalid
data is written to 1_YEAR, the clock will update with invalid data in 1_YEAR until the counter rolls over; thereafter, the
data in 1_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup
power supply to main power supply.
Table 11. CAL_CFG1 Register
Address
0x07
Name
CAL_CFG1
10000000b
Initial Value
Description
Calibration and control
D7
OUT
r/w
1
D6
FT
r/w
0
D5
S
D4
D3
D2
CAL
r/w
0
D1
D0
BIT(S)
Name
r/w
0
Read/Write
Initial
0
0
0
0
UC
UC
UC
UC
UC
UC
UC
UC
Cycle
OUT
FT
Logic output, when FT = 0. When FT is zero, the logic output of IRQ pin reflects the value of OUT.
0
1
IRQ is logic 0
IRQ is logic 1
Frequency test. The FT bit is used to enable the frequency test signal on the IRQ pin. When FT is 1, a square wave is
produced on the IRQ pin. The FTF bit in the SFR register determines the frequency of the test signal.
0
1
Disable
Enable
S
Calibration sign. The S bit determines the polarity of the calibration applied to the oscillator. If S is 0, then the calibration
slows the RTC. If S is 1, then the calibration speeds the RTC.
0
1
Slowing (+)
Speeding (–)
CAL
Calibration. The CAL bits along with S determine the calibration amount as shown in Table 12.
Table 12. Calibration
CAL (DEC)
S = 0
+0 ppm
S = 1
–0 ppm
0
1
+2 ppm
–4 ppm
N
+N / 491520 (per minute)
+61 ppm
–N / 245760 (per minute)
–122 ppm
30
31
+63 ppm
–126 ppm
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Table 13. CFG2 Register
Address
0x09
Name
CFG2
Initial Value
Description
10101010b
Configuration 2
D7
RSVD
r/w
1
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
RSVD
RSVD
r/w
RSVD
r/w
r/w
0
Read/Write
Initial
1
0
1
1
0
0
1
1
0
0
1
0
UC
UC
Cycle
RSVD
Reserved. The RSVD bits should always be written as 0.
7.6.3 Special Function Registers
Table 14. SF KEY 1 Register
Address
0x20
Name
SF KEY 1
Initial Value
Description
00000000b
Special function key 1
D7
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
SF KEY B1
r/w
Read/Write
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cycle
SF KEY B1
Special function access key byte 1. Reads as 0x00, and key is 0x5E.
The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to
SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the
SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2.
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Table 15. SF KEY 2 Register
Address
0x21
Name
SF KEY 2
Initial Value
Description
00000000b
Special function key 2
D7
D6
D5
D4
D3
D2
D1
D0
BIT(S)
Name
SF KEY 2
r/w
Read/Write
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cycle
SF KEY 2
Special function access key byte 2. Reads as 0x00, and key is 0xC7.
The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to
SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the
SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2.
Table 16. SFR Register
Address
0x22
Name
SFR
Initial Value
Description
00000000b
Special function register 1
D7
D6
D5
D4
RSVD
r/w
0
D3
D2
D1
D0
FTF
r/w
0
BIT(S)
Name
Read/Write
Initial
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cycle
RSVD
FTF
Reserved. The RSVD bits should always be written as 0.
Force calibration to 1 Hz. FTF allows the frequency of the calibration output to be changed from 512 Hz to 1 Hz. By
default, FTF is cleared, and the RTC outputs a 512-Hz calibration signal. Setting FTF forces the calibration signal to 1
Hz, and the calibration tracks the internal ppm adjustment. Note: The default 512-Hz calibration signal does not include
the effect of the ppm adjustment.
0
1
Normal 512-Hz calibration
1-Hz calibration
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The typical application for the BQ32002 is to provide precise time and date to a system. The backup power
supply provides additional reliability by automatically switching over from the main supply when it drops under the
voltage threshold.
8.2 Typical Application
The following design is a common application of the BQ32002.
V
CC
bq32002
V
OSCI
CC
32.768 kHz
1 µF
4.7 kΩ 4.7 kΩ 4.7 kΩ
OSCO
IRQ
SCL
SDA
V
BACK
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Typical Application Schematic
8.2.1 Design Requirements
Table 17 lists the parameters for this design example.
Table 17. Design Parameters
DESIGN PARAMETER
Supply Voltage
REFERENCE
VCC
EXAMPLE VALUE
3.3 V
Backup Supply
VBACK
XT
BR1225
Crystal Oscillator
32.768 kHz
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8.2.2 Detailed Design Procedure
8.2.2.1 Reading From a Register
The report details the read-back of the SECONDS register. Figure 9 depicts the first condition that will be used
as a benchmark to compare the values taken from the SECONDS register in the BQ32002, to the internal PC
time of the oscilloscope. In this example two modes of operation are demonstrated.
Condition 1 The main power supply, VCC, is greater than the backup power supply, VBACK, and the internal
reference voltage, VREF. In this mode, the device's internal registers are fully operational with READ
and WRITE access. Analyzing Figure 9, the known register values are compared to the system
clock; in this case, the PC clock which is shown at the bottom of the screen capture.
The BQ32002 during this condition is reading back [101][0010]= [5][2], which corresponds to
52 seconds at PC time of 2:22:43 PM.
Condition 2 VCC is now lowered to 2 V (VBACK > VCC). In this mode, the I2C communications are halted.
However, the internal time-keeping registers maintain full functional operation and accuracy which
will be available to be reliably read by the controller 1 second after the RTC switches from VBACK to
VCC supply.
Condition 3 During this final test condition, the RTC is restored to operate from the main power supply and I2C
communications are now fully functional.
Figure 10 demonstrates a read-back value from the SECONDS register of [100][0101]=
[4][5], or 45 seconds at PC time of 2:23:36 PM. This proves that the BQ32002 managed to
accurately maintain the time-keeping registers functional while the VCC dropped below VBACK
.
8.2.2.2 Leap Year Compensation
The BQ32002 classifies a leap year as any year that is evenly divisible by 4. Using this rule allows for reliable
leap year compensation until 2100. Years that fall outside this rule will need to be compensated for by the
external controller.
8.2.2.3 Utilizing the Backup Supply
In order for the BQ32002 to achieve a low backup supply current as specified in the Electrical Characteristics,
the VCC pin must be initialized after every total power loss situation. Initialization Is achieved by powering on VCC
with a voltage between 3 to 3.6 V for at least 1 ms immediately after the backup supply is connected. If the VCC
is not powered on while connecting the backup supply, then the expected leakage current from VBACK will be
much greater than specified.
8.2.3 Application Curves
Figure 9. Master and Slave I2C Communication for the
SECONDS Register
Figure 10. Master and Slave I2C Communication for the
SECONDS Register After Recovering from the Backup
Supply
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9 Power Supply Recommendations
The BQ32002 is designed to operate from an input voltage supply, VCC, range between 3 and 3.6 V. The user
must place a minimum of 1-µF ceramic bypass capacitor rated for at least the maximum voltage as close as
possible to VCC and GND pin.
10 Layout
10.1 Layout Guidelines
The VCC pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a minimum
recommended value of 1 µF. This capacitor must be placed as close to the VCC and GND pins as possible with
thick trace or ground plane connection to the device GND pin.
Locate the 32.768-kHz crystal oscillator as close as possible to the OSCI and OSCO pins. This will minimize
stray capacitance.
10.2 Layout Example
1 µF
VCC
OSCI
____
IRQ
OSCO
0.22F
SCL
VBACK
SDA
GND
Figure 11. Recommended PCB Layout
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ32002D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
32002
32002
BQ32002DR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ32002DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
BQ32002DR
D
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
BQ32002D
D
8
75
506.6
8
3940
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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