BQ4015MA-120 [TI]
512Kx8 Nonvolatile SRAM; 512Kx8非易失SRAM
| 型号： | BQ4015MA-120 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 512Kx8 Nonvolatile SRAM |
| 文件： | 总13页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4015/Y
512Kx8 Nonvolatile SRAM
is unconditionally write-protected to
prevent an inadvertent write opera-
tion.
- Snap-on power-source for
Features
lithium battery backup
➤ Data retention for at least 10
years without power
- Replaceable power-source
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns
valid.
(part number: bq40MS)
➤ Automatic write-protection during
power-up/power-down cycles
General Description
➤ Conventional SRAM operation,
including unlimited write cycles
The bq4015/Y uses extremely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EE-
PROM.
The CMOS bq4015/Y is a nonvola-
tile 4,194,304-bit static RAM organ-
ized as 524,288 words by 8 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
limited write cycles of standard
SRAM.
➤ Internal isolation of battery be-
fore power application
➤ Industry standard 32-pin DIP
pinout
➤ 34-pin LIFETIME LITHIUM™
The bq4015/Y requires no external
circuitry and is compatible with the
industry-standard 4Mb SRAM pin-
out.
module
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When
VCC falls out of tolerance, the SRAM
- Module completely
surface-mounted
Pin Connections
Pin Names
A0–A18
Address inputs
DQ0–DQ7 Data input/output
A
32
1
V
CC
18
A
A
31
30
2
3
4
A
A
WE
16
14
15
17
NC
A15
A16
A18
1
2
34
CE
Chip enable input
Output enable input
Write enable input
No connect
33 A17
A
29
28
27
26
25
24
23
22
21
20
19
18
17
12
3
32 A14
31 A13
30 A12
29 A11
28 A10
27 A9
5
A
A
A
A
A
A
A
13
NC
4
7
6
5
4
3
2
VCC
WE
OE
5
OE
6
7
8
9
10
11
12
13
14
15
16
A
A
9
A
OE
A
CE
DQ
DQ
DQ
DQ
DQ
8
6
7
8
CE
11
WE
NC
VCC
VSS
DQ7
A8
25 A7
9
26
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VSS
10
11
12
24
23
22
21
20
19
A6
A5
A4
A3
A2
A1
10
A
1
0
0
1
2
13
14
15
16
17
A
DQ
DQ
DQ
7
6
5
4
3
Supply voltage input
Ground
18 A0
V
SS
34-Pin LIFETIME LITHIUM Module
PN4015Yncm.eps
32-Pin DIP Module
PN401501.eps
Selection Guide
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Maximum
Negative
Supply
Tolerance
Part
Number
Part
Number
Access
Time (ns)
bq4015x -70
bq4015x -85
70
85
-5%
-5%
bq4015Yx -70
bq4015Yx -85
70
85
-10%
-10%
Note: x = MA for PDIP or MS for LIFETIME LITHIUM module.
5/99 E
1
bq4015/Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4015/Y operates as a stan-
dard CMOS SRAM. During power-down and power-up
cycles, the bq4015/Y acts as a nonvolatile memory, auto-
matically protecting and preserving the memory con-
tents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC
. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly moni-
tors the VCC supply for a power-fail-detect threshold
V
PFD. The bq4015 monitors for VPFD = 4.62V typical for
The internal coin cells used by the bq4015/Y have an ex-
tremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
use in systems with 5% supply tolerance. The bq4015Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
As shipped from Unitrode, the integral lithium cells of
the MT-type module are electrically isolated from the
memory. (Self-discharge in this condition is approxi-
mately 0.5% per year.) Following the first application of
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs be-
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
V
CC, this isolation is broken, and the lithium backup
provides data retention on subsequent power-downs.
The LIFETIME LITHIUM package option is shipped as
two parts.
Block Diagram
OE
A –A
0
18
1024K x 8
SRAM
WE
Block
DQ –DQ
0
7
CE
CON
Power
CE
V
Power-Fail
Control
CC
Lithium
Cell
BD4015.eps
2
bq4015/Y
Truth Table
Mode
CE
H
L
WE
X
OE
X
I/O Operation
High Z
High Z
DOUT
Power
Standby
Active
Active
Active
Not selected
Output disable
Read
H
H
L
L
H
Write
L
L
X
DIN
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
VT ≤ VCC + 0.3
-0.3 to 7.0
V
0 to +70
-40 to +85
-40 to +70
-40 to +85
-10 to +70
-40 to +85
+260
°C
°C
°C
°C
°C
°C
°C
Commercial
TOPR
Operating temperature
Storage temperature
Temperature under bias
Industrial “N”
Commercial
TSTG
Industrial “N”
Commercial
TBIAS
Industrial “N”
For 10 seconds
TSOLDER Soldering temperature
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
3
bq4015/Y
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
Parameter
Minimum
4.5
Typical
Maximum
Unit
V
Notes
bq4015Y
bq4015
5.0
5.0
0
5.5
5.5
VCC
Supply voltage
4.75
0
V
VSS
VIL
VIH
Supply voltage
0
V
Input low voltage
Input high voltage
-0.3
-
0.8
V
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (T = T
, V
OPR CCmin
≤ V
≤ V
)
CCmax
A
CC
Symbol
Parameter
Minimum Typical
Maximum
Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
1
µA
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
-
-
1
µA
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
0.4
5
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
3
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2
ISB2
Standby supply current
Operating supply current
-
-
0.1
-
1
mA
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA,
A17 < VIL or A17 > VIH
A18 < VIL or A18 > VIH
ICC
90
,
4.55
4.30
-
4.62
4.37
3
4.75
4.50
-
V
V
V
bq4015
VPFD
Power-fail-detect voltage
Supply switch-over voltage
bq4015Y
VSO
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
CI/O
CIN
Parameter
Input/output capacitance
Input capacitance
Minimum
Typical
Maximum
Unit
pF
pF
Conditions
Output voltage = 0V
Input voltage = 0V
-
-
-
-
8
10
Note:
These parameters are sampled and not 100% tested.
4
bq4015/Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = T
A
, V
≤ V
CC
≤ V
)
OPR CCmin
CCmax
-70
-85/-85N
-120/-120N
Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
tRC
Read cycle time
70
-
-
85
-
-
120
-
-
120
120
60
-
tAA
Address access time
70
70
35
-
85
85
45
-
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
tACE
tOE
Chip enable access time
-
-
-
Output enable to output valid
Chip enable to output in low Z
-
-
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
5
0
0
10
5
0
0
0
10
5
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-
-
0
-
25
25
-
35
25
-
0
45
35
-
0
10
5
bq4015/Y
Read Cycle No. 1 (Address Access) 1, 2
Read Cycle No. 2 (CE Access) 1, 2, 3
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
6
bq4015/Y
Write Cycle (T = T
, V
OPR CCmin
≤ V
CC
≤ V
)
CCmax
A
-70
-85/-85N
-120/-120N
Min. Max. Min. Max. Min. Max.
Symbol
tWC
Parameter
Write cycle time
Chip enable to end of write
Units
ns
Conditions/Notes
70
65
65
-
-
-
85
75
75
-
-
-
120
100
100
-
-
-
tCW
ns
(1)
(1)
tAW
Address valid to end of write
ns
Measured from address
valid to beginning of
write. (2)
tAS
Address setup time
0
55
5
-
-
-
-
-
-
-
0
65
5
-
-
-
-
-
-
-
0
85
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Measured from begin-
ning of write to end of
write. (1)
tWP
Write pulse width
Measured from WE go-
ing high to end of write
cycle. (3)
Write recovery time
(write cycle 1)
tWR1
tWR2
tDW
tDH1
Measured from CE going
high to end of write cy-
cle. (3)
Write recovery time
(write cycle 2)
15
30
0
15
35
0
15
45
0
Measured to first low-
to-high transition of ei-
ther CE or WE.
Data valid to end of write
Measured from WE go-
ing high to end of write
cycle. (4)
Data hold time
(write cycle 1)
Measured from CE going
high to end of write cy-
cle. (4)
Data hold time
(write cycle 2)
tDH2
10
10
10
Write enabled to output in
high Z
I/O pins are in output
state. (5)
tWZ
0
5
25
-
0
0
30
-
0
0
40
-
ns
ns
Output active from end of
write
I/O pins are in output
state. (5)
tOW
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
7
bq4015/Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
8
bq4015/Y
Power-Down/Power-Up Cycle (T = T
)
OPR
A
Symbol
tPF
Parameter
Minimum
Typical
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
-
-
-
-
-
-
tFS
µs
tPU
VCC slew, VSO to VPFD (max.)
µs
Time during which
SRAM is write-protected
after VCC passes VPFD on
power-up.
tCER
Chip enable recovery time
40
10
40
80
-
120
-
ms
years
µs
Data-retention time in
absence of VCC
T
A = 25°C. (2)
tDR
Delay after VCC slews
down past VPFD before
SRAM is write-
tWPT
Write-protect time
100
150
protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9
bq4015/Y
MA: 32-Pin A-Type Module
(
)
32-Pin MA A-Type Module
Dimension
Minimum
0.365
0.015
0.017
0.008
1.670
0.710
0.590
0.090
0.120
0.075
Maximum
0.375
-
A
A1
B
C
D
E
e
0.023
0.013
1.700
0.740
0.630
0.110
0.150
0.110
G
L
S
All dimensions are in inches.
MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module
34-Pin LCR LIFETIME LITHIUM Module
Dimension
Minimum
0.920
0.980
-
Maximum
0.930
0.995
0.080
0.060
0.055
0.025
0.030
0.090
0.073
A
B
C
D
E
F
G
H
J
0.052
0.045
0.015
0.020
-
0.053
All dimensions are in inches.
1
2
3
Centerline of lead within ±±0±±ꢀ of true position0
Leads coplanar within ±±0±±ꢁ at seatinꢂ plane0
Components and location may vary0
10
bq4015/Y
MS: LIFETIME LITHIUM Module Housing
LIFETIME LITHIUM Module Housing
Dimension
Minimum
0.845
Maximum
0.855
A
B
C
D
E
0.955
0.965
0.210
0.220
0.065
0.075
0.065
0.075
All dimensions are in inches.
1
Edꢂes coplanar within ±±0±2ꢀ0
MS: LIFETIME LITHIUM Module with LCR attached
LIFETIME LITHIUM Module
Dimension
Minimum
0.955
Maximum
0.965
A
B
C
D
E
F
0.980
0.995
0.240
0.250
0.052
0.060
0.045
0.055
0.015
0.025
All dimensions are in inches.
1
2
Leads coplanar within ±±0±±ꢁ at seatinꢂ plane0
Components and location may vary0
11
bq4015/Y
Data Sheet Revision History
Change No.
Page No.
3
Description
ICC test conditions
Nature of Change
Clarification
Addition
1
2
1, 2, 3, 4, 7, 8, 10
bq4015MA part
Added industrial temperature
range
Addition
3
2, 10
4
5
1, 3, 10
1, 10
Removed MB package selection
Added MS package
Deletion
Addition
Notes:
Change 1 = Sept. 1992 B changes from Sept. 1990 A.
Change 2 = Nov. 1993 C changes from Sept. 1992 B.
Change 3 = June 1995 C changes from Nov. 1993 C.
Change 4 = Nov. 1997 D changes from June 1995 C.
Change 5 = May 1999 E changes from Nov. 1997 D.
Ordering Information
bq4015 xx -
Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)1
Speed Options:
70 = 70 ns
85 = 85 ns
120 = 120 ns
Package Option:
MA = A-type Module
MS = LIFETIME LITHIUM LCR34 (preliminary package option)2
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4013 128K x 8 NVSRAM
Notes:
1. Only 10% supply (“Y-MA”) version is available in industrial
temperature range; contact factory for speed grade availability.
2. The LIFETIME LITHIUM module is ordered seperately under
part number bq40MS.
12
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