BQ40Z60RHBR [TI]
完整的多节电池管理器 | 电池电量监测计 | RHB | 32 | -40 to 85;
| 型号： | BQ40Z60RHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 完整的多节电池管理器 | 电池电量监测计 | RHB | 32 | -40 to 85 电池 |
| 文件： | 总46页 (文件大小：2032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
bq40z60 可编程电池管理单元
1 特性
3 说明
1
•
全集成 2 节至 4 节串联锂离子或锂聚合物电池管理
单元
德州仪器 (TI) bq40z60 器件是一款可编程的电池管理
单元，其集成有电池充电控制输出、电量监测和相关保
护功能，能够完全自主地操作 2 至 4 节串联锂离子和
锂聚合物电池组。此架构在电量监测处理器与电池充电
器控制器之间实现内部通信，从而在系统负载瞬变和适
配器电流限制期间根据外部负载条件和电源路径来源管
理来优化充电量。可通过 NFET、电感和感测电阻等外
部元件针对具体功率传输情况来调节充电电流效率。
•
•
•
•
Pack+ 上的输入电压范围：2.5V 至 25V
电池充电器效率 > 92%
电池充电器工作范围：4V 至 25V
针对外部 N 沟道场效应晶体管 (NFET) 的电池充电
器 1MHz 同步降压控制器
–
–
–
软启动，限制浪涌电流
外部开关限流保护
可编程充电
器件信息(1)
器件型号
bq40z60
封装
VQFN (32)
封装尺寸（标称值）
–
支持 JEITA/增强型充电模式
5.00mm × 5.00mm
•
电量监测
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
–
–
用于库伦计数器的 16 位高分辨率积分器
16 位模数转换器 (ADC)，通过 16 通道多路复
用器实现电压、电流和温度的精密测量
简化电路原理图
Power
–
–
同步恒流 (CC) 和 ADC 采样支持（功率转换）
支持两线制 SMBus v2.0 接口，工作频率选项
最高可设定为 400kHz
Adapter
FUSE
–
SHA-1 哈希消息验证码 (HMAC) 响应器，用于
提高电池组安全性
–
存储在安全存储器中的分裂密钥 (Split Key)
(2 × 64)
AFEFUSE
SMBD
SMBC
SMBD
SMBC
DSG
CHG
–
支持字段更新
GPIO0
GPIO1
GPIO0
GPIO1
BAT
VC4
•
模拟前端 (AFE) 保护
可编程电流保护
VC3
VC2
VC1
–
–
–
–
放电过流
充电短路
放电短路
Pack–
•
•
•
•
N-FET 高侧保护 FET 驱动
Copyright © 2017, Texas Instruments Incorporated
支持 4 个发光二极管 (LED)
负温度系数 (NTC) 热敏电阻输入
32 引脚紧凑型四方扁平无引脚 (QFN) 封装 (RHB)
2 应用
•
笔记本电脑、超极本、上网本、平板电脑和超便携
移动个人电脑 (UMPC)
医疗与测试设备
便携式仪表
•
•
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSAW3
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
目录
7.32 Battery Charger Current Sense (HSRP, HSRN)... 14
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Supply Voltage.......................................................... 6
7.6 Supply Current .......................................................... 7
7.7 Power Supply Control ............................................... 7
7.8 Low-Voltage General Purpose I/O (TSx) .................. 7
7.9 High-Voltage General Purpose I/O (GPIO0, GPIO1) 8
7.10 AFE Power-On Reset ............................................. 8
7.11 Internal 1.8-V LDO................................................. 8
7.12 Current Wake Comparator...................................... 9
7.13 Coulomb Counter.................................................... 9
7.14 CC Digital Filter....................................................... 9
7.15 ADC......................................................................... 9
7.16 ADC Digital Filter .................................................. 10
7.17 ADC Multiplexer .................................................... 10
7.18 Cell Balancing Support ......................................... 10
7.19 Cell Detach Detection ........................................... 10
7.20 Internal Temperature Sensor ................................ 11
7.21 NTC Thermistor Measurement Support (ADCx)... 11
7.22 High-Frequency Oscillator..................................... 11
7.23 Low-Frequency Oscillator ..................................... 11
7.24 Voltage Reference 1 ............................................. 11
7.25 Voltage Reference 2 ............................................. 12
7.26 Instruction Flash.................................................... 12
7.27 Data Flash............................................................. 12
7.28 Current Protection Thresholds .............................. 12
7.29 N-CH FET Drive (CHG, DSG)............................... 13
7.30 FUSE Drive (AFEFUSE) ....................................... 14
7.31 Battery Charger Voltage Regulation (VFB)........... 14
7.33 Battery Charger Precharge Current Sense (HSRP,
HSRN)...................................................................... 15
7.34 AC Adapter Fault Detect (HSRN, VCC)................ 15
7.35 Battery Charger Overcurrent Detection (V)HSRP
(V)HSRN..................................................................... 15
7.36 Battery Charger Undercurrent Detection (V)HSRP
,
,
(V)HSRN..................................................................... 15
7.37 System Operation Detection (V)HSRN.................... 15
7.38 Battery Overvoltage Comparator (VFB)................ 15
7.39 Regulator (REGN)................................................. 16
7.40 PWM High-Side Driver (HiDRV) ........................... 16
7.41 PWM Low-Side Driver (LoDRV)............................ 16
7.42 PWM Information .................................................. 16
7.43 Charger Power-Up Sequence............................... 16
7.44 Thermal Shutdown Comparator............................ 16
7.45 SMBus High Voltage I/O....................................... 17
7.46 SMBus................................................................... 17
7.47 SMBus XL ............................................................. 17
7.48 Timing Requirements............................................ 18
7.49 Typical Characteristics ......................................... 18
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
Application and Implementation ........................ 29
9.1 Application Information .......................................... 29
9.2 Typical Applications ................................................ 30
8
9
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example ................................................... 36
12 器件和文档支持 ..................................................... 37
12.1 相关文档ꢀ ............................................................ 37
12.2 社区资源................................................................ 37
12.3 商标....................................................................... 37
12.4 静电放电警告......................................................... 37
12.5 Glossary................................................................ 37
13 机械、封装和可订购信息....................................... 37
4 修订历史记录
Changes from Revision C (July 2015) to Revision D
Page
•
•
•
•
•
•
•
•
•
已更改 简化电路原理图........................................................................................................................................................... 1
Changed Pin Configuration and Functions............................................................................................................................. 3
Changed Absolute Maximum Ratings ................................................................................................................................... 5
Changed Recommended Operating Conditions .................................................................................................................... 6
Changed High-Voltage General Purpose I/O (GPIO0, GPIO1) ............................................................................................. 8
Changed Detailed Description Overview ............................................................................................................................. 19
Changed Functional Block Diagram .................................................................................................................................... 20
Changed Internal Power Source Selection........................................................................................................................... 22
Changed Power Path Overview .......................................................................................................................................... 25
2
Copyright © 2014–2017, Texas Instruments Incorporated
bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
修订历史记录 (continued)
•
已更改 Typical Application Schematic ................................................................................................................................. 30
5 说明 （续）
该器件提供了电池阵列和系统安全功能，包括电池放电过流、充电短路和放电短路保护，以及针对 N 沟道 FET 的
FET 保护、内部 AFE 看门狗和电池断开连接检测。器件可通过固件提供更多保护 功能， 包括过压、欠压、过热
等。
6 Pin Configuration and Functions
QFN Package (RHB)
32 Pins
'()
+'0
&
2
3
*
6
9
7
5
2*
23
22
2&
2/
&#
&5
&7
+",-
1ꢀ",
$
$ *
$ 3
$ 2
$ &
%1,
%1+
(ꢁꢀꢁ4%ꢀ
!%1+
!%1,
$ꢁ'
)CBDE@A
+@F
%;'
,<= =< >?@AB
Pin Functions
PIN
DESCRIPTION
NAME
BAT
NUMBER
I/O(1)
P
1
2
Battery input pin. Primary power supply
Power supply backup input pin
PBI
P
Sense voltage input pin for the most positive cell, balance current input for the most positive cell,
and battery stack measurement input
VC4
3
4
5
6
7
8
IA
IA
IA
IA
IA
IA
Sense voltage input pin for the third most positive cell, balance current input for the third most
positive cell, and return balance current for the most positive cell
VC3
VC2
VC1
SRN
SRP
Sense voltage input pin for the second most positive cell, balance current input for the second
most positive cell, and return balance current for the most positive cell
Sense voltage input pin for the least positive cell, balance current input for the least positive cell,
and return balance current for the second most positive cell
Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN, where SRP is the top of the sense resistor.
Analog input pin connected to the internal coulomb counter peripheral for integrating a small
voltage between SRP and SRN, where SRP is the top of the sense resistor.
VSS
TS1
TS2
TS3
TS4
9
P
Device ground
10
11
12
13
IA
IA
IA
IA
Thermistor input for temperature sensor channel 1
Thermistor input for temperature sensor channel 2
Thermistor input for temperature sensor channel 3
Thermistor input for temperature sensor channel 4
Multi-function I/O (open drain). For more information, see IO Configuration in the bq40z60
Technical Reference Manual (SLUUA04).
GPIO0
14
I/O
(1) P = Power Connection, O = Digital Output, IA = Analog Input, I = Digital Input, I/OD = Digital Input/Output
Copyright © 2014–2017, Texas Instruments Incorporated
3
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Pin Functions (continued)
PIN
DESCRIPTION
NAME
GPIO1
NUMBER
I/O(1)
Multi-function I/O (open drain). See IO Configuration in the bq40z60 Technical Reference Manual
(SLUUA04).
15
I/O
SMBD
SMBC
VFB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/OD
I/OD
IA
IA
IA
O
SMBus data pin
SMBus clock pin
Feedback sense input for charger control loop
High sense resistor negative node input
High sense resistor positive node input
Fuse drive output pin
HSRN
HSRP
AFEFUSE
VCC
P
Power supply input
REGN
PGND
LODRV
PH
O
Charger FET gate drive regulator
Power ground
P
O
Low side charging FET gate control output
Charger phase signal input
High side charging FET gate control output
High side bootstrap capacitor input
AC FET gate control output
N-CH FET drive output pin
Adapter input pin
I/O
O
HIDRV
BTST
ACFET
DSG
IA
O
O
ACP
IA
O
CHG
N-CH FET drive output pin
4
Copyright © 2014–2017, Texas Instruments Incorporated
bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
TYP
MAX
UNIT
V
BAT, VCC, PBI
30
Supply voltage
range, VSupply
REGN
7
V
ACP, SMBC, SMBD, GPIO0, GPIO1
30
V
TS1, TS2, TS3, TS4
SRP, SRN
HSRP, HSRN
PH
VREG + 0.3
V
0.3
30
32
16
V
V
V
VFB
V
Input voltage range,
VIN
VC3 + 8.5 V,
or VSS + 30
VC4
VC3
VC2
VC1
VC3 – 0.3
VC2 – 0.3
VC1 – 0.3
VSS – 0.3
V
V
V
V
VC2 + 8.5 V,
or VSS + 30
VC1 + 8.5 V,
or VSS + 30
VSS + 8.5 V,
or VSS + 30
CHG, DSG
–0.3
–0.3
–0.3
–0.3
32
36
7
V
V
HIDRV, BTST, ACFET
LODRV
Output voltage
range, VO
V
AFEFUSE
30
V
Maximum VSS current, ISS
50
mA
°C
Functional Temperature, TFUNC
–40
110
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
HBM(1)
CDM(2)
V(ESD) Rating
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
2.2
0
NOM
MAX UNIT
BAT, VCC, PBI
ACFET, BTST
26
35
V
V
V
V
V
VSupply
Supply voltage
REGN
0
6.5
VSHUTDOWN–
Shutdown voltage
VACP < VSHUTDOWN–
VACP > VSHUTDOWN– + VHYS
1.8
2.05
2.0
2.2
VSHUTDOWN+ Start-up voltage
2.25
2.45
Shutdown voltage
hysteresis
VHYS
VSHUTDOWN+ – VSHUTDOWN–
250
mV
Copyright © 2014–2017, Texas Instruments Incorporated
5
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Recommended Operating Conditions (continued)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX UNIT
ACP, SMBC, SMBD, GPIO0, GPIO1
26
VREG
0.2
TSx
SRP, SRN
–0 .2
–0 .5
–2
HSRP, HSRN
0.5
PH
VACP
VIN
Input voltage range
V
VFB
0
14
VC4
VVC3
VVC2
VVC1
VVSS
VVC3 + 5
VC3
VVC2 + 5
VVC1 + 5
VVSS + 5
26
VC2
VC1
CHG, DSG, AFEFUSE
HIDRV
V
V
V
Output voltage
range
VO
35
LODRV
0
6.5
External PBI
capacitor
CPBI
2.2
µF
°C
Operating
temperature
TOPR
–40
85
7.4 Thermal Information
bq40z60
THERMAL METRIC(1)
RHB (VQFN)
UNIT
32 PINS
36
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
31.5
8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.5
ψJB
7.9
RθJCbot
2.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Supply Voltage
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Operation with charger enabled
Operation with charger disabled
VCC falling
MIN
4.0
2.5
2.2
TYP
MAX
25
UNIT
VCC
Device Operating Range
V
25
VCC-UV Undervoltage lock out
2.45
V
6
Copyright © 2014–2017, Texas Instruments Incorporated
bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
7.6 Supply Current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CPU = ACTIVE, HFO = ON, ADC_FILTER = ON,
CC_FILTER = ON, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = ON, CC = ON, Charger
Enabled, No Communication
1250
1850
INORMAL
NORMAL mode(1)
µA
CPU = HALT, HFO = ON, ADC_FILTER = ON,
CC_FILTER = ON, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = ON, CC = ON, Charger
Disabled, No Communication
310
122
92
445
183
138
128
83
CPU = HALT, HFO = ON, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = OFF, CC = OFF, Charger
Disabled, No Communication
CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= ON, DSG = ON, ADC = OFF, CC = OFF, Charger
Disabled, No Communication
ISLEEP
SLEEP mode(1)
µA
CPU = HALT, HFO = ON, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication
82
CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = ON, REG18 = ON, CHG
= OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication
52
CPU = HALT, HFO = OFF, ADC_FILTER = OFF,
CC_FILTER = OFF, LFO = OFF, REG18 = OFF,
CHG = OFF, DSG = OFF, ADC = OFF, CC = OFF,
Charger Disabled, No Communication
ISHUTDOWN
SHUTDOWN mode
0.5
2
µA
(1)
VCC ≤ 20 V when CHG = ON and DSG = ON
7.7 Power Supply Control
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT < VSWITCHOVER–
VBAT > VSWITCHOVER– + VHYS
MIN
TYP
MAX UNIT
BAT to VCC
VSWITCHOVER–
VSWITCHOVER+
VHYS
2.0
2.1
2.2
3.2
V
V
switchover voltage
VCC to BAT
3.0
3.1
switchover voltage
Switchover voltage
hysteresis
VSWITCHOVER+ – VSWITCHOVER–
1000
mV
BAT pin, BAT = 0 V, VCC = 25 V
VCC pin, BAT = 25 V, VCC = 0 V
1
1
Input leakage
current
ILKG
µA
BAT and VCC pins, BAT = 0 V, VCC = 0 V, PBI =
25 V
1
Internal pulldown
resistance
RPD
ACP
30
40
50
kΩ
7.8 Low-Voltage General Purpose I/O (TSx)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
High-level input
Low-level input
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
VIL
0.65 × VREG
V
0.35 × VREG
V
V
V
IOH = –1.0 mA
IOH = –10 µA
IOL = 1.0 mA
VOH
VOL
Output voltage high
Output voltage low
0.75 × VREG
0.2 × VREG
Copyright © 2014–2017, Texas Instruments Incorporated
7
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ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Low-Voltage General Purpose I/O (TSx) (continued)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CIN
Input capacitance
Input leakage current
5
pF
ILKG
1
µA
7.9 High-Voltage General Purpose I/O (GPIO0, GPIO1)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
High-level input
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
VIL
1.3
V
Low-level input
0.55
0.4
1
V
VBAT > 5.5 V, IOH = –0 µA
3.5
1.8
Output voltage
high
VOH
V
VBAT > 5.5 V, IOH = –10 µA
Output voltage
low
VOL
CIN
ILKG
RO
IOL = 1.5 mA
V
Input
capacitance
5
pF
µA
kΩ
Input leakage
current
Output reverse
resistance
Between GPIO0/1 and PBI
5
7.10 AFE Power-On Reset
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Negative-going
voltage input
VREGIT–
VREG
VREGIT+ – VREGIT–
1.51
1.55
1.59
V
Power-on reset
hysteresis
VHYS
tRST
70
100
300
130
400
mV
µs
Power-on reset time
200
7.11 Internal 1.8-V LDO
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Regulator voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
VREG
1.6
1.8
2.0
V
Regulator output
over temperature
ΔVO(TEMP)
ΔVREG/ΔTA, IREG = 10 mA
±0.25%
ΔVO(LINE)
ΔVO(LOAD)
Line regulation
Load regulation
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6%
–1.5%
0.5%
1.5%
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
Regulator output
current limit
IREG
VREG = 0.9 × VREG(NOM), VIN > 2.2 V
VREG = 0 × VREG(NOM)
20
25
mA
mA
dB
Regulator short-
circuit current limit
ISC
40
40
50
Power supply
rejection ratio
PSRRREG
ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz
Slew rate
VSLEW
enhancement
voltage threshold
1.58
1.65
V
8
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7.12 Current Wake Comparator
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VWAKE = VSRP – VSRN
MIN
±0.3
±0.6
±1.2
±2.4
TYP
±0.625
±1.25
±2.5
MAX UNIT
±0.9
VWAKE = VSRP – VSRN
VWAKE = VSRP – VSRN
VWAKE = VSRP – VSRN
±1.8
mV
Wake voltage
threshold
VWAKE
±3.6
±5.0
±7.2
Temperature drift
of VWAKE accuracy
VWAKE(DRIFT)
0.5%
0.25
500
°C
Time from
application of
current to wake
tWAKE
0.5
ms
µs
Wake comparator
startup time
tWAKE(SU)
1000
7.13 Coulomb Counter(1)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Input voltage range
TEST CONDITIONS
MIN
–0.1
TYP
MAX
0.1
UNIT
V
Full scale range
Integral nonlinearity(2)
Offset error
–VREF1/10
VREF1/10
±22.3
±10
V
16-bit, Best fit over input voltage range
16-bit, Post-calibration
±5.2
±5
LSB
µV
Offset error drift
Gain error
15-bit + sign, Post-calibration
0.2
0.3
µV/°C
15-bit + sign, Over input voltage range
15-bit + sign, Over input voltage range
±0.2%
±0.8% FSR(3)
150 PPM/°C
MΩ
Gain error drift
Effective input resistance
2.5
(1) Coulomb counter electrical specifications are assured when battery charging function is disabled.
(2) 1 LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71 µV
(3) Full-scale reference
7.14 CC Digital Filter
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Conversion time
TEST CONDITIONS
Single conversion
Single conversion
MIN
TYP
MAX
UNIT
ms
250
Effective resolution
15
Bits
7.15 ADC(1)
Over-operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal reference (VREF1
External reference (VREG
VFS = VREF1 or VREG
MIN
–0.2
–0.2
–VFS
TYP
MAX
1
UNIT
V
)
Input voltage range
)
0.8 × VREG
VFS
Full scale range
Integral nonlinearity(2)
Offset error(3)
V
16-bit, Best fit, –0.1 V to 0.8 × VREF1
16-bit, Best fit, –0.2 V to –0.1 V
16-bit, Post-calibration, VFS = VREF1
±6.6
LSB
µV
±13.1
±157
±67
(1) ADC electrical specifications are assured when battery charging function is disabled.
(2) 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when ADCTL[SPEED1, SPEED0] = 0, 0)
(3) For VC1–VSS, VC2–VC1, VC3–VC2, VC3–VSS, ACP–VSS, and VREF1/2, the offset error is multiplied by (1/ADC multiplexer scaling
factor (K)).
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ADC(1) (continued)
Over-operating free-air temperature range (unless otherwise noted)
PARAMETER
Offset error drift
TEST CONDITIONS
16-bit, Post-calibration, VFS = VREF1
16-bit, –0.1 V to 0.8 × VFS
MIN
TYP
0.6
MAX
UNIT
µV/°C
FSR
3
Gain error
±0.2%
±0.8%
Gain error drift
16-bit, –0.1 V to 0.8 × VFS
150 PPM/°C
Effective input resistance
8
MΩ
7.16 ADC Digital Filter
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADCTL[SPEED1, SPEED0] = 0, 0
MIN
TYP
31.25
15.63
7.81
MAX
UNIT
ADCTL[SPEED1, SPEED0] = 0, 1
Conversion time
ms
ADCTL[SPEED1, SPEED0] = 1, 0
ADCTL[SPEED1, SPEED0] = 1, 1
1.95
Resolution
No missing codes, ADCTL[SPEED1, SPEED0] = 0, 0
With sign, ADCTL[SPEED1, SPEED0] = 0, 0
With sign, ADCTL[SPEED1, SPEED0] = 0, 1
With sign, ADCTL[SPEED1, SPEED0] = 1, 0
With sign, ADCTL[SPEED1, SPEED0] = 1, 1
16
14
13
11
9
Bits
Bits
15
14
12
10
Effective resolution
7.17 ADC Multiplexer
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.1980
0.049
0.490
0.049
–0.2
TYP
0.2000
0.050
0.500
0.050
MAX
0.2020
0.051
UNIT
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
VC4–VSS, ACP–VSS
K
Scaling factor
—
VREF2
0.510
HSRN–VSS
0.051
VC4–VSS, ACP–VSS
20
VIN
Input voltage range
Input leakage current
TSx
TSx
–0.2
0.8 × VREF1
0.8 × VREG
V
–0.2
VC1, VC2, VC3, VC4, cell balancing off, cell
detach detection off, ADC multiplexer off
ILKG
1
µA
7.18 Cell Balancing Support
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal cell balance
resistance
RCB
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
200
Ω
7.19 Cell Detach Detection
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal cell detach
check current
ICD
VCx > VSS + 0.8 V
30
50
70
µA
10
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7.20 Internal Temperature Sensor
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
–1.9
TYP
–2.0
MAX
–2.1
UNIT
VTEMPP
VTEMPP – VTEMPN, assured by design
Internal temperature
sensor voltage drift
VTEMP
mV/°C
0.177
0.178
0.179
7.21 NTC Thermistor Measurement Support (ADCx)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal pullup
resistance
RNTC(PU)
14.4
18
21.6
kΩ
Resistance drift over
temperature
RNTC(DRIFT)
–360
–280
–200 PPM/°C
7.22 High-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fHFO
Operating frequency
16.78
MHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–2.5% ±0.25%
–3.5% ±0.25%
2.5%
3.5%
fHFO(ERR)
Frequency error
Start-up time
TA = –20°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator
frequency within +/–3% of nominal
4
ms
µs
tHFO(SU)
CLKCTL[HFRAMP] = 0, oscillator frequency within +/–3%
of nominal
100
7.23 Low-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Operating frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fLFO
262.144
kHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–1.5% ±0.25%
1.5%
2.5
fLFO(ERR)
Frequency error
–2.5
±0.25
Failure detection
frequency
fLFO(FAIL)
30
80
100
kHz
7.24 Voltage Reference 1
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF1
TA = 25°C, after trim
1.21
1.215
1.22
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF1(DRIFT)
PPM/°C
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7.25 Voltage Reference 2
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF2
TA = 25°C, after trim
1.22
1.225
1.23
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF2(DRIFT)
PPM/°C
7.26 Instruction Flash
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
Years
Flash programming
write cycles
1000
Cycles
µs
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
tMASSERASE
tPAGEERASE
IFLASHREAD
IFLASHWRITE
IFLASHERASE
Mass-erase time
Page-erase time
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
2
ms
ms
mA
mA
mA
Flash-read current TA = –40°C to 85°C
Flash-write current TA = –40°C to 85°C
Flash-erase current TA = –40°C to 85°C
5
15
7.27 Data Flash
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
Years
Flash programming
write cycles
20000
Cycles
µs
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
tMASSERASE
tPAGEERASE
IFLASHREAD
IFLASHWRITE
IFLASHERASE
Mass-erase time
Page-erase time
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
1
ms
ms
mA
mA
mA
Flash-read current TA = –40°C to 85°C
Flash-write current TA = –40°C to 85°C
Flash-erase current TA = –40°C to 85°C
5
15
7.28 Current Protection Thresholds
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OCD detection
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
–16.6
–100
VOCD
ΔVOCD
VSCC
threshold voltage
range
mV
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
–8.3
–50
OCD detection
threshold voltage
program step
–5.56
–2.78
mV
mV
SCC detection
threshold voltage
range
44.4
22.2
200
100
12
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Current Protection Thresholds (continued)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCC detection
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
22.2
ΔVSCC
threshold voltage
program step
mV
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0
11.1
SCD1 detection
threshold voltage
range
–44.4
–22.2
–200
–100
VSCD1
mV
mV
mV
SCD1 detection
threshold voltage
program step
–22.2
–11.1
ΔVSCD1
SCD2 detection
threshold voltage
range
–44.4
–22.2
–200
–100
VSCD2
SCD2 detection
threshold voltage
program step
–22.2
–11.1
ΔVSCD2
mV
mV
OCD, SCC, and
SCDx offset error
VOFFSET
VSCALE
Post-trim
–2.5
2.5
No trim
–10%
–5%
10%
5%
OCD, SCC, and
SCDx scale error
Post-trim
7.29 N-CH FET Drive (CHG, DSG)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT
4.07 V, 10 MΩ between HSRN and DSG
<
<
2.133
2.333
2.533
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT
4.07 V, 10 MΩ between BAT and CHG
Output voltage ratio
2.133
2.133
9.0
2.333
2.333
9.5
2.533
2.533
10
—
RatioACFET = (VACFET – VBAT)/VBAT, 2.2 V < VBAT
< 4.07 V, 10 MΩ between ACP and ACFET
VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.07 V, 10 MΩ
between VHSRN and DSG, VBAT = 18 V
Output voltage, CHG and
DSG on
VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.07 V, 10 MΩ
between BAT and CHG, VBAT = 18 V
V(FETON)
9.0
9.5
10
V
V
VACFET(ON) = VACFET – VBAT, VBAT ≥ 4.07 V, 10
MΩ between ACP and ACFET, VBAT = 18 V
ACFET
9.0
9.5
10
VDSG(OFF) = VDSG – VACP, 10 MΩ between HSRN
and DSG
–0.4
–0.4
–0.4
0.4
Output voltage, CHG and
DSG off
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT
and CHG
V(FETOFF)
0.4
VACFET(OFF) = VACFET – VACP, VBAT ≥ 4.07 V, 10
MΩ between ACP and ACFET, VBAT = 18 V
ACFET
0.4
VDSG from 0% to 35% VDSG(ON)(TYP), VACP ≥ 2.2 V,
CL = 4.7 nF between DSG and VHSRN, 5.1 kΩ
between DSG and CL, 10 MΩ between VHSRN and
DSG
200
200
200
500
500
500
VCHG from 0% to 35% VCHG(ON)(TYP), VACP ≥ 2.2
V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ
between CHG and CL, 10 MΩ between BAT and
CHG
tR
Rise time
µs
VACFET from 0% to 35% VACFET(ON)(TYP), VACP
≥
2.2 V, CL = 4.7 nF between ACFET and ACP, 5.1
kΩ between CHG and CL, 10 MΩ between ACP
and ACFET
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N-CH FET Drive (CHG, DSG) (continued)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDSG from VDSG(ON)(TYP) to 1 V, VACP ≥ 2.2 V, CL
= 4.7 nF between DSG and ACP, 5.1 kΩ between
DSG and CL, 10 MΩ between ACP and DSG
40
300
VCHG from VCHG(ON)(TYP) to 1 V, VACP ≥ 2.2 V, CL
= 4.7 nF between CHG and BAT, 5.1 kΩ between
CHG and CL, 10 MΩ between BAT and CHG
40
40
200
200
tF
Fall time
µs
VACFET from VACFET(ON)(TYP) to 1 V, VACP ≥ 2.2 V,
CL = 4.7 nF between ACFET and ACP, 5.1 kΩ
between CHG and CL, 10 MΩ between ACP and
ACFET
7.30 FUSE Drive (AFEFUSE)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8.65
VBAT
2.5
UNIT
V
BAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA
6
VBAT – 0.1
1.5
7
VOH
VIH
Output voltage high
V
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA
High-level input
2.0
150
2.6
5
V
IAFEFUSE(PU) Internal pullup current
V
BAT ≥ 8 V, VAFEFUSE = VSS
330
3.2
nA
kΩ
pF
µs
µs
RAFEFUSE
CIN
tDELAY
tRISE
Output impedance
2
Input capacitance
Fuse trip detection delay
Fuse output rise time
128
256
20
V
BAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V
5
7.31 Battery Charger Voltage Regulation (VFB)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VFB
Regulation range
Based on internal DAC reference setting
0.61
1.22
V
Voltage feedback
accuracy
VFBACC
VFB = 1.22 V
–2%
2%
Programmable regulation
steps
VFB(STEPS)
RVFB
2.5
mV
Total feedback resistor
divider range
500
700
kΩ
7.32 Battery Charger Current Sense (HSRP, HSRN)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC range for current measurement
VHSRP – VHSRN = 50 mV, RSense= 10 mΩ
MIN
TYP
MAX
100
5%
UNIT
VIN(Normal
range)
Differential Input range
Measurement accuracy
2
mV
VACC
–5%
14
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7.33 Battery Charger Precharge Current Sense (HSRP, HSRN)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN(Normal
range)
Differential Input range
DAC range for current measurement
2
20
mV
VHSRP – VHSRN = 2 mV, RSense= 10 mΩ
(VHSRN > 2.3 V)
VACC
Measurement accuracy
–70%
70%
7.34 AC Adapter Fault Detect (HSRN, VCC)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Battery > AC adapter input (Falling)
AC adapter input > Battery (Rising)
MIN
150
50
TYP
225
100
MAX
UNIT
AC adapter input fault
detect
VHSRN – VCC
VHys
300
mV
Recovery hysteresis
150
mV
7.35 Battery Charger Overcurrent Detection (V)HSRP, (V)HSRN
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Charger overcurrent
threshold
Charging current as a percentage of max sense
voltage range
IOC(max)
IOC(min)
180
200
mV
Charger overcurrent
threshold
Minimum charging overcurrent detected
45
55
mV
7.36 Battery Charger Undercurrent Detection (V)HSRP, (V)HSRN
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Detect under current for
negative inductor current
VHSRP – VHSRN < 0 mV, for negative inductor
current, VHSRP > 2.3 V
IUC(Detect)
1
5
16
mV
Minimum sense voltage to
IUC(Non-synch) enter non-synchronous
mode
1.7
mV
7.37 System Operation Detection (V)HSRN
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.05
100
TYP
2.15
150
MAX
2.25
200
UNIT
V
VHSRN
VHys
Input voltage for operation VHSRN Falling
Recovery hysteresis
VHSRN Rising
mV
7.38 Battery Overvoltage Comparator (VFB)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VFB > Set value (Rising)
VFB < VOV (Falling)
MIN
TYP
MAX
UNIT
Battery over-voltage
detection
VOV(max)
106%
Battery over-voltage
recovery
VOV(Recovery)
103%
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7.39 Regulator (REGN)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gate drive for low side
charger FET
VLODRV
VCC > 10 V, ILoad = 0 to 60 mA
5.7
6.0
6.3
V
I SC
Short circuit current limit
Power good indicator
Hysteresis
VLODRV = 0 V
VREGN Rising
VREGN Falling
60
3.6
mA
V
VREGN
VHys
3.68
260
3.75
280
240
mV
7.40 PWM High-Side Driver (HiDRV)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
6.0
2.5
2.9
4.1
MAX
8.6
UNIT
Ω
RON
Driver turn ON resistance VBTST – VPH ≥ 5.5 V
ROFF
Driver turn OFF resistance VFB < VOV (Falling)
3.3
Ω
VCC = 4 V to 6 V
VCC > 6 V
2.6
3.9
V
Bootstrap refresh
comparator
VBOOTSTRAP
V
7.41 PWM Low-Side Driver (LoDRV)
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RON
Driver turn ON resistance VREGN – VPGND ≥ 5.5 V
5.2
7.6
Ω
Driver turn OFF
VFB < VOV (Falling)
resistance
ROFF
1.9
2.4
Ω
7.42 PWM Information
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Deadtime between FET
driver output switching
tDEADTIME
30
ns
Duty cycle
fSW
99.5%
1.1
PWM switching frequency
0.8
1.0
MHz
7.43 Charger Power-Up Sequence
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tDELAY
Power-up sequence
Soft start steps
8
8
2
ms
tSS(STEPS)
tSS(STEP TIME) Soft start time
ms
7.44 Thermal Shutdown Comparator
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
135
12
MAX
UNIT
C
TSHUTDOWN
THys
145
C
16
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7.45 SMBus High Voltage I/O
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SMBC, SMBD, VREG = 1.8 V
MIN
TYP
MAX
UNIT
V
VIH
Input voltage high
Input voltage low
Output low voltage
Input capacitance
Input leakage current
pulldown resistance
1.3
VIL
SMBC, SMBD, VREG = 1.8 V
0.8
0.4
V
VOL
CIN
ILKG
RPD
SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA
V
5
pF
µA
MΩ
1
0.7
1.0
1.3
7.46 SMBus
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SMBus operating
frequency
fSMB
SLAVE mode, SMBC 50% duty cycle
10
100
kHz
SMBus master clock
frequency
fMAS
MASTER mode, no clock low slave extend
51.2
kHz
µs
Bus free time between
start and stop
tBUF
4.7
4.0
4.7
Hold time after
(repeated) start
tHD(START)
tSU(START)
µs
Repeated start setup
time
µs
tSU(STOP)
tHD(DATA)
tSU(DATA)
tTIMEOUT
tLOW
Stop setup time
Data hold time
4.0
300
250
25
µs
ns
ns
ms
µs
µs
ns
ns
Data setup time
Error signal detect time
Clock low period
Clock high period
Clock rise time
35
4.7
4.0
tHIGH
50
1000
300
tR
10% to 90%
90% to 10%
tF
Clock fall time
Cumulative clock low
slave extend time
tLOW(SEXT)
tLOW(MEXT)
25
10
ms
ms
Cumulative clock low
master extend time
7.47 SMBus XL
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSMBXL
tBUF
SMBus XL operating frequency SLAVE mode
40
400
kHz
Bus free time between start and
stop
4.7
µs
tHD(START)
tSU(START)
tSU(STOP)
tTIMEOUT
tLOW
Hold time after (repeated) start
Repeated start setup time
Stop setup time
4.0
4.7
4.0
5
µs
µs
µs
ms
µs
µs
Error signal detect time
Clock low period
20
20
20
tHIGH
Clock high period
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7.48 Timing Requirements
Typical values stated where TA = 25°C and VCC = 10.8 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
TYP
MAX
UNIT
CURRENT PROTECTION TIMING
OCD detection delay
time
tOCD
1
31
ms
ms
µs
OCD detection delay
ΔtOCD
2
time program step
SCC detection delay
time
tSCC
0
915
SCC detection delay
ΔtSCC
61
µs
time program step
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
0
0
915
SCD1 detection delay
time
tSCD1
µs
µs
µs
1850
61
SCD1 detection delay
ΔtSCD1
time program step
121
0
0
458
915
SCD2 detection delay
time
tSCD2
30.5
61
SCD2 detection delay
ΔtSCD2
µs
µs
time program step
Current fault detect
time
VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2,
VSRP – VSRN = VT + 3 mV for SCC
tDETECT
160
Current fault delay time
accuracy
tACC
Max delay setting
–10%
10%
7.49 Typical Characteristics
1050000
Typical Charger Switching Frequency
1040000
1030000
1020000
1010000
1000000
990000
980000
970000
960000
950000
-40
10
Temperature (°C)
60
C001
Figure 1. Charger Switching Frequency Across Temperature
18
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8 Detailed Description
8.1 Overview
The bq40z60 is a fully integrated battery manager that employs flash-based firmware and integrated hardware
protection to provide a complete solution for 2-series to 4-series cell battery stack architectures. The bq40z60
interfaces with a host system via an SBS v1.1-compliant SMBus interface, and processes instructions and data
using a state-of-the-art, ultra-low-power TI bqBMP CPU. High-performance, integrated analog peripherals enable
support for a sense resistor down to 5 mΩ, battery charge control, and simultaneous current/voltage data
conversion for instant power calculations.
The bq40z60 controls the cell charging profile based on user-programmed data flash parameters for charging
current and voltage based on temperature and cell voltage. The gas gauge provides the cell voltage and
charging information to the battery charging through an internal communication bus. The charger function is
controlled based on cell voltage measurements both on individual cell and total series stack readings.
The analog front end provides this voltage-based information to the charging circuit to set the profiles pre-
programmed in the data flash settings, which are useful for zero voltage and PRECHARGE mode operation. The
following sections detail all of the major component blocks in the bq40z60 device.
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8.2 Functional Block Diagram
Cell
Balancing
Cell Detach
Detection
Cell, Stack,
Pack
Voltage
High-Side
N-CH FET
Drive
Power Mode
Control
Zero-Volt
Charge
Control
Power On
Reset
Fuse
Control
AFEFUSE
AC FET High
Side N-CH
FET Drive
ACFET
High
Voltage I/O
GPIO1
GPIO0
Watchdog
Timer
VCC
Wake
Comparator
High-Side
Current Sense/
Voltage
HSRP
HSRN
VFB
SRP
SRN
Voltage
Reference2
Feedback
Short Circuit
Comparator
High-Side
N-CH FET
Drive
HIDRV
BTST
Over
Current
Comparator
Random
Number
Generator
PH
Low-Side
N-CH FET
Drive
LODRV
PGND
NTC Bias
Internal
Temp
Sensor
TS1
TS2
TS3
TS4
Regulated
Supply
REGN
Voltage
Reference1
AFE Control
ADC MUX
1.8-V LDO
Regulator
Low
Frequency
Oscillator
High
Voltage
Translation
SMBD
SMBC
ADC/CC
FRONTEND
AFE COM
Engine
High
Frequency
Oscillator
Low
Voltage I/O
I/O
I/O &
Interrupt
Controller
ADC/CC
Digital Filter
Timers &
PWM
AFE COM
Engine
In-Circuit
Emulator
COM
Engine
Data (8bit)
DMAddr (16bit)
bqBMP
CPU
PMInstr
)
PMAddr
(16 bit)
(8 bit
Program
Flash
EEPROM
Data Flash
EEPROM
Data
SRAM
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8.3 Feature Description
The bq40z60 consists of an integrated analog front end, charge controller, and fuel gauge. The following sections
provide an overview of the device features. For additional details, refer to the bq40z60 Technical Reference
Manual (SLUUA04).
8.3.1 Safety Features
The bq40z60 provides support for primary safety, including:
•
•
•
•
Cell Over/Undervoltage Protection
Charge and Discharge Overcurrent
Short Circuit Protection
Charge and Discharge Overtemperature
The secondary safety features of the bq40z60 can be used to indicate more serious faults via the FUSE pin. This
pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. The
secondary safety features provide protection against:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Safety Over/Undervoltage Permanent Failure
Safety Overtemperature Permanent Failure
Safety FET Overtemperature Permanent Failure
Qmax Imbalance Permanent Failure
Impedance Imbalance Permanent Failure
Capacity Degradation Permanent Failure
Cell Balancing Permanent Failure
Fuse Failure Permanent Failure
Voltage Imbalance at Rest Permanent Failure
Voltage Imbalance Active Permanent Failure
Charge/Discharge FET Permanent Failure
Second Level Protector Permanent Failure
Instruction Flash Checksum Permanent Failure
Open Cell Connection Permanent Failure
Data Flash Permanent Failure
Open Thermistor Permanent Failure
8.3.2 Analog Front End (AFE) Details
The analog front end (AFE) consists of circuits responsible for managing internal power and interfacing to outside
components for measuring current, voltage, and temperature. The bq40z60 AFE includes an active-high interrupt
output connected internally to the fuel gauge to notify it of important changes in some of the AFE registers.
The bq40z60 manages its supply voltage dynamically according to operating conditions. When VBAT
VSWITCHOVER– + VHYS, the AFE connects an internal switch to BAT and uses this pin to supply power to its internal
1.8-V LDO, which subsequently powers all device logic and flash operations. Once BAT decreases to VBAT
>
<
VSWITCHOVER–, the AFE disconnects its internal switch from BAT and connects another switch to VCC, allowing
sourcing of power from a charger (if present). An external capacitor connected to PBI provides a momentary
supply voltage to help guard against system brownouts due to transient short-circuit or overload events that pull
VBAT below VSWITCHOVER–
.
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Feature Description (continued)
ACP
AC
FET
ACP
ACFET
VCC
VSWITCHOVER
–
BAT
–
SRP
SRN
Power Regulator
Pack–
Copyright © 2016, Texas Instruments Incorporated
Figure 2. Internal Power Source Selection
In the event of a power-cycle, the bq40z60 AFE will hold its internal RESET output pin high for tRST duration to
allow its internal 1.8-V LDO and LFO to stabilize before running the analog gas gauge (AGG). The AFE enters
power-on reset when the voltage at VREG falls below VREGIT–, and exits reset when VREG rises above VREGIT–
VHYS for tRST time. After tRST, the bq40z60 AGG writes its trim values to the AFE.
+
tRST
normal operation
(untrimmed)
normal operation
(trimmed)
tOSU
VIT+
1.8-V Regulator
LFO
VIT–
AFE RESET
AGG writes trim values to
AFE
Figure 3. Power-On Reset Operation
The bq40z60 AFE includes a low frequency oscillator (LFO) running at 262.144 kHz. The AFE monitors the LFO
frequency and indicates a failure via LATCH_STATUS[LFO] if the output frequency is much lower than normal.
The bq40z60 AFE provides two internal voltage references: VREF1, used by the ADC and CC, and VREF2 used by
the LDO, LFO, current wake comparator, and over- and short-current protection circuitry.
8.3.2.1 Wake Up Comparator
The internal wake comparator can be used to wake the bq40z60 from a HALT state if a configurable threshold is
detected across SRP and SRN.
22
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Feature Description (continued)
8.3.2.2 Cell Balancing Support
The integrated cell balancing FETs included in the bq40z60 device allow the AFE to bypass cell current around a
given cell or numerous cells to effectively balance the entire battery stack. External series resistors placed
between the cell connections and the VCx input pins set the balancing current magnitude. The cell balancing
circuitry can be enabled or disabled via the CELL_BAL_DET[CB3, CB2, CB1] control register. Series input
resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.
BAT
VC4
VC3
VC2
VC1
SRP
SRN
Pack–
Figure 4. Cell Balancing Configuration
8.3.2.3 FET Drive
The bq40z60 controls two external N-CH MOSFETs in a back-to-back configuration for battery protection. The
charge (CHG) and discharge (DSG) FETs are automatically disabled if a safety fault is detected and can also be
manually turned off using AFE_CONTROL[CHGEN, DSGEN] = 0, 0. When the gate drive is disabled, an internal
circuit discharges CHG to BAT and DSG to HSRN.
The AC FET (N-CH MOSFET) controls power input from the AC adaptor to the battery charging system by
monitoring the voltage at the VCC pin, and turning ON the ACFET if the voltage exceeds the VHSRN voltage. The
following register command sets the AC FET gate drive output control, AFE_STATUS register (0x01) ACFET
(Pin 2): Setting this pin to 1 allows the AC FET gate drive to be on if other conditions are satisfied.
8.3.2.4 Fuse Drive
The bq40z60 AFE has the ability to blow an external fuse in the event of a permanent failure. The fuse drive
itself is supplied from the BAT input pin and its state can be monitored using the AFE_STATUS[FUSE_RAW]
register. If AFE_STATUS[FUSE_RAW} = 1 for tDELAY duration, then LATCH_STATUS[FUSE] is set to 1, and after
an additional 500 ms, the CHG and DSG FET drive outputs will be disabled if LATCH_STATUS[FUSE] has not
been cleared by then. If the AFEFUSE output is not used, it should be connected to VSS. When AFEFUSE is in
the low state, it uses an internal weak pullup to enable detection of disconnection between the AFEFUSE pin and
the fuse drive circuitry.
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Feature Description (continued)
8.3.3 Charge Controller Details
The charge controller, under control from the fuel gauge's processor, provides autonomous control over the
charging of the battery pack. The controller uses a 1-MHz buck architecture using external FETs driven by
internal gate drivers. The charge voltage and current can be adjusted via data flash values to account for the
temperature and voltage of the battery cells, allowing for a JEITA type charge profile. The voltage and current
may also be directly written to the charge controller from an external host, allowing for a user-defined charging
profile. The charger runs in Narrow Voltage DC, that is, the output voltage of the charger will only exceed the
battery voltage by a small amount; by contrast, a charger that does not run in Narrow Voltage DC mode will
output the adapter voltage to the system.
The charger is designed to enable the system to continue to run while the battery is charged. If the system
requires more current than the charger is able to provide, the battery supplements the current to the system. The
charger can support an external precharge FET, allowing the VSYS to remain above a minimum voltage needed
for the system to operate.
The charger supports precharge, constant current/constant voltage, and termination, as shown below. The
voltage and current thresholds for precharge and termination are controlled by data flash values. Refer to the
bq40z60 Technical Reference Manual (SLUUA04) for more information.
Pre
Constant
Constant
Voltage
Termination
Charge Current
I
CHG
I
BAT
I
/
PRECHG
I
TERM
0mA
Termination Detect
Current Loop
Voltage Loop
V
SYS
V
BAT
VSYS = VBAT + IBAT · (RBAT+RSNS
)
V
PRECHG
CHGR
Figure 5. Normal Charge Profile
24
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Feature Description (continued)
The charger maintains a cycle-by-cycle current limit by sensing across a resistor in series with the inductor
(shown in Figure 6 as RCHG). In precharge and constant voltage, the DC current is regulated by sensing the
current across the sense resistor at the bottom on of the cell stack. When the charger is enabled, the initial
current is set for either the Precharge or Constant Current/Constant Voltage (CC/CV) value, based on the
minimum cell voltage. Once the charger enters CONSTANT CURRENT mode, the temperature and maximum
cell voltage-adjusted–charging current is set, and the voltage output of the charger is automatically regulated to
maintain the current across RCHG. Once the temperature-adjusted voltage is reached by the charger output, the
current starts to taper.
Throughout the charge cycle, the current available from the charger is limited by the ChargingCurrent() value.
The system draws more current, however, with the battery supplementing the difference. Once battery charging
is terminated, the charger is capable of supplying all of the current defined by the Advanced Charge
Algorithm:Maximum Current Register value. Refer to the bq40z60 Technical Reference Manual (SLUUA04) for
more information.
Figure 6 shows the system power path with the adaptor current and battery current overlaid. Further information
is available in Application and Implementation.
Power
I
ADAPTER
Path
RCHG
R1
R2
I
AC
FET
BAT
Path
Adapter
GND
ACFET
ACP
VCC
HIDRV
LODRV
HSRP
HSRN FB
DSG
FET
Charger
Current Sense
DSG
Protection
FET
Control
Charger PWM
Control
CHG
FET
CHG
BAT
Zero Volt
Charge Enable
SRN
SRP
Pack–
RSNS
Copyright © 2016, Texas Instruments Incorporated
Figure 6. Power Path Overview
8.3.3.1 Precharge Modes
The charge controller is designed to allow for both internal precharge control and external precharge control. The
device can operate in precharge with external FETs and a current limiting resistor. Refer to the bq40z60
Technical Reference Manual (SLUUA04) for more information.
8.3.3.2 Zero-Volt Charge Support
This mode of operation is similar to PRECHARGE mode switched charging, but with the charge FET operation in
the saturation region. The NVDC out is connected to the CHG gate drive output internally to allow for precharge
current from the charger through the CHG FET. This current is limited based on the value of the external Rsense
(10-mΩ resistor the lowest precharge current = 200 mA). This will increase the power dissipation of the charge
FET and will require thermal heat management and protection to ensure correct operation.
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Feature Description (continued)
8.3.3.3 Charge Termination
Once the highest cell voltage reaches the value specified in the data flash, the charger output voltage will no
longer increase and the current will start to taper. Once the highest cell voltage is within the Charge Term
Voltage window and the measured current is below Charge Term Taper Current for 40 s or more, the charger
will terminate by disabling the CHG FET and setting the appropriate flags. Refer to the bq40z60 Technical
Reference Manual (SLUUA04) for more information.
The system can still provide load current from the battery pack if the adaptor current cannot support the system
load. The diode of the CHG FET starts to conduct as the system voltage decreases to a point where the pack
voltage is greater than the system regulation voltage – Vdiode. If the average discharge current is high, the system
can turn ON the CHG FET for improved efficiency and minimized line losses during the discharge phase.
8.3.4 Fuel Gauge and Control Details
The bq40z60 uses the Impedance Track™ algorithm to measure and calculate the available capacity in battery
cells. The bq40z60 accumulates a measure of charge and discharge currents and compensates the charge
current measurement for the temperature and state-of-charge of the battery. The bq40z60 estimates self-
discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device also
has TURBO BOOST mode support, which enables the bq40z60 to provide the necessary data for the MCU to
determine what level of peak power consumption can be applied without causing a system reset or a transient
battery voltage level spike to trigger termination flags. See the bq40z60 Technical Reference Manual (SLUUA04)
for further details.
8.3.4.1 Battery Trip Point (BTP)
Required for WIN8 OS, the Battery Trip Point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based
thresholds that govern triggering a BTP interrupt on the BTP_INT pin, and setting or clearing the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external
pullup may be required to put on the BTP_INT pin. See High-Voltage General Purpose I/O (GPIO0, GPIO1) for
details.
8.3.4.2 Lifetime Data Logging Features
The bq40z60 offers lifetime data logging for several critical battery parameters. The following parameters are
updated every 10 hours if a difference is detected between values in RAM and data flash:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum and Minimum Cell Voltages
Maximum Delta Cell Voltage
Maximum Charge Current
Maximum Discharge Current
Maximum Average Discharge Current
Maximum Average Discharge Power
Maximum and Minimum Cell Temperature
Maximum Delta Cell Temperature
Maximum and Minimum Internal Sensor Temperature
Maximum FET Temperature
Number of Safety Events Occurrences and the Last Cycle of the Occurrence
Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
Number of Shutdown Events
Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
•
26
Copyright © 2014–2017, Texas Instruments Incorporated
bq40z60
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ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
8.3.5 Authentication
The bq40z60 supports authentication by the host using SHA-1. More information about the algorithm can be
found in the bq40z60 Technical Reference Manual (SLUUA04).
8.3.6 LED Display
The bq40z60 can drive a 4-segment LED display for remaining capacity indication and/or a permanent fail (PF)
error code indication.
8.3.7 Internal Temperature Sensor
An internal temperature sensor is available on the bq40z60 to reduce the cost, power, and size of the external
components necessary to measure temperature. It is available for connection to the ADC using the multiplexer,
and is ideal for determining pack temperature during storage and IC temperature during normal operation.
8.3.8 External Temperature Sensor Support
Each of the TSx input pins can be enabled with an 18-kΩ (Typ.) linearization pullup resistor to support using a 10
kΩ (25°C) NTC external thermistor, such as the Semitec 103AT–2. One or more thermistors can be connected
between VSS and the individual RCx pin. The analog measurement is then taken via the ADC through its input
multiplexer. If a different thermistor type is required, then changes to the external support components may be
required.
&%"#
)ꢁ+*)'
$!%
! "
!"#$ꢀ $
Figure 7. Thermistor Pin Configuration
8.3.9 High Frequency Oscillator
The bq40z60 includes a high frequency oscillator (HFO) running at 16.78 MHz. It is synthesized from the LFO
output and scaled down to 8.388 MHz with 50% duty cycle. There is no need for external oscillator components.
8.3.10 Communications
The bq40z60 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
Copyright © 2014–2017, Texas Instruments Incorporated
27
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
Feature Description (continued)
8.3.10.1 SMBus On and Off State
The bq40z60 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this
state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
8.3.10.2 SBS Commands
The ManufacturerAccess() Command List shows the supported Manufacturer Access and SBS commands. See
the bq40z60 Technical Reference Manual (SLUUA04) for further details.
Table 1. ManufacturerAccess() Command List
MANUFACTURER
SBS
COMMAND
DATA READ ON
0x44 OR 0x23
AVAILABLE IN
SEALED MODE
FUNCTION
ACCESS
COMMAND
ACCESS
FORMAT
DeviceType
FirmwareVersion
HardwareVersion
IFChecksum
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0008
0x0009
0x0010
0x0011
0x0013
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0028
R
R
Block
Block
Block
Block
Block
Block
Block
Block
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
R
R
StaticDFSignature
ChemID
R
R
StaticChemDFSignature
AllDFSignature
ShutdownMode
SleepMode
R
R
W
W
W
W
W
W
W
W
W
W
W
W
W
W
—
—
AutoCCOfset
—
—
—
FuseToggle
—
—
—
PrechargeFET
ChargeFET
—
—
—
—
—
—
DischargeFET
Gauging
—
—
—
—
—
—
FETControl
—
—
—
LifetimeDataCollection
PermanentFailure
BlackBoxRecorder
Fuse
—
—
—
—
—
—
—
—
—
—
—
—
LifetimeDataReset
—
—
—
PermanentFailureData
Reset
0x0029
0x002E
0x002F
W
W
W
—
—
—
—
—
—
—
—
—
LifetimeDataFlush
LifetimeDataSpeedUp
Mode
BlackBoxRecorderReset
CalibrationMode
SealDevice
0x002A
0x002D
0x0030
0x0035
0x0037
0x0041
0x0050
0x0051
0x0052
0x0053
0x0054
0x0055
0x0056
W
W
W
R/W
R/W
W
R
—
—
—
—
—
—
—
—
—
SecurityKeys
AuthenticationKey
DeviceReset
Block
Block
—
Yes
—
—
—
—
—
SafetyAlert
0x50
0x51
0x52
0x53
0x54
0x55
0x56
Block
Block
Block
Block
Block
Block
Block
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SafetyStatus
R
PFAlert
R
PFStatus
R
OperationStatus
ChargingStatus
GaugingStatus
R
R
R
28
Copyright © 2014–2017, Texas Instruments Incorporated
bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
Feature Description (continued)
Table 1. ManufacturerAccess() Command List (continued)
MANUFACTURER
ACCESS
SBS
COMMAND
DATA READ ON
0x44 OR 0x23
AVAILABLE IN
SEALED MODE
FUNCTION
ACCESS
FORMAT
COMMAND
ManufacturingStatus
AFERegister
0x0057
0x0058
0x0060
0x0061
0x0062
0x0070
0x0071
0x0072
0x0073
0x0074
0x0075
0x0077
0x00C0
0x00C1
0x00C2
0x00C3
0x0F00
0xF080
0x57
0x58
0x60
0x61
0x62
0x70
0x71
0x72
0x73
0x74
0x75
R
R
Block
Block
Block
Block
Block
Block
Block
Block
Block
Block
Block
Block
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
LifetimeDataBlock1
LifetimeDataBlock2
LifetimeDataBlock3
ManufacturerInfo
DAStatus1
R
R
R
R
R
DAStatus2
R
GaugeStatus1
GaugeStatus2
GaugeStatus3
StateofHealth
CHGR_EN
R
R
R
R
W
W
W
W
W
R/W
CVRD_ARM
—
—
Yes
No
ACFETEST
—
—
CHGONTEST
ROMMode
—
—
No
—
—
—
ExitCalibrationOutput
Block
Yes
—
OutputCCandADCfor
Calibration
0xF081
0xF082
R/W
R/W
Block
Block
Yes
Yes
—
—
OutputShortedCCand
ADCforCalibration
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq40z60 is a monolithic charger and gas gauge solution for multi-cell battery packs. By integrating these
devices, software control can be handed off from the host microcontroller to the gas gauge controller, providing
for potential energy savings that correlate to runtime.
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29
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
9.2 Typical Applications
, 3 2 , 1
, 3 2 , 1
, 3 2 , 1
8 , 7
, 6 , 5
8 , 7
, 6 , 5
8 , 7
, 6 , 5
2
3
4
4
1
3
2
3
3
3
3
2
2
2
2
2
4
3
2
m h o k 0 . 0 1
t °
m h o k 0 . 0 1
t °
m h o k 0 . 0 1
t °
m h o k 0 . 0 1
t °
A P D
图 8. Typical Application Schematic
30
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bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
Typical Applications (接下页)
注
The feedback resistor to VFB from charging output will have different values based on the
number of series cells configured for charging the pack.
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
Design Parameter
Input Voltage Range
Example Value
15–22 V
3-Cell Battery Voltage Range
4-Cell Battery Voltage Range
Operating Frequency
9 V–12.6 V
12 V–16.8 V
1000 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The bq40z60 has a 1000-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
I
³ I
+ (1/2) I
SAT
CHG RIPPLE
(1)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and
inductance (L):
V
´ D ´ (1 - D)
IN
IRIPPLE
=
fS ´ L
(2)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For 20-V adaptor voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is a 4-cell battery: The battery voltage range is from 12 V
to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20%–40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
The bq40z60 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-current
sensing resistor to prevent negative inductor current. The typical UCP threshold is 5-mV falling edge
corresponding to 0.5-A falling edge for a 10-mΩ charging-current sensing resistor.
9.2.2.2 Input Capacitor
The input capacitor should have enough ripple-current rating to absorb input switching ripple current. The worst-
case RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor RMS current ICIN occurs where the duty cycle is closest
to 50% and can be estimated using the following equation:
ICIN = ICHG
´
D ´ (1-D)
(3)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input-decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V or higher-rating
capacitor is preferred for 20-V input voltage. 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4-A
charging current.
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ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
9.2.2.3 Output Capacitor
Output capacitor also should have enough ripple-current rating to absorb the output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
RIPPLE
I
=
» 0.29 ´ I
RIPPLE
COUT
2 ´
3
(4)
The output capacitor voltage ripple can be calculated as follows:
2
æ
ç
ç
è
ö
÷
÷
ø
VBAT
1
DVo =
V
-
BAT
2
V
8LCfs
IN
(5)
At a certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC. The bq40z60 has an internal loop compensator. To get good loop stability, the resonant
frequency of the output inductor and output capacitor should be designed between 21 kHz and 27 kHz. The
preferred ceramic capacitor has a 25-V or higher rating, X7R or X5R for a 4-cell application.
9.2.2.4 Power MOSFETs Selection
Two external N-CH MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are
preferred for 20-V input voltage, and 40 V or higher-rating MOSFETs are preferred for 20-V to 28-V input
voltage.
Figure-of-merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET on-
resistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product
of the MOSFET on-resistance, rDS(on), and the total gate charge, QG.
FOMtop = RDS(on) ´ QGD
FOMbottom = RDS(on) ´ QG
(6)
The lower the FOM value, the lower the total power loss. Usually a lower rDS(on) has a higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHG), the MOSFET on-resistance tDS(on)), input voltage (VIN), switching frequency
(fS), turn-on time (ton), and turn-off time (toff):
1
2
= D ´ ICHG ´ RDS(on)
P
+
´ V ´ ICHG
´
ton+ toff ´ f
S
(
)
top
IN
2
(7)
The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with 100°C junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are
given by:
Q
Q
SW
SW
t
=
, t
=
off
on
I
I
on
off
(8)
where Qsw is the switching charge, Ion is the turn-on gate-driving current, and Ioff is the turn-off gate driving
current. If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain
charge (QGD) and gate-to-source charge (QGS):
1
Q
= Q
+
´ Q
GS
SW
GD
2
(9)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turn-on gate resistance (Ron), and turn-off gate resistance (Roff) of the gate driver:
VREGN - Vplt
Vplt
Ion
=
, Ioff =
Ron
Roff
(10)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous-conduction mode:
2
= (1 - D) ´ ICHG ´ RDS(on)
P
bottom
(11)
32
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bq40z60
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ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
If the HSRP–HSRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when
the average HSRP–HSRN voltage is lower than 1.7 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. As a result, all the freewheeling current goes through the
body diode of the bottom-side MOSFET. The maximum charging current in non-synchronous mode can be up to
1.6 A (0.5 A typ) for a 10-mΩ charging-current sensing resistor, considering IC tolerance. Choose the bottom-
side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous
mode charging current.
MOSFET gate-driver power loss contributes to the dominant losses on the controller IC when the buck converter
is switching. The combined high side and low side MOSFET gate charge, Qg_total, is proportional to the power
dissipation of the IC, as shown in 公式 12:
P
= V ×Qg_total ×fs
IN
ICLoss_driver
(12)
Choosing FETs with a lower Qg_total will reduce power loss.
9.2.2.5 Input Filter Design
During adaptor hot plug-in, the parasitic inductance and input capacitor from the adaptor cable form a second-
order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin.
There are several methods for damping or limiting the overvoltage spike during adaptor hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an
IC safe level. However, these two solutions may not have low cost or small size.
图 9 shows a cost-effective and small size solution. The R1 and C1 are composed of a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the body diode of input ACFET). C2 is a VCC pin-
decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping
RC network to further protect the IC from high dv/dt and high-voltage spike. The C2 value should be less than
the C1 value so R1 can be dominant over the ESR of C1 to get enough of a damping effect for hot plug-in. The
R1 and R2 packages must be sized to handle inrush-current power loss according to the resistor manufacturer’s
datasheet. The filter component values always must be verified with the real application, and minor adjustments
may be needed to fit in the real application circuit.
D1
(1206)
R2
1 Ω
R1
2 Ω
(2010)
Adapter
connector
VCC pin
C1
2.2 µF
C2
0.1-1 µF
图 9. Input Filter
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33
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
9.2.3 Application Curves
!
$&$% "
"#
!
'(%% #&
1 A/div (on both channels)
4 s/div Timescale
10 V/div
400 ns/div Timescale
图 10. Battery Current with Load Steps
图 11. Charge Controller Phase (Switch) Node Operation
During Constant Current Charging
10 Power Supply Recommendations
The bq40z60 is designed to operate from a well-regulated input voltage supply range between 4.0 V and 25 V;
however, with a multi-cell pack, the input voltage should be a minimum of 1 V above the maximum stack voltage.
If the input supply is more than a few inches from the bq40z60, additional bulk capacitance in the form of a 47-µF
electrolytic capacitor should be used.
11 Layout
11.1 Layout Guidelines
The following information is related to external component selection and guidelines for PCB layout.
11.1.1 PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high-frequency current-path loop (see 图 12) is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections and
use the shortest possible copper trace connection. The capacitors should be placed on the same layer as the
FETs instead of using vias to connect the capacitor and the FETs. Additionally, any vias connecting the input
capacitor to the adaptor node should not be placed between the capacitor and the FETs; the capacitor
should have a solid copper path to the FET.
2. The IC should be placed close to the switching MOSFET gate pins to keep the gate-drive signal traces short
for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching MOSFETs.
3. Place the inductor input pin as close as possible to the switching MOSFET output pin. Minimize the copper
area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance
from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
34
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bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
Layout Guidelines (接下页)
area) and do not route the sense leads through a high-current path (see 图 13 for Kelvin connection for best
current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Place the sense resistor and filter components, R1, C2, and C3, as close as possible to the IC and directly
adjacent to the decoupling capacitor between HSRN and HSRP.
8. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper-pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect analog ground and power ground together using the thermal pad as the single ground
connection point. Or use a 0-Ω resistor to tie analog ground to power ground (thermal pad should tie to
analog ground in this case). A star connection under the thermal pad is highly recommended.
9. It is critical that the exposed thermal pad on the back side of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other
layers.
10. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
11. Size and number of all vias should be enough for a given current path.
L1
R1
V
BAT
SW
High
Frequency
Current
Path
V
BAT
IN
C2
C3
C1
PGND
图 12. High-Frequency Current Path
Current Direction
R
SNS
Current Sensing Direction
To SRP – SRN pin or HSRP – HSRN pin
图 13. Sensing Resistor PCB Layout
For the recommended component placement with trace and via locations, see the bq40z60EVM SBS 1.1
Impedance Track™ Technology Enabled Battery Management Solution Evaluation Module User's Guide
(SLUUB71).
For the QFN information, see the Quad Flatpack No-Lead Logic Packages Application Note (SCBA017) and the
QFN/SON PCB Attachment Application Note (SLUA271).
版权 © 2014–2017, Texas Instruments Incorporated
35
bq40z60
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
www.ti.com.cn
11.2 Layout Example
*6.02ꢀ58:>=ꢀ0.:ꢀ069<2ꢀ=9ꢀ',ꢀ%$-ꢀ@5=4ꢀ
89ꢀ?5.<ꢀ/2=@228ꢁ
('
! %
"$
! %
+
*'
!1.:=2;
+
(58575A2ꢀ">ꢀ15<=.802ꢀ
/2=@228ꢀ%$-<ꢀ.81ꢀ581>0=9;
#$
! %
*'
+
#
&)#
&)#
',+*
',+)
(58575A2ꢀ699:ꢀ.;2.ꢀ93ꢀ=42ꢀ
',+* ',+)ꢀ098820=598<
图 14. Board Layout Example
36
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bq40z60
www.ti.com.cn
ZHCSDZ3D –DECEMBER 2014–REVISED JANUARY 2017
12 器件和文档支持
12.1 相关文档ꢀ
如需相关文档，请参阅《bq40z60 技术参考手册》（文献编号：SLUUA04）。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
Impedance Track, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2014–2017, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ40Z60RHBR
BQ40Z60RHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ40Z60
BQ40Z60
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ40Z60RHBR
BQ40Z60RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ40Z60RHBR
BQ40Z60RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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