BQ4802LYDWG4 [TI]
PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR; 与CPU监控并行实时时钟
| 型号： | BQ4802LYDWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR |
| 文件： | 总26页 (文件大小：920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR AND
EXTERNAL SRAM NONVOLATILE MEMORY BACKUP
FEATURES
APPLICATIONS
D
Real-Time Clock Counts Seconds Through
D
D
D
D
D
D
Telecommunications Base Stations
Servers
Centuries in BCD Format
– bq4802Y: 5-V Operation
– bq4802LY: 3.3-V Operation
Handheld Data Collection Equipment
Medical Equipment
D
D
D
D
On-Chip Battery-Backup Switchover Circuit
With Nonvolatile Control for External SRAM
Handheld Instrumentation
Test Equipment
Less Than 500 nA of Clock Operation Current
in Backup Mode
Microprocessor Reset With Push-Button
Override
DESCRIPTION
Independent Watchdog Timer With
Programmable Time-Out Period
The bq4802Y/bq4802LY real-time clock is a low-power
microprocessor peripheral that integrates a time-of-
day clock, a century-based calendar, and a CPU super-
visor, with package options including a 28-pin SOIC,
TSSOP, or SNAPHAT that requires the bq48SH-28x6
to complete the two-piece module. The bq4802Y/
bq4802LY is ideal for fax machines, copiers, industrial
control systems, point-of-sale terminals, data loggers,
and computers.
D
Power-Fail Interrupt Warning
D
Programmable Clock Alarm Interrupt Active
in Battery-Backup Mode
D
D
D
Programmable Periodic Interrupt
Battery-Low Warning
28-pin SOIC, TSSOP, and SNAPHAT Package
Options
5 kΩ
TYPICAL APPLICATION
V
bq4802
CC
RST
A0–A3
ADDRESS BUS
DATA BUS
TO µP
WDO
INT
DQ0–DQ7
CS
CMOS SRAM
FROM
ADDRESS
DECODE
LOGIC
62256L
A0–A3
ADDRESS BUS
CE
IN
DQ0–DQ7
DATA BUS
V
V
OUT
OUT
CC
CE
OE
FROM µP
I/O LINE
WDI
CE
WR
OE
READ/
WRITE
CONTROL
FROM µP
WE
X1
X2
32.768 kHz
CRYSTAL
BC
3 V
LITHIUM
CELL
V
SS
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring
storageor handling to prevent electrostatic damage to the MOS gates.
The bq4802Y/bq4802LY contains a temperature-
DESCRIPTION (CONTINUED)
compensated reference and comparator circuit that
monitors the status of its voltage supply. When the
bq4802Y/bq4802LY detects an out-of-tolerance
condition, it generates an interrupt warning and sub-
sequently a microprocessor reset. The reset stays
The bq4802Y/bq4802LY provides direct connections
for a 32.768-kHz quartz crystal and a 3-V backup
battery. Through the use of the conditional chip enable
output(CE
)andbatteryvoltageoutput(V
)pins,
OUT
OUT
the bq4802Y/bq4802LY can write-protect and make
non- volatile external SRAMs. The backup cell powers
the real-time clock and maintains SRAM information in
the absence of system voltage. The crystal and battery
are contained within the modules for a more integrated
solution.
active for 200 ms after V
rises within tolerance, to
CC
allow for power supply and processor stabilization. The
reset function also allows for an external push-button
override.
ORDERING INFORMATION
DEVICES
T
A
OPERATION
SYMBOL
(1)
(1)
(1)(2)(3)
SNAPHAT (DSH)
SOIC (DW)
TSSOP (PW)
5 V
bq4802YDW
bq4802LYDW
bq4802YPW
bq4802LYPW
bq4802YDSH
bq4802LYDSH
bq4802Y
bq4802LY
0°C to +70°C
3.3 V
(1)
(2)
(3)
The DW, PW and DSH packages are available taped and reeled. Add an R suffix to the device type (i.e., bq4802YDWR).
The DSH package is available taped only.
The bq48SH–28x6 should be ordered to complete the SNAPHAT module and is the same part number for both 3.3-V and 5-V modules.
CAUTION: Wave soldering of DSH package may cause damage to SNAPHAT sockets.
ABSOLUTE MAXIMUM RATINGS
overoperating free-air temperature range unless otherwise noted
(1)
bq4802Y
bq4802LY
Input voltage range, VCC, V (V ≤ VCC +0.3)
–0.3 V to 6.0 V
0°C to 70°C
–55°C to 125°C
–40°C to 85°C
300°C
T
T
Operatingtemperaturerange, T
J
Storage temperature range, T
stg
Temperature under bias, T
Jbias
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
MAX
5.5
UNIT
bq4802Y
Supply voltage, V
CC
V
bq4802LY
2.7
3.6
Input low voltage, V
–0.3
2.2
0.8
V
V
V
V
V
IL
Input high voltage, V
V
V
+ 0.3
4.0
IH
CC
Backup cell voltage, V
2.4
BC
Push button reset input low, V
–0.3
2.2
0.4
BC
Push button reset input high, V
+ 0.3
PBRH
CC
2
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
ELECTRICAL CHARACTERISTICS
(T = 25°C, V
A
≤ V
CC
≤ V unless otherwise noted)
CC(max)
CC(min)
INPUT SUPPLY
PARAMETER
TEST CONDITIONS
100% Minimum duty cycle,
MIN
TYP
5
MAX
UNIT
I
Supplycurrent
9
mA
CC
CS = V
CS = V
CS = V
,
I
= 0 mA
IL
I/O
3
IH
– 0.2 V,
I
Standby supply current
mA
CC
SB1
1.5
0 V ≤ V ≤ 0.2 V or V = V
– 0.2 V
IN
IN
CC
V
= 3 V,
T
= 25°C,
BC
A
I
Battery operation supply current
0.3
0.5
µA
CCB
No load at V
OUT
or CE
, I
OUT I/O
= 0 mA
IL
I
I
Input leakage current
Output leakage current
V
IN
= V
to V
CC
–1
–1
1
1
µA
µA
LI
SS
CS = V or OE = V or WE = V
LO
IH
IH
V
I
I
= 80 mA,V
> V
V
-0.3
-0.3
OUT(1)
OUT(2)
OUT
OUT
CC
V
BC
CC
Outputvoltage
V
V
V
V
= 100 µA,
< V
V
BC
CC
BC
bq4802Y
bq4802LY
4.30
2.4
4.37
2.53
4.5
V
Power fail detect voltage
Supply switch over voltage
PFD
SO
2.65
V
V
> V
< V
V
PFD
BC
BC
(PFD)
(PFD)
V
V
BC
(1)
RST output voltage
(1)
INT output voltage
V
RST
V
INT
I
I
= 4 mA
0.4
0.4
V
V
(RST)
= 4 mA
(INT)
(1)
RST and INT are open drain outputs.
WATCHDOG
PARAMETER
TEST CONDITIONS
MIN
TYP
–10
20
MAX
UNIT
I
I
Low-level watchdog input current
High-level watchdog input current
–50
(WDIL)
(WDIH)
µA
50
I
I
= 4 mA
0.4
SINK
SOURCE
V
WDO output voltage
V
(WDO)
= 2 mA
2.4
CRYSTAL SPECIFICATIONS (DT-26) OR EQUIVALENT)
PARAMETER
TEST CONDITIONS
MIN
TYP
32.768
6
MAX
UNIT
kHz
pF
f
O
Oscillationfrequency
Loadcapacitance
C
L
T
k
Temperatureturnoverpoint
Parabolic curvature constant
Quality factor
20
25
30
°C
P
–0.042 ppm/°C
Q
40,000 70,000
R
C
Series resistance
45
1.8
600
1
kΩ
1
Shuntcapacitance
Capacitanceratio
1.1
pF
0
C /C
0
430
1
D
L
Drive level
µW
∆f/f
Aging (first year at 25°C)
1
–
ppm
0
CAPACITANCE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
Input/outputcapacitance
Inputcapacitance
V
= 0 V
7
5
I/O
Out
V = 0 V
pF
C
I
3
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
AC TEST CONDITIONS, INPUT PULSE LEVELS V = 0 V to 3.0 V, t = t = 5 NS, VREF = 1.5 V
I
R
F
3 V
3 V
962 Ω
962 Ω
D
OUT
D
OUT
5 pF
100 pF
510 Ω
510 Ω
Figure 2. Output Load B
Figure 1. Output Load A
OPERATING CHARACTERISTICS
READ CYCLE (T = T
, V
= 5 V)
A
OPR CC
PARAMETER
Read cycle time
TEST CONDITIONS
MIN
200
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
RC
Address access time
Output load A
100
ns
AA
Chip select access time
Output enable to output valid
Chip select to output low Z
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
100
100
ns
ACS
OE
ns
8
0
ns
CLZ
OLZ
CHZ
OHZ
OH
Output enable until output low Z
Output enable until output high Z
Output disable until output high Z
Output hold from address change
ns
0
45
45
ns
0
ns
10
ns
READ CYCLE (T = T
, V
= 3.3 V)
A
OPR CC
PARAMETER
Read cycle time
TEST CONDITIONS
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
300
RC
Address access time
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
150
150
150
ns
AA
Chip select access time
ns
ACS
OE
Output enable to output valid
Chip select to output low Z
Output enable until output low Z
ns
15
0
ns
CLZ
OHL
CLH
OLZ
OH
ns
Output enable until output high Z
Output disable until output high Z
Output hold from address change
0
60
60
ns
0
ns
18
ns
4
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
PIN ASSIGNMENTS
DW OR PW PACKAGE
(TOP VIEW)
DSH PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
CC
WE
V
WE
CE
CE
NC
WDI
OE
CS
NC
DQ7
DQ6
DQ5
DQ4
DQ3
V
OUT
X1
X2
CC
OUT
NC
NC
2
2
3
3
CE
IN
IN
4
4
WDO
INT
RST
A3
CE
WDO
INT
RST
A3
OUT
OUT
5
5
BC
WDI
OE
6
6
7
7
8
A2
A1
A0
CS
8
A2
A1
A0
9
V
9
SS
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
13
14
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
V
SS
V
SS
NC – No internal connection
Terminal Functions
TERMINAL
I/O
DESCRIPTION
A0 – A3 allow access to the 16 bytes of real-time clock and control registers.
NAME
NO.
10
9
A0
A1
A2
A3
BC
8
7
(1)
24
BC should be connected to a 3-V backup cell. A voltage within the V
range on the BC pin should be present
BC
uponpower up to provide proper oscillator start-up. Not accessible in module packages.
CE
CE
26
Input to the chip-enable gating circuit
IN
25
CE
OUT
goes low only when CE is low and V
IN CC
is above the power fail threshold. If CE is low, and power fail
IN
OUT
occurs, CE
stays low for 100 µs or until CE goes high, whichever occurs first.
IN
OUT
CS
21
11
12
13
15
16
17
18
19
5
I
I
I
I
I
I
I
I
I
Chip-selectinput
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
INT
DQ0–DQ7providex8 data for real-time clock information. These pins connect to the memory data bus.
INT goes low when a power fail, periodic, or alarm condition occurs. INT is an open-drain output.
OE provides the read control for the RTC memory locations.
OE
22
6
RST
RST goes low whenever V
falls below the power fail threshold. RST remains low for 200 ms (typical) after
CC
V
crossesthethresholdonpower-up. Thebq4802Y/bq4802LY also enters the reset cycle when RST is released
CC
from being pulled low for more than 1 µs.
V
V
28
1
I
5-V or 3.3-V input
CC
O
V
provides the higher of V or V , switched internally, to supply external RAM.
CC BC
OUT
OUT
Ground
14
V
SS
(1)
20
(1)
This pin should be left unconnected (NC) when using the SNAPHAT (DSH) package.
5
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
WDI
23
I
WDIisathree-levelinput.IfWDIremainseitherhighorlowforlongerthanthewatchdogtime-outperiod(1.5-sdefault),
WDOgoes low. WDOremainslowuntilthenexttransitionatWDI. LeavingWDIunconnecteddisablesthewatchdog
function.WDI connects to an internal voltage divider between V
unconnected.
and VSS, which sets it to mid-supply when left
OUT
WDO
4
WDOgoes low if WDI remains either high or low longer than the watchdog time-out period. WDO returns high on the
next transition at WDI. WDO remains high if WDI is unconnected.
WE
X1
27
WE provides the write control for the RTC memory locations.
Crystalconnection
(1)
2
3
(1)
X2
FUNCTIONAL BLOCK DIAGRAM
Figure 3 is a block diagram of the bq4802Y/bq4802LY. The following sections describe the bq4802Y/bq4802LY
functional operation including clock interface, data-retention modes, power-on reset timing, watchdog timer
activation, and interrupt generation.
Time-
Base
Oscillator
X1
X2
÷8
÷64
÷64
4
16:1 MUX
Control/Status
Registers
Clock/Calendar
Update
Interrupt
Generator
INT
Watchdog
Transition
Detector
WDO
Clock/Calendarand
AlarmRegisters
User Buffer
(16 Bytes)
RST
Power-Fail
µP Bus
Interface
Control, Battery
Switchoverand
ResetCircuits
V
OUT
CE
OUT
A
0
– A
3
DQ – DQ
0
7
CS
OE WE
WDI
CE
IN
V
CC
BC
Figure 3. Block Diagram
6
bq4802Y
bq4802LY
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SLUS464C – AUGUST 2000 – REVISED JUNE 2002
READ CYCLE TIMING DIAGRAMS
t
RC
Address
t
AA
t
OH
D
OUT
Previous Data Valid
Data Valid
NOTES: A. WE is held high for a read cycle.
B. Device is continuously selected: CS = OE = V
.
IL
Figure 4. Read Cycle No. 1 – Address Access
t
CS
RC
t
CHZ
t
ACS
t
CLZ
D
OUT
High-Z
High-Z
NOTES: A. WE is held high for a read cycle.
B. Device is continuously selected: CS = OE = V
.
IL
C. OE = V
.
IL
Figure 5. Read Cycle No. 2 – CS Access
t
RC
Address
t
AA
OE
t
OE
t
OHZ
t
OLZ
D
OUT
Data Valid
High-Z
NOTES: A. WE is held high for a read cycle.
B. CS = V
High-Z
.
IL
Figure 6. Read Cycle No. 3 – OE Access
7
bq4802Y
bq4802LY
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SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WRITE CYCLE TIMING DIAGRAMS
t
WC
Address
t
t
AW
WR1
t
CW
CS
t
t
WP
AS
WE
t
t
DH1
DW
D
IN
Data-In Valid
t
t
OW
WZ
D
OUT
Data Undefined (see Note B)
High-Z
NOTES: A. WE or CS must be held high during address transition.
B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.
C. If OE is high, the I/O pins remain in a state of high impedance.
Figure 7. Write Cycle No. 1 – WE Controlled
t
WC
Address
t
t
AW
WR2
t
t
CW
AS
CS
t
WP
WE
t
t
DH2
DW
D
IN
Data-In Valid
t
WZ
Data Undefined (see Note B)
NOTES: A. WE or CS must be held high during address transition.
D
OUT
High-Z
B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.
C. If OE is high, the I/O pins remain in a state of high impedance.
D. Either t
E. Either t
or t
must be met.
WR1
DH1
WR2
must be met.
or t
DH2
Figure 8. Write Cycle No. 2 – CS Controlled
8
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bq4802LY
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SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WRITE CYCLE (T = T
A
, V
= 5 V)
OPR CC
PARAMETER
TEST CONDITIONS
MIN
200
195
195
30
165
5
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Write cycle time
WC
CW
AW
Chip select to end of write
Address valid to end of write
Address setup time
See Note 1
See Note 1
(2)
Measured from address valid to beginning of write
AS
(1)
Measured from beginning of write to end of write
Write pulse width
WP
(3)
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Measured from WE going high to end of write cycle
(3)
WR1
WR2
DW
DH1
DH2
WZ
Measured from CS going high to end of write cycle
Measured to first low-to-high transition of either CS or WE
(4)
15
50
0
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enable to output high Z
Output active from end of write
Measured from WE going high to end of write cycle
(4)
Measured from CS going high to end of write cycle
10
0
(5)
(5)
I/O pins are in output state.
I/O pins are in output state.
45
0
OW
(1)
(2)
(3)
(4)
(5)
A write cycle ends at the earlier transition of CS going high and WE going high.
A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.
Either t
Either t
or t
must be met.
WR1
DH1
WR2
must be met.
or t
DH2
If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.
WRITE CYCLE (T = T
A
, V
= 3.3 V)
OPR CC
PARAMETER
TEST CONDITIONS
MIN
300
250
250
56
280
8
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Write cycle time
WC
CW
AW
Chip select to end of write
Address valid to end of write
Address setup time
See Note 1
See Note 1
(2)
Measured from address valid to beginning of write
AS
(1)
Measured from beginning of write to end of write
Write pulse width
WP
(3)
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Measured from WE going high to end of write cycle
(3)
WR1
WR2
DW
DH1
DH2
WZ
Measured from CS going high to end of write cycle
Measured to first low-to-high transition of either CS or WE
(4)
25
80
0
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enable to output high Z
Output active from end of write
Measured from WE going high to end of write cycle
(4)
Measured from CS going high to end of write cycle
15
0
(5)
(5)
I/O pins are in output state.
I/O pins are in output state.
60
0
OW
(1)
(2)
(3)
(4)
(5)
A write cycle ends at the earlier transition of CS going high and WE going high.
A write occurs during the overlap of a low CS and a low WE. A write cycle begins at the later transition of CS going low or WE going low.
Either t
Either t
or t
must be met.
WR1
DH1
WR2
must be met.
or t
DH2
If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in high Z state.
9
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bq4802LY
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SLUS464C – AUGUST 2000 – REVISED JUNE 2002
POWER-DOWN/POWER-UP TIMING (T = T
A
)
OPR
PARAMETER
TEST CONDITIONS
3.0 V to 0 V
MIN
300
100
6
TYP
MAX
UNIT
t
t
V
V
slew rate fall time
slew rate rise time
F
CC
VSO to VPDF(max)
R
CC
bq4802Y
24
40
t
t
t
Interrupt delay time from V
µs
PF
PFD
bq4802LY
bq4802Y
bq4802LY
bq4802Y
bq4802LY
10
See Note 1
See Note 1
See Note 2
See Note 2
90
100
170
200
330
125
210
300
500
Write-protect time for external SRAM
WPT
CSR
150
100
170
CS at V after power-up
HI
ms
t
t
V
to RST active (reset active time-out period)
PFD
Device enable recovery time
t
t
t
CSR
RST
CSR
See Note 3
t
CER
CSR
CSR
15
bq4802Y
bq4802LY
9
t
t
Device enable propagation delay time to external SRAM
Push-button low time
Output load A
ns
CED
15
25
1
µs
PBL
(1)
(2)
(3)
Delay after V
Internal write-protection period after V
Time during which external SRAM is write protected after V
CC
slews down past V
before SRAM is write protected and RST activated.
passes V on power up.
CC
PFD
CC
PFD
passes V
on power up.
PFD
CAUTION:NEGATIVE UNDERSHOOTS BELOW THE ABSOLUTE MAXIMUM RATING OF –0.3 V IN BATTERY-
BACKUP MODE MAY AFFECT DATA INTEGRITY.
t
F
t
R
t
FS
V
CC
V
PFD(max)
V
PFD
2.8
V
t
PFD
V
CC
V
V
SO
SO
CSR
t
PF
CS
t
t
CER
WPT
CE
IN
t
t
CED
CED
V
OHB
CE
OUT
t
RST
RST
INT
High-Z
NOTES: A. PWRIE set to 1 to enable power fail interrupt.
B. RST and INT are open drain and require and external pullup resistor.
Figure 9. Power-Down/Power-Up Timing Diagram
10
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
t
t
RST
PBL
V
PBRH
RST
V
PBRL
Figure 10. Push-Button Reset Timing
11
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
FUNCTIONAL DESCRIPTION
The following sections describe the bq4802Y/bq4802LY functional operation including clock interface, data-retention
modes, power-on reset timing, watchdog timer activation, and interrupt generation.
Table 1. Operational Truth Table
V
CS
OE
X
WE
CE
OUT
CEIN
V
MODE
Deselect
Write
DQ
POWER
Standby
CC
OUT
< V
V
IH
X
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT2
High Z
CC(MAX)
V
IL
V
IL
V
IL
X
V
CEIN
CEIN
CEIN
D
IN
Active
IL
IH
IH
> V
V
IL
V
V
Read
D
OUT
Active
CC(MIN)
V
IH
Read
High-Z
Active
<V
>V
PFD(MIN SO
≤ V
X
X
X
V
OH
Deselect
Deselect
High-Z
High-Z
CMOS standby
Battery-backupmode
X
X
X
V
OHB
SO
ADDRESS MAP
Thebq4802Y/bq4802LYprovides16bytesofclockandcontrolstatusregisters. Table1isamapofthebq4802Y/bq4802LY
registers, and Table 2 describes the register bits.
Table 2. Clock and Control Register Map
Addr
(h)
D7
D6
D5
D4
D3
D2
D1
D0
Range (h)
Register
0
0
10-seconddigit
1-seconddigit
00–59
Seconds
ALM0
1
2
3
ALM1
0
1-seconddigit
1-minutedigit
1-minutedigit
00–59
00–59
00–59
Secondsalarm
Minutes
10-seconddigit
10-minutedigit
ALM0
ALM1
Minutesalarm
10-minutedigit
01–12AM
81–92PM
4
5
PM/AM
0
10-hourdigit
1-hourdigit
1-hourdigit
Hours
ALM1
01–12AM
81–92PM
ALM0
10-hourdigit
Hours alarm
PM/AM
6
7
0
ALM1
0
0
ALM0
0
10-daydigit
10-daydigit
1-daydigit
1-daydigit
01–31
01–31
01–07
01–12
00–99
–
Day
Day alarm
Day of Week
Month
8
0
0
0
day of week digit
9
0
0
0
10 mo.
1-monthdigit
1-yeardigit
A
B
C
D
E
F
10-yeardigit
Year
(1)
(1)
(1)
(1)
WD2
(1)
WD1
(1)
WD0
(1)
RS3
AIE
AF
RS2
RS1
PWRIE
PWRF
24/12
RS0
ABE
BVF
DSE
Rates
PIE
PF
–
Enables
Flags
(1)
(1)
(1)
–
(1)
(1)
(1)
UTI
STOP
–
Control
Century
10-centurydigit
1-centurydigit
00–99
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Unused bits; cannot be written to and read as 0.
Internal write-protection period after V passes V
Clock calendar data in BCD. Automatic leap year adjustment up to year 2100.
PM/AM = 1 for PM and 0 for AM.
on power up.
PFD
CC
DSE = 1 to enable daylight savings adjustment.
24/12 = 1 to enable 24–hour data representation and 0 for 12–hour data representation.
Day of week coded as Sunday = 1 through Saturday = 7
BVF = 1 for valid BC input
STOP = 1 to turn the RTC on and 0 stops the RTC in battery-backup mode
12
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WE must return high for a minimum of t
from CS or
Table 3. Clock and Control Register Map
WR2
t
from WE prior to the initiation of another read or write
WR1
BIT
24/12
DESCRIPTION
24-or 12-hour data representation
Alarm interrupt enable in battery-backup mode
Alarminterruptflag
cycle.
Data-in must be valid t
remain valid for t
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CS and
prior to the end of write and
afterward. OE should be kept
DW
ABE
or t
DH1
DH2
AF
AIE
Alarminterruptenable
ALM0–ALM1
BVF
Alarm mask bits
OE, a low on WE disables the outputs t after WE falls.
WZ
Battery-validflag
READING THE CLOCK
DSE
Daylight savings enable
Periodicinterruptflag
Once every second, the user-accessible clock/calendar
locations are updated simultaneously from the internal
real-time counters. To prevent reading data in transition,
updates to the bq4802Y/bq4802LY clock registers should
behalted. Updatingishaltedbysettingtheupdatetransfer
inhibit (UTI) bit D3 of the control register E. As long as the
UTI bit is 1, updates to user-accessible clock locationsare
inhibited. Once the frozen clock information is retrieved by
reading the appropriate clock memory locations, the UTI
bit should be reset to 0 in order to allow updates to occur
from the internal counters. Because the internal counters
are not halted by setting the UTI bit, reading the clock
locationshas no effectonclockaccuracy. Once the UTI bit
is reset to 0, the internal registers update within one
secondtheuser-accessibleregisterswiththecorrecttime.
A halt command issued during a clock update allows the
update to occur before freezing the data.
PF
PIE
Periodicinterruptenable
PM or AM indication
PM/AM
PWRF
PWRIE
RS0–RS3
STOP
UTI
Power-failinterruptflag
Power-failinterruptenable
Periodicinterruptrate
Oscillator stop and start
Updatetransferinhibit
WD0–WD2
Watchdogtime-outrate
CLOCK MEMORY INTERFACE
The bq4802Y/bq4802LY has the same interface for
clock/calendar and control information as standard
SRAM. To read and write to these locations, the user must
put the bq4802Y/bq4802LY in the proper mode and meet
the timing requirements.
SETTING THE CLOCK
READ MODE
The UTI bit must also be used to set the
bq4802Y/bq4802LY clock. Once set, the locations can be
written with the desired information in BCD format.
Resetting the UTI bit to 0 causes the written values to be
transferred to the internal clock counters and allows
updates to the user-accessible registers to resume within
one second.
The bq4802Y/bq4802LY is in read mode whenever OE
(output enable) is low and CS (chip select) is low. The
unique address, specified by the four address inputs,
defines which one of the 16 clock/calendar bytes is to be
accessed. The bq4802Y/bq4802LY makes valid data
available at the data I/O pins within t (address access
AA
STOPPING AND STARTING THE CLOCK
OSCILLATOR
time). This occurs after the last address input signal is
stable, and providing the CS and OE (output enable)
access times are met. If the CS and OE access times are
not met, valid data is available after the latter of chip select
Thebq4802Y/bq4802LY clock can beprogrammedtoturn
offwhenthepartgoesintobatteryback-upmodebysetting
STOP to 0 prior to power down. If the board using the
bq4802Y/bq4802LY is to spend a significant period of time
in storage, the STOP bit can be used to preserve some
battery capacity. STOP set to 1 keeps the clock running
access time (t
) or output enable access time (t ).
ACS
OE
CS and OE control the state of the eight three-state data
I/O signals. Iftheoutputsareactivatedbeforet , the data
AA
lines are driven to an indeterminate state until t . If the
AA
when V drops below V . With V greater than V ,
CC
SO
CC
SO
address inputs are changed while CS and OE remain low,
thebq4802Y/bq4802LY clock runs regardless of the state
of STOP.
output data remains valid for t (output data hold time),
OH
but goes indeterminate until the next address access.
POWER-DOWN/POWER-UP CYCLE
WRITE MODE
The bq4802Y/bq4802LY continuously monitors V
for
CC
The bq4802Y/bq4802LY is in write mode whenever WE
and CS are active. The start of a write is referenced from
the latter-occurring falling edge of WE or CS. A write is
terminated by the earlier rising edge of WE or CS. The
addresses must be held valid throughout the cycle. CS or
out-of-tolerance. During a power failure, when V falls
CC
below V
, the bq4802Y/bq4802LY write-protects the
PFD
clock and storage registers. The power source isswitched
to BC when V is less than V and BC is greater than
CC
PFD
V
, or when V is less than V and V is less than
PFD
CC BC BC
13
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
V
. RTC operation and storage data are sustained by a
PFD
Power-On Reset
validbackupenergysource. WhenV is above V
,the
CC
PFD
Thebq4802Y/bq4802LYprovidesapower-onreset,which
pulls the RST pin low on power down and remains low on
power source is V . Write-protection continues for t
CC
CSR
time after V rises above V
.
CC
PFD
power up for t
after V
passes V
. With valid
PFD
RST
CC
battery voltage on BC, RST remains valid for V = V
.
SS
CC
An external CMOS static RAM is battery-backed using the
and chip enable output pins from the bq4802Y/
V
Push-Button Reset
OUT
bq4802LY. As the voltage input V slews down during a
CC
The bq4802Y/bq4802LY also provides a push-button
override to the reset when the device is not already in a
reset cycle. When the RST pin is released after being
pulled low for 1 µs then the RST stays low for 200 ms
(typical).
power failure, the chip enable output, CE
, is forced
OUT
inactive independent of the chip enable input CE .
IN
This activity unconditionally write-protects the external
SRAM as V falls below V
. If a memory access is in
PFD
CC
progress to the external SRAM during power-fail
detection, that memory cycle continues to completion
beforethe memory is write-protected. If the memory cycle
WATCHDOG TIMER
The watchdog monitors microprocessor activity through
the watchdog input (WDI). To use the watchdog function,
connect WDI to a bus line or a microprocessor I/O line. If
WDI remains high or low for longer than the watchdog
time-out period (1.5 seconds default), the bq4802Y/
bq4802LY asserts WDO and RST.
is not terminated within time t
, the chip enable output
WPT
is unconditionally driven high, write-protecting the
controlled SRAM.
As the supply continues to fall past V
, an internal
PFD
switching device forces V
to the external backup
OUT
Watchdog Input
energy source. CE
source.
is held high by the V
energy
OUT
OUT
The bq4802Y/bq4802LY resets the watchdog timer if a
change of state (high-to-low, low-to-high, or a minimum
100 ns pulse) occurs at the watchdog input (WDI) during
the watchdog period. The watchdog time-out is set by
WD0 – WD2 in register B. The bq4802Y/bq4802LY
maintains the watchdog time-out programming through
power cycles. The default state (no valid battery power) of
WD0 – WD2 is 000 or 1.5 s on power up. Table 3 shows
the programmable watchdog time-out rates. The
watchdog time-out period immediately after a reset is
equal to the programmed watchdog time-out.
Duringpowerup,V
isswitchedbacktothemainsupply
OUT
as V rises above the backup cell input voltage sourcing
CC
V
. If V
OUT
< V onthebq4802Y/bq4802LY the switch
PFD BC
to the main supply occurs at V
.
is held inactive
PFD CEOUT
for time t
(200-ms maximum) after the power supply
CER
has reached V
, independent of the CE input, to allow
PFD
IN
for processor stabilization.
During power-valid operation, the CE input is passed
IN
through to the CE
output with a propagation delay of
OUT
To disable the watchdog function, leave WDI floating. An
internalresistornetwork(100-kΩ equivalentimpedanceat
WDI) biases WDI to approximately 1.6 V. Internal
comparators detect this level and disable the watchdog
less than 12 ns. Figure 2 shows the hardware hookup for
the external RAM, battery, and crystal.
A primary backup energy source input is provided on the
bq4802Y/bq4802LY. The BC input accepts a 3-V primary
battery, typically some type of lithium chemistry. Since the
bq4802Y/bq4802LY provides for reverse battery charging
protection, no diode or current limiting resistor is needed
in series with the cell. To prevent battery drain when there
timer. When V
is below the power-fail threshold, the
CC
bq4802Y/bq4802LY disables the watchdog function and
disconnects WDI from its internal resistor network, thus
making it high impedance.
Watchdog Output
is no valid data to retain, V
and CE
are internally
OUT
OUT
isolated from BC by the initial connection of a battery.
Following the first application of V above V , this
The watchdog output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
period. The bq4802Y/bq4802LY disables the watchdog
CC
PFD
isolation is broken, and the backup cell provides power to
and CE for the external SRAM. The crystal
V
function and WDO is a logic high when V is below the
OUT
OUT
CC
should be located as close to X1 and X2 as possible and
meetthespecificationsinthecrystalspecificationssection
of the electrical characteristics tables. With the specified
crystal, the bq4802Y/bq4802LY RTC is accurate to within
oneminutepermonthatroomtemperature.Intheabsence
ofacrystal,a32.768-kHzwaveformcanbefedintoX1with
X2grounded.Thepowersource andcrystalareintegrated
into the SNAPHAT modules.
power fail threshold, battery-backup mode is enabled, or
WDI is an open circuit. In watchdog mode, if no transition
occurs at WDI during the watchdog time-out period, the
bq4802Y/bq4802LY asserts RST for the reset time-out
period t1. WDO goes low and remains low until the next
transition at WDI. If WDI is held high or low indefinitely,
RST generates pulses (t1 seconds wide) every t3
seconds. Figure 11 shows the watchdog timing.
14
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WDI
WDO
t
2
RST
t
1
t
1
t
3
Figure 11. Watchdog Time-Out Period and Reset Active Time
Table 4. Watchdog and Reset Timeout Rates Table 5. Periodic Interrupt Rates
WATCHDOG
RESET TIMEOUT
PERIOD
WD2 WD1 WD0
PERIODIC
REGISTER BITS
TIMEOUT PERIOD
INTERRUPT
PERIOD
RS3
0
RS2
0
RS1
0
RS0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.50 s
23.4375ms
46.875 ms
93.750 ms
187.5 ms
375 ms
0.25 ms
3.9063 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
NONE
30.5175µs
61.035 µs
122.070µs
244.141µs
488.281µs
976.5625µs
1.95315ms
3.90625ms
7.8125 ms
15.625 ms
31.25 ms
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
750 ms
125 ms
0
1
1
0
3.0 s
0.5 s
0
1
1
1
INTERRUPTS
1
0
0
0
Thebq4802Y/bq4802LYallowsthreeindividuallyselected
interrupteventstogenerateaninterruptrequestontheINT
pin. These three interrupt events are:
1
0
0
1
1
0
1
0
1
0
1
1
D
D
D
The periodic interrupt, programmable to occur once
every 30.5 µs to 500 ms.
1
1
0
0
62.5 ms
1
1
0
1
125 ms
The alarm interrupt, programmable to occur once per
second to once per month.
1
1
1
0
250 ms
1
1
1
1
500 ms
The power-fail interrupt, which can be enabled to be
asserted when the bq4802Y/bq4802LY detects a
power failure.
ALARM INTERRUPT
An individual interrupt-enable bit in register C, the
interrupts register, enables the periodic, alarm and
power-fail interrupts. When an event occurs, its event flag
bit in the flags register, register D, is set. If the
corresponding event enable bit is also set, then an
interrupt request is generated. Reading the flags register
clearsallflagbitsandmakesINThighimpedance.Toreset
the flag register, the bq4802Y/bq4802LY addresses must
be held stable at register D for at least 50 ns to avoid
inadvertent resets.
Registers1, 3, 5, and 7 program the real-time clock alarm.
During each update cycle, the bq4802Y/bq4802LY
compares the date, hours, minutes, and seconds in the
clock registers with the corresponding alarm registers. If a
match between all the corresponding bytes is found, the
alarm flag AF in the flags register is set. If the alarm
interrupt is enabled with AIE, an interrupt request is
generatedonINT. Thealarmconditionisclearedbyaread
to the flags register. ALM1 – ALM0 in the alarm registers,
mask each alarm compare byte. Setting ALM1 (D7) and
ALM0 (D6) to 1 masks an alarm byte. Alarm byte masking
can be used to select the frequency of the alarm interrupt,
according to Table 6. The alarm interrupt can be made
active while the bq4802Y/bq4802LY is in the battery-
backup mode by setting ABE in the interrupts register.
Normally, the INT pin goes high-impedance during battery
backup. With ABE set, INT is driven low if an alarm
condition occurs and the AIE bit is set.
Periodic Interrupt
Bits RS3 – RS0 in the interrupt register program the rate
for the periodic interrupt. The user can interpret the
interruptin two ways, either by polling the flags register for
PF assertion or by setting PIE so that INT goes active
when the bq4802Y/bq4802LY sets the periodic flag.
ReadingtheflagsregisterresetsthePFbitandreturnsINT
to the high-impedance state. Table 5 shows the periodic
rates.
15
bq4802Y
bq4802LY
www.ti.com
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
Table 6. Alarm Frequency
1h
3h
5h
7h
ALARM FREQUENCY
Once per second
ALM1–ALM0 ALM1–ALM0 ALM1–ALM0 ALM1–ALM0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
Once per minute when seconds match
Once per hour, when minutes and seconds match
Once per day, when hours, minutes and seconds match
When date, hours minutes and seconds match
POWER–FAIL INTERRUPT
BATTERY–LOW WARNING
Thebq4802Y/bq4802LY checks the battery on power-up.
When the battery voltage is approximately 2.1 V, the
battery valid flag BVF in the flags register is set to a 0
indicating that clock and RAM data may be invalid.
When V
falls to the power-fail-detect point, the
CC
power-fail flag PWRF is set. If the power-fail interrupt
enable bit (PWRIE) is also set, then INT is asserted low.
The power-fail interrupt occurs
t
before the
WPT
bq4802Y/bq4802LY generates a reset and deselects.
16
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
BQ4802LYDSH
BQ4802LYDW
OBSOLETE
ACTIVE
SOP
DSH
28
28
TBD
Call TI
Call TI
0 to 70
0 to 70
4802LYDSH
4802LYDW
SOIC
DW
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BQ4802LYDWG4
BQ4802LYDWR
BQ4802LYDWRG4
BQ4802LYPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
DW
PW
PW
PW
PW
DW
DW
DW
DW
PW
PW
28
28
28
28
28
28
28
28
28
28
28
28
28
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
4802LYDW
4802LYDW
4802LYDW
4802LYPW
4802LYPW
4802LYPW
4802LYPW
4802YDW
4802YDW
4802YDW
4802YDW
4802YPW
4802YPW
1000
1000
50
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
Green (RoHS
& no Sb/Br)
BQ4802LYPWG4
BQ4802LYPWR
BQ4802LYPWRG4
BQ4802YDW
50
Green (RoHS
& no Sb/Br)
2000
2000
20
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
BQ4802YDWG4
BQ4802YDWR
BQ4802YDWRG4
BQ4802YPW
SOIC
20
Green (RoHS
& no Sb/Br)
SOIC
1000
1000
50
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
BQ4802YPWG4
50
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ4802LYDWR
BQ4802YDWR
SOIC
SOIC
DW
DW
28
28
1000
1000
330.0
330.0
32.4
32.4
11.35 18.67
11.35 18.67
3.1
3.1
16.0
16.0
32.0
32.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ4802LYDWR
BQ4802YDWR
SOIC
SOIC
DW
DW
28
28
1000
1000
367.0
367.0
367.0
367.0
55.0
55.0
Pack Materials-Page 2
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