BQ4852YMC-85 [TI]
RTC Module With 512Kx8 NVSRAM; RTC模块512Kx8 NVSRAM
| 型号： | BQ4852YMC-85 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RTC Module With 512Kx8 NVSRAM |
| 文件： | 总16页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4852Y
RTC Module With 512Kx8 NVSRAM
Registers for the rea l-time clock,
alarm and other special functions
Features
General Description
➤ I n t e gr a t e d S R AM , r e a l-t im e
clock, CPU supervisor, crysta l,
power-fa il con t r ol cir cu it , a n d
battery
The bq4852Y RTC Module is a non-
volatile 4,194,304-bit SRAM organ-
ized as 524,288 words by 8 bits with
a n in t egr a l a ccessible r ea l-t im e
clock and CPU supervisor. The CPU
supervisor provides a programmable
watchdog timer and a microproces-
sor reset. Other features include
alarm, power-fail, and periodic inter-
rupts, and a battery-low warning.
are located in registers 7FFF0h–
7FFFFh of the memory array.
The clock and alarm registers are
du a l-por t r ea d/wr it e SRAM loca-
tions that are updated once per sec-
ond by a clock control circuit from
the internal clock counters. The
dual-port registers allow clock up-
dates to occur without interrupting
n or m a l a ccess t o t h e r est of t h e
SRAM array.
➤ Rea l-Tim e Clock cou n t s h u n-
dredths of seconds through years
in BCD format
➤ RAM-like clock access
➤ Compatible with industry-
The device combines an internal lith-
ium battery, quartz crystal, clock and
power-fail chip, and a full CMOS
SRAM in a plastic 36-pin DIP mod-
ule. The RTC Module directly re-
places industry-standard SRAMs and
also fits into many EPROM and EE-
PROM sockets without any require-
ment for special write timing or limi-
tations on the number of write cycles.
standard 512K x 8 SRAMs
The bq4852Y also contains a power-
fail-detect circuit. The circuit dese-
lects the device whenever VCC falls
below tolerance, providing a high de-
gree of data security. The battery is
electrically isolated when shipped
from the factory to provide maxi-
mum battery capacity. The battery
remains disconnected until the first
➤ Unlimited write cycles
➤ 10-year minimum data retention
and clock operation in the ab-
sence of power
➤ Automatic power-fail chip dese-
lect and write-protection
➤ Watchdog timer, power-on reset,
alarm/periodic interrupt, power-
fail and battery-low warning
application of VCC
.
➤ Soft wa r e clock ca libr a t ion for
gr e a t e r t h a n ±1 m in u t e p e r
month accuracy
Pin Connections
Pin Names
A0–A18
CE
Address input
Chip enable
RST
NC
36
V
CC
1
2
3
4
5
6
7
8
NC
35
34
33
32
31
30
29
28
27
26
A
A
A
A
A
A
6
A
A
4
A
A
2
A
INT
18
16
14
12
A
A
15
17
RST
WE
Microprocessor reset
Write enable
WE
A
A
A
9
A
13
8
7
9
OE
Output enable
5
10
11
12
13
14
15
16
17
18
11
OE
3
DQ0–DQ7 Data in/data out
A
25
24
23
22
21
20
19
10
CE
DQ
1
INT
VCC
VSS
Programmable interrupt
A
0
7
DQ
0
DQ
DQ
DQ
DQ
6
5
4
3
DQ
+5 volts
Ground
1
DQ
2
V
SS
36-Pin DIP Module
PN485201.eps
Aug. 1996
1
bq4852Y
modes, power-on reset timing, watchdog timer activa-
tion, and interrupt generation.
Functional Description
Figure 1 is a block diagram of the bq4852Y. The follow-
ing sections describe the bq4852Y functional operation,
including memory and clock interface, data-retention
Internal
Quartz
Crystal
Time-
Base
Oscillator
.
.
.
.
.
.
-
-
-
64
8
64
4
3
:
16 1 MUX
Control/Status
Registers
CE
OE
RST
INT
Reset and
DQ -DQ
Interrupt
0
7
Clock/Calendar,
Alarm,
P
Bus
I/F
Generator
and Control Bytes
AD -AD
0
18
User Buffer
(16 Bytes)
WE
Clock/Calendar
Update
Storage
Registers
(524,288 Bytes)
V
Power-
Fail
Control
CC
Write-
Protect
Internal
Battery
BD-962
Figure 1. Block Diagram
Truth Table
VCC
CE
VIH
VIL
VIL
VIL
X
OE
X
WE
X
Mode
Deselect
Write
DQ
Power
Standby
Active
< VCC (max.)
High Z
DIN
X
VIL
VIH
VIH
X
> VCC (min.)
VIL
VIH
X
Read
DOUT
Active
Read
High Z
High Z
High Z
Active
< VPFD (min.) > VSO
Deselect
Deselect
CMOS standby
X
X
X
Battery-backup mode
≤ VSO
Aug. 1996
2
bq4852Y
output data remains valid for tOH (output data hold time),
but goes indeterminate until the next address access.
Address Map
The bq4852Y provides 16 bytes of clock and control status
registers and 524,272 bytes of storage RAM.
Write Mode
Figure 2 illustrates the address map for the bq4852Y. Table
1 is a map of the bq4852Y registers, and Table 2 describes
the register bits.
The bq4852Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the latter-
occurring falling edge of WE or CE. A write is terminated
by the earlier rising edge of WE or CE. The addresses
must be held valid throughout the cycle. CE or WE must
return high for a minimum of tWR2 from CE or tWR1 from
WE prior to the initiation of another read or write cycle.
Memory Interface
Read Mode
Data-in must be valid tDW prior to the end of write and re-
main valid for tDH1 or tDH2 afterward. OE should be kept
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CE and
OE, a low on WE disables the outputs tWZ after WE falls.
The bq4852Y is in read mode whenever OE (output enable)
is low and CE (chip enable) is low. The device architecture
allows ripple-through access of data from eight of 4,194,304
locations in the static storage array. Thus, the unique ad-
dress specified by the 19 address inputs defines which one
of the 524,288 bytes of data is to be accessed. Valid data is
available at the data I/O pins within tAA (address access
time) after the last address input signal is stable, providing
that the CE and OE (output enable) access times are also
satisfied. If the CE and OE access times are not met, valid
data is available after the latter of chip enable access time
(tACE) or output enable access time (tOE).
Data-Retention Mode
With valid VCC applied, the bq4852Y operates as a
conventional static RAM. Should the supply voltage
decay, t he RAM a ut om a t ica lly power-fa il deselect s,
write-protecting itself tWPT after VCC falls below VPFD
.
All outputs become high impedance, and all inputs are
treated as “don’t care.”
CE and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the
address inputs are changed while CE and OE remain low,
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory cycle
fails to terminate within time tWPT, write-protection takes
0
1
Year
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
7FFF7
7FFF6
7FFF5
7FFFF
Clock and
Control Status
Registers
16 Bytes
Month
Date
7FFF0
2
7FFEF
3
Days
4
Hours
5
Minutes
6
Seconds
Control
7
8
Watchdog
Interrupts
Storage
RAM
524,272
Bytes
9
10
11
Alarm Date
Alarm Hours 7FFF4
12 Alarm Minutes 7FFF3
Alarm Seconds
13
14
15
7FFF2
7FFF1
7FFF0
Tenths/
Hundredths
0000
Flags
FG4852Y1
Figure 2. Address Map
3
Aug. 1996
bq4852Y
place. When VCC drops below VSO, the control circuit
switches power to the internal energy source, which pre-
serves data.
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because
the internal counters are not halted by setting the read
bit, reading the clock locations has no effect on clock ac-
curacy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
The internal coin cell maintains data in the bq4852Y af-
ter the initial application of VCC for an accumulated period
of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to external VCC
.
Write-protection continues for tCER after VCC reaches VPFD to
allow for processor stabilization. After tCER, normal RAM op-
eration can resume.
Setting the Clock
Clock Interface
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (7FFFF–7FFF9).
Reading the Clock
The interface to the clock and control registers of the
bq4852Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4852Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
Table 1. bq4842 Clock and Control Register Map
Address
7FFFF
7FFFF
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
7FFF7
7FFF6
7FFF5
7FFF4
7FFF3
7FFF2
7FFF1
7FFF0
D7
D6
D5
X
D4
D3
D2
Year
D1
D0
Range (h)
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–31
Register
Year
10 Years
X
X
X
X
10 Month
Month
Date
Month
10 Date
Date
X
FTE
X
X
X
X
Day
Hours
Days
X
10 Hours
Hours
X
10 Minutes
10 Seconds
S
Minutes
Seconds
Minutes
OSC
W
Seconds
R
Calibration
Control
WDS
AIE
ALM3
ALM2
ALM1
ALM0
BM4
BM3
BM2
PIE
BM1
RS3
BM0
RS2
WD1 WD0
RS1 RS0
Watchdog
Interrupts
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.1/0.01 seconds
Flags
PWRIE ABE
X
X
10-date alarm
10-hour alarm
Alarm date
Alarm hours
Alarm minutes
Alarm seconds
0.01 seconds
01–31
00–23
00–59
00–59
00–99
Alarm 10 minutes
Alarm 10 seconds
0.1 seconds
AF PWRF
WDF
BLF
PF
X
X
X
Notes:
X = Unused bits; can be written and read.
Clock/Calendar data in 24-hour BCD format.
BLF = 1 for low battery.
OSC = 1 stops the clock oscillator.
Interrupt enables are cleared on power-up.
Aug. 1996
4
bq4852Y
adjust the calibration based on the typical operating
temperature of individual applications.
Table 2. Clock and Control Register Bits
The software calibration bits are located in the control
register. Bits D0–D4 control the magnitude of correc-
tion, and bit D5 the direction (positive or negative) of
correction. Assuming that the oscillator is running at
exactly 32,786 Hz, each calibration step of D0–D4 ad-
justs the clock rate by +4.068 ppm (+10.7 seconds per
month) or -2.034 ppm (-5.35 seconds per month) depend-
ing on the value of the sign bit D5. When the sign bit is
1, positive adjustment occurs; a 0 activates negative ad-
justment. The total range of clock calibration is +5.5 or
-2.75 minutes per month.
Bits
Description
Alarm interrupt enable in
battery-backup mode
ABE
AF
Alarm interrupt flag
AIE
Alarm interrupt enable
ALM0–ALM3 Alarm repeat rate
BLF
Battery-low flag
BM0–BM4
FTE
Watchdog multiplier
Frequency test mode enable
Oscillator stop
Two methods can be used to ascertain how much cali-
bration a given bq4852Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system’s environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.
OSC
PF
Periodic interrupt flag
Periodic interrupt enable
Power-fail interrupt flag
Power-fail interrupt enable
Read clock enable
PIE
PWRF
PWRIE
R
RS0–RS3
S
Periodic interrupt rate
Calibration sign
The second approach uses a bq4852Y test mode. When
the frequency test mode enable bit FTE in the days reg-
ister is set to a 1, and the oscillator is running at exactly
32,768 Hz, the LSB of the seconds register toggles at
512 Hz. Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz
W
Write clock enable
WD0–WD1
WDF
WDS
Watchdog resolution
Watchdog flag
indicates a (1E6 0.01024)/512 or +20 ppm oscillator fre-
Watchdog steering
*
quency error, requiring ten steps of negative calibration
(10 -2.034 or -20.34) or 001010 to be loaded into the calibra-
*
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock on or
off. If the bq4852Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
Calibrating the Clock
The bq4852Y real-time clock is driven by a quartz con-
trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4852Y
package along with the battery. The clock accuracy of
the bq4852Y module is tested to be within 20ppm or
about 1 minute per month at 25°C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4852Y of-
fers onboard software clock calibration. The user can
Figure 3. Frequency Error
Aug. 1996
5
bq4852Y
tion byte for correction. To read the test frequency, the
bq4852Y must be selected and held in an extended read
of the seconds register, location 7FFF9, without having
the read bit set. The frequency appears on DQ0. The FTE
bit must be set using the write bit control. The FTE bit must
be reset to 0 for normal clock operation to resume.
Interrupts
The bq4852Y allows four individually selected interrupt
events to generate an interrupt request on the INT pin.
These four interrupt events are:
The watchdog timer interrupt, programmable to
occur according to the time-out period and conditions
described in the watchdog timer section
Power-On Reset
The bq4852Y provides a power-on reset, which pulls the
RST pin low on power-down and remains low on power-
up for tCER after VCC passes VPFD.
The periodic interrupt, programmable to occur once
every 122µs to 500ms.
The alarm interrupt, programmable to occur once per
second to once per month
Watchdog Timer
The power-fail interrupt, which can be enabled to be
asserted when the bq4852Y detects a power failure
The watchdog circuit monitors the microprocessor’s ac-
tivity. If the processor does not reset the watchdog timer
within the programmed time-out period, the circuit as-
serts the INT or RST pin. The watchdog timer is acti-
vated by writing the desired time-out period into the
eight-bit watchdog register described in Table 3 (device
address 7FFF7). The five bits (BM4–BM0) store a bi-
The periodic, alarm, and power-fail interrupts are en-
abled by an individual interrupt-enable bit in register
7FFF6, the interrupts register. When an event occurs,
its event flag bit in the flags register, location 7FFF0, is
set. If the corresponding event enable bit is also set,
then an interrupt request is generated. Reading the
flags register clears all flag bits and makes INT high im-
pedance. To reset the flag register, the bq4852Y ad-
dresses must be held stable at location 7FFF0 for at
least 50ns to avoid inadvertent resets.
n a r y m u lt ip lie r, a n d t h e t w o low e r -or d e r b it s
1
(WD1–WD0) select the resolution, where 00 =
second,
01 = second, 10 = 1 second, and 11 = 4 seconds. 16
1
4
The time-out period is the multiplication of the five-bit
multiplier with the two-bit resolution. For example,
writing 00011 in BM4–BM0 and 10 in WD1–WD0 re-
sults in a total time-out setting of 3 x 1 or 3 seconds. A
multiplier of zero disables the watchdog circuit. Bit 7 of
the watchdog register (WDS) is the watchdog steering
bit. When WDS is set to a 1 and a time-out occurs, the
watchdog asserts a reset pulse for tCER on the RST pin.
During the reset pulse, the watchdog register is cleared to all
zeros disabling the watchdog. When WDS is set to a 0, the
watchdog asserts the INT pin on a time-out. The INT pin re-
mains low until the watchdog is reset by the microprocessor
or a power failure occurs. Additionally, when the watchdog
times out, the watchdog flag bit (WDF) in the flags register,
location 7FFF0, is set.
Periodic Interrupt
Bits RS3–RS0 in the interrupts register program the
rate for the periodic interrupt. The user can interpret
the interrupt in two ways: either by polling the flags
register for PF assertion or by setting PIE so that INT
goes active when the bq4852Y sets the periodic flag. Read-
ing the flags register resets the PF bit and returns INT to
the high-impedance state. Table 4 shows the periodic
rates.
Alarm Interrupt
Registers 7FFF5–7FFF2 program the real-time clock
alarm. During each update cycle, the bq4852Y com-
pares the date, hours, minutes, and seconds in the clock
registers with the corresponding alarm registers. If a
match between all the corresponding bytes is found, the
alarm flag AF in the flags register is set. If the alarm
interrupt is enabled with AIE, an interrupt request is
generated on INT. The alarm condition is cleared by a
To reset the watchdog timer, the microprocessor must
write to the watchdog register. After being reset by a
write, the watchdog time-out period starts over. As a
precaution, the watchdog circuit is disabled on a power
failure. The user must, therefore, set the watchdog at
boot-up for activation.
Table 3. Watchdog Register Bits
MSB
7
Bits
LSB
0
6
5
4
3
2
1
WDS
BM4
BM3
BM2
BM1
BM0
WD1
WD0
Aug. 1996
6
bq4852Y
read to the flags register. ALM3–ALM0 puts the alarm
into a periodic mode of operation. Table 5 describes the
selectable rates.
Power-Fail Interrupt
When VCC falls to the power-fail-detect point, the power-
fail flag PWRF is set. If the power-fail interrupt enable bit
(PWRIE) is also set, then INT is asserted low. The power-
fail interrupt occurs tWPT before the bq4852Y generates a
reset and deselects. The PWIE bit is cleared on power-up.
The a la rm int errupt ca n be m a de a ct ive while t he
bq4852Y is in the battery-backup mode by setting ABE
in the interrupts register. Normally, the INT pin tri-
states during battery backup. With ABE set, however, INT
is driven low if an alarm condition occurs and the AIE bit is
set. Because the AIE bit is reset during power-on reset, an
alarm generated during power-on reset updates only the
flags register. The user can read the flags register during
boot-up to determine if an alarm was generated during
power-on reset.
Battery-Low Warning
The bq4852Y checks the internal battery on power-up.
If the battery voltage is below 2.2V, the battery-low flag
BLF in the flags register is set to a 1 indicating that
clock and RAM data may be invalid.
Table 4. Periodic Rates
RS3
0
RS2
0
RS1
0
RS0
0
Interrupt Rate
None
0
0
0
1
10ms
0
0
1
0
100ms
0
0
1
1
122.07µs
244.14µs
488.281
976.5625
1.953125ms
3.90625ms
7.8125ms
15.625ms
31.25ms
62.5ms
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
125ms
1
1
1
0
250ms
1
1
1
1
500ms
Table 5. Alarm Frequency (Alarm Bits DQ7 of Alarm Registers)
ALM3
ALM2
ALM1
ALM0
Alarm Frequency
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per second
Once per minute when seconds match
Once per hour when minutes, and seconds match
Once per day when hours, minutes, and seconds match
When date, hours, minutes, and seconds match
Aug. 1996
7
bq4852Y
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
V
T ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
0 to +70
-40 to +70
-10 to +70
+260
°C
°C
°C
°C
Storage temperature (VCC off; oscillator off)
Temperature under bias
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Maxim u m Ratin gs are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (T = T
)
OPR
A
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical
Maximum
Unit
V
Notes
4.5
0
5.0
5.5
0
VSS
Supply voltage
0
-
V
VIL
Input low voltage
Input high voltage
-0.3
2.2
0.8
V
VIH
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
Aug. 1996
8
bq4852Y
DC Electrical Characteristics (T = T
V
≤ V
≤ V
CC CCMAX)
A
OPR, CCMIN
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
± 1
µA
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
-
-
± 1
µA
VOH
VOL
IOD
Output high voltage
Output low voltage
2.4
-
-
-
-
0.4
-
V
V
IOH = -1.0 mA
IOL = 2.1 mA
VOL = 0.4V
CE = VIH
RST, INT sink current
Standby supply current
10
-
-
mA
mA
ISB1
3
6
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ISB2
Standby supply current
-
2
4
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
ICC
Operating supply current
-
-
90
mA
VPFD
VSO
Power-fail-detect voltage
Supply switch-over voltage
4.30
-
4.37
3
4.50
-
V
V
Notes:
Typical values indicate operation at TA = 25°C, VCC = 5V.
RST and INT are open-drain outputs.
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
A
CC
Symbol
CI/O
Parameter
Minimum
Typical
Maximum
Unit
pF
Conditions
Output voltage = 0V
Input voltage = 0V
Input/output capacitance
Input capacitance
-
-
-
-
10
10
CIN
pF
Note:
These parameters are sampled and not 100% tested.
Aug. 1996
9
bq4852Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5 ns
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 4 and 5
Figure 4. Output Load A
Figure 5. Output Load B
Read Cycle (T = T
V
≤ V
CCMAX)
A
OPR, CCMIN ≤ VCC
-85
Min.
Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
tRC
Read cycle time
85
-
-
85
85
45
-
tAA
Address access time
Output load A
tACE
tOE
Chip enable access time
-
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
0
-
0
35
25
-
0
10
Aug. 1996
10
bq4852Y
1,2
Read Cycle No. 1 (Address Access)
1,3,4
Read Cycle No. 2 (CE Access)
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
.
Aug. 1996
11
bq4852Y
Write Cycle (T =T
V
V
≤ V
)
A
OPR , CCMIN ≤ CC
CCMAX
-85
Min.
85
Max.
Symbol
tWC
Parameter
Write cycle time
Units
ns
Conditions/Notes
-
-
-
tCW
Chip enable to end of write
Address valid to end of write
75
ns
(1)
(1)
tAW
75
ns
Measured from address valid to begin-
ning of write. (2)
tAS
Address setup time
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Measured from beginning of write to
end of write. (1)
tWP
Write pulse width
65
5
Measured from WE going high to end
of write cycle. (3)
tWR1
tWR2
tDW
tDH1
tDH2
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Measured from CE going high to end of
write cycle. (3)
15
35
0
Measured to first low-to-high transi-
tion of either CE or WE.
Measured from WE going high to end
of write cycle. (4)
Measured from CE going high to end of
write cycle. (4)
10
tWZ
tOW
Write enabled to output in high Z
Output active from end of write
0
0
30
-
ns
ns
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1996
12
bq4852Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Aug. 1996
13
bq4852Y
Power-Down/Power-Up Cycle (T = T
A
OPR)
Typical
Symbol
tPF
Parameter
Minimum
300
Maximum
Unit
µs
Conditions
VCC slew, 4.50 to 4.20 V
VCC slew, 4.20 to VSO
-
-
-
-
tFS
10
µs
VCC slew, VSO to VPFD
(max.)
tPU
0
-
-
µs
Time during which SRAM is
write-protected after VCC
passes VFPD on power-up.
tCER
Chip enable recovery time
40
100
200
ms
Data-retention time in
absence of VCC
tDR
10
40
-
-
years TA = 25°C. (2)
Delay after VCC slews down
tWPT
Write-protect time
100
160
µs
past VPFD before SRAM is
write-protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing
Notes:
1. PWRIE is set to “1” to enable power fail interrupt.
2. RST and INT are open drain and require an external pull-up resistor.
Aug. 1996
14
bq4852Y
MC: 36-Pin C-Type Module
(C-Type Module)
36-Pin MC
Inches
Millimeters
Min.
0.365
0.015
0.017
0.008
2.070
0.710
0.590
0.090
0.120
0.175
Max.
0.375
-
Min.
9.27
0.38
0.43
0.20
52.58
18.03
14.99
2.29
3.05
4.45
Max.
9.53
-
Dimension
A
A1
B
C
D
E
0.023
0.013
2.100
0.740
0.630
0.110
0.150
0.210
0.58
0.33
53.34
18.80
16.00
2.79
3.81
5.33
e
G
L
S
Ordering Information
bq4852Y MC -
Sp eed Op tion s:
85 = 85 ns
Pa ck a ge Op tion :
MC = C-type module
Device:
bq4852Y 512K x 8 Real-Time Clock Module
May 1997
15
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