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bq51020, bq51021

ZHCSCI8 –MAY 2014

bq5102x 5W (WPC) 单芯片无线电源接收器

1 特性

3 说明

1

•

功耗减少 50% 的强健 5W 解决方案，以改进热性

能

bq5102x 器件是一款全封闭无线电源接收器，此接收

器能够在 WPC v1.1 协议下运行，这使得无线电源系

统在与 Qi 感应发射器一同使用时能够向系统传送高达

5W 的功率。 bq5102x 器件提供针对这 WPC 技术规

格的单个器件功率转换（整流和稳压），以及数字控制

和通信。借助市场领先的效率和可调输出电

压，bq5102x 器件可实现独一无二的效率和系统优

化。 I²C 还使得系统设计人员能够执行有趣的全新特

性，诸如发射器表面的接收器对齐，或者检测接收器上

的异物。此接收器可在市场领先的封装尺寸、效率和

解决方案尺寸中同时实现同步整流、稳压和控制与通

信。

–

针对最薄解决方案的无电感器接收器

–

可调节输出电压（4.5 至 8V），以实现线圈和

热性能优化

–

完全同步整流器的效率达 96%

效率 97% 的高效后置稳压器

功率 5W 时，系统效率 79%

•

符合 WPC v1.1 标准的通信

已获专利的发射器垫 (Transmitter Pad) 检测功能提

升了用户体验

通过 I²C 实现的对齐特性使得用户协商能够在 TX

表面找到最佳位置

•

器件信息⁽¹⁾

2 应用范围

产品型号

封装

封装尺寸（标称值）

bq51020

芯片尺寸球状引脚栅

格阵列 (DSBGA)

(42)

•

智能手机、平板电脑和头戴式耳机

Wi-Fi 热点

3.60mm x 2.89mm²

bq51021

移动电源

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

其他手持式器件

4 简化电路原理图

bq5102X

System

Load

AD-EN

bq5102x 系统效率 5V 输出

AD

OUT

C_COMM1

COMM1

C_BOOT1

BOOT1

C₁

90

80

70

60

50

40

30

20

C₄

C₃

R₇

R₆

RECT

AC1

VO_REG

VTSB

C₂

COIL

AC2

BOOT2

COMM2

TS/CTRL

TMEM

C_BOOT2

z

HOST

NTC

C_COMM2

C_CLAMP2

C_CLAMP1

CLAMP2

CLAMP1

C₅

WPG

PD_DET

SCL

TERM

SDA

CM_ILIM

10

PGND

FOD

ILIM

WPC A1 TX

1.1 1.2

0

R₁

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_OUT(A)

1

D001

R_FOD

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLUSBX1

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 19

8.5 Register Maps......................................................... 22

Applications and Implementation ...................... 26

9.1 Application Information............................................ 26

9.2 Typical Applications ................................................ 26

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 Handling Ratings....................................................... 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Typical Characteristics............................................ 10

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 13

9

10 Power Supply Recommendations ..................... 34

11 Layout................................................................... 35

11.1 Layout Guidelines ................................................. 35

11.2 Layout Example .................................................... 35

12 器件和文档支持 ..................................................... 36

12.1 相关链接................................................................ 36

12.2 Trademarks........................................................... 36

12.3 Electrostatic Discharge Caution............................ 36

12.4 Glossary................................................................ 36

13 机械封装和可订购信息 .......................................... 37

8

5 修订历史记录

日期

修订版本

注释

2014 年 5 月

*

最初发布版本

2

bq51020, bq51021

www.ti.com.cn

ZHCSCI8 –MAY 2014

Device Comparison Table

Device

Mode

More

bq51221

bq51021

bq51020

Dual (WPC v1.1, PMA)

WPC v1.1

Adjustable output voltage, highest system efficiency, I²C

Adjustable output voltage, highest system efficiency, standalone

WPC v1.1

6 Pin Configuration and Functions

YFP (42 PINS)

A1

PGND

A2

PGND

A3

PGND

A4

PGND

A5

PGND

A6

PGND

B1

AC1

B2

AC1

B3

AC1

B4

AC2

B5

AC2

B6

AC2

C1

BOOT1

C2

RECT

C3

RECT

C4

RECT

C5

RECT

C6

BOOT2

D1

OUT

D2

OUT

D3

OUT

D4

OUT

D5

OUT

D6

OUT

E4

SCL

EN1

E1

CLAMP1

E2

AD

E3

AD_EN

E5

VTSB

E6

CLAMP2

F4

SDA

EN2

F1

COMM1

F2

FOD

F3

TERM

F5

WPG

F6

COMM2

G1

G2

G3

G4

G5

G6

VO_REG

ILIM

CM_ILIM

TS/CTRL

TMEM

PD_DET

Pin Functions

NUMBER

TYPE

DESCRIPTION

NAME

AC1

B1, B2, B3

B4, B5, B6

E2

I

AC input power from receiver resonant tank

Adapter sense pin

AC2

AD

Push-pull driver for dual PFET circuit that can pass AD input to the OUT pin; used for adapter mux

control

AD-EN

E3

O

BOOT1

BOOT2

CLAMP1

CLAMP2

COMM1

COMM2

C1

C6

E1

E6

F1

F6

O

Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier

Open-drain FETs used to clamp the secondary voltage by providing low impedance across

secondary

Open-drain FETs used to communicate with primary by varying reflected impedance

Enables or disables communication current limit; can be pulled high to disable or pull low enable

communication current limit

CM_ILIM

G3

I

EN1 and EN2 are used for I²C communication in bq5020. Ground if not needed. SCL and SDA are

used in bq51021.

EN1

EN2

FOD

ILIM

E4

F4

F2

G2

I

Input that is used for scaling the received power message

Output current or overcurrent level programming pin

I/O

D1, D2, D3, D4,

D5, D6

OUT

O

Output pin, used to deliver power to the load

3

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NUMBER

PD_DET

G6

O

–

Open drain output that allows user to sense when receiver is on transmitter surface

Power and logic ground

A1, A2, A3, A4,

A5, A6

PGND

RECT

SCL

C2, C3, C4, C5

O

I

Filter capacitor for the internal synchronous rectifier

SCL and SDA are used for I²C communication in bq5021. Ground if not needed. EN1 and EN2 are

used in bq51020.

E4

F4

F3

SDA

I

TERM

I

Unused. Float in all WPC receivers

TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to

retain memory of state

TMEM

G5

G4

O

I

Temperature sense. Can be pulled high to send end power transfer (EPT – charge complete) to TX.

Can be pulled low to send EPT – Overtemperature

TS/CTRL

VO_REG

VTSB

G1

E5

F5

I

Sets the regulation voltage for output. Default value is 0.5 V

Voltage bias for temperature sense

WPG

O

Open-drain output that allows user to sense when power is transferred to load

4

bq51020, bq51021

www.ti.com.cn

ZHCSCI8 –MAY 2014

7 Specifications

7.1 Absolute Maximum Ratings

(2)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

AC1, AC2

–0.8

20

RECT, COMM1, COMM2, OUT, , CLAMP1, CLAMP2, WPG,

PD_DET

–0.3

20

Input voltage

AD, AD-EN

–0.3

30

20

V

BOOT1, BOOT2

SCL, SDA, TERM, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VTSB,

VO_REG, LPRBEN

–0.3

7

Input current

AC1, AC2 (RMS)

OUT

2.5

1.5

15

A

Output current

Output sink current

T_J, junction temperature

WPG, PD_DET

COMM1, COMM2

mA

A

1.0

–40

150

°C

(1) All voltages are with respect to the PGND pin, unless otherwise noted.

(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN

–65

–2

MAX UNIT

T_stg

Storage temperature range

150

2

°C

kV

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾, 100 pF, 1.5 kΩ

Electrostatic

discharge

(1)

V_ESD

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾

–500

500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

10.0

1.0

UNIT

V

V_RECT

I_OUT

RECT voltage

4.0

Output current

A

I_AD-EN

I_COMM

T_J

Sink current

1

mA

ºC

COMMx sink current

Junction temperature

500

125

0

5

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

7.4 Thermal Information

bq5102x

THERMAL METRIC⁽¹⁾

UNIT

YFP (42 PINS)

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

49.7

0.2

6.1

1.4

6.0

°C/W

ψ_JB

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

6

bq51020, bq51021

www.ti.com.cn

ZHCSCI8 –MAY 2014

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) , I_LOAD= I_OUT

PARAMETER

TEST CONDITIONS

V_RECT: 0 to 3 V

MIN

TYP

2.8

MAX

UNIT

V

V_UVLO

Undervoltage lockout

Hysteresis on UVLO

2.9

V_HYS-UVLO

V_RECT: 3 to 2 V

V_RECT: 5 to 16 V

V_RECT: 16 to 5 V

393

mV

Input overvoltage

threshold

V_RECT-OVP

V_HYS-OVP

14.6

15.1

1.5

15.6

V

Hysteresis on OVP

Voltage at RECT pin set

by communication with

primary

V_RECT(REG)

V_RECT(TRACK)

I_LOAD-HYS

V_OUT+ 0.120

V_OUT+ 2.0

V

V_RECTregulation above

V_OUT

V_ILIM= 1.2 V

140

4

mV

I_LOADhysteresis for

dynamic V_RECTthresholds I_LOADfalling

as a % of I_ILIM

Rectifier under voltage

protection, restricts I_OUTat

V_RECT-DPM

3

3.1

8.8

3.2

9.2

V

Rectifier reverse voltage

protection with a supply at

the output

V_RECT-REV= V_OUT– V_RECT

V_OUT= 10 V

,

V_RECT-REV

QUIESCENT CURRENT

Quiescent current at the

I_OUT(standby)

output when wireless

power is disabled

V_OUT≤ 5 V, 0°C ≤ T_J≤ 85°C

20

35

µA

ILIM SHORT CIRCUIT

Highest value of R_ILIM

R_ILIM: 200 to 50 Ω. I_OUT

latches off, cycle power to

reset

resistor considered a fault

(short). Monitored for I_OUT

> 100 mA

R_ILIM-SHORT

t_DGL-Short

I_{LIM_SC}

209

1

235

Ω

Deglitch time transition

from ILIM short to I_OUT

disable

ms

mA

I_LIM-SHORT,OKenables the

ILIM short comparator

when I_OUTis greater than

this value

I_LOAD: 0 to 200 mA

I_LOAD: 200 to 0 mA

110

125

140

I_LIM-SHORT,OK

Hysteresis for I_LIM-

20

mA

A

_SHORT,OKcomparator

HYSTERESIS

Maximum I_LOADthat can be

delivered for 1 ms when ILIM

is shorted

Maximum output current

limit

I_OUT-CL

3.7

OUTPUT

I_LOAD= 1000 mA

I_LOAD= 1 mA

0.4950

0.4951

0.5013

0.5014

0.5075

0.5076

Feedback voltage set

point

V_{O_REG}

V

Current programming

factor for hardware short

circuit protection

R_ILIM= K_ILIM/ I_ILIM, where I_ILIM

is the hardware current limit

I_OUT= 850 mA

K_ILIM

842

AΩ

Current limit programming

range

I_{OUT_RANGE}

1500

mA

I

_OUT≥ 320 mA

I_OUT– 50

I_OUT+ 50

200

Output current limit during

communication

I_COMM

100 mA ≤ I_OUT< 320 mA

mA

s

I_OUT< 100 mA

Hold off time for the

communication current

limit during startup

t_HOLD-OFF

1

7

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) , I_LOAD= I_OUT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TS/CTRL

I_TS-Bias< 100 µA and

communication is active

(periodically driven, see

V_TS-Bias

TS bias voltage (internal)

1.8

V

t_TS/CTRL-Meas

)

CTRL pin threshold for a

high

V_CTRL-HI

V_TS/CTRL: 50 to 150 mV

90

105

120

mV

Time period of TS/CTRL

measurements, when TS

is being driven

TS bias voltage is only driven

when power packets are sent

T_TS/CTRL-Meas

V_TS-HOT

1700

ms

V

Voltage at TS pin when

device shuts down

0.38

THERMAL PROTECTION

Thermal shutdown

temperature

T_J(OFF)

155

20

°C

Thermal shutdown

hysteresis

T_J(OFF-HYS)

OUTPUT LOGIC LEVELS ON WPG

V_OL

Open drain WPG pin

I_SINK= 5 mA

V_WPG= 20 V

550

1

mV

µA

WPG leakage current

when disabled

I_OFF,STAT

COMM PIN

R_DS-ON(COMM)

COMM1 and COMM2

V_RECT= 2.6 V

1.0

Ω

Signaling frequency on

COMMx pin for WPC

f_COMM

2.00

Kb/s

COMMx pin leakage

current

V_COMM1= 20 V, V_COMM2= 20

V

I_OFF,COMM

1

µA

Ω

CLAMP PIN

R_DS-ON(CLAMP)

CLAMP1 and CLAMP2

0.5

ADAPTER ENABLE

V_ADrising threshold

voltage

V_AD-EN

V_AD0 V to 5 V

3.5

3.6

3.8

V

V_AD-EN-HYS

I_AD

V_AD-ENhysteresis

Input leakage current

V_AD5 V to 0 V

450

mV

V_RECT= 0 V, V_AD= 5 V

50

μA

Pullup resistance from AD-

EN to OUT when adapter

mode is disabled and

V_OUT> V_AD

R_{AD_EN-OUT}

V_AD= 0 V, V_OUT= 5 V

230

350

Ω

Voltage difference

between V_ADand V_AD-EN

when adapter mode is

enabled

V_AD= 5 V, 0°C ≤ T_J≤ 85°C

V_AD= 9 V, 0°C ≤ T_J≤ 85°C

4

3

4.5

6

5

7

V

V_{AD_EN-ON}

SYNCHRONOUS RECTIFIER

I_OUTat which the

synchronous rectifier

enters half synchronous

mode

I_SYNC-EN

I_OUT: 200 to 0 mA

I_OUT0 to 200 mA

100

mA

Hysteresis for I_OUT,RECT-EN

(full-synchronous mode

enabled)

I_SYNC-EN-HYST

40

mA

V

High-side diode drop when

the rectifier is in half

synchronous mode

I_AC-VRECT= 250 mA, and

T_J= 25°C

V_HS-DIODE

0.7

8

bq51020, bq51021

www.ti.com.cn

ZHCSCI8 –MAY 2014

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) , I_LOAD= I_OUT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I²C (ONLY FOR bq51021)

V_IL

Input low threshold level

SDA

V(PULLUP) = 1.8 V, SDA

V(PULLUP) = 1.8 V, SCL

Typical

0.4

V

V_IH

Input high threshold level

SDA

1.4

V_IL

Input low threshold level

SCL

0.4

V

V_IH

Input high threshold level

SCL

V

I²C speed

100

kHz

9

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

7.6 Typical Characteristics

0.50155

0.5015

0.50145

0.5014

0.50135

0.5013

0.50125

0.5012

60

50

40

30

20

10

0

0.0001

0.001

0.01

0.1

1

4

5

6

7

8

9

Load Current (A)

V_OUT(V)

D001

D002

Temp = 25°C

TX = bq500212A

Figure 1. Output Regulation as a Function of Load

Figure 2. Quiescent Current as a Function of Output Voltage

850

845

840

835

830

825

820

815

810

805

2.88

2.865

2.85

2.835

2.82

2.805

2.79

2.775

2.76

2.745

2.73

-60 -40 -20

0

20

40

60

80 100 120 140

250

350

450

550

650

750

850

950

Temperature (qC)

Load Current (mA)

D004

D001

Figure 4. UVLO as a Function of Junction Temperature

Figure 3. KILIM as a Function of Load Current

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

I²C Code

D001

Figure 5. VO_REG by Different I²C Codes, 1-mA Load

Figure 6. VO_REG by Different I²C Codes, 1-A Load

10

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www.ti.com.cn

ZHCSCI8 –MAY 2014

8 Detailed Description

8.1 Overview

WPC-based wireless power systems consist of a charging pad (primary, transmitter) and the secondary-side

equipment (receiver). There are coils placed in the charging pad and secondary equipment, which magnetically

couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the

secondary by transformer action between the coils. The receiver can achieve control over the amount of power

transferred by requesting the transmitter to change the field strength by changing the frequency, or duty cycle, or

voltage rail energizing the primary coil.

The receiver equipment communicates with the primary by modulating the load seen by the primary. This load

modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and

demodulated by the transmitter.

A WPC system communication is digital — packets are transferred from the secondary to the primary. Differential

bi-phase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication packets are

defined. These include identification and authentication packets, error packets, control packets, power usage

packets, and end power transfer packets, among others.

Power

bq5102x

Voltage/

System

Current

AC to DC

Drivers

Rectification

Load

Conditioning

Communication

LI-Ion

Battery

Charger

Controller

V/I

Sense

Controller

Transmitter

Receiver

Figure 7. Dual Mode Wireless Power System Indicating the Functional Integration of the bq5102x Family

The bq5102x device integrates fully-compliant WPC v1.1 communication protocol in order to streamline the

wireless power receiver designs (no extra software development required). Other unique algorithms such as

Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the smallest

solution size of the industry.

As a WPC system, when the receiver (shown in Figure 7) is placed on the charging pad, the secondary coil

couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the

secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the

LDO which feeds the output.

11

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

Overview (continued)

The bq5102x device identifies itself to the primary using the COMMx pins, switching on and off the COMM FETs,

and hence switching in and out COMM capacitors. If the authentication is successful, the primary remains

powered-up. The bq5102x device measures the voltage at the RECT pin, calculates the difference between the

actual voltage and the desired voltage V_RECT(REG), and sends back error packets to the transmitter. This process

goes on until the input voltage settles at V_{RECT(REG) MAX}. During a load change, the dynamic rectifier algorithm

sets the targets specified by targets between V_{RECT(REG) MAX}and V_{RECT(REG) MIN}shown in Table 1. This algorithm

enhances the transient response of the power supply while still allowing for very high efficiency at high loads.

After the voltage at the RECT pin is at the desired value, an internal pass FET (LDO) is enabled. The voltage

control loop ensures that the output voltage is maintained at V_OUT(REG), powering the downstream charger. The

bq5102x device meanwhile continues to monitor the RECT voltage, and keeps sending control error packets

(CEP) to the primary on average every 250 ms. If a large transient occurs, the feedback to the primary speeds

up to 32-ms communication periods to converge on an operating point in less time.

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8.2 Functional Block Diagram

RECT

,

OUT

V_REF,ILIM

V_ILIM

V_OUT,FB

V_OUT,REG

_

+

_

VOREG

V_REF,IABS

V_IABS,FB

+

_

ILIM

V_IN,FB

+

_

V_IN,DPM

AD

+

_

VREF_AD,OVP

BOOT2

BOOT1

_

+

VREF_AD,UVLO

AD-EN

AC1

AC2

Sync

Rectifier

Control

VIREG

T_S

COMM1

COMM2

V_BG,REF

V_IN,FB

V_OUT,FB

V_ILIM

ADC

DATA_OUT

V_IABS,FB

TS/CTRL

CLAMP1

CLAMP2

V_IABS,REF

V_IC,TEMP

V_FOD1

V_FOD2

V_FOD

V_RECT

V_OVP,REF

Digital Control

FOD

+

_

OVP

LPRB1 or

WPG

SCL

LPRB2 or

PD_DET

SDA

50uA

CM_ILIM

TMEM

+

_

LPRBEN or

TERM

ILIM

PGND

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8.3 Feature Description

8.3.1 Dynamic Rectifier Control

The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given

maximum output current setting. This is achieved by providing enough voltage headroom across the internal

regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a

relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target.

Therefore, a transient response is dependent on the loosely coupled transformer's output impedance profile. The

Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed

at the output of the internal regulator (output of the bq5102x device). A 1-A application allows up to a 2-Ω output

impedance. The Dynamic Rectifier Control behavior is illustrated in Figure 12.

8.3.2 Dynamic Power Scaling

The Dynamic Power Scaling feature allows for the loss characteristics of the bq5102x device to be scaled based

on the maximum expected output power in the end application. This effectively optimizes the efficiency for each

application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the

maximum output current. Note that the maximum output current is set by the K_ILIMterm and the R_ILIMresistance

(where R_ILIM= K_ILIM/ I_ILIM). The flow diagram in Figure 12 shows how the rectifier is dynamically controlled

(Dynamic Rectifier Control) based on a fixed percentage of the I_ILIMsetting. Table 1 summarizes how the rectifier

behavior is dynamically adjusted based on two different R_ILIMsettings. Table 1 shows I_MAX, which is typically

lower than I_ILIM(about 20% lower). See section RILIM Calculations about setting the ILIM resistor for more

details.

Table 1. Dynamic Rectifier Regulation

R_ILIM= 1400 Ω

I_MAX= 0.5 A

R_ILIM= 700 Ω

I_MAX= 1.0 A

Output Current Percentage

V_RECT

0 to 10%

10 to 20%

20 to 40%

> 40%

0 to 0.05 A

0.05 to 0.1 A

0.1 to 0.2 A

> 0.2 A

0 to 0.1 A

0.1 to 0.2 A

0.2 to 0.4 A

> 0.4 A

V_OUT+ 2.0

V_OUT+ 1.68

V_OUT+ 0.56

V_OUT+ 0.12

Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different R_ILIMsettings. With

the rectifier voltage (V_RECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control

thresholds dynamically adjusts the power dissipation across the LDO where,

P_DIS V

ꢂ V_OUTI

OUT

ꢀ

ꢁ

RECT

(1)

Figure 21 shows how the system efficiency is improved due to the Dynamic Power Scaling feature. Note that this

feature balances efficiency with optimal system transient response.

8.3.3 VO_REG Calculations

The bq5102x device allows the designer to set the output voltage by setting a feedback resistor divider network

from the OUT pin to the VO_REG pin, as seen in Figure 8. The resistor divider network should be chosen so that

the voltage at the VO_REG pin is 0.5 V at the desired output voltage. For the device bq51021 which has I²C

enabled, this applies to the default I²C code for VO_REG shown in I²C register in Figure 8.

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OUT

R₇

VO_REG

R₆

Figure 8. VO_REG Network

Choose the desired output voltage V_OUTand R₆:

0.5 V

K_VO

V_OUT

(2)

(3)

K _VOu R ₇

1 ꢀ K _VO

R ₆

8.3.4 RILIM Calculations

The bq5102x device includes a means of providing hardware overcurrent protection (I_ILIM) through an analog

current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum

allowable output current (for example, current compliance). The R_ILIMresistor size also sets the thresholds for the

dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The

calculation for the total R_ILIMresistance is as follows:

R_ILIM= K_ILIM/ I_ILIM

R₁= R_ILIM– R_FOD

(4)

(5)

R_ILIMallows for the ILIM pin to reach 1.2 V at an output current equal to I_ILIM. When choosing R_ILIM, two options

are possible.

If the user's application requires an output current equal to or greater than the external I_ILIMthat the circuit is

designed for (input current limit on the charger where the receiver device is tied higher than the external I_ILIM),

ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver

device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output

does not drop to 0. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on

the charger, the charger will pull the output of the receiver device to ground when the receiver device enters

current regulation. If the user's applications are designed to extract less than the I_ILIM(1-A maximum), typical

designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10%

more than maximum current is drawn from the output. Such a design would have input current limit on the

charger lower than the external ILIM of the receiver device. In both cases, the charger must be capable of

regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same

behavior is also necessary during the WPC communication. The following calculations show how such a design

is achieved:

R_ILIM= K_ILIM/ (1.1 × I_ILIM

R₁= R_ILIM– R_FOD

)

(6)

where I_LIMis the hardware current limit

(7)

When referring to the application diagram shown in Typical Applications, R_ILIMis the sum of the R₁and R_FOD

resistance (that is, the total resistance from the ILIM pin to GND). R_FODis chosen according to the application.

The tool for calculating R_FODcan be obtained by contacting your TI representative. Use R_FODto allow the

receiver implementation to comply with WPC v1.1 requirements related to received power accuracy. For the

device bq51021 which has I²C enabled, this applies to the default I²C code for IO_REG (100%) shown in I²C

register in Figure 8.

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8.3.5 Adapter Enable Functionality

The bq5102x device can also help manage the multiplexing of adapter power to the output and can turn off the

TX when the adapter is plugged in and is above the V_AD-EN. After the adapter is plugged in and the output turns

off, the RX device sends an EOC to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V

below AD, which allows the device turn on the back-to-back PMOS connected between AD and OUT (Figure 28).

Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. It must also be noted that it is

required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions.

Also, when AD mode is enabled, no load can be pulled from the RECT pin as this could cause an internal device

overvoltage in the bq5102x device.

For the device bq51021, the wired power will always take priority over wireless power, and thus when the

adapter is plugged in, the device will first send an EPT to the TX and then will send allow for up to 30 ms after

disabling the output allowing the WPG to go high impedance. It will then allow the wired power to be delivered to

the output by pulling the AD_EN below the AD pin to allow the adapter power to be passed on the output.

For the device bq51020, the EN1 and EN2 pins will determine the preference of wired or wireless power. Table 2

shows the EN1 and EN2 state and the corresponding device selection.

Table 2. Adapter Functionality EN1 and EN2

EN1

EN2

Adapter Insert

AD_EN

V_AD– 4 V

V_OUT/ V_AD

V_AD– 4 V

EPT Message

EPT 0x00

No EPT

Preference

0

1

0

1

0

5 V

Wired preference

Wireless preference

Wired preference⁽¹⁾

EPT 0x00

Neither wired nor

wireless⁽¹⁾

1

5 V

V_OUT/ V_AD

EPT 0x00

(1) Only valid when wireless power is present.

8.3.6 Turning Off the Transmitter

WPC v1.1 specification allows the receiver to turn off the transmitter and put the system in a low-power standby

mode. There are two different ways to accomplish this with the bq5102x device. The first method is by using the

TS/CTRL pin. By pulling the pin high or low, EPT can be sent to the transmitter.

Pulling the TS/CTRL pin high will send EPT (code 0x01), which corresponds to charge complete. The transmitter

will then respond to this EPT code as per the transmitter's design. After this EPT code is sent, some transmitters

will then periodically check to make sure that the receiver is not looking for a refresh charge on the battery. The

period of how often the transmitter checks varies based on the transmitter design. The transmitter will use the

digital ping or a shortened version of it to check the receiver status. It is this energy on the digital ping that the

receiver uses to indicate whether it is still sitting on the transmitter surface by storing the energy from the digital

ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the periodicity of the digital ping

and the bleed off resistor attached in parallel to the TMEM cap) determine when the receiver indicates that it is

no longer on the surface of the transmitter by allowing the PD_DET pin to go high impedance.

The TS/CTRL pin can also be pulled low. This will allow the receiver to determine that the host processor would

like to shut down the transmitter because of thermal reasons. Therefore, the receiver will send EPT (code 0x03)

indicating an overtemperature event.

8.3.6.1 End Power Transfer (EPT)

The WPC allows for a special command to terminate power transfer from the TX termed EPT packet. The v1.1

specifies the following reasons and their responding data field value in Table 3.

Table 3. End Power Transfer Codes in WPC

Reason

Unknown

Charge complete

Value

0x00

0x01

Condition⁽¹⁾

AD > 3.6 V

TS/CTRL > 1.4V

(1) The Condition column corresponds to the case where the bq5102x device will send the WPC EPT

command.

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Table 3. End Power Transfer Codes in WPC (continued)

Reason

Internal fault

Value

0x02

0x03

0x04

0x06

0x07

0x08

Condition⁽¹⁾

T_J> 150°C or R_ILIM< 100 Ω

TS < V_HOT, or TS/CTRL < 100 mV

Over temperature

Over voltage

Battery failure

Reconfigure

V_RECTtarget does not converge and stays higher or lower than target

Not sent

No response

8.3.7 Communication Current Limit

Communication current limit is a feature that allows for error free communication to happen between the RX and

TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current

during communication with the TX. The communication current limit is set according to the Table 4. The

communication current limit can be disabled by pulling CM_ILIM pin high (> 1.4 V) or enabled by pulling the

CM_ILIM pin low. There is an internal pulldown that enables communication current limit when the CM_ILIM pin

is left floating.

Table 4. Communication Current Limit

I_OUT

Communication Current Limit

None

0 mA < I_OUT< 100 mA

100 mA < I_OUT< 320 mA

320 mA < I_OUT< Max current

I_OUT+ 50 mA

I_OUT– 50 mA

When the communication current limit is enabled, the amount of current that the load can draw is limited. If the

charger in the system does not have a VIN-DPM feature, the output of the receiver will collapse if communication

current limit is enabled. To disable communication current limit, pull CM_ILIM pin high.

8.3.8 PD_DET and TMEM

PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM

is higher than 1.6 V, PD_DET will be low. The voltage on the TMEM pin depends on capturing the energy from

the digital ping from the transmitter and storing it on the C₅capacitor in Figure 9. After the receiver sends an EPT

(charge complete), the transmitter shuts down and goes into a low-power mode. After this EPT code is sent,

some transmitters will then periodically check to make sure that the receiver is not looking for a refresh charge

on the battery. The period of how often the transmitter checks varies based on the transmitter design. The

transmitter will use the digital ping or a shortened version of it to check the receiver status. It is this energy on the

digital ping that the receiver uses to indicate whether it is still sitting on the transmitter surface by storing the

energy from the digital ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the

periodicity of the digital ping and the bleed off resistor attached in parallel to the TMEM cap) determine when the

receiver indicates that it is no longer on the surface of the transmitter by allowing the PD_DET pin to go high

impedance. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes

the capacitor. A bleedoff resistor R_MEMcan be chosen in parallel with C₅that sets the time constant so that the

TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is

indeterminate and depends on each transmitter manufacturer.

TMEM

R_MEM

C₅

Figure 9. TMEM Configuration

Set capacitor on C₅= TMEM to 2.2 µF. Resistor R_MEMacross C₅can be set by understanding the duration

between digital pings (tping). Set the resistor such that:

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tping

R_MEM

4 u C₅

(8)

PD_DET typically requires a pullup resistor to an external source. The choice of the pullup resistor determines

load regulation; the suggested values for the pullup resistor are between 5.6 and 100 kΩ. The higher values offer

better load regulation.

8.3.9 TS/CTRL

The bq5102x device includes a ratio metric external temperature sense function. The temperature sense function

has a low ratio metric threshold which represents a hot condition. TI recommends an external temperature

sensor in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring

the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC)

resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to

adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel

resistor implementation for setting the threshold at which V_TS-HOTis reached. Once the V_TS-HOTthreshold is

reached, the device will send an EPT – overtemperature signal for a WPC transmitter.

VTSB

(1.8 V)

R₂

20 kꢀ

R₁

TS/CTRL

R₃

NTC

Figure 10. NTC Resistor Setup

Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of V_TS-HOT. T_S-HOTis VS. After

the NTC is chosen and R_NTCHOTat V_TS-HOTis determined from the data sheet of the NTC, Equation 9 can be

used to calculate R₁and R₃. In many cases depending on the NTC resistor, R₁or R₃can be omitted. To omit R₁,

set R₁to 0, and to omit R₃, set R₃to 10 MΩ.

R

ꢃ R₁u R

y

R

ꢃ R₁ꢃ R₃

ꢀ

ꢁ

ꢀ

ꢁ

ꢀ

ꢁ

NTCHO T

3

NTCHO T

T_{S ꢂHO T} 1.8 V u

R

ꢃ R₁u R

y

R

ꢃ R₁ꢃ R₃ꢃ R ₂

ꢀ

ꢁ

ꢀ

ꢁ

ꢀ

ꢁ

NTCHO T

3

NTCHO T

(9)

8.3.10 I²C Communication

Only bq51021

The bq5102x device allows for I²C communication with the internal CPU. In case the I²C is not used, ground SCL

and SDA. See Register Maps for more information.

8.3.11 Input Overvoltage

If the input voltage suddenly increases in potential for some condition (for example, a change in position of the

equipment on the charging pad), the voltage-control loop inside the bq5102x device becomes active, and

prevents the output from going beyond V_OUT(REG). The receiver then starts sending back error packets every 30

ms until the input voltage comes back to an acceptable level, and then maintains the error communication every

250 ms.

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If the input voltage increases in potential beyond V_RECT-OVP, the device switches off the LDO and informs the

primary to bring the voltage back to V_RECT(REG). In addition, a proprietary voltage protection circuit is activated by

means of C_CLAMP1and C_CLAMP2that protects the device from voltages beyond the maximum rating of the device.

8.4 Device Functional Modes

At startup operation, the bq5102x device must comply with proper handshaking to be granted a power contract

from the WPC transmitter. The transmitter initiates the handshake by providing an extended digital ping after

analog ping detects an object on the transmitter surface. If a receiver is present on the transmitter surface, the

receiver then provides the signal strength, configuration, and identification packets to the transmitter (see volume

1 of the WPC specification for details on each packet). These are the first three packets sent to the transmitter.

The only exception is if there is a true shutdown condition on the AD, or TS/CTRL pins where the receiver shuts

down the transmitter immediately. See Table 3 for details. After the transmitter has successfully received the

signal strength, configuration, and identification packets, the receiver is granted a power contract and is then

allowed to control the operating point of the power transfer. With the use of the bq5102x device Dynamic

Rectifier Control algorithm, the receiver will inform the transmitter to adjust the rectifier voltage approximately 8V

prior to enabling the output supply. This method enhances the transient performance during system startup. For

the startup flow diagram details, see Figure 11.

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Device Functional Modes (continued)

Tx Powered

without Rx

Active

Tx Extended Digital Ping

Yes

EN1/EN2/AD/TS-CTRL

EPT Condition?

Send EPT packet with

reason value

No

Identification,

Configuration, and SS,

Received by Tx?

No

Yes

Power Contract

Established. All

proceeding control is

dictated by the Rx.

Yes

Send control error packet

Is V

< 8 V?

RECT

to increase V

RECT

No

Startup operating point

established. Enable the

Rx output.

Rx Active

Power Transfer

Stage

Figure 11. Wireless Power Startup Flow Diagram on WPC TX

After the startup procedure is established, the receiver will enter the active power transfer stage. This is

considered the main loop of operation. The Dynamic Rectifier Control algorithm determines the rectifier voltage

target based on a percentage of the maximum output current level setting (set by K_ILIMand the R_ILIM). The

receiver will send control error packets in order to converge on these targets. As the output current changes, the

rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it

can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the

instantaneous transient response of the system is open loop and dependent on the receiver coil output

impedance at that operating point. The main loop also determines if any conditions in Table 3 are true in order to

discontinue power transfer. Figure 12 shows the active power transfer loop.

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Device Functional Modes (continued)

RX Active Power

Transfer Stage

TX Powered

without RX

Active

RX Shutdown

conditions per the

EPT Table?

Yes

Send EPT packet with reason

value

No

VRECT target = VO + 2 V.

Send control error packets to

converge.

Yes

VILIM < 0.1 V?

No

VRECT target = VO + 1.3 V.

Send control error packets to

converge.

Yes

VILIM < 0.2 V

No

VRECT target = VO + 0.6 V.

Send control error packets to

converge.

VILIM < 0.4 V

No

VRECT target = VO + 0.12 V.

Send control error packets to

converge.

Measure Received Power

and Send Value to TX

Figure 12. Active Power Transfer Flow Diagram on WPC

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8.5 Register Maps

Locations 0x01 and 0x02 can be written to any time. Locations 0xE0 to 0xFF are only functional when V_RECT

V_UVLO. When V_RECTgoes below V_UVLO, locations 0xE0 to 0xFF are reset.

>

Table 5. Wireless Power Supply Current Register 1 (READ / WRITE)

Memory Location: 0x01, Default State: 00000001

BIT

B7 (MSB)

B6

NAME

READ / WRITE

Read / Write

FUNCTION

Not used

B5

B4

B3

B2

V_OREG2

V_OREG1

V_OREG0

450, 500, 550, 600, 650, 700, 750, or 800 mV

Changes VO_REG target

Default value 001

B1

B0

SPACE

Table 6. Wireless Power Supply Current Register 2 (READ / WRITE)

Memory Location: 0x02, Default State: 00000111

BIT

B7 (MSB)

B6

NAME

READ / WRITE

Read / Write

FUNCTION

Not used

JEITA

B5

I_TERM2

I_TERM1

I_TERM0

I_OREG2

I_OREG1

I_OREG0

B4

Not used for bq5102x

B3

B2

10%, 20%, 30%, 40%, 50%, 60%, 90%, and 100% of I_ILIMcurrent

based on configuration

000, 001, …111

B1

B0

SPACE

Table 7. I²C Mailbox Register (READ / WRITE)

Memory Location: 0xE0, Reset State: 10000000

BIT

NAME

READ / WRITE

FUNCTION

B7

USER_PKT_DONE

Read

Set bit to 0 to send proprietary packet with header in 0xE2.

CPU checks header to pick relevant payload from 0xF1 to 0xF4

This bit will be set to 1 after the user packet with the header in register

0xE2 is sent.

B6

B5

USER_PKT_ERR

Read

00 = No error in sending packet

01 = Error: no transmitter present

10 = Illegal header found (packet will not be sent)

11 = Error: not defined yet

B4

B3

FOD Mailer

Read / Write

Not used

ALIGN Mailer

Setting this bit to 1 will enable alignment aid mode where the CEP = 0

will be sent until this bit is set to 0 (or CPU reset occurs) – see register

0xED

B2

B1

B0

FOD Scaler

Reserved

Read / Write

Not used

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Table 8. Wireless Power Supply FOD RAM (READ / WRITE)

Memory Location: 0xE1, Reset State: 00000000⁽¹⁾

BIT

B7 (MSB)

B6

NAME

ESR_ENABLE

OFF_ENABLE

Ro_FOD5

READ / WRITE

Read / Write

FUNCTION

Enables I²C based ESR in received power, Enable = 1, Disable = 0

Enables I²C based offset power, Enable = 1, Disable = 0

B5

000 – 0 mW

101 – +195 mW

110 – +234 mW

111 – +273 mW

The value is added to received power

message

001 – +39 mW

010 – +78 mW

011 – +117 mW

100 – +156 mW

B4

Ro_FOD4

B3

Ro_FOD3

B2

B1

B0

Rs_FOD2

Rs_FOD1

Rs_FOD0

Read / Write

000 – ESR

001 – ESR

010 – ESR × 2

011 – ESR × 3

100 – ESR × 4

101 – Not used

110 – Not used

111 – ESR/2

(1) A non-zero value will change the I²R calculation resistor and offset in the received power calculation by a factor shown in the table.

SPACE

Table 9. Wireless Power User Header RAM (WRITE)

Memory Location: 0xE2, Reset State: 00000000⁽¹⁾

BIT

B7 (MSB)

B6

READ / WRITE

Read / Write

B5

B4

B3

B2

B1

B0

(1) Must write a valid header to enable proprietary package. As soon as mailer (0xE0) is written, payload bytes are sent on the next

available communication slot as determined by CPU. After payload is sent, the mailer (USER_PKT_DONE) is set to 1.

SPACE

Table 10. Wireless Power USER V_RECTStatus RAM (READ)⁽¹⁾

Memory Location: 0xE3, Reset State: 00000000

Range – 0 to 12 V

This register reads back the V_RECTvoltage with LSB = 46 mV

BIT

B7 (MSB)

B6

NAME

V_RECT7

V_RECT6

V_RECT5

V_RECT4

V_RECT3

V_RECT2

V_RECT1

V_RECT0

READ / WRITE

Read

FUNCTION

Read

B5

Read

B4

Read

LSB = 46 mV

B3

Read

B2

Read

B1

Read

B0

Read

(1) V_RECTis above UVLO.

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Table 11. Wireless Power V_OUTStatus RAM (READ)⁽¹⁾

Memory Location: 0xE4, Reset State: 00000000

This register reads back the V_OUTvoltage with LSB = 46 mV

BIT

B7 (MSB)

B6

NAME

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

VOUT0

Read / Write

FUNCTION

B5

B4

LSB = 46 mV

B3

B2

B1

B0

(1) Ouput is enabled.

SPACE

Table 12. Wireless Power REC PWR Most Significant Byte Status RAM (READ)

Memory Location: 0xE8, Reset State: 00000000

This register reads back the received power with LSB = 39 mW

BIT

B7 (MSB)

B6

Read / Write

B5

B4

B3

B2

B1

B0

SPACE

Table 13. Wireless Power Prop Packet Payload RAM Byte 0 (WRITE)

Memory Location: 0xF1, Reset State: 00000000

BIT

B7 (MSB)

B6

Read / Write

B5

B4

B3

B2

B1

B0

SPACE

Table 14. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE)

Memory Location: 0xF2, Reset State: 00000000

BIT

B7 (MSB)

B6

Read / Write

B5

B4

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Table 14. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE) (continued)

Memory Location: 0xF2, Reset State: 00000000

BIT

B3

B2

B1

B0

Read / Write

SPACE

Table 15. Wireless Power Prop Packet Payload RAM Byte 2 (WRITE)

Memory Location: 0xF3, Reset State: 00000000

BIT

B7 (MSB)

B6

Read / Write

B5

B4

B3

B2

B1

B0

SPACE

Table 16. Wireless Power Prop Packet Payload RAM Byte 3 (WRITE)

Memory Location: 0xF4, Reset State: 00000000

BIT

B7 (MSB)

B6

Read / Write

B5

B4

B3

B2

B1

B0

SPACE

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9 Applications and Implementation

9.1 Application Information

The bq5102x device complies with the WPC v1.1 standard. There are several tools available for the design of

the system. These tools may be obtained by checking the product page at www.ti.com. The following sections

detail how to design a WPC v1.1 mode RX system.

9.2 Typical Applications

9.2.1 WPC Power Supply 5-V Output With 1-A Maximum Current and I²C

System

Load

Q1

bq51021

AD-EN

AD

OUT

C_COMM1

C₄

C₃

COMM1

BOOT1

AC1

C_BOOT1

R₇

R₆

RECT

C₁

VO_REG

VTSB

C₂

COIL

AC2

R₉

BOOT2

COMM2

TS/CTRL

TMEM

C_BOOT2

z

HOST

NTC

C_COMM2

C_CLAMP2

C_CLAMP1

CLAMP2

CLAMP1

C₅

WPG

PD_DET

SCL

GPIO

TERM

SCL

SDA

CM_ILIM

PGND

FOD

ILIM

R₁

R_OS

RECT

R_FOD

Figure 13. WPC 5-W Schematic Using bq5102x

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ZHCSCI8 –MAY 2014

Typical Applications (continued)

9.2.1.1 Design Requirements

Table 17. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_OUT

I_OUTMAXIMUM

MODE

5 V

1 A

WPC v1.1

9.2.1.2 Detailed Design Procedure

To begin the design procedure, start by determining the following:

•

Mode of operation – in this case WPC v1.1

Output voltage

Maximum output current

9.2.1.2.1 Output Voltage Set Point

The output voltage of the bq5102x device can be set by adjusting a feedback resistor divider network. The

resistor divider network is used to set the voltage gain at the VO_REG pin. The device is intended to operate

where the voltage at the VO_REG pin is set to 0.5 V. This value is the default setting and can be changed

through I²C (for the device bq51021). In Figure 14, R₆and R₇are the feedback network for the output voltage

sense.

OUT

C₄

R₇

R₆

VO_REG

Figure 14. Voltage Gain for Feedback

0.5 V

K_VO

V_OUT

(10)

(11)

K _VOu R ₇

1 ꢀ K _VO

R ₆

Choose R₇to be a standard value. In this case, take care to choose R₆and R₇to be large values in order to

avoid dissipating excessive power in the resistors, and thereby lowering efficiency.

K_VOis set to be 0.5 / 5 = 0.1, choose R₇to be 102 kΩ, and thus R₆to be 11.3 kΩ.

9.2.1.2.2 Output and Rectifier Capacitors

Set C₄between 1 and 4.7 µF. This example uses 1 µF.

Set C₃between 4.7 and 22 µF. This example uses 20 µF.

27

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ZHCSCI8 –MAY 2014

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9.2.1.2.2.1 TMEM

Set C₅to 2.2 µF. In order to determine the bleed off resistor, the WPC transmitters for which the PD_DET is

being set for needs to be determined. After the ping timing (time between two consecutive digital pings after EPT

charge complete is sent) is determined, the bleedoff resistor can be determined. This example uses TI

transmitter EVMs for the use case. In this case, the time between pings is 5 s. To set the time constant using the

Equation 8, it is set to 5600 kΩ.

9.2.1.2.3 Maximum Output Current Set Point

FOD1

ILIM

R₁

R_OS

RECT

R_FOD

Figure 15. Current Limit Setting for bq5102x

The bq5102x device includes a means of providing hardware overcurrent protection by means of an analog

current regulation loop. The hardware current limit provides a level of safety by clamping the maximum allowable

output current (for example, a current compliance). The R_ILIMresistor size also sets the thresholds for the

dynamic rectifier levels and thus providing efficiency tuning per each application’s maximum system current. The

calculation for the total R_ILIMresistance is as follows:

K_ILIM

R_ILIM

I_ILIM

R₁ R_ILIMꢀ R_{FO D}

(12)

(13)

The R_ILIMwill allow for the ILIM pin to reach 1.2 V at an output current equal to I_ILIM. When choosing R_ILIM, two

options are possible.

If the application requires an output current equal to or greater than external ILIM that the circuit is designed for

(input current limit on the charger where the RX is delivering power to is higher than the external ILIM), ensure

that the downstream charger is capable of regulating the voltage of the input into which the RX device output is

tied to by lowering the amount of current being drawn. This will ensure that the RX output does not collapse.

Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the

charger will pull the output of the RX device to ground when the RX device enters current regulation.

If the applications are designed to extract less than the ILIM (1-A maximum), typical designs should leave a

design margin of at least 20% so that the voltage at ILIM pin reaches 1.2 V when 20% more than maximum

current of the system is drawn from the output of the RX. Such a design would have input current limit on the

charger lower than the external ILIM of the RX device.

In both cases, the charger must be capable of regulating the current drawn from the device to allow the output

voltage to stay at a reasonable value. This same behavior is also necessary during the WPC V1.1

Communication. See Communication Current Limit for more details. The following calculations show how such a

design is achieved:

K_ILIM

R_ILIM

1.2 u I_ILIM

(14)

(15)

R₁ R_ILIMꢀ R_{FO D}

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ZHCSCI8 –MAY 2014

When referring to the application diagram shown in Figure 15, R_ILIMis the sum of the R₁and R_FODresistance

(that is, the total resistance from the ILIM pin to GND). R_FODis chosen according to the FOD application note that

can be obtained by contacting your TI representative. This is used to allow the RX implementation to comply with

WPC v1.1 requirements related to received power accuracy.

In many applications, the resistor R_OSis needed in order to comply with WPC V1.1 requirements. In such a case,

the offset on the FOD pin from the voltage on R_FODcan cause a shift in the calculation that can reduce the

expected current limit. Therefore, it is always a good idea to check the output current limit after FOD calibration is

performed according to the FOD application note. Because the RECT voltage is not deterministic, and depends

on transmitter operation to a certain degree, it is not possible to determine R₁with R_OSpresent in a deterministic

manner.

In this example, set maximum current for the example to be 1000 mA. Set I_ILIM= 1.2 A to allow for the 20%

margin.

840

R_ILIM

700 :

1.2

(16)

9.2.1.2.4 TERM Pin

The term pin is not used for bq5102x. Leave the pin floating.

9.2.1.2.5 I²C

The I²C lines are used to communicate with the device. To enable the I²C, they can be pulled up to an internal

host bus. The device address is 0x6C. I²C is enabled only for the device bq51021.

9.2.1.2.6 Communication Current Limit

Communication current limit allows the device to communicate with the transmitter in an error free manner by

decoupling the coil from load transients on the OUT pin during WPC communication. This is done by setting the

current limit in a manner that is consistent with Table 4. However, this will require the downstream charger to

have a function such as VIN_DPM. In some cases this communication current limit feature is not desirable if the

charger does not have this feature. In this design, the user enables the communication current limit by tying the

CM_ILIM pin to GND. In the case that this is not needed, the CM_ILIM pin can be tied to OUT pin to disable the

communication current limit. In this case, take care that the voltage on the CM_ILIM pin does not exceed the

maximum rating of the pin which is 7 V.

9.2.1.2.7 Receiver Coil

The receiver coil design is the most open part of the system design. The choice of the receiver inductance,

shape, and materials all intimately influence the parameters themselves in an intertwined manner. This design

can be complicated and involves optimizing many different aspects; refer to the user's guide for the EVM

(SLUUAX6).

The typical choice of the inductance of the receiver coil for a WPC only 5-V solution is between 8 to 11 µH

depending on the mutual inductance between the transmitter coil and the receiver coil.

9.2.1.2.8 Series and Parallel Resonant Capacitors

Resonant capacitors C₁and C₂are set according to WPC specification.

The equations for calculating the values of the resonant capacitors are shown:

-1

é

ê

ù

ú

2

'

S

C = f ×2p ×L

( )

1

S

ê

ú

ë

û

-1

é

ù

ú

2

1

ê

C =

f ×2p ×L -

( )

D

S

C

2

ê

ú

1

ë

û

(17)

29

bq51020, bq51021

ZHCSCI8 –MAY 2014

www.ti.com.cn

9.2.1.2.9 Communication, Boot, and Clamp Capacitors

Set C_COMMxto a value ranging from C₁/ 8 to C₁/ 3. Note that higher capacitors lower the overall efficiency of the

system. Make sure these are X7R ceramic material and have at least a minimum voltage rating of 25 V; TI

recommends a minimum voltage rating of 50 V.

Set C_BOOTxto be 15 nF. Make sure these are X7R ceramic material and have at least a minimum voltage rating

of 25 V; TI recommends a minimum voltage rating of 50 V.

Set C_CLAMPxto be 470 nF. Make sure these are X7R ceramic material and have at least a minimum voltage

rating of 25 V; TI recommends a minimum voltage rating of 50 V.

30

bq51020, bq51021

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ZHCSCI8 –MAY 2014

9.2.1.3 Application Performance Plots

Figure 16. bq5102x No Load Start-up on a WPC TX

Figure 17. 0- to 1000-mA Step on a WPC TX

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

Min

Max

Difference

0

200

400

600

I_OUT(mA)

800

1000

1200

D001

Figure 18. 1000 to 0 mA Load Dump on a WPC TX

Figure 19. Received Power Variation (mW) vs I_OUT(mA) on

a WPC TX

7.5

700 :

1400 :

7.25

7

6.75

6.5

6.25

6

5.75

5.5

5.25

5

4.75

4.5

4.25

4

0

200

400

600

800

1000

1200

I_OUT(mA)

D001

Figure 20. TS Voltage Bias Without TS Resistor

Figure 21. Rectifier Regulation as a Function or R_ILIMon a

WPC TX

31

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ZHCSCI8 –MAY 2014

www.ti.com.cn

90

80

70

60

50

40

30

20

10

0

200

190

180

170

160

150

140

130

120

110

100

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_OUT(A)

1

1.1 1.2

0

200

400

600

I_OUT(mA)

800

1000

1200

D001

Figure 22. bq5102x WPC Efficiency 5 V, 1 A on a WPC TX

Figure 23. Frequency Range of 5-V, 1-A RX on a WPC TX

8

5.115

VRECT ASC

VRECT DEC

7.5

7

5.1125

5.11

6.5

6

5.1075

5.105

5.1025

5.5

5

4.5

4

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

I_OUT(mA)

D013

D001

Figure 24. Dynamic Regulation, RILIM = 700 Ω on a

Figure 25. Output Regulation on a WPC TX

WPC TX

555

V_{O_REG}

V_RECT

554

553

552

551

550

549

548

547

546

545

2.5

3

3.5

4

4.5

5

Voltage (V)

D015

Figure 27. Start-Up WPC TX 7-V Out

Figure 26. Rect Foldback in Current Limit on a WPC TX

32

bq51020, bq51021

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ZHCSCI8 –MAY 2014

9.2.2 bq5102x Standalone in System Board or Back Cover

When the bq5102x device is implemented as an embedded device on the system board, the EN1 and EN2 pins

are the only differences from the previous design using I²C.

System

Load

Q1

bq51020

AD-EN

AD

OUT

C_COMM1

C₄

C₃

COMM1

BOOT1

AC1

C_BOOT1

R₇

R₆

RECT

C₁

VO_REG

VTSB

C₂

COIL

AC2

R₉

BOOT2

COMM2

TS/CTRL

TMEM

C_BOOT2

z

HOST

NTC

C_COMM2

C_CLAMP2

C_CLAMP1

CLAMP2

CLAMP1

C₅

WPG

PD_DET

EN1

GPIO

TERM

GPIO

EN2

CM_ILIM

PGND

FOD

ILIM

R₁

R_OS

RECT

R_FOD

Figure 28. bq5102x Embedded in a System Board

Refer to WPC Power Supply 5-V Output With 1-A Maximum Current and I²C for all design and application

details.

33

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ZHCSCI8 –MAY 2014

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10 Power Supply Recommendations

These devices are intended to be operated within the ranges shown in the Recommended Operating Conditions.

Because the system involves a loosely coupled inductor setup, the voltages produced on the receiver are a

function of the inductances and the available magnetic field. Ensure that the design in the worst case keeps the

voltages within the Absolute Maximum Ratings.

34

bq51020, bq51021

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ZHCSCI8 –MAY 2014

11 Layout

11.1 Layout Guidelines

•

Keep the trace resistance as low as possible on AC1, AC2, and OUT.

Detection and resonant capacitors need to be as close to the device as possible.

COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible.

Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance.

High frequency bypass capacitors need to be placed close to RECT and OUT pins.

ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized.

Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually

measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being

interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main

source of noise in the board. These traces should be shielded from other components in the board. It is

usually preferred to have a ground copper area placed underneath these traces to provide additional

shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a

ground plane (return) connected directly to the return of all components through vias (two vias per capacitor

for power-stage capacitors, one via per capacitor for small-signal components.

For a 1-A fast charge current application, the current rating for each net is as follows:

•

AC1 = AC2 = 1.2 A

OUT = 1 A

RECT = 100 mA (RMS)

COMMx = 300 mA

CLAMPx = 500 mA

All others can be rated for 10 mA or less

11.2 Layout Example

Keep the trace

AD is also a

power trace.

resistance as

low as possible

on AC1, AC2,

and OUT.

Isolate noisy

traces using

GND trace.

Place signal and

sensing

components as

close as possible

to the IC.

Place detection

and resonant

capacitors Cd

and Cs here.

Place COMM,

CLAMP, and

BOOT capacitors

as close as

possible to the IC

terminals.

It is always a good

practice to place high

frequency bypass

capacitors next to RECT

and OUT.

The via interconnect is important and

must be optimized near the power pad

of the IC and the GND for good thermal

dissipation.

Figure 29. Layout Example for bq5102x

35

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ZHCSCI8 –MAY 2014

www.ti.com.cn

12 器件和文档支持

12.1 相关链接

以下表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访问。

Table 18. 相关链接

部件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

bq51020

bq51021

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

36

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ZHCSCI8 –MAY 2014

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

37

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OUTLINE

YFP0042

DSBGA - 0.5 mm max height

S

C

A

L

E

4

.

7

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.5 MAX

SEATING PLANE

0.05 C

BALL TYP

0.19

0.13

2 TYP

SYMM

G

F

E

D: Max = 3.586 mm, Min =3.526 mm

E: Max = 2.874 mm, Min =2.814 mm

SYMM

2.4

D

C

TYP

0.3

0.2

42X

B

A

0.015

C A

B

0.4 TYP

2

3

4

5

6

1

0.4 TYP

4221555/B 04/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

YFP0042

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

42X ( 0.23)

(0.4) TYP

4

1

6

2

5

A

B

C

SYMM

D

E

F

G

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

METAL

UNDER

(

0.23)

METAL

SOLDER MASK

(

0.23)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221555/B 04/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN

YFP0042

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

42X ( 0.25)

(R0.05) TYP

4

1

2

3

5

6

A

(0.4)

TYP

B

C

METAL

TYP

SYMM

D

E

F

G

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4221555/B 04/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

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TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	BQ51020YFPR
厂家：	TEXAS INSTRUMENTS
描述：	5W (WPC) 单芯片无线电源接收器 \| YFP \| 42 \| -40 to 125 PC 无线电信电信集成电路
文件：	总44页 (文件大小：1015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ51020YFPR [TI]

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