BQ77207 [TI]
3 系列至 7 系列锂离子电池、内部延迟计时器、电压和温度保护器;
| 型号： | BQ77207 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 系列至 7 系列锂离子电池、内部延迟计时器、电压和温度保护器 电池 |
| 文件： | 总26页 (文件大小：1406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ77207
ZHCSPB8A –DECEMBER 2021 –REVISED JUNE 2022
BQ77207 具有内部延迟计时器、适用于3 节至7 节串联锂离子电池的电压和
温度保护器
1 特性
3 说明
• 3 节至7 节串联电池保护
• 高精度过压保护
BQ77207 产品系列提供了多种电压和温度监控功能，
包括适用于锂离子电池组系统的过压 (OVP)、欠压
(UVP)、开路(OW)、过热(OT) 保护，可独立监控每节
电池是否具有过压、欠压和开路情况。通过增加外部
NTC 或PTC 热敏电阻，该器件可以检测到过热情况。
– 25°C 时为± 10mV
– 0°C 至60°C 时为± 20mV
• 3.55V 至5.1V 的
过压保护选项
• 1.0V 至3.5V 的欠压保护选项
• 开路连接检测
• 使用NTC 或PTC 的过热保护
• 支持电池随机连接
• 提供功能安全
• 固定内部延迟计时器
• 固定检测阈值
当检测到存在过压、欠压、开路或过热情况时，
BQ77207 器件即启动内部延迟计时器。延迟计时器过
期时，将触发相应的输出进入其工作状态（根据配置的
不同，为高电平或低电平状态）。
器件信息表
封装(1)
封装尺寸（标称值）
器件型号
BQ7720700
WSON (12)
3.0mm × 2.0mm
• 固定输出驱动类型，适用于每个COUT 和DOUT
(1) 如需了解可用封装，请参阅数据表末尾的可订购产品附录和
Device Comparison Table。
– 高电平有效或低电平有效
– 高电平有效驱动达6V
PACK+
Fuse or
Back-to-Back FETs
– 漏极开路，可从外部上拉至VDD
• 低功耗ICC ≈1µA
CVD
(VCELL(ALL) < VOV
)
• 每节电池输入具有小于100nA 的低泄漏电流，且禁
用开路检测
• 封装尺寸选项
VDD
RIN
– 12 引脚WSON，引线间距为0.5mm
V7
CIN
2 应用
DOUT
• 锂离子电池组保护，可应用于：
– 手持园艺工具
RIN
V3
RDOUT
CIN
– 手持电动工具
– 无线真空吸尘器
RIN
GND
V2
CIN
RIN
– UPS 备用电池
V1
CIN
COUT
– 轻型电动车辆（电动自行车、电动踏板车、踏板
辅助自行车）
RCOUT
VSS
TS
RNTC
PACK-
GND
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEG7
BQ77207
www.ti.com.cn
ZHCSPB8A –DECEMBER 2021 –REVISED JUNE 2022
Table of Contents
9.4 Device Functional Modes..........................................10
10 Application and Implementation................................12
10.1 Application Information........................................... 12
10.2 Systems Example................................................... 14
11 Power Supply Recommendations..............................15
12 Layout...........................................................................16
12.1 Layout Guidelines................................................... 16
12.2 Layout Example...................................................... 16
13 Device and Documentation Support..........................17
13.1 第三方产品免责声明................................................17
13.2 接收文档更新通知................................................... 17
13.3 支持资源..................................................................17
13.4 Trademarks.............................................................17
13.5 Electrostatic Discharge Caution..............................17
13.6 术语表..................................................................... 17
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................3
8 规格................................................................................... 4
8.1 Absolute Maximum Ratings........................................ 4
8.2 ESD Ratings............................................................... 4
8.3 Recommended Operating Conditions.........................4
8.4 Thermal Information....................................................4
8.5 DC Characteristics......................................................5
8.6 Timing Requirements..................................................7
9 Detailed Description........................................................8
9.1 Overview.....................................................................8
9.2 Functional Block Diagram...........................................8
9.3 Feature Description.....................................................8
Information.................................................................... 17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (June 2022)
Page
• Added the BQ7720701 and BQ7720702 devices to 节6; added the OVP and UVP output delays...................3
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5 说明（续）
如果检测到过压故障，将触发COUT 引脚。如果检测到欠压故障，将触发DOUT 引脚。如果检测到过热或开路故
障，则同时触发 DOUT 和 COUT 引脚。为了实现更快速的产品线测试，BQ77207 器件可提供延迟时间大幅减少
的客户测试模式(CTM)。
6 Device Comparison Table
OVP OUTPUT
DELAY
PART NUMBER(1)
TA
PACKAGE
PACKAGE DESIGNATOR
OVP (V)
OV HYSTERESIS (V)
UVP (V)
BQ7720700
BQ7720701
BQ7720702
12-Pin WSON
12-Pin WSON
12-Pin WSON
DSS
DSS
DSS
4.325
4.275
4.275
0.100
0.100
0.100
1 s
2.25
2
–40°C to 110°C
–40°C to 110°C
–40°C to 110°C
1 s
4 s
2
PART NUMBER
(CONT.)(1)
UV HYSTERESIS (V)
UVP OUTPUT DELAY
OT (°C)
OW
LATCH
OUTPUT DRIVE
TAPE AND REEL
BQ7720700
BQ7720701
BQ7720702
0.100
0.100
0.100
1 s
1 s
2 s
70
80
80
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Active High 6 V
Active High 6 V
Active High 6 V
BQ7720700DSSR
BQ7720701DSSR
BQ7720702DSSR
(1) For future options, contact TI for more information.
7 Pin Configuration and Functions
VDD
TS
V7
DOUT
COUT
VSS
V6
V5
V4
V3
V1
V2
图7-1. BQ77207 Pin Diagram
12-Pin Functions
NO.
1
NAME
VDD
V7
TYPE(1)
DESCRIPTION
P
I
Power supply
2
Sense input for positive voltage of the seventh cell from the bottom of the stack
Sense input for positive voltage of the sixth cell from the bottom of the stack
Sense input for positive voltage of the fifth cell from the bottom of the stack
Sense input for positive voltage of the fourth cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the first cell from the bottom of the stack
3
V6
I
4
V5
I
5
V4
I
6
V3
I
7
V2
I
8
V1
I
9
VSS
COUT
DOUT
TS
P
O
O
I
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
Output drive for overvoltage, open wire, and overtemperature. It can be left floating if not used.
Output drive for undervoltage, open wire, and overtemperature. It can be left floating if not used.
Temperature sensor input. If not used, leave it NC.
10
11
12
(1) I = Input, O = Output, P = Power Connection
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8 规格
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–40
–65
MAX
45
UNIT
V
Supply voltage range
Input voltage range
VDD - VSS (2)
Vn - VSS where n = 1 to 7
TS
45
V
1.5
45
V
Output voltage range
COUT - VSS, DOUT - VSS
V
Functional temperature,TFUNC
Storage temperature, TSTG
110
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) DC Voltage applied on this pin should be limited to a maximum of 40 V. Stresses to this pin at voltages beyond this level, up to the 45-
V specified maximum level, should be limited to short transients.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
NOM
MAX
38.5
5
UNIT
V
VDD
VIN
Supply voltage (1)
Input voltage range of Vn - Vn-1 where n = 2 to 7 and V1 - VSS
TS
0
V
0
1.5
13
V
VCTM
CTS
TA
Customer Test Mode Entry VDD > V7 + VCTM
Total capacitance on the TS Pin
Ambient temperature
12
V
200
85
pF
°C
°C
–40
–65
TJ
Junction temperature
150
(1) VDD is equal to top of stack voltage.
8.4 Thermal Information
DEVICE
THERMAL METRIC(1)
DSS
12 PINS
67.3
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
68.6
35.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.9
35.9
ΨJB
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8.4 Thermal Information (continued)
DEVICE
THERMAL METRIC(1)
DSS
12 PINS
14
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 DC Characteristics
Typical values stated where TA = 25°C and VDD = 25 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V
to 38.5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVER VOLTAGE PROTECTION (OV)
VOV
OV Detection Range
OV Detection Steps
3.55
5.1
V
VOV_STEP
25
mV
Selected OV Hysteresis depends on
part number. See device selection
table for details.
mV
mV
VOV –50
VOV_HYS
OV Detection Hysteresis
Selected OV Hysteresis depends on
part number. See device selection
table for details.
VOV –
100
TA = 25℃
OV Detection Accuracy
OV Detection Accuracy
OV Detection Accuracy
10
20
50
mV
mV
mV
–10
–20
–50
0℃≤TA ≤60℃
-40℃≤TA ≤110℃
VOV_ACC
UNDER VOLTAGE PROTECTION (UV)
VUV
UV Detection Range
UV Detection Steps
1.0
3.5
V
VUV_STEP
50
mV
Selected OV Hysteresis depends on
part number. See device selection
table for details.
VUV + 50
mV
mV
VUV_HYS
UV Detection Hysteresis
Selected OV Hysteresis depends on
part number. See device selection
table for details.
VUV + 100
UV Detection Accuracy
UV Detection Accuracy
30
50
mV
mV
TA = 25℃
–30
–50
VUV_ACC
-40 ≤TA ≤110℃
UV Detection Disabled
Threshold
Vn - Vn-1 where n = 2 to 7 and V1 -
VSS
VUV_MIN
450
500
550
mV
OVER TEMPERATURE PROTECTION (OT)
Available options: 62°C, 65°C, 70°C,
75°C, 80°C, 83°C
TOT
OT Detection Range
62.0
83.0
°C
2850
2570
2195
1915
1651
1525
NTC OT Detection External
Resistance
ROT_EXT_NTC
Ω
Ω
PTC OT Detection External
Resistance
ROT_EXT_PTC
111100
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8.5 DC Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 25 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V
to 38.5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
(1)
(2)
TOT_ACC
TOT_HYS
RTC
OT Detection Accuracy (NTC)
5
–5
°C
–10
4186
3530
20
OT Detection Hysteresis (NTC)
Internal Pull Up Resistor
Ω
Ω
After TI Factory Trim
19.4
20.6
0.0
kΩ
UNDER TEMPERATURE PROTECTION (UT)
TUT
UT Detection Threshold
°C
–30.0
111100
68900
42200
26700
NTC UT Detection External
Resistance
RUT_EXT_NTC
Ω
UT Detection External
Resistance Accuracy
RUT_ACC
2%
5
–2%
–5
10
°C
TUT_HYS
UT Detection Hysteresis (NTC)
17800
Ω
(1)
TUT_ACC
UT Detection Accuracy (NTC)
°C
OPEN WIRE PROTECTION (OW)
Vn < Vn-1 where n = 2 to 7
V1 - VSS
mV
mV
mV
mV
–200
500
VOW
OW Detection Threshold
VOW_HYS
VOW_ACC
OW Detection Hysteresis
OW Detection Accuracy
Vn < Vn-1 where n = 1 to 7
-40 ℃≤TA ≤110℃
VOW +100
25
–25
SUPPLY AND LEAKAGE CURRENT
ICC
Supply Current
Supply Current
No fault detected.
2
3.5
25
µA
µA
Fault detected, COUT active High 6V
output, DOUT active low. Other faults
ICC_FAULT
20
Fault detected, COUT active High 6V
output, DOUT active low. UV fault
only
ICC_FAULT
Supply Current
3
5
µA
Vn - Vn-1 and V1 - VSS = 4V, where
n = 2 to 7, Open Wire Enabled
0.3
0.1
µA
µA
–0.3
–0.1
(2)
IIN
Input Current at Vx Pins
Vn - Vn-1 and V1 - VSS = 4V, where
n = 2 to 7, Open Wire Disabled
OUTPUT DRIVE, COUT and DOUT, CMOS ACTIVE HIGH VERSIONS ONLY
Vn - Vn-1 or V1 - VSS > VOV, where
n = 2 to 7, VDD = 25V, IOH = 100 µA
measured out of COUT, DOUT pin.
Output Drive Voltage for COUT
and DOUT, Active High 6V
6
0
V
V
VDD - VCOUT or VDOUT, Vn - Vn-1 or
Output Drive Voltage for COUT V1 - VSS > VOV, where n = 2 to 7, IOH
1
1
1.5
1.5
and DOUT, Active High VDD
= 10 µA measured out of COUT,
DOUT pin.
VOUT_AH
VDD - VCOUT or VDOUT, If 6 of 7 cells
Output Drive Voltage for COUT are short circuited and only one cell
0
V
and DOUT, Active High 6V
remains powered and > VOV, VDD =
Vx (cell voltage), IOH = 100 µA,
Output Drive Voltage for COUT Vn - Vn-1 and V1 - VSS < VOV, where
and DOUT, Active High 6V and n = 2 to 7, VDD = 25 V, IOH = 100 µA
250
100
400
120
mV
VDD
measured into pin
ROUT_AH
Internal Pull Up Resistor
80
kΩ
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8.5 DC Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 25 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V
to 38.5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vn - Vn-1 or V1 - VSS > VOV, where
n = 2 to 7, VDD = 25 V, OUT = 0V.
Measured out of COUT, DOUT pin
OUT Source Current (during
OV)
IOUT_AH_H
6.5
mA
Vn - Vn-1 and V1 - VSS < VOV, where
n = 2 to 7, VDD = 25 V, OUT = VDD.
Measured into COUT, DOUT pin
IOUT_AH_L
OUT Sink Current (no OV)
0.3
3
mA
OUTPUT DRIVE, COUT and DOUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
Vn - Vn-1 or V1 - VSS > VOV, where
Output Drive Voltage for COUT
and DOUT, Active Low
VOUT_AL
IOUT_AL_L
IOUT_AL_H
n = 2 to 7, VDD = 25 V, IOH = 100 µA
measured into COUT, DOUT pin.
250
400
3
mV
mA
nA
Vn - Vn-1 or V1 - VSS > VOV, where
n = 2 to 7, VDD = 25 V, OUT = VDD.
Measured into COUT, DOUT pin.
OUT Source Current (during
OV)
0.3
Vn - Vn-1 and V1 - VSS < VOV, where
n = 2 to 7, VDD = 25 V, OUT = VDD.
Measured out of COUT, DOUT pin.
OUT Sink Current (no OV)
100
(1) Assured by design. This accuracy assumes the external resistance is within ±2% of the R_OT_EXT values for the corresponding
temperature threshold.
(2) Assured by design
8.6 Timing Requirements
Typical values stated where TA = 25°C and VDD = 25 V, MIN/MAX values stated where TA = –40°C to 85°C and VDD = 5 V
to 38.5 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25
0.5
1
MAX UNIT
s
s
s
s
s
s
s
s
s
s
s
tOV_DELAY
OV Delay Time
2
4
0.25
0.5
1
tUV_DELAY
UV Delay Time
2
tOT_DELAY
tOW_DELAY
tDELAY_ACC
tDELAY_ACC
OT Delay Time
4
OW Delay Time
4
Delay Time Accuracy
Delay Time Accuracy
For 0.25s, 0.5s delays
128
150
ms
ms
–128
–150
For 1s delays
For all delays other than 0.25s, 0.5s,
1s delays
tDELAY_DR
Delay time drift across operating temp
10%
–10%
Fault Detection Delay Time during
Customer Test Mode
tCTM_DELAY
See Customer Test Mode.
50
ms
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9 Detailed Description
9.1 Overview
The BQ77207 family of devices provides a range of voltage and temperature monitoring including overvoltage
(OVP), undervoltage (UVP), open wire (OW), and overtemperature (OT) protection for Li-ion battery pack
systems. Each cell is monitored independently for overvoltage, undervoltage, and open-wire conditions. With the
addition of an external NTC thermistor, the device can detect overtemperature conditions. An internal delay timer
is initiated upon detection of an overvoltage, undervoltage, open-wire, or overtemperature condition. Upon
expiration of the delay timer, the respective output is triggered into its active state (either high or low depending
on the configuration). The overvoltage triggers the COUT pin if a fault is detected, and undervoltage triggers the
DOUT pin if a fault is detected. If an undertemperature, overtemperature, or open-wire fault is detected, then
both the DOUT and COUT are triggered.
For quicker production-line testing, the BQ77207 device provides a Customer Test Mode (CTM) with greatly
reduced delay time.
9.2 Functional Block Diagram
VDD
V7
Internal
Regulator
VSS
DOUT
Oscillator
Delay
Timer
V3
V2
Osc.
Monitor
VUV
VSS
+
œ
VSS
VOV
COUT
V1
VOT
Delay
Timer
VSS
VSS
TS
9.3 Feature Description
9.3.1 Voltage Fault Detection
In the BQ77207 device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. When the timer expires, the COUT pin goes from inactive to active state. The timer is reset if
the cell voltage falls below the recovery threshold (VOV – VOV_HYS). Undervoltage is detected by comparing the
actual cell voltage to a protection voltage reference, VUV. If any cell voltage falls below the programmed UV
value, a timer circuit is activated. When the timer expires, the DOUT pin goes from inactive to active state. The
timer is reset if the cell voltage rises below the recovery threshold (VUV + VUV_HYS).
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VOV
VOV
–
VOV_HYS
tOV_DELAY
Active
Inactive
图9-1. Timing for Overvoltage Sensing
VuV +
VuV_HYS
VUV
tUV_DELAY
Active
Inactive
图9-2. Timing for Undervoltage Sensing
9.3.2 Open Wire Fault Detection
In the BQ77207 device, each cell input is monitored independently to determine if the input is connected to a cell
or not by applying a 50-μA pull down current to ground that is activated for 128 μs every 128 ms. If the device
detects that Vn < Vn-1 –VOW V, then a timer is activated. When the timer expires, the COUT and DOUT pins go
from an inactive to active state. The timer is reset if the cell input rises above the recovery threshold (VOW
+
VOW_HYS). To recover both the COUT and DOUT output from active to inactive state, the open wire fault must be
cleared (such as the broken connection from the device to the battery needs to be restored), and any other
remaining faults (such as existing OVP or UVP faults) need to be cleared as well.
9.3.3 Temperature Fault Detection
In the BQ77207 device, the TS pin is ratiometrically monitored with an internal pull up resistance RNTC
.
Overtemperature is detected by evaluating the TS input voltage to determine the external resistance falls below
a protection resistance, ROT_EXT. If the resistance falls below the programmed OT value, a timer circuit is
activated. When the timer expires, the COUT and DOUT pins go from inactive to active state. The timer is reset
if the resistance rises above the recovery threshold (ROT + ROT_HYS). If external capacitance is added to the TS
pin, it needs to be within the spec limit shown in recommended operating conditions.
备注
Texas Instruments does not recommend adding an external capacitor to the TS pin. The capacitance
on this pin will affect the TS measurement accuracy if greater than CTS.
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9.3.4 Oscillator Health Check
The device can detect if the internal oscillator slows down below the fOSC_FAULT threshold. When this occurs then
the COUT and DOUT go from inactive to active state. If the oscillator returns to normal then the fault recovers.
9.3.5 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
9.3.6 Output Drive, COUT and DOUT
These pins serve as the fault signal outputs, and may be ordered in either active HIGH with drive to 6V or active
LOW options configured through internal OTP.
The COUT and DOUT will respond per the following table when a fault is detected, if the specific fault is enabled.
表9-1. Fault Detection vs COUT and DOUT Action
FAULT Detected
Overvoltage
COUT
Active
Inactive
Active
Active
Active
DOUT
Inactive
Active
Active
Active
Active
Undervoltage
Open Wire
Over Temperature
Oscillator Health
9.3.7 The LATCH Function
The device can be enabled to latch the fault signal, which effectively disables the recovery functions of all fault
detections. The only way to recover from a fault state when the latch is enabled is a POR of the device.
9.3.8 Supply Input, VDD
This pin is the unregulated input power source for the IC. A series resistor is connected to limit the current, and a
capacitor is connected to ground for noise filtering.
9.4 Device Functional Modes
9.4.1 NORMAL Mode
When COUT and DOUT are inactive (no fault detected) the device operates in NORMAL mode and device is
monitoring for voltage, open wire and temperature faults.
The COUT and DOUT pins are inactive and if configured:
• Active high is low.
• Active low is being externally pulled up and is an open drain.
9.4.2 FAULT Mode
FAULT mode is entered if the COUT or DOUT pins are activated. The OUT pin will either pull high internally, if
configured as active high, or will be pulled low internally, if configured as active low. When COUT and DOUT are
deactivated the device returns to NORMAL mode.
9.4.3 Customer Test Mode
Customer Test Mode (CTM) helps to reduce test time for checking the delay timer parameter once the circuit is
implemented in the battery pack. To enter CTM, VDD should be set to at least VCTM higher than V7 (see 图 9-3).
The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal operation. To exit
Customer Test Mode, remove the VDD to a V7 voltage differential of 10 V so that the decrease in this value
automatically causes an exit.
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CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into Customer
Test Mode. Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (VCn–
VCn-1) and (V1–VSS). Stressing the pins beyond the rated limits may cause permanent damage to
the device.
图9-3 shows the timing for the Customer Test Mode.
VCTM
VOV
VOV – VOV_HYS
tCTM_DELAY
Active
Inactive
图9-3. Timing for Customer Test Mode
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
Changes to the ranges stated in 表10-1 will impact the accuracy of the cell measurements.
QDSG
QCHG
PACK+
CVD
VDD
RIN
V7
CIN
DOUT
RIN
RIN
RIN
V3
V2
V1
RDOUT
CIN
CIN
CIN
GND
COUT
RCOUT
VSS
TS
RNTC
PACK-
GND
图10-1. Application Configuration
10.1.1 Design Requirements
Changes to the ranges stated in 表 10-1 will impact the accuracy of the cell measurements. 图 10-1 shows each
external component.
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PARAMETER
ZHCSPB8A –DECEMBER 2021 –REVISED JUNE 2022
表10-1. Parameters
EXTERNAL COMPONENT
MIN
900
0.01
100
0.05
NOM
MAX
1100
0.1
1K
UNIT
Voltage monitor filter resistance
RIN
CIN
1000
Ω
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
µF
RVD
CVD
300
0.1
Ω
1
µF
备注
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
10.1.2 Detailed Design Procedure
图10-2 shows the measurement for current consumption for the product for both VDD and Vx.
PACK+
ICC
VDD
V7
IIN
CELL7
DOUT
IIN
V3
CELL3
V2
IIN
CELL2
V1
IIN
COUT
CELL1
VSS
TS
RNTC
PACK-
GND
图10-2. Configuration for IC Current Consumption Test
10.1.2.1 Cell Connection Sequence
The BQ77207 device can be connected to the array of cells in any order without damaging the device.
During cell attachment, the device could detect a fault if the cells are not connected within a fault detection delay
period. If this occurs, then COUT and/or DOUT could transition from inactive to active. Both COUT and DOUT
can be tied to VSS or VDD to prevent any change in output state during cell attach.
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10.2 Systems Example
In this application example, the choice of a FUSE or FETs is required on the COUT and DOUT pins—configured
as an active high drive to 6-V outputs.
PACK+
Fuse or
Back-to-Back FETs
CVD
VDD
V7
V6
RIN
V5
CIN
RIN
V4
CIN
DOUT
RIN
V3
RDOUT
CIN
RIN
GND
V2
CIN
RIN
V1
CIN
COUT
RCOUT
VSS
TS
RNTC
PACK-
GND
图10-3. 5-Series Cell Configuration with Active High 6-V Option
When paring with the BQ769x2 or BQ76940 devices, the top cell must be used. For the BQ77207 device to drive
the CHG and DSG FETs, the active high 6-V option is preferred. Its COUT and DOUT are controlling two N-CH
FETs to jointly control the CHG and DSG FETs with the monitoring device. For such joint architecture, the open-
wire feature of the BQ77207 device may be affected if the primary protector or monitor device is actively
measuring the cells. Care is needed to ensure the VOW spec of the BQ77207 device is met or to choose a
version of the BQ77207 device with open wire disabled. When working with a BQ769x2 device, the LOOPSLOW
setting of the BQ769x2 device should be set to 0x11 to ensure the BQ77207 VOW spec is met.
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FUSE
PCHG
PDSG
PACK+
COUT
DOUT
CAN
5V
COMM TO
TRANSCEIVER
SYSTEM
DOUT
V16
V15
V14
V13
V12
V11
V10
V9
+
+
+
+
COMM
VC15
VC14
VC13
VC12
VC11
VC10
VC9
REGIN
REG1
3.3V
VDD
REG2
GPIO
RST_SHUT
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
DSG Logic Out
CHG Logic Out
DDSG
DCHG
DFETOFF
CFETOFF
HDQ
:
:
:
:
:
:
:
:
MCU
DOUT
COUT
COUT
GPIO
GPIO
VC8
V8
VC7
V7
SDA
SCL
INT
SDA
VC6
V6
SCL
VC5
V5
+
+
ALERT
VC4
V4
V3
GND
V2
V1
VSS
TS
TS1
+
TS2
TS1
+
+
TS3
PACK-
图10-4. BQ77207 with BQ76952
11 Power Supply Recommendations
The maximum power supply of this device is 38.5 V on VDD.
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12 Layout
12.1 Layout Guidelines
• Ensure the RC filters for the Vn and VDD pins are placed as close as possible to the target terminal.
• The VSS pin should be routed to the CELL–terminal.
12.2 Layout Example
Place the RC filters close to the device
terminals
Power Trace
VDD
Pack +
V7
COUT
VSS
COUT
Pack -
VCELL7
V4
V3
V1
V2
VCELL4
VCELL3
VCELL2
VCELL1
图12-1. Example Layout
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13 Device and Documentation Support
13.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7720700DSSR
BQ7720701DSSR
BQ7720702DSSR
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
DSS
DSS
DSS
12
12
12
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 110
-40 to 110
-40 to 110
720700
Samples
Samples
Samples
NIPDAU
NIPDAU
720701
720702
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ7720700DSSR
BQ7720701DSSR
BQ7720702DSSR
WSON
WSON
WSON
DSS
DSS
DSS
12
12
12
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
2.25
2.25
2.25
3.25
3.25
3.25
1.05
1.05
1.05
4.0
4.0
4.0
8.0
8.0
8.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ7720700DSSR
BQ7720701DSSR
BQ7720702DSSR
WSON
WSON
WSON
DSS
DSS
DSS
12
12
12
3000
3000
3000
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSS0012B
WSON - 0.8 mm max height
SCALE 4.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
0.35
0.25
PIN 1 INDEX AREA
0.3
0.2
3.1
2.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
1
0.1
(0.2) TYP
SYMM
0.05
0.00
EXPOSED
THERMAL PAD
6
7
SEE TERMINAL
DETAIL
2X
13
SYMM
2.5
2.65 0.1
1
12
10X 0.5
0.3
12X
0.2
0.1
0.05
0.35
0.25
12X
PIN 1 ID
(OPTIONAL)
C A B
C
4218908/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1)
12X (0.5)
SYMM
1
12
12X (0.25)
13
SYMM
(2.65)
10X (0.5)
(R0.05) TYP
(1.075)
(
0.2) VIA
TYP
7
6
(1.9)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MIN
ALL AROUND
EXPOSDE METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218908/A 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSS0012B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
EXPOSED METAL
TYP
12X (0.5)
SYMM
1
13
12
12X (0.25)
(0.685)
SYMM
10X (0.5)
2X (1.17)
(R0.05) TYP
7
6
2X (0.95)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 13:
83% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218908/A 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2023，德州仪器 (TI) 公司
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