BUF16821-Q1 [TI]
具有集成双列存储器的汽车类、16 通道伽玛电压发生器和 Vcom 校准器;
| 型号： | BUF16821-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成双列存储器的汽车类、16 通道伽玛电压发生器和 Vcom 校准器 存储 电压发生器 |
| 文件： | 总37页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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BUF16821-Q1
ZHCSCF9 –MAY 2014
BUF16821-Q1 可编程伽马电压生成器和
具有集成型 2 组存储器的 VCOM 校准器
1 特性
3 说明
1
•
具有符合 AEC-Q100 标准的以下结果：
BUF16821-Q1 提供 16 条可编程伽马通道，以及两个
可编程 VCOM 通道。 最终的伽马和 VCOM 值可被存
储在片上、非易失性存储器中。 为了应对编程错误时
或使液晶显示屏 (LCD) 面板重新开始工作，此器件支
持多达 16 个对片上存储器的写操作。
–
–
–
温度等级 3：-40°C 至 85°C
人体模型 (HBM) 静电放电 (ESD) 分类等级 2
充电器件模型 (CDM) ESD 分类等级 C4B
•
•
•
•
16 通道 P 伽马，2 通道 P-VCOM，10 位分辨率
16x 可重写非易失性存储器
两个独立的引脚可选存储器组
轨至轨输出：
此器件具有两个独立的存储器组，可实现两个不同伽马
曲线的同时存储，从而使伽马曲线之间的切换更加便
捷。 所有伽马和 VCOM 通道提供一个轨到轨输出，此
输出在 10mA 负载时，通常在任一电源轨的 150mV 内
摆动。 可使用一个 I2C 接口对所有通道进行编程，这
个接口支持高达 400kHz 的标准运行，以及高达
2.7MHz 的高速数据传输。
–
–
300mV（最小值）电源轨摆幅 (10mA)
> 300mA（最大值）IOUT
•
•
•
电源电压：9V 至 20V
数字电源：2V 至 5.5V
I2C™ 接口：支持 400kHz 和 2.7MHz
此器件使用德州仪器 (TI) 专有的、最先进的高压
CMOS 工艺制造。 这一工艺提供高达 20V 的高密度逻
辑和高电源电压运行。此器件采用带散热片薄型小外形
尺寸 (HTSSOP)-28 PowerPAD™ 封装，并且在 -40°C
至 +85°C 的温度范围内额定运行。
2 应用范围
TFT-LCD 基准驱动器
功能方框图
Digital Analog
(2.0 V to 5.5 V) (9 V to 20 V)
BKSEL
1
器件信息(1)
封装
产品型号
封装尺寸（标称值）
BUF16821-Q1
HTSSOP (28)
9.70mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
OUT1
OUT2
OUT15
OUT16
BUF16821-Q1
VCOM1
VCOM2
SDA
SCL
Control IF
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBOS712
BUF16821-Q1
ZHCSCF9 –MAY 2014
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 19
7.5 Programming .......................................................... 20
7.6 Register Maps......................................................... 24
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 25
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 29
11 器件和文档支持 ..................................................... 30
11.1 文档支持................................................................ 30
11.2 Trademarks........................................................... 30
11.3 Electrostatic Discharge Caution............................ 30
11.4 Glossary................................................................ 30
12 机械封装和可订购信息 .......................................... 30
7
4 修订历史记录
日期
修订版本
注释
2014 年 5 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
BUF16821-Q1
www.ti.com.cn
ZHCSCF9 –MAY 2014
Related Products
FEATURES
DEVICE
22-channel gamma correction buffer
12-channel gamma correction buffer
18-, 20-channel programmable buffer, 10-bit, VCOM
18-, 20-channel programmable buffer with memory
Programmable VCOM driver
BUF22821
BUF12800
BUF20800
BUF20820
BUF01900
BUF11704
BUF11705
18-V supply, traditional gamma buffers
22-V supply, traditional gamma buffers
5 Pin Configuration and Functions
PWP Package
HTSSOP-28
(Top View)
VCOM2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
1
28 VCOM1
27 OUT16
26 OUT15
25 OUT14
2
3
4
5
6
7
8
9
GNDA(1)
24
PowerPAD
Lead-Frame
Die Pad
Exposed on
Underside
23 VS
22 OUT13
21 OUT12
20 OUT11
19 OUT10
GNDA(1)
VS
(must connect to
GNDA and GNDD)
OUT7 10
OUT8 11
OUT9 12
VSD 13
SCL 14
GNDD(1)
18
17 BKSEL
16 A0
15 SDA
(1) GNDA and GNDD must be connected together.
Copyright © 2014, Texas Instruments Incorporated
3
BUF16821-Q1
ZHCSCF9 –MAY 2014
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Pin Functions
PIN
DESCRIPTION
NO.
1
NAME
VCOM2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GNDA
VS
VCOM channel 2
DAC output 1
DAC output 2
DAC output 3
DAC output 4
DAC output 5
DAC output 6
2
3
4
5
6
7
8
Analog ground; must be connected to digital ground (GNDD).
VS connected to analog supply
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OUT7
OUT8
OUT9
VSD
DAC output 7
DAC output 8
DAC output 9
Digital supply; connect to logic supply
Serial clock input; open-drain, connect to pull-up resistor.
Serial data I/O; open-drain, connect to pull-up resistor.
A0 address pin for I2C address; connect to either logic 1 or logic 0; refer to Table 2.
SCL
SDA
A0
BKSEL
GNDD
OUT10
OUT11
OUT12
OUT13
VS
Selects memory bank 0 or 1; connect to either logic 1 to select bank 1 or logic 0 to select bank 0.
Digital ground; must be connected to analog ground at the BUF16821-Q1.
DAC output 10
DAC output 11
DAC output 12
DAC output 13
VS connected to analog supply
GNDA
OUT14
OUT15
OUT16
VCOM1
Analog ground; must be connected to digital ground (GNDD).
DAC output 14
DAC output 15
DAC output 16
VCOM channel 1
4
Copyright © 2014, Texas Instruments Incorporated
BUF16821-Q1
www.ti.com.cn
ZHCSCF9 –MAY 2014
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VS
Supply voltage
22
DVDD
Digital power supply (VSD pin)
6
6
V
SCL, SDA, AO, BKSEL: voltage
SCL, SDA, AO, BKSEL: current
–0.5
(V–) – 0.5
–40
V
Digital input pins
±10
mA
V
Output pins, OUT1 through OUT16, VCOM1 and VCOM2(2)
Output short-circuit(3)
(V+) + 0.5
Continuous
95
Ambient operating temperature
Junction temperature
°C
°C
TJ
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Output Protection section.
(3) Short-circuit to ground, one amplifier per package.
6.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
Electrostatic discharge
°C
Human body model (HBM), per AEC Q100-002(1)
–2000
2000
Corner pins (1, 14, 15,
V(ESD)
–750
–500
750
500
V
Charged device model (CDM), per
AEC Q100-011
and 28)
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
9.0
NOM
18.0
3.3
MAX
UNIT
VS
Supply voltage
20.0
5.5
V
V
DVDD
Digital power supply (VSD pin)
2.0
6.4 Thermal Information
BUF16821-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
28 PINS
34.3
19.9
17.4
0.7
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
17.2
3.0
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
5
BUF16821-Q1
ZHCSCF9 –MAY 2014
www.ti.com.cn
6.5 Electrical Characteristics
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
PARAMETER
ANALOG GAMMA BUFFER CHANNELS
Reset value
CONDITIONS
MIN
TYP
MAX
UNIT
Code 512
9
17.85
0.07
16.2
0.6
V
V
OUT 1–16 output swing: high
OUT 1–16 output swing: low
VCOM1, 2 output swing: high
VCOM1, 2 output swing: low
Continuous output current(1)
Output accuracy
Code = 1023, sourcing 10 mA, TA = –40°C to 85°C
Code = 0, sinking 10 mA, TA = –40°C to 85°C
Code = 1023, sourcing 100 mA, TA = –40°C to 85°C
Code = 0, sinking 100 mA, TA = –40°C to 85°C
17.7
13
0.3
2
V
V
V
30
mA
mV
μV/°C
LSB
LSB
mV/mA
±20
±25
0.3
±50
Output accuracy over temperature
Code 512, TA = –40°C to 85°C
INL
Integral nonlinearity
DNL
Differential nonlinearity
Load regulation, 10 mA
0.3
ΔVO(ΔIO)
Code 512 or VCC / 2, IOUT = 5-mA to –5-mA step
0.5
1.5
16
OTP MEMORY
Number of OTP write cycles
Cycles
Years
Memory retention
ANALOG POWER SUPPLY
Operating range
100
12
9
20
14
18
V
ICC(tot)
Total analog supply current
Outputs at reset values, no load
TA = –40°C to 85°C
mA
mA
ICC(tot) over temperature
DIGITAL
VIH
Logic 1 high input voltage
Logic 0 low input voltage
Logic 0 low output voltage
Input leakage
0.7 × VSD
V
V
VIL
0.3 × VSD
0.4
VOL
ISINK = 3 mA
0.15
V
±0.01
±10
μA
kHz
MHz
Standard, fast mode, TA = –40°C to 85°C
High-speed mode, TA = –40°C to 85°C
400
fCLK
Clock frequency
2.7
DIGITAL POWER SUPPLY
DVDD
ISD
Digital power supply (VSD pin)
Digital supply current(1)
2.0
5.5
V
Outputs at reset values, no load, two-wire bus inactive
TA = –40°C to 85°C
115
115
150
μA
μA
ISD over temperature
TEMPERATURE RANGE
Specified range
–40
–40
–65
85
95
°C
°C
°C
Operating range
Junction temperature < 125°C
Storage range
150
Thermal resistance,
RθJA
40
°C/W
HTSSOP-28(1)(2)
(1) Observe maximum power dissipation.
(2) Thermal pad is attached to the printed circuit board (PCB), 0-lfm airflow, and 76-mm × 76-mm copper area.
6
Copyright © 2014, Texas Instruments Incorporated
BUF16821-Q1
www.ti.com.cn
ZHCSCF9 –MAY 2014
6.6 Timing Requirements
FAST MODE
MIN MAX
HIGH-SPEED MODE
PARAMETER
SCL operating frequency
MIN
0.001
230
MAX
UNIT
MHz
ns
f(SCL)
0.001
1300
0.4
2.7
t(BUF)
Bus free time between stop and start conditions
t(HDSTA)
Hold time after repeated start condition. After this period,
the first clock is generated.
600
230
ns
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
Repeated start condition setup time
Stop condition setup time
Data hold time
600
600
20
230
230
20
ns
ns
ns
ns
ns
ns
900
300
130
Data setup time
100
1300
600
20
SCL clock low period
SCL clock high period
230
60
t(HIGH)
tR(SDA)
,
Data rise and fall time
80
40
ns
tF(SDA)
tR(SCL)
,
Clock rise and fall time
300
ns
ns
tF(SCL)
tR
Clock and data rise time for SCLK ≤ 100 kHz
1000
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH) t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 1. Timing Requirements Diagram
Copyright © 2014, Texas Instruments Incorporated
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BUF16821-Q1
ZHCSCF9 –MAY 2014
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6.7 Typical Characteristics
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
18
17.5
17
18
17.5
17
16.5
16
16.5
16
VCOM1
Output Swing High
15.5
15
15.5
15
3
2.5
2
3
2.5
2
1.5
1
1.5
1
VCOM2
Output Swing Low
0.5
0
0.5
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Output Current (mA)
Output Current (mA)
Figure 2. Output Voltage vs Output Current
(VCOM1 and VCOM2)
Figure 3. Output Voltage vs Output Current
(Channels 1–16)
11
10.5
10
120
118
116
114
112
110
108
106
104
102
100
9.5
9
8.5
8
7.5
7
6.5
-50
-25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 4. Digital Supply Current vs Temperature
Figure 5. Analog Supply Current vs Temperature
0.15
0.1
9.02
9.015
9.01
9.005
9
0.05
0
8.995
8.99
8.985
8.98
–0.05
–0.1
–0.15
256
512
768
0
1024
–50
–25
0
25
50
75
100
125
Temperature (°C)
Input Code
10 Typical Units Shown
Figure 6. Output Voltage vs Temperature
Figure 7. Differential Linearity Error
8
Copyright © 2014, Texas Instruments Incorporated
BUF16821-Q1
www.ti.com.cn
ZHCSCF9 –MAY 2014
Typical Characteristics (continued)
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
0.15
0.1
BKSEL (2 V/div)
0.05
780 ms
0
9 V
–0.05
DAC Channel
(2 V/div)
–0.1
5 V
–0.15
1 ms/div
256
768
1024
0
512
Input Code
Figure 9. BKSEL Switching Time Delay
Figure 8. Integral Linearity Error
Time (1 ms/div)
Figure 10. Large-Signal Step Response
Copyright © 2014, Texas Instruments Incorporated
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BUF16821-Q1
ZHCSCF9 –MAY 2014
www.ti.com.cn
7 Detailed Description
7.1 Overview
The BUF16821-Q1 programmable voltage reference allows fast and easy adjustment of 16 programmable
gamma reference outputs and two VCOM outputs, each with 10-bit resolution. The device is programmed
through a high-speed, I2C interface. The final gamma and VCOM values can be stored in the onboard,
nonvolatile memory. To allow for programming errors or liquid crystal display (LCD) panel rework, the device
supports up to 16 write operations to the onboard memory. The device has two separate memory banks, allowing
simultaneous storage of two different gamma curves to facilitate dynamic switching between gamma curves.
Figure 19 illustrates a typical configuration of the device.
7.2 Functional Block Diagram
Digital Analog
(2.0 V to 5.5 V) (9 V to 20 V)
BKSEL
1
OUT1
OUT2
OUT15
OUT16
VCOM1
VCOM2
SDA
SCL
Control IF
Device
7.3 Feature Description
7.3.1 Two-Wire Bus Overview
The device communicates over an industry-standard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the communication is called a master, and the devices
controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the start and stop conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a
high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising
edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
10
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BUF16821-Q1
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ZHCSCF9 –MAY 2014
Feature Description (continued)
When all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high
while SCL is high. The device can act only as a slave device and therefore never drives SCL. SCL is an input
only for the BUF16821-Q1.
7.3.2 Data Rates
The two-wire bus operates in one of three speed modes:
•
•
•
Standard: allows a clock frequency of up to 100 kHz;
Fast: allows a clock frequency of up to 400 kHz; and
High-speed mode (also called Hs mode): allows a clock frequency of up to 2.7 MHz.
The device is fully compatible with all three modes. No special action is required to use the device in standard or
fast modes, but high-speed mode must be activated. To activate high-speed mode, send a special address byte
of 00001 xxx, with SCL ≤ 400 kHz, following the start condition; where xxx are bits unique to the Hs-capable
master, which can be any value. This byte is called the Hs master code. Table 1 provides a reference for the
high-speed mode command code. (Note that this configuration is different from normal address bytes—the low
bit does not indicate read or write status.) The device responds to the high-speed command regardless of the
value of these last three bits. The device does not acknowledge this byte; the communication protocol prohibits
acknowledgment of the Hs master code. Upon receiving a master code, the device switches on its Hs mode
filters, and communicates at up to 2.7 MHz. Additional high-speed transfers may be initiated without resending
the Hs mode byte by generating a repeat start without a stop. The device switches out of Hs mode with the next
stop condition.
Table 1. Quick-Reference of Command Codes
COMMAND
CODE
General-call reset
Address byte of 00h followed by a data byte of 06h.
00001xxx, with SCL ≤ 400 kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
High-speed mode
7.3.3 General-Call Reset and Power-Up
The device responds to a general-call reset, which is an address byte of 00h (0000 0000) followed by a data byte
of 06h (0000 0110). The device acknowledges both bytes. Table 1 provides a reference for the general-call reset
command code. Upon receiving a general-call reset, the device performs a full internal reset, as though it was
powered off and then on. The device always acknowledges the general-call address byte of 00h (0000 0000), but
does not acknowledge any general-call data bytes other than 06h (0000 0110).
The device automatically performs a reset when powered up. As part of the reset, the device is configured for all
outputs to change to the last programmed nonvolatile memory values, or 1000000000 if the nonvolatile memory
values are not programmed.
7.3.4 Output Voltage
The buffer output values are determined by the analog supply voltage (VS) and the decimal value of the binary
input code used to program that buffer. The value is calculated using Equation 1:
CODE10
VOUT = VS ´
1024
(1)
The device outputs are capable of a full-scale voltage output change in typically 5 μs; no intermediate steps are
required.
7.3.5 Updating the DAC Output Voltages
Updating the digital-to-analog converter (DAC) and the VCOM register is not the same as updating the DAC and
VCOM output voltage because the device features a double-buffered register structure. There are two methods
for updating the DAC and VCOM output voltages.
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BUF16821-Q1
ZHCSCF9 –MAY 2014
www.ti.com.cn
Method 1: Method 1 is used when the DAC and VCOM output voltage are desired to change immediately after
writing to a DAC register. For each write transaction, the master sets data bit 15 to a 1. The DAC and VCOM
output voltage update occurs after receiving the 16th data bit for the currently-written register.
Method 2: Method 2 is used when all DAC and VCOM output voltages are desired to change at the same time.
First, the master writes to the desired DAC and VCOM channels with data bit 15 a 0. Then, when writing the last
desired DAC and VCOM channel, the master sets data bit 15 to a 1. All DAC and VCOM channels are updated
at the same time after receiving the 16th data bit.
7.3.6 DIE_ID and DIE_REV Registers
The user can verify the presence of the BUF16821-Q1 in the system by reading from address 111101. When
read at this address, the BUF16821-Q1A returns 0101100100100111 and the BUF16821-Q1B returns
0101100100100100.
The user can also determine the die revision of the device by reading from register 111100. The device returns
0000000000000000 when a RevA die is present. RevB is designated by 0000000000000001, and so on.
7.3.7 Read and Write Operations
Read and write operations can be done for a single DAC and VCOM or for multiple DACs and VCOMs. Writing
to a DAC and VCOM register differs from writing to the nonvolatile memory. Bits D15–D14 of the most significant
byte of data determine if data are written to the DAC and VCOM register or the nonvolatile memory.
7.3.7.1 Read and Write: DAC and VCOM Register (Volatile Memory)
The device is able to read from a single DAC and VCOM, or multiple DACs and VCOMs, or write to the register
of a single DAC and VCOM, or multiple DACs and VCOMs in a single communication transaction. The DAC
pointer addresses begin with 000000 (which corresponds to OUT1) through 001111 (which corresponds to
OUT16). Addresses 010010 and 010011 are VCOM1 and VCOM2, respectively.
Write commands are performed by setting the read and write bit low. Setting the read or write bit high performs a
read transaction.
7.3.7.2 Writing: DAC and VCOM Register (Volatile Memory)
To write to a single DAC and VCOM register:
1. Send a start condition on the bus.
2. Send the device address and read and write bit = low. The device acknowledges this byte.
3. Send a DAC and VCOM pointer address byte. Set bit D7 = 0 and D6 = 0. Bits D5–D0 are the DAC and
VCOM address. Although the device acknowledges 000000 through 010111, data are stored and returned
only from these addresses:
–
–
000000 through 001111
010010 through 010011
The device returns 0000 for reads from 010000 through 010001, and 010100 through 010111. See Table 4
for valid DAC and VCOM addresses.
4. Send two bytes of data for the specified register. Begin by sending the most significant byte first (bits
D15–D8, of which only bits D9 and D8 are used, and bits D15–D14 must not be 01), followed by the least
significant byte (bits D7–D0). The register is updated after receiving the second byte.
5. Send a stop or start condition on the bus.
The device acknowledges each data byte. If the master terminates communication early by sending a stop or
start condition on the bus, the specified register is not updated. Updating the DAC and VCOM register is not the
same as updating the DAC and VCOM output voltage; see the Updating the DAC Output Voltages section.
The process of updating multiple DAC and VCOM registers begins the same as when updating a single register.
However, instead of sending a stop condition after writing the addressed register, the master continues to send
data for the next register. The device automatically and sequentially steps through subsequent registers as
additional data are sent. The process continues until all desired registers are updated or a stop or start condition
is sent.
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To write to multiple DAC and VCOM registers:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever DAC and VCOM is the first in the sequence of DACs and VCOMs to be updated. The device
begins with this DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send the bytes of data; begin by sending the most significant byte (bits D15–D8, of which only bits D9 and
D8 have meaning, and bits D15–D14 must not be 01), followed by the least significant byte (bits D7–D0).
The first two bytes are for the DAC and VCOM addressed in the previous step. The DAC and VCOM register
is automatically updated after receiving the second byte. The next two bytes are for the following DAC and
VCOM. That DAC and VCOM register is updated after receiving the fourth byte. This process continues until
the registers of all following DACs and VCOMs are updated. The device continues to accept data for a total
of 18 DACs; however, the two data sets following the 16th data set are meaningless. The 19th and 20th data
sets apply to VCOM1 and VCOM2. The write disable bit cannot be accessed using this method. This bit must
be written to using the write to a single DAC register procedure.
5. Send a stop or start condition on the bus.
The device acknowledges each byte. To terminate communication, send a stop or start condition on the bus.
Only DAC registers that have received both bytes of data are updated.
7.3.7.3 Reading: DAC, VCOM, Other Register (Volatile Memory)
Reading a register returns the data stored in that DAC, VCOM, other register.
To read a single DAC, VCOM, other register:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send the DAC, VCOM, other pointer address byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are the DAC,
VCOM, other address. Note that the device stores and returns data only from these addresses:
–
–
–
–
000000 through 001111
010010
010011
111100 through 111111
The device returns 0000 for reads from 010000 and 010001, and 010100 through 010111. See Table 4 for
valid DAC, VCOM, other addresses.
4. Send a start or stop and start condition.
5. Send the correct device address and read or write bit = high. The device acknowledges this byte.
6. Receive two bytes of data. These bytes are for the specified register. The most significant byte (bits D15–D8)
is received first; next is the least significant byte (bits D7–D0). In the case of DAC and VCOM channels, bits
D15–D10 have no meaning.
7. Acknowledge after receiving the first byte.
8. Send a stop or start condition on the bus or do not acknowledge the second byte to end the read transaction.
Communication may be terminated by sending a premature stop or start condition on the bus, or by not
acknowledging.
To read multiple registers:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte.
3. Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever register is the first in the sequence of DACs and VCOMs to be read. The device begins with this
DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send a start or stop and start condition on the bus.
5. Send the correct device address and read or write bit = high. The device acknowledges this byte.
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6. Receive two bytes of data. These bytes are for the specified DAC and VCOM. The first received byte is the
most significant byte (bits D15–D8; only bits D9 and D8 have meaning), next is the least significant byte (bits
D7–D0).
7. Acknowledge after receiving each byte of data.
8. When all desired DACs are read, send a stop or start condition on the bus.
Communication may be terminated by sending a premature stop or start condition on the bus, or by not sending
the acknowledge bit. Reading the DieID, DieRev, and MaxBank registers is not supported in this mode of
operation (these values must be read using the single register read method).
7.3.7.4 Write: Nonvolatile Memory for the DAC Register
The device is able to write to the nonvolatile memory of a single DAC and VCOM in a single communication
transaction. In contrast to the BUF20820, writing to multiple nonvolatile memory words in a single transaction is
not supported. Valid DAC and VCOM pointer addresses begin with 000000 (which corresponds to OUT1)
through 001111 (which corresponds to OUT16). Addresses 010010 and 010011 are VCOM1 and VCOM2,
respectively.
When programming the nonvolatile memory, the analog supply voltage must be between 9 V and 20 V. Write
commands are performed by setting the read or write bit low.
To write to a single nonvolatile register:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte. Although the device
acknowledges 000000 through 010111, data are stored and returned only from these addresses:
–
–
000000 through 001111
010010 and 010011
The device returns 0000 for reads from 010000 through 010001, and 010100 through 010111. See Table 4
for DAC and VCOM addresses.
3. Send a DAC and VCOM pointer address byte. Set bit D7 = 0 and D6 = 0. Bits D5–D0 are the DAC and
VCOM address.
4. Send two bytes of data for the nonvolatile register of the specified DAC and VCOM. Begin by sending the
most significant byte first (bits D15–D8, of which only bits D9 and D8 are data bits, and bits D15–D14 must
be 01), followed by the least significant byte (bits D7–D0). The register is updated after receiving the second
byte.
5. Send a stop condition on the bus.
The device acknowledges each data byte. If the master terminates communication early by sending a stop or
start condition on the bus, the specified nonvolatile register is not updated. Writing a nonvolatile register also
updates the DAC and VCOM register and output voltage.
The DAC and VCOM register and DAC and VCOM output voltage are updated immediately, while the
programming of the nonvolatile memory takes up to 250 μs. When a nonvolatile register write command is
issued, no communication with the device should take place for at least 250 μs. Writing or reading over the serial
interface while the nonvolatile memory is being written jeopardizes the integrity of the data being stored.
7.3.7.5 Read: Nonvolatile Memory for the DAC Register
To read the data present in nonvolatile register for a particular DAC and VCOM channel, the master must first
issue a general acquire command, or a single acquire command with the appropriate DAC and VCOM channel
chosen. This action updates both the DAC and VCOM registers and DAC and VCOM output voltages. The
master may then read from the appropriate DAC and VCOM register as described earlier.
14
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Figure 11. Write DAC Register Timing
Figure 12. Read Register Timing
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Figure 13. Write Nonvolatile Register Timing
Figure 14. Acquire Operation Timing
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Figure 15. General-Call Reset Timing
Figure 16. High-Speed Mode Timing
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7.3.8 Output Protection
The device output stages can safely source and sink the current levels indicated in Figure 2 and Figure 3.
However, there are other modes where precautions must be taken to prevent the output stages from being
damaged by excessive current flow. The outputs (OUT1 through OUT16, VCOM1 and VCOM2) include
electrostatic discharge (ESD) protection diodes, as shown in Figure 17. Normally, these diodes do not conduct
and are passive during typical device operation. Unusual operating conditions can occur where the diodes may
conduct, potentially subjecting them to high, even damaging current levels. These conditions are most likely to
occur when a voltage applied to an output exceeds (VS) + 0.5 V, or drops below GND – 0.5 V.
One common scenario where this condition can occur is when the output pin is connected to a sufficiently large
capacitor and the device power-supply source (VS) is suddenly removed. Removing the power-supply source
allows the capacitor to discharge through the current-steering diodes. The energy released during the high
current flow period causes the power dissipation limits of the diode to be exceeded. Protection against the high
current flow may be provided by placing current-limiting resistors in series with the output; see Figure 19. Select
a resistor value that restricts the current level to the maximum rating for the particular pin.
VS
ESD Current-Steering
Diodes
Device
OUTx or VCOMx
Figure 17. Output Pins ESD Protection Current-Steering Diodes
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7.4 Device Functional Modes
7.4.1 End-User Selected Gamma Control
The device is well-suited for providing two levels of gamma control by using the BKSEL pin because the device
has two banks of nonvolatile memory, as shown in Figure 18. When the state of the BKSEL pin changes, the
device updates all 18 programmable buffer outputs simultaneously after 750 μs (±80 μs).
To update all 18 programmable output voltages simultaneously via hardware, toggle the BKSEL pin to switch
between gamma curve 0 (stored in Bank0) and gamma curve 1 (stored in Bank1).
All DAC and VCOM registers and output voltages are updated simultaneously after approximately 750 μs.
5 V
Device
BKSEL
OUT1
Switch
Change in
Output Voltages
OUT16
I2C
Figure 18. Gamma Control
7.4.2 Dynamic Gamma Control
Dynamic gamma control is a technique used to improve the picture quality in LCD television applications. This
technique typically requires switching gamma curves between frames. Using the BKSEL pin to switch between
two gamma curves does not often provide good results because of the 750 μs required to transfer the data from
the nonvolatile memory to the DAC register. However, dynamic gamma control can still be accomplished by
storing two gamma curves in an external electrically erasable programmable read-only memory (EEPROM) and
writing directly to the DAC register (volatile).
The double register input structure saves programming time by allowing updated DAC values to be pre-stored
into the first register bank. Storage of this data can occur while a picture is still being displayed. Because the
data are only stored into the first register bank, the DAC and VCOM output values remain unchanged—the
display is unaffected. At the beginning or the end of a picture frame, the DAC and VCOM outputs (and therefore,
the gamma voltages) can be quickly updated by writing a 1 in bit 15 of any DAC and VCOM register. For details
on the operation of the double register input structure, see the Updating the DAC Output Voltages section.
To update all 18 programmable output voltages simultaneously via software, perform the following actions:
STEP 1: Write to registers 1–18 with bit 15 always 0.
STEP 2: Write any DAC and VCOM register a second time with identical data. Make sure that bit 15 is set to 1.
All DAC and VCOM channels are updated simultaneously after receiving the last bit of data.
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7.5 Programming
7.5.1 Addressing the Device
The device address 111010x, where x is the state of the A0 pin. When the A0 pin is low, the device
acknowledges on address 74h (1110100). If the A0 pin is high, the device acknowledges on address 75h
(1110101). Table 2 shows the A0 pin settings and device address options.
Other valid addresses are possible through a simple mask change. Contact your TI representative for
information.
Table 2. Quick-Reference of Device Addresses
DEVICE, COMPONENT
ADDRESS
(Device Address)
A0 pin is low
(device acknowledges on address 74h)
1110100
1110101
A0 pin is high
(device acknowledges on address 75h)
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Device
(1)
(1)
(1)
VCOM2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
GNDA(2)
VS
VCOM2
1
2
VCOM1 28
OUT16 27
OUT15 26
OUT14 25
GNDA(2) 24
VCOM1
(1)
(1)
(1)
Source
Driver
3
(1)
(1)
4
Source
Driver
(1)
5
(1)
VS
6
VS
23
100 nF
10 mF
(1)
(1)
7
OUT13 22
OUT12 21
OUT11 20
OUT10 19
GNDD(2) 18
BKSEL 17
A0 16
(1)
8
Source
Driver
(1)
VS
9
100 nF
10 mF
(1)
(1)
OUT7
OUT8
OUT9
VSD
10
11
12
13
14
(1)
Source
Driver
(1)
3.3 V
1 mF
100 nF
SCL
SDA 15
Timing
Controller
(1) RC combination optional; see the Output Protection section.
(2) GNDA and GNDD must be connected together.
Figure 19. Typical Application Configuration
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7.5.2 Nonvolatile Memory
7.5.2.1 BKSEL Pin
The device has 16x rewrite capability of the nonvolatile memory. Additionally, the device is capable of storing two
distinct gamma curves in two different nonvolatile memory banks, each of which has 16x rewrite capability. One
of the two available banks is selected using the external input pin, BKSEL. When this pin is low, Bank0 is
selected; when this pin is high, Bank1 is selected.
When the BKSEL pin changes state, the device acquires the last programmed DAC and VCOM values from the
nonvolatile memory associated with this newly chosen bank. At power-up, the state of the BKSEL pin determines
which memory bank is selected.
The I2C master can also update (acquire) the DAC registers with the last programmed nonvolatile memory
values using software control. The bank to be acquired depends on the state of BKSEL.
7.5.2.2 General Acquire Command
A general acquire command is used to update all registers and DAC and VCOM outputs to the last programmed
values stored in nonvolatile memory. A single-channel acquire command updates only the register and DAC and
VCOM output of the DAC and VCOM corresponding to the DAC and VCOM address used in the single-channel
acquire command.
These are the steps of the sequence to initiate a general channel acquire:
1. Be sure BKSEL is in its desired state and is stable for at least 1 ms.
2. Send a start condition on the bus.
3. Send the appropriate device address (based on A0) and the read or write bit = low. The device
acknowledges this byte.
4. Send a DAC and VCOM pointer address byte. Set bit D7 = 1 and D6 = 0. Bits D5–D0 are any valid DAC and
VCOM address. Although the device acknowledges 000000 through 010111, data are stored and returned
only from these addresses:
–
–
000000 through 001111
010010 and 010011
The device returns 0000 for reads from 010000 and 010001, and 010100 through 010111. See Table 4 for
valid DAC and VCOM addresses.
5. Send a stop condition on the bus.
Approximately 750 μs (±80 μs) after issuing this command, all DAC and VCOM registers and DAC and VCOM
output voltages change to the respective, appropriate nonvolatile memory values.
7.5.2.3 Single-Channel Acquire Command
These are the steps to initiate a single-channel acquire:
1. Be sure BKSEL is in its desired state and is stable for at least 1 ms.
2. Send a start condition on the bus.
3. Send the device address (based on A0) and read or write bit = low. The device acknowledges this byte.
4. Send a DAC and VCOM pointer address byte using the DAC and VCOM address corresponding to the
output and register to update with the OTP memory value. Set bit D7 = 0 and D6 = 1. Bits D5–D0 are the
DAC and VCOM address. Although the device acknowledges 000000 through 010111, data are stored and
returned only from these addresses:
–
–
000000 through 001111
010010 and 010011
The device returns 0000 reads from 010000 and 010001, and 010100 through 010111. See Table 4 for valid
DAC and VCOM addresses.
5. Send a stop condition on the bus.
Approximately 36 μs (±4 μs) after issuing this command, the specified DAC and VCOM register and DAC and
VCOM output voltage change to the appropriate OTP memory value.
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7.5.2.4 MaxBank
The device can provide the user with the number of times the nonvolatile memory of a particular DAC and VCOM
channel nonvolatile memory is written to for the current memory bank. This information is provided by reading the
register at pointer address 111111.
There are two ways to update the MaxBank register:
1. After initiating a single acquire command, the device updates the MaxBank register with a code
corresponding to how many times that particular channel memory is written to.
2. Following a general acquire command, the device updates the MaxBank register with a code corresponding
to the maximum number of times the most used channel (OUT1–16 and VCOMs) is written to.
MaxBank is a read-only register and is only updated by performing a general- or single-channel acquire.
Table 3 shows the relationship between the number of times the nonvolatile memory is programmed and the
corresponding state of the MaxBank Register.
Table 3. MaxBank Details
NUMBER OF TIMES WRITTEN TO
RETURNS CODE
0000
0
1
0000
2
0001
3
0010
4
0011
5
0100
6
0101
7
0110
8
0111
9
1000
10
11
12
13
14
15
16
1001
1010
1011
1100
1101
1110
1111
7.5.2.5 Parity Error Correction
The device provides single-bit parity error correction for data stored in the nonvolatile memory to provide
increased reliability of the nonvolatile memory. If a single bit of nonvolatile memory for a channel fails, the device
corrects for the failure and updates the appropriate DAC with the intended value when its memory is acquired.
If more than one bit of nonvolatile memory for a channel fails, the device does not correct for it, and updates the
appropriate DAC and VCOM with the default value of 1000000000.
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7.6 Register Maps
Table 4. DAC Register Pointer Addresses
DAC REGISTER
OUT1
POINTER ADDRESS
000000
000001
OUT2
OUT3
000010
OUT4
000011
OUT5
000100
OUT6
000101
OUT7
000110
OUT8
000111
OUT9
001000
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
VCOM1
VCOM2
001001
001010
001011
001100
001101
001110
001111
010010
010011
OTHER REGISTER
Die_Rev
POINTER ADDRESS
111100
Die_ID
111101
MaxBank
111111
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8 Application and Implementation
8.1 Application Information
The BUF16821-Q1 is a multichannel programmable voltage reference. Featuring 16 programmable gamma
reference outputs and two programmable VCOM outputs, the device is designed to interface between timing
controllers and source drivers commonly used in LCD displays.
8.2 Typical Application
BKSEL
I/O
OUT1
.
Timing Controller
BUF16821
.
.
Source Driver
SCL
SDA
SCL
SDA
OUT16
Figure 20. Gamma Control Block Diagram
8.2.1 Design Requirements
If the nonvolatile memory has never been programmed, the BUF16821-Q1 outputs defaults to VS / 2 following
power-up. Refer to the Power Supply Recommendations section for proper power-supply sequencing
requirements. Figure 21 shows the typical output response when the analog power supply (VS) ramps to its
desired value. When the analog supply is below 2 V, the outputs follow the analog supply voltage. After the
analog supply voltage (VS) exceeds approximately 2 V, the outputs begin to track at VS / 2. This sequence is
illustrated in Figure 21.
If the nonvolatile memory is pre-programmed, the device outputs ramp to their pre-programmed values.
Figure 22 and Figure 23 illustrate the power-up behavior of the device pre-programmed to a 4-V and 8-V output
voltage, respectively. Note that when the analog power supply voltage (VS) exceeds approximately 5 V, the
device performs an automatic read of the nonvolatile memory, acquiring the pre-programmed values to ensure
the proper output value when the analog supply voltage ramps to its final value. During the nonvolatile memory
acquire operation, the output tracks at VS / 2 for approximately 1 ms. This sequence is illustrated in Figure 22
and Figure 23 . Note that the minimum valid analog supply voltage, VS, is specified as 9 V. Below this value the
outputs should not be considered valid.
Figure 24 illustrates the device output response to a general-call reset. During the internal reset, the output
momentarily tracks at VS / 2 while the nonvolatile memory values are acquired. Following the reset, the output
returns to the pre-programmed value.
8.2.2 Detailed Design Procedure
Proper power-supply bypassing is required when using the BUF16821-Q1. TI recommends connecting a 10-μF
capacitor in parallel with a 100-nF capacitor at each analog supply pin (pins 9 and 23), as illustrated in Figure 19.
Similarly, connecting a 1-μF capacitor in parallel with a 100-nF capacitor at the digital supply pin (pin 13) is also
recommended. However, adding more than 200-pF capacitance at any gamma or VCOM output is not
recommended; see the Output Protection section.
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Typical Application (continued)
8.2.3 Application Curves
Output Voltage
Analog Supply Voltage
Output Volatge
Analog Supply Voltage
Time (2 ms/div)
Time (2 ms/div)
Figure 21. Power-On Response Prior to Programming the
Nonvolatile Memory
Figure 22. Power-On Response with Nonvolatile Memory
Programmed for 4-V Output
Output Voltage
Output Voltage
Analog Supply Voltage
Analog Supply Voltage
Time (2 ms/div)
Time (2 ms/div)
Figure 23. Power-On Response with Nonvolatile Memory
Programmed for 8-V Output
Figure 24. Output Response to a General-Call Reset
9 Power Supply Recommendations
The device can be powered using an analog supply voltage from 9 V to 20 V, and a digital supply from 2 V to
5.5 V. The digital supply must be applied before the analog supply to avoid excessive current and power
consumption, or possibly even damage to the device if left connected only to the analog supply for extended
periods of time.
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10 Layout
10.1 Layout Guidelines
10.1.1 General PowerPAD Design Considerations
The device is available in a thermally-enhanced PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted; see Figure 25(a) and Figure 25(b). This arrangement results
in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 25(c). This
thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing
a good thermal path away from the thermal pad.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 25. Views of a Thermally-Enhanced PWP Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have
low power dissipation. This technique provides the necessary thermal and mechanical connection between the
lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for
the HTSSOP-28 PWP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package
(SLMA002), available for download at www.ti.com. These holes should be 13 mils (0.33 mm) in diameter.
Keep these holes small, so that solder wicking through the holes is not a problem during reflow. An example
thermal land pattern mechanical drawing is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area to help
dissipate the heat generated by the device. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. These vias can be larger because they are not in the thermal pad area to
be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
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Layout Guidelines (continued)
5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This configuration makes the soldering of vias that have plane
connections easier. In this application, however, low thermal resistance is desired for the most efficient heat
transfer. Therefore, the holes under the device PowerPAD package should make their connection to the
internal plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the pins of the package and the thermal pad area with its twelve
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all device pins.
8. With these preparatory steps in place, simply place the device in position and run the chip through the solder
reflow operation as any standard surface-mount component. This preparation results in a properly installed
part.
For a given RθJA (listed in the Electrical Characteristics), the maximum power dissipation is shown in Figure 26
and calculated by Equation 2:
TMAX - TA
PD =
qJA
where
•
•
•
PD = maximum power dissipation (W),
TMAX = absolute maximum junction temperature (125°C), and
TA = free-ambient air temperature (°C).
(2)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
TA, Free-Air Temperature (°C)
Figure 26. Maximum Power Dissipation
vs Free-Air Temperature
(With PowerPAD Soldered Down)
28
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10.2 Layout Example
To Source
Drivers
GND
VS
SCL
VSD BKSEL SDA
To Timing Controller
Figure 27. PCB Layout Example
Copyright © 2014, Texas Instruments Incorporated
29
BUF16821-Q1
ZHCSCF9 –MAY 2014
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
《BUF16821EVM-USB 用户指南》，SBOU106
《BUF20820 数据表》，SBOS330
《PowerPAD 散热增强型封装》，SLMA002
《用伽马缓冲器驱动电容负载》，SBOA134
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
30
Copyright © 2014, Texas Instruments Incorporated
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BUF16821AIPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
B16821Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
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邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
BUF16821A
Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory
TI
BUF16821AIPWPR
Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory
TI
BUF16821B
Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory
TI
BUF16821BIPWPR
Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory
TI
BUF16821_1
Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory
TI
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