BUF20800AIDCPR [TI]
具有两个可编程 VCOM 通道的 18 通道伽马电压发生器 | DCP | 38 | -40 to 95;
| 型号： | BUF20800AIDCPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有两个可编程 VCOM 通道的 18 通道伽马电压发生器 | DCP | 38 | -40 to 95 光电二极管 电压发生器 |
| 文件： | 总31页 (文件大小：1473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUF20800
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
18-Channel GAMMA VOLTAGE GENERATOR
with Two Programmable VCOM Channels
FD EATURES
AD PPLICATIONS
18-CHANNEL GAMMA CORRECTION
2-CHANNEL PROGRAMMABLE V
REPLACES RESISTOR-BASED GAMMA
SOLUTIONS
D
:
COM
100mA I
OUT
D
TFT-LCD REFERENCE DRIVERS
DYNAMIC GAMMA CONTROL
D
D
D
D
D
D
10-BIT RESOLUTION
D
RAIL-TO-RAIL OUTPUT
LOW SUPPLY CURRENT: 900µA/ch
SUPPLY VOLTAGE: 7V to 18V
DIGITAL SUPPLY: 2.0V to 5.5V
DESCRIPTION
The BUF20800 is a programmable voltage reference
generator designed for gamma correction in TFT-LCD
panels. It provides 18 programmable outputs for gamma
correction and two channels for VCOM adjustment, each
with 10-bit resolution.
INDUSTRY-STANDARD, TWO-WIRE
INTERFACE:
3.4MHz High-Speed Mode
D
D
HIGH ESD RATING:
4kV HBM, 1kV CDM, 200V MM
This programmability replaces the traditional, time-
consuming process of changing resistor values to optimize
the various gamma voltages and allows designers to
determine the correct gamma voltages for a panel very
quickly. Required changes can also be easily implemented
without hardware changes.
DEMO BOARD AND SOFTWARE AVAILABLE
Analog
Digital
(7V to 18V)
REFH
(2.0V to 5.5V)
BUF20800
REFH OUT
VCOM OUT1
The BUF20800 uses TI’s latest, small-geometry analog
CMOS process, which makes it a very competitive choice
for full production, not just evaluation.
Programming of each output occurs through an industry-
standard, two-wire serial interface. Unlike existing
programmable buffers, the BUF20800 offers a high-speed
mode that allows clock speeds up to 3.4MHz.
VCOM OUT2
OUT 1
OUT 2
For lower channel count, please contact your local sales
or marketing representative.
The BUF20800 is available in an HTSSOP-38
PowerPAD package. It is specified from −40°C to +85°C.
18 Output Channels plus
Two VCOM Channels
BUF20800 RELATED PRODUCTS
OUT 17
FEATURES
PRODUCT
18-Channel Programmable, Two V
+ OTP Memory
BUF20820
BUF12800
BUF01900
BUFxx704
SN10501
OUT 18
COM
12-Channel Programmable Buffer, 10-Bit
Programmable V
REFL OUT
COM
11-, 6-, 4-Channel Gamma Correction Buffer, 18V Supply
High-Speed V , 1 and 2 Channels
SDA
SCL
Control IF
COM
Complete LCD DC/DC Solution
TPS65100
LD
AO
REFL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2005−2007, Texas Instruments Incorporated
www.ti.com
ꢠꢄ ꢡ ꢢ ꢣꢤ ꢣ ꢣ
www.ti.com
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +19V
S
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
SD
Signal Input Terminals, SCL, SDA, AO, LD:
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
(2)
Output Short Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1)
(2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is
not supported.
Short-circuit to ground, one amplifier per package.
(1)
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
PACKAGE MARKING
BUF20800
HTSSOP-38
DCP
BUF20800
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
2
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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, T = −40°C to +85°C.
A
At T = +25°C, V = 18V, V
= 5V, R = 1.5kΩ connected to ground, and C = 200pF, unless otherwise noted.
A
S
SD
L
L
BUF20800
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG
Gamma Output Swing—High
OUT 1−9, Sourcing 10mA, V
= 17.8V, Code 1023
17.7
17.0
17.8
17.2
0.6
0.2
15.5
1
V
V
REFH
OUT 10−18, Sourcing 10mA, V
= 17.8V, Code 1023
= 0.2V, Code 00
REFH
Gamma Output Swing—Low
OUT 1−9, Sinking 10mA, V
1.0
0.3
V
REFL
OUT 10−18, Sinking 10mA, V
= 0.2V, Code 00
V
REFL
V
V
Buffer Output Swing—High
V
COM
, Sourcing 100mA, V
= 17.8V
= 0.2V
13
V
COM
REFH
Buffer Output Swing—Low
V
COM
, Sinking 100mA, V
2.0
V
COM
REFL
(1)
Output Current
I
O
All Channels, Code 512, Sinking/Sourcing
40
4
45
mA
V
(2)
REFH Input Range
V
S
(2)
REFL Input Range
GND
V
S
− 4
V
Integral Nonlinearity
Differential Nonlinearity
Gain Error
INL
No Load, V
No Load, V
= 17V, V
= 17V, V
= 1V
= 1V
0.3
0.3
0.12
5
1.5
1
Bits
Bits
%
REFH
REFL
DNL
REFH
REFL
Program to Out Delay
Output Accuracy
t
D
µs
No Load, V
= 17V, V
= 1V
20
50
mV
mV
MΩ
mV/mA
mV/mA
REFH
REFL
Over Temperature
Input Resistance at V
25
and V
R
INH
100
0.5
0.5
REFH
REFL
Load Regulation, All References
40mA, All Channels
REG
V
= V /2, I = +5mA to −5mA Step
OUT
1.5
1.5
OUT
S
V
= V /2, I
= 40mA, I
= 40mA
OUT
S
SINKING
SOURCING
ANALOG POWER SUPPLY
Operating Range
V
I
7
18
28
28
V
S
Total Analog Supply Current
over Temperature
No Load
18
mA
mA
S
DIGITAL
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic 0 Output Voltage
Input Leakage
V
0.7× V
V
V
IH
SD
V
0.3× V
SD
0.4
IL
V
OL
I
= 3mA
0.15
0.01
V
SINK
10
µA
kHz
MHz
Clock Frequency
f
Standard/Fast Mode
High-Speed Mode
400
3.4
CLK
DIGITAL POWER SUPPLY
Operating Voltage Range
V
I
2.0
5.5
50
V
SD
(3)
Digital Supply Current
Outputs at Reset Values, No-Load, Two-Wire Bus Inactive
25
µA
µA
SD
over Temperature
100
TEMPERATURE
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Resistance, HTSSOP-38
Junction-to-Ambient
−40
−40
−65
+85
+95
°C
°C
°C
Junction Temperature < +125°C
+150
q
30
15
°C/W
°C/W
JA
Junction-to-Case
q
JC
(1)
(2)
(3)
See typical characteristic Output Voltage vs Output Current.
See applications information section REFH and REFL Input Range.
See typical characteristic Digital Supply Current vs Temperature.
3
ꢠꢄ ꢡ ꢢ ꢣꢤ ꢣ ꢣ
www.ti.com
HTSSOP
SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
PIN CONFIGURATIONS
Top View
VCOM OUT 2
1
2
3
4
5
6
7
8
9
38 VCOM OUT 1
37
36
35
REFH
NC(1)
REFL
NC(1)
NC(1)
NC(1)
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
34 REFL OUT
33 OUT 18
32
31
30
OUT 17
OUT 16
OUT 15
PowerPAD
Lead−Frame
Die Pad
OUT 6 10
29 OUT 14
Exposed on
Underside
(2)
(2)
11
12
13
28
27
26
GNDA
GNDA
VS
VS
OUT 7
OUT 13
OUT 8 14
OUT 9 15
25 OUT 12
24 OUT 11
16
17
18
23
22
21
REFH OUT
VSD
OUT 10
(2)
GNDD
SCL
LD
SDA 19
20 AO
(1) NC denotes no connection.
(2) GND and GND are internally connected and must be at the same voltage potential.
D
A
4
ꢠ ꢄꢡ ꢢꢣ ꢤꢣꢣ
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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS
At T = +25°C, V = 18V, V = 5V, V
= 17V, V
= 1V, R = 1.5kΩ connected to ground, and C = 200pF, unless otherwise noted.
A
S
SD
REFH
REFL
L
L
DIGITAL SUPPLY CURRENT vs TEMPERATURE
VS = 5V
ANALOG SUPPLY CURRENT vs TEMPERATURE
VS = 18V
30
25
20
15
10
5
16
14
12
10
8
V
S = 10V
VS = 3.3V
6
4
2
0
0
−
−
20
40
0
20
40
60
80
100
−
−
20
40
0
20
40
60
80
100
_
Tem pe r at ur e ( C)
_
Temperature ( C)
Figure 1
Figure 2
OUTPUT VOLTAGE vs OUTPUT CURRENT
FULL−SCALE OUTPUT SWING
18
17
16
15
REFH = 17V
REFL = 1V
OUT10−18 (sourcing), Code = 3FFh
VREFL = 0.2V, VREFH = 17V
→
OUT1−9, VCOM1−2 (sourcing)
Code = 3FFh
Code 3FF 000
RLOAD Connected to GND
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to GND
OUT1−9, VCOM1−2 (sinking)
3
2
1
0
OUT10−18 (sinking), Code = 000h
REFL = 0.2V, VREFH = 17V
RLOAD Connected to 18V
Code = 000h
V
→
Code 000 3FF
VREFL = 1V, VREFH = 17.8V
RLOAD Connected to 18V
0
10
20
30
40
50
60
70
80
90
100
µ
Time (1 s/div)
Output Current (mA)
Figure 3
Figure 4
DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE
INTEGRAL NONLINEARITY ERROR vs INPUT CODE
0.6
0.6
0.4
0.2
0
0.4
0.2
0
−
−
−
0.2
0.4
0.6
−
−
−
0.2
0.4
0.6
0
200
400
600
800
1000
0
200
400
600
800
1000
Input Code
Input Code
Figure 5
Figure 6
5
ꢠꢄ ꢡ ꢢ ꢣꢤ ꢣ ꢣ
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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
the serial clock on the clock signal line (SCL), controls the
bus access, and generates the START and STOP
conditions.
APPLICATIONS INFORMATION
The BUF20800 programmable voltage reference allows
fast, easy adjustment of 18 programmable reference
outputs and two channels for VCOM adjustment, each with
10-bit resolution. It offers very simple, time-efficient
adjustment of the gamma reference and VCOM voltages.
The BUF20800 is programmed through a high-speed,
standard, two-wire interface. The BUF20800 features a
double-register structure for each DAC channel to simplify
the implementation of dynamic gamma control. This
structure allows pre-loading of register data and rapid
updating of all channels simultaneously.
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to a LOW logic level while SCL is HIGH. All slaves on the
bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the 9th clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Data transfer is then initiated and eight bits of data are sent
followed by an Acknowledge Bit. During data transfer,
SDA must remain stable while SCL is HIGH. Any change
in SDA while SCL is HIGH will be interpreted as a START
or STOP condition.
Buffers 1−9 are able to swing to within 200mV of the
positive supply rail, and to within 0.6V of the negative
supply rail. Buffers 10−18 are able to swing to within 0.8V
of the positive supply rail and to within 200mV of the
negative supply rail.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF20800 can be powered using an analog supply
voltage from 7V to 18V, and a digital supply from 2V to
5.5V. The digital supply must be applied prior to or
simultaneously with the analog supply to avoid excessive
current and power consumption; damage to the device
may occur if it is left connected only to the analog supply
for extended periods of time. Figure 7 shows the power
supply timing requirements.
The BUF20800 can act only as a slave device; therefore,
it never drives SCL. SCL is only an input for the BUF20800.
Table 1 and Table 2 summarize the address and
command codes, respectively, for the BUF20800.
ADDRESSING THE BUF20800
VSD
The address of the BUF20800 is 111010x, where x is the
state of the A0 pin. When the A0 pin is LOW, the device will
acknowledge on address 74h (1110100). If the A0 pin is
HIGH, the device will acknowledge on address 75h
(1110101).
Digital Supply:
Analog Supply:
GNDD
VS
GND
t1
Other valid addresses are possible through a simple mask
change. Contact your TI representative for information.
t1: 0s minimum delay between Digital Supply and Analog Supply.
Figure 7. Power Supply Timing Requirements
Table 1. Quick-Reference Table of BUF20800
Addresses
DEVICE/COMPONENT
BUF20800 Address:
ADDRESS
Figure 8 shows the BUF20800 in a typical configuration.
In this configuration, the BUF20800 device address is 74h.
The output of each digital-to-analog converter (DAC) is
immediately updated as soon as data are received in the
corresponding register (LD = 0). For maximum dynamic
range, set VREFH = VS − 0.2V and VREFL = GND + 0.2V.
A0 pin is LOW
(device will acknowledge on address 74h)
1110100
1110101
A0 pin is HIGH
(device will acknowledge on address 75h)
TWO-WIRE BUS OVERVIEW
Table 2. Quick-Reference Table of Command
Codes
The BUF20800 communicates through an industry-
standard, two-wire interface to receive data in slave mode.
This standard uses a two-wire, open-drain interface that
supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the
communication is called a master, and the devices
controlled by the master are slaves. The master generates
COMMAND
CODE
Address byte of 00h followed by a data byte
of 06h.
General Call Reset
00001xxx, with SCL ≤ 400kHz; where xxx
are bits unique to the Hs-capable master.
This byte is called the Hs master code.
High-Speed Mode
6
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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
BUF20800
(1)
(1)
VCOM2
VCOM OUT2
REFH(3)
NC
VCOM1
1
2
38
37
36
VCOM OUT1
REFL(3)
NC
VS
VS
3
NC
4
NC 35
(1)
(1)
(1)
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
5
REFL OUT 34
(1)
(1)
(1)
(1)
6
33
32
OUT18
OUT17
(1)
7
Source
Driver
(1)
Source
Driver
8
OUT16 31
OUT15 30
OUT14 29
GNDA(2) 28
VS 27
(1)
9
(1)
10
11
12
13
14
15
16
17
18
19
(2)
GNDA
VS
VS
VS
µ
µ
10 F
100nF
10 F
100nF
(1)
(1)
OUT7
OUT8
OUT9
REFH OUT
VSD
26
25
24
23
22
OUT13
OUT12
OUT11
OUT10
(1)
(1)
Source
Driver
Source
Driver
(1)
(1)
(1)
(2)
3.3V
GNDD
µ
100nF
1 F
SCL
LD 21
AO 20
Timing
Controller
SDA
(1)
(2)
(3)
RC combination optional.
GND and GND must be connected together.
Connecting a capacitor to this node is not recommended.
A
D
Figure 8. Typical Application Configuration
7
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ꢄ
ꢡ
ꢢ
ꢣ
ꢤ
ꢣ
ꢣ
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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007
DATA RATES
OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (VREFH and VREFL) and the decimal value of the
binary input code used to program that buffer. The value is
calculated using Equation 1:
DThe Stwtaon-wdairred:baulsloowpseraactelosciknforenqeuoefntchyreoef suppeteod1m00okdHezs;:
D
D
Fast: allows a clock frequency of up to 400kHz; and
High-speed mode (or Hs mode): allows a clock
frequency of up to 3.4MHz.
V
* V
REFL
1024
REFH
+ ƪ
Decimal Value of Codeƫ) V
V
REFL
OUT
(1)
The BUF20800 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master,
which can be any value. This byte is called the Hs master
code. (Note that this is different from normal address
bytes—the low bit does not indicate read/write status.) The
BUF20800 will respond to the High-speed command
regardless of the value of these last three bits. The
BUF20800 will not acknowledge this byte; the
communication protocol prohibits acknowledgement of
the Hs master code. On receiving a master code, the
BUF20800 will switch on its Hs mode filters, and
communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF20800 will switch out of Hs mode with the next STOP
condition.
The valid voltage ranges for the reference voltages are:
4V v VREFH v VS * 0.2V and 0.2V v VREFL v VS * 4V
(2)
The BUF20800 outputs are capable of a full-scale voltage
output change in typically 5µs—no intermediate steps are
required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the
DAC output voltage, because the BUF20800 features a
double-buffered register structure. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output
voltages.
Method 1 requires externally setting the latch pin (LD)
LOW, LD = LOW, which will update each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
and until LD = LOW, which will then simultaneously update
the output voltages of all DACs to the new register values.
Use this method to transfer a future data set in advance to
prepare for a very fast output voltage update.
GENERAL CALL RESET AND POWER-UP
The BUF20800 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF20800 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF20800 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges the
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
Method 3 uses software control. LD is maintained HIGH,
and all DACs are updated when the master writes a 1 in bit
15 of any DAC register. The update will occur after
receiving the 16-bit data for the currently-written register.
The BUF20800 automatically performs a reset upon
power up. As part of the reset, all outputs are set to
(VREFH − VREFL)/2. Other reset values are available as a
custom modification—contact your TI representative for
details.
The General Call Reset and the power-up reset will update
the DAC regardless of the state of the latch pin.
READ/WRITE OPERATIONS
The BUF20800 is able to read from a single DAC, or
multiple DACs, or write to the register of a single DAC, or
multiple DACs in a single communication transaction.
DAC addresses begin with 0000 0000, which corresponds
to DAC_1, through 0001 0011, which corresponds to
VCOM OUT2.
The BUF20800 resets all outputs to (VREFH − VREFL)/2
after sending the device address, if a valid DAC address
is sent with bits D7 to D5 set to ‘100’. If these bits are set
to ‘010’, only the DAC being addressed in this most
significant byte (MSB) and the following least significant
byte (LSB) will be reset.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH will perform a read
transaction.
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To write to multiple DAC registers:
Writing:
1. Send a START condition on the bus.
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20800 will acknowledge this byte.
2. Send the device address and read/write bit = LOW.
The BUF20800 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be updated.
The BUF20800 will begin with this DAC and step
through subsequent DACs in sequential order.
3. Send a DAC address byte. Bits D7−D5 must be set to
0. Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be
acknowledged. Table 3 shows the DAC addresses.
4. Send the bytes of data; begin by sending the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning), followed by the least
significant byte (bits D7−D0). The first two bytes are
for the DAC addressed in step 3 above. Its register is
automatically updated after receiving the second byte.
The next two bytes are for the following DAC. That
DAC register is updated after receiving the fourth byte.
This process continues until the registers of all
following DACs have been updated.
4. Send two bytes of data for the specified DAC register.
Begin by sending the most significant byte first (bits
D15−D8, of which only bits D9 and D8 are used, and
bits D15−D14 must not be 01), followed by the least
significant byte (bits D7−D0). The register is updated
after receiving the second byte.
5. Send a STOP condition on the bus.
Table 3. DAC Addresses
5. Send a STOP condition on the bus.
DAC
ADDRESS
DAC_1
DAC_2
DAC_3
DAC_4
DAC_5
DAC_6
DAC_7
DAC_8
DAC_9
DAC_10
DAC_11
DAC_12
DAC_13
DAC_14
DAC_15
DAC_16
DAC_17
DAC_18
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
0001 0011
The BUF20800 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be updated.
Reading:
Reading a DAC register will return the data stored in the
DAC. This data can differ from the data stored in the DAC
register. See the Output Latch section.
To read the DAC value:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20800 will acknowledge this byte.
3. Send the DAC address byte. Bits D7−D5 must be set
to 0; Bits D4−D0 are the DAC address. Only DAC
addresses 00000 to 10011 are valid and will be
acknowledged.
V
V
COM OUT1
COM OUT2
4. Send a START or STOP/START condition on the bus.
The BUF20800 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage. See the
Output Latch section.
5. Send correct device address and read/write
bit = HIGH. The BUF20800 will acknowledge this
byte.
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8; only bits D9 and D8 have
meaning); the next byte is the least significant byte
(bits D7−D0).
The process of updating multiple DAC registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master continues to send data for
the next register. The BUF20800 automatically and
sequentially steps through subsequent registers as
additional data is sent. The process continues until all
desired registers have been updated or a STOP condition
is sent.
7. Acknowledge after receiving the first byte.
8. Do not acknowledge the second byte to end the read
transaction.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
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To Read Multiple DACs:
6. Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15−D8, only bits D9 and D8 have
meaning); the next byte is the least significant byte
(bits D7−D0).
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF20800 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be read. The
BUF20800 will begin with this DAC and step through
subsequent DACs in sequential order.
7. Acknowledge after receiving each byte of data except
for the last byte. The acknowledge bit of the last byte
should be HIGH to end the read operation.
8. When all desired DACs have been read, send a STOP
or repeated START condition on the bus.
4. Send a START or STOP/START condition on the bus.
5. Send correct device address and read/write
bit = HIGH. The BUF20800 will acknowledge this
byte.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
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a. Write Single DAC
b. Write Multiple DACs
Figure 9. Timing Diagram for Write DAC Register
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a. Read Single DAC
b. Read Multiple DACs
Figure 10. Timing Diagram for Read DAC Register
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BUF20800 uses the most advanced high-voltage CMOS
process available today, which allows it to be competitive
with traditional gamma buffers.
REPLACEMENT OF TRADITIONAL GAMMA
BUFFER
Traditional gamma buffers rely on a resistor string (often
using expensive 0.1% resistors) to set the gamma
voltages. During development, the optimization of these
gamma voltages can be time-consuming. Programming
these gamma voltages with the BUF20800 can
significantly reduce the time required for gamma voltage
optimization. The final gamma values can be written into
an external EEPROM to replace a traditional gamma
buffer solution. During power-up of the LCD panel, the
timing controller reads the EEPROM and loads the values
into the BUF20800 to generate the desired gamma
voltages. Figure 11a shows the traditional resistor string;
Figure 11b shows the more efficient alternative method
using the BUF20800.
This technique offers significant advantages:
D
D
It shortens development time significantly.
It allows demonstration of various gamma curves to
LCD monitor makers by simply uploading a different
set of gamma values.
D
D
It allows simple adjustment of gamma curves during
production to accommodate changes in the panel
manufacturing process or end-customer require-
ments.
It decreases cost and space.
a) Traditional
BUFxx704
b) BUF20800 Solution
BUF20800
VCOM OUT1
VCOM
VCOM OUT2
Timing
Controller
OUT1
OUT2
PC
SDA
SCL
Gamma
EEPROM
References
OUT17
OUT18
SDA
SCL
Control Interface
LCD Panel Electronics
Figure 11. Replacement of the Traditional Gamma Buffer
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PROGRAMMABLE V
REFH AND REFL INPUT RANGE
COM
The VCOM channels of the BUF20800 can swing to 2V from
the positive supply rail while sourcing 100mA and to 1V
above the negative rail while sinking 100mA (see Figure 4,
typical characteristic Output Voltage vs Output Current).
To store the gamma and the VCOM values, an external
EEPROM is required. During power-up of the LCD panel,
the timing controller can then read the EEPROM and load
the values into the BUF20800 to generate the desired
Best performance and output swing range of the
BUF20800 are achieved by applying REFH and REFL
voltages that are slightly below the power-supply
voltages. Most specifications have been tested at
REFH = VS − 200mV and REFL = GND + 200mV. The
REFH internal buffer is designed to swing very closely to
VS and the REFL internal buffer to GND. However, there
is a finite limit on how close they can swing before
saturating. To avoid saturation of the internal REFH and
REFL buffers, the REFH voltage should not be greater
than VS −100mV and REFL voltage should not be lower
than GND + 100mV. Figure 13 shows the swing capability
of the REFH and REFL buffers.
V
COM voltages, as illustrated in Figure 11 and Figure 12.
The VCOM channels can be programmed independently
from the gamma channels.
The other consideration when trying to maximize the
output swing capability of the gamma buffers is the
limitation in the swing range of output buffers (OUT1−18,
V
COM1, and VCOM2), which depends on the load current. A
typical load in the LCD application is 5−10mA. For
example, if OUT1 is sourcing 10mA, the swing is typically
limited to about VS − 200mV. The same applies to OUT18,
which typically limits at GND + 200mV when sinking
10mA. An increase in output swing can only be achieved
for much lighter loads. For example, a 3mA load typically
allows the swing to be increased to approximately VS −
100mV and GND + 100mV.
BUF20800
VCOM OUT1
VCOM
VCOM OUT2
Connecting REFH directly to VS and REFL directly to GND
does not damage the BUF20800. As discussed above
however, the output stages of the REFH and REFL buffers
will saturate. This condition is not desirable and can result
in a small error in the measured output voltages of
OUT1−18, VCOM1, and VCOM2. As described above, this
method of connecting REFH and REL does not help to
maximize the output swing capability.
OUT1
OUT2
Gamma
References
OUT17
OUT18
18
17
16
SDA
REFH OUT (sourcing), Code = 3FFh
15
Control Interface
SCL
V
REFL = 1V, VREFH = 17.8V
RLOAD Connected to GND
3
2
1
0
REFL OUT (sinking), Code = 000h
REFL = 0.2V, VREFH = 17V
RLOAD Connected to 18V
V
0
10
20
30
40
50
60
70
80
90
100
Output Current (mA)
Figure 12. BUF20800 Used for Programmable
Figure 13. Reference Buffer Output Voltage vs
Output Current
V
COM
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CONFIGURATION FOR 20 GAMMA CHANNELS
15V
2V−5.5V
14.8V
The VCOM outputs can be used as additional gamma
references in order to achieve two additional gamma
channels (20 total). The VCOM outputs will behave the
same as the OUT1−9 outputs when sourcing or sinking
smaller currents (see the Typical Characteristics,
Figure 4). The VCOM outputs are better able to swing to the
positive rail than to the negative rail. Therefore, it is better
to use the VCOM outputs for higher reference voltages, as
shown in Figure 14.
REFH
Digital
BUF20800
Analog
REFH OUT
14.8V
Source
Driver
VCO M OUT1
GMA 1
GMA 2
VCO M OUT2
CONFIGURATION FOR 22 GAMMA
CHANNELS
OUT1
OUT2
In addition to the VCOM outputs, the REFH and REFL OUT
outputs can also be used as fixed gamma references. The
output voltage will be set by the REFH and REFL input
voltages, respectively. Therefore, REFH OUT should be
used for the highest voltage gamma reference, and REFL
OUT for the lowest voltage gamma reference. A
22-channel solution can be created by using all 18 outputs,
the two VCOM outputs, and both REFH/L OUT outputs for
gamma references—see Figure 15. However, the REFH
and REFL OUT buffers were designed to only drive light
loads on the order of 5−10mA. Driving capacitive loads is
not recommended with these buffers. In addition, the
REFH and REFL buffers must not be allowed to saturate
from sourcing/sinking too much current from REFH OUT
or REFL OUT. Saturation of the REFH and REFL buffers
results in errors in the voltages of OUT1−18 and VCOM
OUT1−2. The BUF01900 can be used to provide a
programmable VCOM output.
GMA 3
GMA 4
18 Gamma Channels
OUT17
OUT18
GMA 19
GMA 20
REFL OUT
0.2V
SDA
SCL
Control IF
A0
REFL
LD
15V
0.2V
Figure 14. 20 Gamma Channel Solution −
Two V Channels Used as
COM
Additional Gamma Channels
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18V
Reference buffer
and V OUT
outputs can be used
COM
17.8V
2V−5.5V
for extra gamma channels.
(REFH OUT
will be a
fixed voltage.)
Digital
BUF20800
Analog
REFH
Source
Driver
REFH OUT
17V
GMA 1
V
V
OUT 1
OUT 2
COM
COM
GMA 2
GMA 3
OUT1
OUT2
GMA 4
GMA 5
2 V
Channels plus
COM
18 Output Channels
OUT17
OUT18
GMA 20
GMA 21
GMA 22
Panel
REFL OUT
0.2V
SDA
SCL
Control IF
LD
A0
REFL
Output of reference
buffer can be used
for an extra fixed
gamma channel
18V
0.2V
V
COM
18V
2V−5.5V
Digital
Analog
BIAS
(1)
BUF01900
Voltage Regulator
V
4 x OTP
ROM
COM
Switch
Control
10−Bit
DAC
Buffer
V
OUT
COM
SDA
SCL
Control IF
A0
NOTE: (1) Expected availability is Q4’ 06.
Figure 15. 22-Channel Gamma Solution
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a picture is still being displayed. Because the data are only
stored into the first register bank, the DAC output values
remain unchanged—the display is unaffected. During the
vertical sync period, the DAC outputs (and therefore, the
gamma voltages) can be quickly updated either by using
an additional control line connected to the LD pin, or
through software—writing a ‘1’ in bit 15 of any DAC
register. For the details on the operation of the double
register input structure, see the Output Latch section.
DYNAMIC GAMMA CONTROL
Dynamic gamma control is a technique used to improve
the picture quality in LCD TV applications. The brightness
in each picture frame is analyzed and the gamma curves
are adjusted on a frame-by-frame basis. The gamma
curves are typically updated during the short vertical
blanking period in the video signal. Figure 16 shows a
block diagram using the BUF20800 for dynamic gamma
control and VCOM output.
The BUF20800 is ideally suited for rapidly changing the
gamma curves because of its unique topology:
Example: Update all 18 gamma registers simultaneously
via software.
D
D
D
double register input structure to the DAC;
fast serial interface;
Step 1: Check if LD pin is placed in HIGH state.
Step 2: Write DAC Registers 1−18 with bit 15 always ‘0’.
simultaneous updating of all DACs by software. See
the Read/Write Operations to write to all registers and
the Output Latch sections.
Step 3: Write any DAC register a second time with identi-
cal data. Make sure that bit 15 is ‘1’. All DAC channels will
be updated simultaneously after receiving the last bit of
data. (Note: this step may be eliminated by setting bit 15
of DAC 18 to ‘1’ in the previous step.)
The double register input structure saves programming
time by allowing updated DAC values to be pre-loaded into
the first register bank. Storage of this data can occur while
Histogram
SDA
Gamma
Adjustment
Algorithm
Digital
Picture
Data
BUF20800
Gamma References
SCL
Black
White
1 through 18
µ
Timing Controller/ Controller
Source Driver
Source Driver
VCOM
Figure 16. Dynamic Gamma Control
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outputs, and other functions. The BUF20800, with its 20
total programmable DAC channels, provides great
flexibility to the entire system by allowing the designer to
change all these parameters via software.
TOTAL TI PANEL SOLUTION
In addition to the BUF20800 programmable voltage
reference, TI offers a complete set of ICs for the LCD panel
market, including gamma correction buffers, various
power-supply solutions, and audio power solutions. See
Figure 17 for the total IC solution from TI.
Figure 18 provides various ideas on how the BUF20800
can be used in applications. A micro-controller with
two-wire serial interface controls the various DACs of the
BUF20800. The BUF20800 can be used for:
THE BUF20800 IN INDUSTRIAL
APPLICATIONS
D
D
D
D
D
D
sensor excitation
The wide supply range, high output current, and very low
cost make the BUF20800 attractive for a range of medium
accuracy industrial applications such as programmable
power supplies, multi-channel data-acquisition systems,
data loggers, sensor excitation and linearization,
power-supply generation, and other uses. Each DAC
channel features 1LSB DNL and INL.
programmable bias/reference voltages
variable power-supplies
high-current voltage output
4-20mA output
set-point generators for control loops.
Many systems require different levels of biasing and power
supply for various components as well as sensor
excitation, control-loop set-points, voltage outputs, current
NOTE: The output voltages of the BUF20800 DACs will be set
to (V
− V )/2 at power-up or reset.
REFL
REFH
VCOM
Gamma Correction
BUF20800
15V
26V
TPS651xx
LCD
2.7V−5V
Supply
−
14V
3.3V
TPA3005D2
TPA3008D2
Audio
n
n
Speaker
Driver
Source Driver
Logic and
Timing
Controller
High−Resolution
TFT−LCS Panel
Figure 17. TI LCD Solution
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+18V
+5V
BUF20800
0.3V to 17V
Voltage
Output
+5V
High Current
Voltage Output
2V to 16V, 100mA
Sensor Excitation/Linearization
Control Loop
Set Point
4−20mA
+5V
Bias Voltage
Generator
4−20mA
Generator
+2.5V Bias
LED Driver
Offset
INA
Adjustment
Ref
+4V
+4.3V
Comparator
Threshold
Supply Voltage
Generator
Ref
+7.5V
Reference
for MDAC
SDA
SCL
MDAC
µ
C
Figure 18. Industrial Applications for the BUF20800
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Figure 19). Configurations can be quickly evaluated to
determine optimal codes for a given application. Contact
your local TI representative for more information regarding
the evaluation board.
EVALUATION BOARD AND SOFTWARE
An evaluation board is available for the BUF20800. The
evaluation board features easy-to-use software that
allows individual channel voltages to be set (see
Figure 19. Evaluation Board
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3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the BUF20800
IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can
be larger because they are not in the thermal pad area
to be soldered; thus, wicking is not a problem.
GENERAL POWERPAD DESIGN
CONSIDERATIONS
The BUF20800 is available in a thermally-enhanced
PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted, as
shown in Figure 20(a) and Figure 20(b). This arrangement
results in the lead frame being exposed as a thermal pad
on the underside of the package; see Figure 20(c). This
thermal pad has direct thermal contact with the die; thus,
excellent thermal performance is achieved by providing a
good thermal path away from the thermal pad.
4. Connect all holes to the internal plane that is at the
same voltage potential as the GND pins.
5. When connecting these holes to the internal plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the BUF20800
PowerPAD package should make their connection to
the internal plane with a complete connection around
the entire circumference of the plated-through hole.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a
ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board
(PCB) is always required, even with applications that
have low power dissipation. This provides the
necessary thermal and mechanical connection between
the lead frame die pad and the PCB.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its ten
holes exposed. The bottom-side solder mask should
cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the
thermal pad area during the reflow process.
The PowerPAD must be connected to the most negative
supply voltage on the device, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There
should be etching for the leads as well as etch for the
thermal pad.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
2. Place recommended holes in the area of the thermal
pad. Ideal thermal land size and thermal via patterns
(2x5) can be seen in the technical brief, PowerPAD
Thermally-Enhanced Package (SLMA002), available
for download at www.ti.com. These holes should be
13 mils (0.330mm) in diameter. Keep them small, so
that solder wicking through the holes is not a problem
during reflow.
8. With these preparatory steps in place, the BUF20800
IC is simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This preparation results in
a properly installed part.
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DIE
Side View (a)
DIE
Thermal
Pad
End View (b)
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 20. Views of Thermally-Enhanced DCP Package
For a given qJA, the maximum power dissipation is shown
in Figure 21, and is calculated by Equation 3:
6
5
4
3
2
1
0
TMAX * TA
qJA
P + ǒ Ǔ
D
(3)
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (125°C)
TA = free-ambient air temperature (°C)
−
−
20
40
0
20
40
60
80
100
_
TA, Free−Air Temperature ( C)
qJA = qJC + qCA
Figure 21. Maximum Power Dissipation vs
Free-Air Temperature
qJC = thermal coefficient from junction-to-case (°C/W)
qCA = thermal coefficient from case-to-ambient air (°C/W)
(with PowerPAD soldered down)
22
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BUF20800AIDCPR
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 95
BUF20800
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF BUF20800 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Automotive: BUF20800-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF20800AIDCPR
HTSSOP DCP
38
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DCP 38
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
BUF20800AIDCPR
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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