CAVCB164245MDGGEP [TI]
具有可配置转换和三态输出的增强型产品 16 位双电源总线收发器 | DGG | 48 | -55 to 125;
| 型号： | CAVCB164245MDGGEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可配置转换和三态输出的增强型产品 16 位双电源总线收发器 | DGG | 48 | -55 to 125 总线收发器 |
| 文件： | 总21页 (文件大小：1266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVCB164245-EP
www.ti.com.cn
ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
16 位双电源总线收发器
此收发器具有可配置电压转换和 3 态输出
查询样品: SN74AVCB164245-EP
1
特性
2
•
德州仪器 (TI) Widebus™ 系列
•
•
锁断性能超过 100mA（符合 JESD 78，II 类规范
的要求）
•
DOC™ 电路产品成员动态改变输出阻抗，从而在
不降低速度的情况下达到降噪的目的。
静电放电 (ESD) 保护性能超过 JESD 22 规范要求
•
动态驱动能力与 2.5V VCC时 IOH和 IOL为 ±24mA 的
标准输出等效
–
–
–
2000V 人体模型 (A114-A)
200V 机器模型 (A115-A)
750V 充电器件模型 (C101)
•
•
控制输入 VIH和 VIL电平以 VCCB电压为基准
如果任何一个 VCC输入接地 (GND)，那么两个端口
都处于高阻抗状态
支持国防、航空航天、和医疗应用
•
•
•
过压耐受输入和输出可实现混合电压模式数据通信
•
•
•
•
•
•
•
受控基线
I
关闭支持部分断电模式运行
一个组装和测试场所
一个制造场所
完全可配置双电源轨设计可使每个端口在整个
1.4V-3.6V 电源电压范围内运行
(1)
军用（-55°C 至 125°C）温度范围内可用
延长的产品生命周期
延长的产品变更通知
产品可追溯性
(1) 可定制工作温度范围
说明
这个 16 位（双八进制）非反相总线收发器使用两个独立的可配置电源轨。
A 端口被设计用于跟踪 VCCA。 VCCA可接受从 1.4V 到 3.6V 范围内的任一电源电压。B 端口被设计用于跟踪
CCB。 VCCB可接受从 1.4 至 3.6V 间的任一电源电压值。这可实现 1.5V，1.8V，2.5V和 3.3V 电压节点间的通用低
V
压双向转换。
SN74AVCB164245 被设计用来实现数据总线间的异步通信。 根据方向控制 (DIR) 输入上的逻辑电平，此器件将数
据从 A 总线发送至 B 总线，或者将数据从 B 总线发送至 A 总线。 输出使能 (OE) 可被用来禁用输出，这样可有效
隔离总线。
SN74AVCB164245 的设计方式决定了控制引脚（1DIR，2DIR，1OE和 2OE）由 VCCB供电。
为了确保加电或断电期间的高阻抗状态，OE应通过一个上拉电阻器连接至 VCC；该电阻器的最小值由驱动器的电
流吸收能力来决定。
该器件完全符合使用 I关闭的部分断电应用的规范要求。 I关闭电路禁用输出，从而可防止其断电时破坏性电流从该器
件回流。 如果任何一个 VCC输入接地 (GND)，那么两个端口都处于高阻抗状态。
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE
ORDERABLE PART NUMBER
CAVCB164245MDGGREP
CAVCB164245MDGGEP
TOP-SIDE MARKING
VID NUMBER
V62/13602-01XE
V62/13602-01XE-T
Reel of 2000
Tube of 40
–55°C to 125°C
TSSOP-DGG
AVCB164245M
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Widebus, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SCES845
SN74AVCB164245-EP
ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
TERMINAL ASSIGNMENTS
DGG PACKAGE
(TOP VIEW)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
4
5
6
7
V
V
CCA
CCB
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CCA
CCB
2B5
2B6
2A5
2A6
GND
2A7
2A8
2OE
GND
2B7
2B8
2DIR
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
2
Copyright © 2013, Texas Instruments Incorporated
SN74AVCB164245-EP
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ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
1B1
2OE
2B1
36
47
1A1
2A1
2
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VCCA
Supply voltage range
VCCB
–0.5
4.6
V
I/O ports (A port)
–0.5
–0.5
–0.5
–0.5
–0.5
4.6
4.6
4.6
4.6
4.6
VI
Input voltage range(2)
I/O ports (B port)
Control inputs
A port
V
Voltage range applied to any output in the high-impedance or power-off
state(2)
VO
VO
V
V
B port
A port
–0.5 VCCA + 0.5
Voltage range applied to any output in the high or low state(2) (3)
B port
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
°C
Output clamp current
VO < 0
Continuous output current
±50
Continuous current through VCCA, VCCB, or GND
Maximum junction temperature
Storage temperature range
±100
150
TJ
Tstg
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
Copyright © 2013, Texas Instruments Incorporated
3
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UNITS
THERMAL INFORMATION
SN74AVCB164245
THERMAL METRIC(1)
DGG
48 PINS
59.9
θJA
Junction-to-ambient thermal resistance(2)
θJCtop
θJB
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
13.9
27.1
°C/W
ψJT
0.5
ψJB
26.8
θJCbot
N/A
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
(5) 结至顶部特征参数， ψJT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参
数以便获得 θJA
(6) 结至电路板特征参数， ψJB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI
标准 G30-88 中能找到内容接近的说明。
空白
4
Copyright © 2013, Texas Instruments Incorporated
SN74AVCB164245-EP
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ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
RECOMMENDED OPERATING CONDITIONS(1)(2)(3)
TA = −55°C to 125°C, over recommended input voltage range (unless otherwise noted)
VCCI
VCCO
MIN
MAX UNIT
VCCA
VCCB
Supply voltage
Supply voltage
1.4
3.6
3.6
V
V
1.4
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
VCCI × 0.65
VIH
VIL
VIH
VIL
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
1.7
2
V
V
V
V
VCCI × 0.35
0.7
0.8
VCCB × 0.65
Control inputs
(referenced to VCCB
1.7
2
)
)
VCCB × 0.35
Control inputs
(referenced to VCCB
0.7
0.8
3.6
VCCO
3.6
–2
VI
Input voltage
0
0
0
V
V
Active state
3-state
VO
Output voltage
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
–4
IOH
High-level output current
Low-level output current
mA
mA
–8
–12
2
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
4
IOL
8
12
Δt/Δv Input transition rise or fall rate
TA Operating free-air temperature
(1) VCCI is the VCC associated with the data input port.
(2) VCCO is the VCC associated with the data output port.
5
ns/V
°C
–55
125
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2013, Texas Instruments Incorporated
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SN74AVCB164245-EP
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ELECTRICAL CHARACTERISTICS(1)(2)
TA = −55°C to 125°C, over recommended input voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
VCCO – 0.2
1.05
TYP(3)
MAX
UNIT
IOH = –100 μA
VI = VIH
VI = VIH
VI = VIH
VI = VIH
VI = VIH
VI = VIL
VI = VIL
VI = VIL
VI = VIL
VI = VIL
1.4 V to 3.6 V 1.4 V to 3.6 V
IOH = –2 mA
IOH = –4 mA
IOH = –8 mA
IOH = –12 mA
IOH = 100 μA
IOH = 2 mA
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
VOH
1.2
V
1.7
2.2
1.4 V to 3.6 V 1.4 V to 3.6 V
0.2
1.4 V
1.65 V
2.3 V
3 V
1.4 V
1.65 V
2.3 V
3 V
0.35
0.45
VOL
IOH = 4 mA
V
IOH = 8 mA
0.6
0.75
±2.5
±10
±10
±12.5
±12.5
±12.5
35
IOH = 12 mA
VI = VCCB or GND
II
Control inputs
1.4 V to 3.6 V
0 V
3.6 V
0 to 3.6 V
0 V
μA
μA
A port
Ioff
VI or VO = 0 to 3.6 V
B port
0 to 3.6 V
3.6 V
0 V
A or B ports
B port
OE = VIH
3.6 V
3.6 V
0 V
VO = VCCO or GND,
VI = VCCI or GND
(4)
IOZ
μA
OE = don't care
A port
3.6 V
1.6 V
1.95 V
2.7 V
0 V
1.6 V
1.95 V
2.7 V
3.6 V
0 V
35
45
ICCA
VI = VCCI or GND,
IO = 0
μA
-50
50
3.6 V
3.6 V
1.6 V
1.95 V
2.7 V
0 V
3.6 V
1.6 V
1.95 V
2.7 V
3.6 V
0 V
50
35
35
45
ICCB
VI = VCCI or GND,
IO = 0
μA
50
3.6 V
3.6 V
3.3 V
3.3 V
-50
50
3.6 V
3.3 V
3.3 V
Ci
Control inputs
A or B ports
VI = 3.3 V or GND
VO = 3.3 V or GND
4
5
pF
pF
Cio
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
(3) All typical values are at TA = 25°C.
(4) For I/O ports, the parameter IOZ includes the input leakage current.
6
Copyright © 2013, Texas Instruments Incorporated
SN74AVCB164245-EP
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ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
1000000
100000
10000
1000
WB Voiding Fail Mode
100
80
90
100
110
120
130
140
150
160
Junction Temperature, TJ (°C)
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
Figure 2. SN74AVCB164245-EP Operating Life Derating Chart
Copyright © 2013, Texas Instruments Incorporated
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ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
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Switching Characteristics
TA = −40°C to 85°C, VCCA = 1.5 V ± 0.1 V (see )
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.7
1.8
2.5
2.1
2.2
2.1
MAX
6.7
6.8
8.4
9
MIN
1.9
2.2
2.4
2.9
2.3
2.3
MAX
6.3
7.4
7.4
9.8
6.1
6.4
MIN
1.8
2.1
2.1
3.2
1.3
1.7
MAX
5.5
7.6
5.2
10
MIN MAX
A
B
B
A
A
B
A
B
1.7
2.1
1.9
3
5.8
7.3
4.2
9.8
3
tpd
ten
tdis
ns
ns
ns
OE
OE
6.9
7.1
3.6
5.1
1.3
1.6
4.8
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 1.5 V ± 0.1 V (see Figure 4)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
A
B
B
A
A
B
A
B
12.7
12.8
14.8
15
12.3
13.4
13.9
15.8
12.1
12.4
11.5
13.6
12.4
16
11.8
13.3
11.9
15.8
9
tpd
ten
tdis
ns
ns
ns
OE
OE
12.9
13.1
9.6
11.1
10.8
Switching Characteristics
TA = −40°C to 85°C, VCCA = 1.8 V ± 0.15 V (see )
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.7
1.4
2.6
1.8
2.3
1.8
MAX
6.7
5.5
8.5
7.6
7
MIN
1.8
1.8
2.5
2.6
2.3
2.5
MAX
6
MIN
1.7
1.8
2.2
2.6
1.3
1.8
MAX
4.7
5.8
5.3
7.6
3.6
4.7
MIN
1.6
1.8
1.9
2.6
1.3
1.7
MAX
4.3
5.5
4.2
7.4
3
A
B
B
A
A
B
A
B
tpd
ten
tdis
ns
ns
ns
6
7.5
7.7
6.1
6.3
OE
OE
7
4.4
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 1.8 V ± 0.15 V (see Figure 4)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
A
B
B
A
A
B
A
B
12.7
11.5
14.5
13.6
13
12
12
10.7
11.8
12.1
13.6
9.6
10.3
11.5
11.9
13.4
9
tpd
ten
tdis
ns
ns
ns
13.5
13.7
12.1
12.3
OE
OE
13
10.7
10.4
8
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SN74AVCB164245-EP
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ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
Switching Characteristics
TA = −40°C to 85°C, VCCA = 2.5 V ± 0.2 V (see )
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.6
1.3
3.1
1.7
2.4
1.2
MAX
6
MIN
1.8
1.7
2.5
2.2
3
MAX
5.6
4.4
7.5
5.5
6.1
5
MIN
1.5
1.5
2.2
2.2
1.4
1.4
MAX
4
MIN
1.4
1.4
1.9
2.2
1.2
1.3
MAX
3.4
3.7
4.2
5.1
3
A
B
B
A
A
B
A
B
tpd
ten
tdis
ns
ns
ns
4.6
8.5
5.7
7
4
5.3
5.3
3.6
3.6
OE
OE
5.8
1.9
3.3
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 2.5 V ± 0.2 V (see Figure 4)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
A
B
B
A
A
B
A
B
12
10.6
14.5
11.7
13
11.6
10.4
13.5
11.5
12.1
11
10
10
9.4
9.7
10.2
11.1
9
tpd
ten
tdis
ns
ns
ns
11.3
11.3
9.6
OE
OE
11.8
9.6
9.3
Switching Characteristics
TA = −40°C to 85°C, VCCA = 3.3 V ± 0.3 V (see )
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.3
2.6
1.6
2.3
1.3
MAX
5.9
4.5
8.3
4.9
7
MIN
1.7
1.6
2.5
2
MAX
5.4
3.8
7.4
4.5
6
MIN
1.5
1.5
2.2
2
MAX
3.7
3.3
5.2
4.3
3.5
3.8
MIN
1.4
1.4
1.9
1.9
1.2
1.5
MAX
3.1
3.1
4.1
4.1
3.5
3.5
A
B
B
A
A
B
A
B
tpd
ten
tdis
ns
ns
ns
OE
OE
3
1.3
1.6
6.9
2.1
5.5
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 3.3 V ± 0.3 V (see Figure 4)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
A
B
B
A
A
B
A
B
11.9
10.5
14.3
11.3
13
11.4
9.8
9.7
9.3
9.1
9.1
tpd
ten
tdis
ns
ns
ns
13.4
10.5
12
11.2
10.3
9.5
10.1
10.1
9.5
OE
OE
12.9
11.5
9.8
9.5
Copyright © 2013, Texas Instruments Incorporated
9
SN74AVCB164245-EP
ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
OPERATING CHARACTERISTICS
VCCA and VCCB = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
14
7
Power dissipation capacitance per transceiver,
A-port input, B-port output
CpdA
(VCCA
CL = 0,
f = 10 MHz
f = 10 MHz
pF
)
)
20
7
Power dissipation capacitance per transceiver,
B-port input, A-port output
20
7
Power dissipation capacitance per transceiver,
A-port input, B-port output
CpdB
(VCCB
CL = 0,
pF
14
7
Power dissipation capacitance per transceiver,
B-port input, A-port output
OUTPUT DESCRIPTION
The DOC™ circuitry is implemented, which, during the transition, initially lowers the output impedance to
effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs
IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of
the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive
standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology
and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and
Applications, literature number SCEA009.
3.2
T
A
= 25°C
T
A
= 25°C
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
CC
= 3.3 V
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
0
17
34
51
68
85 102 119 136 153 170
−160 −144 −128 −112 −96 −80 −64 −48 −32 −16
− Output Current − mA
0
I
− Output Current − mA
I
OH
OL
Figure 3. Typical Output Voltage vs Output Current
10
Copyright © 2013, Texas Instruments Incorporated
SN74AVCB164245-EP
www.ti.com.cn
ZHCSB16A –JANUARY 2013–REVISED FEBRUARY 2013
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
/t
PLZ PZL
2 × V
CCO
t
/t
PHZ PZH
GND
C
L
R
L
(see Note A)
t
LOAD CIRCUIT
w
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.5 V 0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
15 pF
30 pF
30 pF
30 pF
500 Ω
500 Ω
500 Ω
500 Ω
VOLTAGE WAVEFORMS
PULSE DURATION
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
V
CCB
Output
Control
(low-level
enabling)
V
/2
V
CCB
/2
t
CCB
0 V
t
t
PZL
PLZ
V
V
CCO
Output
V
CCI
V
/2
/2
Waveform 1
S1 at 2 × V
CCO
Input
V
CCI
/2
V
CCI
/2
V
OL
+ V
TP
CCO
OL
0 V
(see Note B)
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
t
t
and t
and t
are the same as t .
dis
are the same as t .
PLZ
PZL
PLH
PHZ
PZH
en
G.
H.
I.
and t
are the same as t .
PHL pd
V
V
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CC
CCO
Figure 4. Load Circuit and Voltage Waveforms
Copyright © 2013, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CAVCB164245MDGGEP
CAVCB164245MDGGREP
V62/13602-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
DGG
48
48
48
48
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
AVCB164245M
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
AVCB164245M
AVCB164245M
AVCB164245M
V62/13602-01XE-T
40
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CAVCB164245MDGGRE TSSOP
P
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
CAVCB164245MDGGREP
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
CAVCB164245MDGGEP
V62/13602-01XE-T
DGG
DGG
TSSOP
TSSOP
48
48
40
40
530
530
11.89
11.89
3600
3600
4.9
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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