CC1070DK-915 [TI]
Single Chip Low Power RF Transceiver for Narrowband Systems; 单芯片低功耗RF收发器窄带系统
| 型号： | CC1070DK-915 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single Chip Low Power RF Transceiver for Narrowband Systems |
| 文件： | 总91页 (文件大小：971K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC1020
CC1020 Single Chip Low Power RF Transceiver for Narrowband Systems
Applications
• Narrowband low power UHF wireless
data transmitters and receivers with
channel spacings as low as 12.5 and
25 kHz
• 402 / 424 / 426 / 429 / 433 / 447 / 449 /
469 / 868 and 915 MHz ISM/SRD
band systems
• AMR – Automatic Meter Reading
• Wireless alarm and security systems
• Home automation
• Low power telemetry
Product Description
CC1020 is a true single-chip UHF trans-
ceiver designed for very low power and
very low voltage wireless applications. The
circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 402, 424, 426, 429, 433, 447,
449, 469, 868 and 915 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 -
470 and 804 - 940 MHz range.
making CC1020 a very flexible and easy to
use transceiver.
In a typical system CC1020 will be used
together with a microcontroller and a few
external passive components.
CC1020 is based on Chipcon’s SmartRF®-
02 technology in 0.35 µm CMOS.
The CC1020 is especially suited for narrow-
band systems with channel spacings of
12.5 or 25 kHz complying with ARIB STD
T-67 and EN 300 220.
The CC1020 main operating parameters
can be programmed via a serial bus, thus
Features
• True single chip UHF RF transceiver
• Frequency range 402 MHz - 470 MHz
and 804 MHz - 940 MHz
• Data rate up to 153.6 kBaud
• OOK, FSK and GFSK data modulation
• Integrated bit synchronizer
• High sensitivity (up to –118 dBm for a
12.5 kHz channel)
• Programmable output power
• Low current consumption (RX: 19.9
mA)
• Image rejection mixer
• Programmable frequency and AFC
make
crystal
temperature
drift
compensation possible without TCXO
• Suitable for frequency hopping systems
• Low supply voltage (2.3 V to 3.6 V)
• No external IF filter needed
• Low-IF receiver
• Very few external components required
• Small size (QFN 32 package)
• Pb-free package
• Suited
for
systems
targeting
compliance with EN 300 220, FCC
CFR47 part 15 and ARIB STD T-67
• Development kit available
• Easy-to-use software for generating the
CC1020 configuration data
• Digital RSSI and carrier sense indicator
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CC1020
Table of Contents
1.
2.
3.
4.
Abbreviations................................................................................................................ 4
Absolute Maximum Ratings......................................................................................... 5
Operating Conditions................................................................................................... 5
Electrical Specifications .............................................................................................. 5
4.1. RF Transmit Section ............................................................................................ 6
4.2. RF Receive Section ............................................................................................. 8
4.3. RSSI / Carrier Sense Section ............................................................................ 11
4.4. IF Section........................................................................................................... 11
4.5. Crystal Oscillator Section................................................................................... 12
4.6. Frequency Synthesizer Section......................................................................... 13
4.7. Digital Inputs / Outputs....................................................................................... 14
4.8. Current Consumption......................................................................................... 15
Pin Assignment........................................................................................................... 15
Circuit Description...................................................................................................... 17
Application Circuit...................................................................................................... 18
Configuration Overview ............................................................................................. 21
8.1. Configuration Software ...................................................................................... 21
Microcontroller Interface............................................................................................ 22
9.1. 4-wire Serial Configuration Interface ................................................................. 23
9.2. Signal Interface.................................................................................................. 25
Data Rate Programming............................................................................................. 27
Frequency Programming ........................................................................................... 28
5.
6.
7.
8.
9.
10.
11.
11.1.
Dithering......................................................................................................... 29
12.
Receiver....................................................................................................................... 30
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
12.8.
12.9.
IF Frequency .................................................................................................. 30
Receiver Channel Filter Bandwidth................................................................ 30
Demodulator, Bit Synchronizer and Data Decision........................................ 31
Receiver Sensitivity versus Data Rate and Frequency Separation ............... 32
RSSI............................................................................................................... 33
Image Rejection Calibration........................................................................... 35
Blocking and Selectivity ................................................................................. 36
Linear IF Chain and AGC Settings................................................................. 37
AGC Settling................................................................................................... 38
12.10. Preamble Length and Sync Word .................................................................. 39
12.11. Carrier Sense ................................................................................................. 39
12.12. Automatic Power-up Sequencing................................................................... 40
12.13. Automatic Frequency Control......................................................................... 41
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CC1020
12.14. Digital FM ....................................................................................................... 42
13.
Transmitter.................................................................................................................. 43
13.1.
13.2.
13.3.
13.4.
FSK Modulation Formats ............................................................................... 43
Output Power Programming........................................................................... 45
TX Data Latency............................................................................................. 46
Reducing Spurious Emission and Modulation Bandwidth.............................. 46
14.
15.
Input / Output Matching and Filtering....................................................................... 46
Frequency Synthesizer .............................................................................................. 50
15.1.
15.2.
15.3.
15.4.
VCO, Charge Pump and PLL Loop Filter....................................................... 50
VCO and PLL Self-Calibration ....................................................................... 51
PLL Turn-on Time versus Loop Filter Bandwidth........................................... 52
PLL Lock Time versus Loop Filter Bandwidth................................................ 53
16.
17.
18.
19.
20.
21.
VCO and LNA Current Control .................................................................................. 53
Power Management.................................................................................................... 54
On-Off Keying (OOK).................................................................................................. 57
Crystal Oscillator........................................................................................................ 58
Built-in Test Pattern Generator ................................................................................. 59
Interrupt on Pin DCLK................................................................................................ 60
21.1.
21.2.
Interrupt upon PLL Lock................................................................................. 60
Interrupt upon Received Signal Carrier Sense .............................................. 60
22.
PA_EN and LNA_EN Digital Output Pins ................................................................. 61
22.1.
22.2.
22.3.
Interfacing an External LNA or PA ................................................................. 61
General Purpose Output Control Pins............................................................ 61
PA_EN and LNA_EN Pin Drive...................................................................... 61
23.
24.
25.
26.
System Considerations and Guidelines................................................................... 62
PCB Layout Recommendations................................................................................ 64
Antenna Considerations ............................................................................................ 65
Configuration Registers............................................................................................. 65
26.1.
CC1020 Register Overview............................................................................ 66
27.
Package Description (QFN 32) .................................................................................. 86
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
Package Marking............................................................................................ 87
Recommended PCB Footprint for Package (QFN 32)................................... 88
Package Thermal Properties.......................................................................... 88
Soldering Information..................................................................................... 88
Plastic Tube Specification.............................................................................. 89
Carrier Tape and Reel Specification .............................................................. 89
28.
29.
Ordering Information.................................................................................................. 89
General Information.................................................................................................... 90
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CC1020
30.
Address Information................................................................................................... 92
1.
Abbreviations
ACP
ACR
ADC
AFC
AGC
AMR
ASK
BER
BOM
bps
Adjacent Channel Power
Adjacent Channel Rejection
Analog-to-Digital Converter
Automatic Frequency Control
Automatic Gain Control
Automatic Meter Reading
Amplitude Shift Keying
Bit Error Rate
Bill Of Materials
bits per second
BT
ChBW
CW
Bandwidth-Time product (for GFSK)
Receiver Channel Filter Bandwidth
Continuous Wave
DAC
DNM
ESR
FHSS
FM
Digital-to-Analog Converter
Do Not Mount
Equivalent Series Resistance
Frequency Hopping Spread Spectrum
Frequency Modulation
Frequency Synthesizer
Frequency Shift Keying
Gaussian Frequency Shift Keying
Integrated Circuit
FS
FSK
GFSK
IC
IF
IP3
Intermediate Frequency
Third Order Intercept Point
Industrial Scientific Medical
kilo bits per second
Low Noise Amplifier
Local Oscillator (in receive mode)
Micro Controller Unit
Non Return to Zero
On-Off Keying
Power Amplifier
ISM
kbps
LNA
LO
MCU
NRZ
OOK
PA
PD
Phase Detector / Power Down
Packet Error Rate
Printed Circuit Board
Pseudo-random Bit Sequence (9-bit)
Phase Locked Loop
Program Select
PER
PCB
PN9
PLL
PSEL
RF
Radio Frequency
RSSI
RX
Received Signal Strength Indicator
Receive (mode)
SBW
SPI
SRD
TBD
T/R
Signal Bandwidth
Serial Peripheral Interface
Short Range Device
To Be Decided/Defined
Transmit/Receive (switch)
Transmit (mode)
TX
UHF
VCO
VGA
XOSC
XTAL
Ultra High Frequency
Voltage Controlled Oscillator
Variable Gain Amplifier
Crystal oscillator
Crystal
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CC1020
2.
Absolute Maximum Ratings
The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Parameter
Supply voltage, VDD
Min
-0.3
Max
5.0
Unit
V
Condition
All supply pins must have the
same voltage
Voltage on any pin
Input RF level
Storage temperature range
Package body temperature
Humidity non-condensing
ESD
-0.3
-50
5
VDD+0.3, max 5.0
V
dBm
°C
°C
%
10
150
260
85
±1
±0.4
Norm: IPC/JEDEC J-STD-020C 1
kV
kV
All pads except RF
RF Pads
(Human Body Model)
Table 1. Absolute maximum ratings
1
The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD_020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devices”.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3.
Operating Conditions
The operating conditions for CC1020 are listed in Table 2.
Parameter
Min
Typ
Max
Unit
Condition / Note
RF Frequency Range
402
804
470
940
MHz
MHz
Programmable in <300 Hz steps
Programmable in <600 Hz steps
Operating ambient temperature
range
-40
2.3
85
°C
Supply voltage
3.0
3.6
V
The same supply voltage should
be used for digital (DVDD) and
analog (AVDD) power.
A 3.0 ±0.1 V supply is
recommended to meet the ARIB
STD T-67 selectivity and output
power tolerance requirements.
Table 2. Operating conditions
4.
Electrical Specifications
Table 3 to Table 10 gives the CC1020 electrical specifications. All measurements were
performed using the 2 layer PCB CC1020EMX reference design. This is the same test circuit
as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if
nothing else stated. Crystal frequency = 14.7456 MHz.
The electrical specifications given for 868 MHz are also applicable for the 902 – 928 MHz
frequency range.
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CC1020
4.1. RF Transmit Section
Parameter
Min
Typ
Max
Unit
Condition / Note
Transmit data rate
0.45
153.6
kBaud The data rate is programmable.
See section 10 on page 27 for
details.
NRZ or Manchester encoding can
be used. 153.6 kBaud equals
153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See section 9.2 on page
25 for details
Minimum data rate for OOK is 2.4
kBaud
Binary FSK frequency separation
0
0
108
216
kHz
kHz
in 402 – 470 MHz range
in 804 – 940 MHz range
108/216 kHz is the maximum
guaranteed separation at 1.84
MHz reference frequency. Larger
separations can be achieved at
higher reference frequencies.
Output power
433 MHz
Delivered to 50 Ω single-ended
load. The output power is
-20 to +10
-20 to +5
dBm
dBm
programmable and should not be
programmed to exceed +10/+5
dBm at 433/868 MHz under any
operating conditions (refer to
CC1020 Errata Note 003). See
section 14 on page 46 for details.
868 MHz
Output power tolerance
Harmonics, radiated CW
At maximum output power
At 2.3 V, +85oC
-4
+3
dB
dB
At 3.6 V, -40oC
Harmonics are measured as
EIRP values according to EN 300
220. The antenna (SMAFF-433
and SMAFF-868 from R.W.
Badland) plays a part in
2
3
nd harmonic, 433 MHz, +10 dBm
rd harmonic, 433 MHz, +10 dBm
-50
-50
dBc
dBc
2
nd harmonic, 868 MHz, +5 dBm
-50
-50
dBc
dBc
3rd harmonic, 868 MHz, +5 dBm
Adjacent channel power (GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
attenuating the harmonics.
For 12.5 kHz channel spacing
ACP is measured in a ±4.25 kHz
bandwidth at ±12.5 kHz offset.
Modulation: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
-46
-52
-49
dBc
dBc
dBc
For 25 kHz channel spacing ACP
is measured in a ±8.5 kHz
bandwidth at ±25 kHz offset.
Modulation: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
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CC1020
Parameter
Min
Typ
Max
Unit
Condition / Note
Occupied bandwidth (99.5%,GFSK)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
Bandwidth for 99.5% of total
average power.
7.5
9.6
9.6
kHz
kHz
kHz
Modulation for 12.5 channel
spacing: 2.4 kBaud NRZ PN9
sequence, ±2.025 kHz frequency
deviation.
Modulation for 25 kHz channel
spacing: 4.8 kBaud NRZ PN9
sequence, ±2.475 kHz frequency
deviation.
Modulation bandwidth, 868 MHz
Bandwidth where the power
envelope of modulation equals
–36 dBm. Spectrum analyzer
RBW = 1 kHz.
19.2 kBaud, ±9.9 kHz frequency
deviation
48
kHz
kHz
38.4 kBaud, ±19.8 kHz frequency
deviation
106
Spurious emission, radiated CW
At maximum output power,
+10/+5 dBm at 433/868 MHz.
47-74, 87.5-118,
174-230, 470-862 MHz
-54
-36
-30
dBm
dBm
dBm
To comply with EN 300 220,
FCC CFR47 part 15 and ARIB
STD T-67 an external (antenna)
filter, as implemented in the
application circuit in Figure 25,
must be used and tailored to
each individual design to reduce
out-of-band spurious emission
levels.
9 kHz – 1 GHz
1 – 4 GHz
Spurious emissions can be
measured as EIRP values
according to EN 300 220. The
antenna (SMAFF-433 and
SMAFF-868 from R.W. Badland)
plays a part in attenuating the
spurious emissions.
If the output power is increased
using an external PA, a filter must
be used to attenuate spurs below
862 MHz when operating in the
868 MHz frequency band in
Europe. Application Note AN036
CC1020/1021 Spurious Emission
presents and discusses a solution
that reduces the TX mode
spurious emission close to 862
MHz by increasing the REF_DIV
from 1 to 7.
Optimum load impedance
433 MHz
Transmit mode. For matching
details see section 14 on page
46.
54 + j44
15 + j24
20 + j35
Ω
Ω
Ω
868 MHz
915 MHz
Table 3. RF transmit parameters
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CC1020
4.2. RF Receive Section
Parameter
Min
Typ
Max
Unit
Condition / Note
Receiver Sensitivity, 433 MHz, FSK
Sensitivity is measured with PN9
sequence at BER = 10−3
12.5 kHz channel spacing, optimized
selectivity, ±2.025 kHz freq. deviation
-114
-118
-112
dBm
dBm
dBm
12.5 kHz channel spacing:
2.4 kBaud, Manchester coded
data.
12.5 kHz channel spacing, optimized
sensitivity, ±2.025 kHz freq. deviation
25 kHz channel spacing
25 kHz channel spacing:
4.8 kBaud, NRZ coded data,
±2.475 kHz frequency deviation.
500 kHz channel spacing
-96
dBm
500 kHz channel spacing:
153.6 kBaud, NRZ coded data,
±72 kHz frequency deviation.
Receiver Sensitivity, 868 MHz, FSK
See Table 19 and Table 20 for
typical sensitivity figures at other
data rates.
12.5 kHz channel spacing, ±2.475
kHz freq. deviation
-116
dBm
25 kHz channel spacing
-111
-94
dBm
dBm
500 kHz channel spacing
Receiver sensitivity, 433 MHz, OOK
Sensitivity is measured with PN9
sequence at BER = 10−3
2.4 kBaud
153.6 kBaud
-116
-81
dBm
dBm
Manchester coded data.
Receiver sensitivity, 868 MHz, OOK
See Table 27 for typical
sensitivity figures at other data
rates.
4.8 kBaud
153.6 kBaud
-107
-87
dBm
dBm
Saturation (maximum input level)
FSK and OOK
10
dBm
kHz
FSK: Manchester/NRZ coded
data
OOK: Manchester coded data
BER = 10−3
System noise bandwidth
9.6
to
307.2
The receiver channel filter 6 dB
bandwidth is programmable from
9.6 kHz to 307.2 kHz. See
section 12.2 on page 30 for
details.
Noise figure, cascaded
433 and 868 MHz
7
dB
NRZ coded data
Input IP3
Two tone test (+10 MHz and +20
MHz)
433 MHz, 12.5 kHz channel spacing
-23
-18
-16
dBm
dBm
dBm
LNA2 maximum gain
LNA2 medium gain
LNA2 minimum gain
868 MHz, 25 kHz channel spacing
-18
-15
-13
dBm
dBm
dBm
LNA2 maximum gain
LNA2 medium gain
LNA2 minimum gain
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CC1020
Parameter
Min
Typ
Max
Unit
Condition / Note
Co-channel rejection, FSK and OOK
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
Adjacent channel rejection (ACR)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
Wanted signal 3 dB above the
sensitivity level, FM jammer (1
kHz sine, ± 2.5 kHz deviation) at
operating frequency,
-11
-11
-11
dB
dB
dB
BER = 10−3
Wanted signal 3 dB above the
sensitivity level, FM jammer (1
kHz sine, ± 2.5 kHz deviation) at
adjacent channel. BER = 10−3
32
37
32
dB
dB
dB
Image channel rejection
433/868 MHz
Wanted signal 3 dB above the
sensitivity level, CW jammer at
image frequency. BER = 10−3.
No I/Q gain and phase calibration
I/Q gain and phase calibrated
26/31
49/52
dB
dB
Image rejection after calibration
will depend on temperature and
supply voltage. Refer to section
12.6 on page 35.
Selectivity*
Wanted signal 3 dB above the
sensitivity level. CW jammer is
swept in 12.5 kHz/25 kHz steps
to within ± 1 MHz from wanted
channel. BER = 10−3. Adjacent
channel and image channel are
excluded.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
41
41
39
dB
dB
dB
(*Close-in spurious response
rejection)
Blocking / Desensitization*
433/868 MHz
Wanted signal 3 dB above the
sensitivity level, CW jammer at ±
1, 2, 5 and 10 MHz offset.
± 1 MHz
± 2 MHz
± 5 MHz
± 10 MHz
50/57
64/71
64/71
75/78
dB
dB
dB
dB
BER = 10−3. 12.5 kHz/25 kHz
channel spacing at 433/868 MHz.
Complying with EN 300 220,
class 2 receiver requirements.
(*Out-of-band spurious response
rejection)
Image frequency suppression,
433/868 MHz
Ratio between sensitivity for a
signal at the image frequency to
the sensitivity in the wanted
No I/Q gain and phase calibration
I/Q gain and phase calibrated
36/41
59/62
dB
dB
channel. Image frequency is RF−
2 IF. The signal source is a 2.4
kBaud, Manchester coded data,
±2.025 kHz frequency deviation,
signal level for BER = 10−3
Spurious reception
40
dB
Ratio between sensitivity for an
unwanted frequency to the
sensitivity in the wanted channel.
The signal source is a 2.4 kBaud,
Manchester coded data, ±2.025
kHz frequency deviation, swept
over all frequencies 100 MHz – 2
GHz. Signal level for BER = 10−3
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CC1020
Parameter
Min
Typ
Max
Unit
Condition / Note
Intermodulation rejection (1)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
Intermodulation rejection (2)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
LO leakage, 433/868 MHz
Wanted signal 3 dB above the
sensitivity level, two CW jammers
at +2Ch and +4Ch where Ch is
channel spacing 12.5 kHz or 25
kHz. BER = 10−2
30
30
dB
dB
Wanted signal 3 dB above the
sensitivity level, two CW jammers
at +10 MHz and +20 MHz offset.
BER = 10−2
56
55
dB
dB
<-80/-66
-64
dBm
dBm
VCO leakage
VCO frequency resides between
1608 – 1880 MHz
Spurious emission, radiated CW
9 kHz – 1 GHz
Complying with EN 300 220,
FCC CFR47 part 15 and ARIB
STD T-67.
<-60
<-60
dBm
dBm
1 – 4 GHz
Spurious emissions can be
measured as EIRP values
according to EN 300 220.
Input impedance
433 MHz
Receive mode. See section 14 on
page 46 for details.
58 – j10
54 – j22
Ω
Ω
868 MHz
Matched input impedance, S11
433 MHz
Using application circuit matching
network. See section 14 on page
46 for details.
-14
-12
dB
dB
868 MHz
Matched input impedance
433 MHz
Using application circuit matching
network. See section 14 on page
46 for details.
39 – j14
32 – j10
Ω
Ω
868 MHz
Bit synchronization offset
8000
ppm
The maximum bit rate offset
tolerated by the bit
synchronization circuit for 6 dB
degradation (synchronous modes
only)
Data latency
Time from clocking the data on
the transmitter DIO pin until data
is available on receiver DIO pin
NRZ mode
4
8
Baud
Baud
Manchester mode
Table 4. RF receive parameters
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CC1020
4.3. RSSI / Carrier Sense Section
Parameter
Min
Typ
Max
Unit
Condition / Note
RSSI dynamic range
55
dB
dB
12.5 and 25 kHz channel spacing
RSSI accuracy
See section 12.5 on page 33 for
details.
± 3
RSSI linearity
dB
± 1
RSSI attach time
Shorter RSSI attach times can be
traded for lower RSSI accuracy.
See section 12.5 on page 33 for
details.
2.4 kBaud, 12.5 kHz channel spacing
4.8 kBaud, 25 kHz channel spacing
153.6 kBaud, 500 kHz channel spacing
3.8
1.9
140
ms
ms
µs
Shorter RSSI attach times can
also be traded for reduced
sensitivity and selectivity by
increasing the receiver channel
filter bandwidth.
Carrier sense programmable range
Adjacent channel carrier sense
12.5 kHz channel spacing
40
dB
Accuracy is as for RSSI
At carrier sense level −110 dBm,
FM jammer (1 kHz sine, ±2.5 kHz
deviation) at adjacent channel.
-72
-72
dBm
dBm
25 kHz channel spacing
Adjacent channel carrier sense is
measured by applying a signal on
the adjacent channel and observe
at which level carrier sense is
indicated.
Spurious carrier sense
-70
dBm
At carrier sense level −110 dBm,
100 MHz – 2 GHz. Adjacent
channel and image channel are
excluded.
Table 5. RSSI / Carrier sense parameters
4.4. IF Section
Parameter
Min
Typ
Max
Unit
Condition / Note
Intermediate frequency (IF)
307.2
kHz
See section 12.1 on page 30 for
details.
Digital channel filter bandwidth
AFC resolution
9.6
to
307.2
kHz
Hz
The channel filter 6 dB bandwidth
is programmable from 9.6 kHz to
307.2 kHz. See section 12.2 on
page 30 for details.
150
At 2.4 kBaud
Given as Baud rate/16. See
section 12.13 on page 41 for
details.
Table 6. IF section parameters
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CC1020
4.5. Crystal Oscillator Section
Parameter
Min
Typ
Max
Unit
Condition / Note
Crystal Oscillator Frequency
4.9152 14.7456
19.6608
MHz
Recommended frequency is
14.7456 MHz. See section 19 on
page 58 for details.
Reference frequency accuracy
requirement
+/- 5.7
+/- 2.8
ppm
ppm
433 MHz (EN 300 220)
868 MHz (EN 300 220)
Must be less than ±5.7 / ±2.8
ppm to comply with EN 300 220
25 kHz channel spacing at
433/868 MHz.
+/- 4
ppm
Must be less than ±4 ppm to
comply with Japanese 12.5 kHz
channel spacing regulations
(ARIB STD T-67).
NOTE:
The reference frequency
accuracy (initial tolerance) and
drift (aging and temperature
dependency) will determine the
frequency accuracy of the
transmitted signal.
Crystal oscillator temperature
compensation can be done using
the fine step PLL frequency
programmability and the AFC
feature. See section 12.13 on
page 41 for details.
Crystal operation
Parallel
C4 and C5 are loading
capacitors. See section 19 on
page 58 for details.
Crystal load capacitance
Crystal oscillator start-up time
12
12
12
22
16
16
30
30
16
pF
pF
pF
4.9-6 MHz, 22 pF recommended
6-8 MHz, 16 pF recommended
8-19.6 MHz, 16 pF recommended
1.55
1.0
0.90
0.95
0.60
0.63
ms
ms
ms
ms
ms
ms
4.9152 MHz, 12 pF load
7.3728 MHz, 12 pF load
9.8304 MHz, 12 pF load
14.7456 MHz, 16 pF load
17.2032 MHz, 12 pF load
19.6608 MHz, 12 pF load
External clock signal drive,
sine wave
The external clock signal must be
connected to XOSC_Q1 using a
DC block (10 nF). Set
300
mVpp
XOSC_BYPASS = 0 in the
INTERFACE register when using
an external clock signal with low
amplitude or a crystal.
External clock signal drive,
full-swing digital external clock
The external clock signal must be
connected to XOSC_Q1. No DC
block shall be used. Set
0 – VDD
V
XOSC_BYPASS = 1 in the
INTERFACE register when using
a full-swing digital external clock.
Table 7. Crystal oscillator parameters
SWRS046
Page 12 of 92
CC1020
4.6. Frequency Synthesizer Section
Parameter
Min
Typ
Max
Unit
Condition / Note
Phase noise, 402 – 470 MHz
12.5 kHz channel spacing
Unmodulated carrier
-90
dBc/Hz At 12.5 kHz offset from carrier
dBc/Hz At 25 kHz offset from carrier
dBc/Hz At 50 kHz offset from carrier
dBc/Hz At 100 kHz offset from carrier
dBc/Hz At 1 MHz offset from carrier
-100
-105
-110
-114
Measured using loop filter
components given in Table 13.
The phase noise will be higher for
larger PLL loop filter bandwidth.
Phase noise, 804 – 940 MHz
25 kHz channel spacing
Unmodulated carrier
-85
-95
-101
-109
-118
dBc/Hz At 12.5 kHz offset from carrier
dBc/Hz At 25 kHz offset from carrier
dBc/Hz At 50 kHz offset from carrier
dBc/Hz At 100 kHz offset from carrier
dBc/Hz At 1 MHz offset from carrier
Measured using loop filter
components given in Table 13.
The phase noise will be higher for
larger PLL loop filter bandwidth.
PLL loop bandwidth
After PLL and VCO calibration.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
PLL lock time (RX / TX turn time)
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
2.7
8.3
kHz
kHz
The PLL loop bandwidth is
programmable.
307.2 kHz frequency step to RF
frequency within ±10% of channel
spacing. Depends on loop filter
component values and PLL_BW
register setting. See Table 26 on
page 53 for more details.
900
640
14
us
us
us
PLL turn-on time. From power down
mode with crystal oscillator running.
Time from writing to registers to
RF frequency within ±10% of
channel spacing. Depends on
loop filter component values and
PLL_BW register setting. See
Table 25 on page 53 for more
details.
12.5 kHz channel spacing, 433 MHz
25 kHz channel spacing, 868 MHz
500 kHz channel spacing
3.2
2.5
700
ms
ms
us
Table 8. Frequency synthesizer parameters
SWRS046
Page 13 of 92
CC1020
4.7. Digital Inputs / Outputs
Parameter
Min
Typ
Max
Unit
Condition / Note
Logic « 0 » input voltage
0
0.3*
V
VDD
Logic « 1 » input voltage
Logic « 0 » output voltage
Logic « 1 » output voltage
Logic “0” input current
0.7*
VDD
VDD
0.4
V
V
0
Output current −2.0 mA,
3.0 V supply voltage
2.5
NA
VDD
−1
V
Output current 2.0 mA,
3.0 V supply voltage
Input signal equals GND.
µA
PSEL has an internal pull-up
resistor and during configuration
the current will be -350 µA.
Logic “1” input current
DIO setup time
NA
20
1
Input signal equals VDD
µA
ns
TX mode, minimum time DIO
must be ready before the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
DIO hold time
10
ns
TX mode, minimum time DIO
must be held after the positive
edge of DCLK. Data should be
set up on the negative edge of
DCLK.
Serial interface (PCLK, PDI, PDO
and PSEL) timing specification
See Table 14 on page 24 for
more details
Pin drive, LNA_EN, PA_EN
Source current
0.90
0.87
0.81
0.69
mA
mA
mA
mA
0 V on LNA_EN, PA_EN pins
0.5 V on LNA_EN, PA_EN pins
1.0 V on LNA_EN, PA_EN pins
1.5 V on LNA_EN, PA_EN pins
Sink current
0.93
0.92
0.89
0.79
mA
mA
mA
mA
3.0 V on LNA_EN, PA_EN pins
2.5 V on LNA_EN, PA_EN pins
2.0 V on LNA_EN, PA_EN pins
1.5 V on LNA_EN, PA_EN pins
See Figure 35 on page 62 for
more details.
Table 9. Digital inputs / outputs parameters
SWRS046
Page 14 of 92
CC1020
4.8. Current Consumption
Parameter
Min
Typ
Max
Unit
Condition / Note
Power Down mode
0.2
1.8
Oscillator core off
µA
Current Consumption,
19.9
mA
receive mode 433 and 868 MHz
Current Consumption,
transmit mode 433/868 MHz :
P = −20 dBm
12.3/14.5
14.4/17.0
16.2/20.5
20.5/25.1
27.1
mA
mA
mA
mA
mA
The output power is delivered to
a 50 Ω single-ended load.
P = −5 dBm
See section 13.2 on page 45 for
more details.
P = 0 dBm
P = +5 dBm
P = +10 dBm (433 MHz only)
Current Consumption, crystal
oscillator
77
500
7.5
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
14.7456 MHz, 16 pF load crystal
µA
µA
Current Consumption, crystal
oscillator and bias
Current Consumption, crystal
oscillator, bias and synthesizer
mA
Table 10. Current consumption
5.
Pin Assignment
Table 11 provides an overview of the
CC1020 pinout.
The CC1020 comes in a QFN32 type
package (see page 86 for details).
PCLK 1
PDI 2
24 VC
23 AVDD
22 AVDD
21 RF_OUT
20 AVDD
19 RF_IN
18 AVDD
17 R_BIAS
PDO 3
DGND 4
DVDD 5
DGND 6
DCLK 7
DIO 8
AGND
Exposed die
attached pad
Figure 1. CC1020 package (top view)
SWRS046
Page 15 of 92
CC1020
Pin no.
Pin name
Pin type
Description
-
AGND
Ground (analog)
Exposed die attached pad. Must be soldered to a solid ground plane as
this is the ground connection for all analog modules. See page 64 for
more details.
1
2
3
4
5
6
7
PCLK
PDI
PDO
DGND
DVDD
DGND
DCLK
Digital input
Digital input
Programming clock for SPI configuration interface
Programming data input for SPI configuration interface
Programming data output for SPI configuration interface
Ground connection (0 V) for digital modules and digital I/O
Power supply (3 V typical) for digital modules and digital I/O
Ground connection (0 V) for digital modules (substrate)
Clock for data in both receive and transmit mode.
Can be used as receive data output in asynchronous mode
Digital output
Ground (digital)
Power (digital)
Ground (digital)
Digital output
8
9
DIO
Digital input/output Data input in transmit mode; data output in receive mode
Can also be used to start power-up sequencing in receive
LOCK
Digital output
PLL Lock indicator, active low. Output is asserted (low) when PLL is in
lock. The pin can also be used as a general digital output, or as receive
data output in synchronous NRZ/Manchester mode
Crystal oscillator or external clock input
10
11
12
13
14
XOSC_Q1
XOSC_Q2
AVDD
AVDD
LNA_EN
Analog input
Analog output
Power (analog)
Power (analog)
Digital output
Crystal oscillator
Power supply (3 V typical) for crystal oscillator
Power supply (3 V typical) for the IF VGA
General digital output. Can be used for controlling an external LNA if
higher sensitivity is needed.
15
16
PA_EN
AVDD
Digital output
General digital output. Can be used for controlling an external PA if
higher output power is needed.
Power supply (3 V typical) for global bias generator and IF anti-alias
filter
Power (analog)
17
18
19
20
21
22
R_BIAS
AVDD
RF_IN
AVDD
RF_OUT
AVDD
Analog output
Power (analog)
RF Input
Power (analog)
RF output
Connection for external precision bias resistor (82 kΩ, ± 1%)
Power supply (3 V typical) for LNA input stage
RF signal input from antenna (external AC-coupling)
Power supply (3 V typical) for LNA
RF signal output to antenna
Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA
stage
Power (analog)
23
24
25
26
27
28
29
30
31
32
AVDD
VC
AGND
AD_REF
AVDD
CHP_OUT
AVDD
DGND
DVDD
PSEL
Power (analog)
Analog input
Power supply (3 V typical) for VCO
VCO control voltage input from external loop filter
Ground connection (0 V) for analog modules (guard)
3 V reference input for ADC
Power supply (3 V typical) for charge pump and phase detector
PLL charge pump output to external loop filter
Power supply (3 V typical) for ADC
Ground connection (0 V) for digital modules (guard)
Power supply connection (3 V typical) for digital modules
Programming chip select, active low, for configuration interface. Internal
pull-up resistor.
Ground (analog)
Power (analog)
Power (analog)
Analog output
Power (analog)
Ground (digital)
Power (digital)
Digital input
Table 11. Pin assignment overview
Note:
DCLK, DIO and LOCK are high-
impedance (3-state) in power down
(BIAS_PD = 1 in the MAIN register).
The exposed die attached pad must be
soldered to a solid ground plane as this is
the main ground connection for the chip.
SWRS046
Page 16 of 92
CC1020
6.
Circuit Description
DIGITAL
DEMODULATOR
ADC
ADC
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
RF_IN
LNA
LNA 2
0
:2
90
DIGITAL
INTERFACE
TO µC
0
FREQ
SYNTH
PDO
PDI
:2
90
PCLK
PSEL
Power
Control
DIGITAL
MODULATOR
Multiplexer
- Modulation
- Data shaping
- Power Control
PA
RF_OUT
BIAS
XOSC
XOSC_Q1 XOSC_Q2
VC
PA_EN
LNA_EN
R_BIAS
CHP_OUT
Figure 2. CC1020 simplified block diagram
amplifier (PA). The RF output is frequency
shift keyed (FSK) by the digital bit stream
that is fed to the DIO pin. Optionally, a
Gaussian filter can be used to obtain
Gaussian FSK (GFSK).
A simplified block diagram of CC1020 is
shown in Figure 2. Only signal pins are
shown.
CC1020 features a low-IF receiver. The
received RF signal is amplified by the low-
noise amplifier (LNA and LNA2) and
down-converted in quadrature (I and Q) to
the intermediate frequency (IF). At IF, the
I/Q signal is complex filtered and
amplified, and then digitized by the ADCs.
Automatic gain control, fine channel
The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the
LO_I and LO_Q signals to the down-
conversion mixers in receive mode. The
VCO operates in the frequency range
1.608-1.880 GHz. The CHP_OUT pin is
the charge pump output and VC is the
control node of the on-chip VCO. The
external loop filter is placed between these
pins. A crystal is to be connected between
XOSC_Q1 and XOSC_Q2. A lock signal is
available from the PLL.
filtering,
demodulation
and
bit
synchronization is performed digitally.
CC1020 outputs the digital demodulated
data on the DIO pin. A synchronized data
clock is available at the DCLK pin. RSSI is
available in digital format and can be read
via the serial interface. The RSSI also
features a programmable carrier sense
indicator.
The 4-wire SPI serial interface is used for
configuration.
In transmit mode, the synthesized RF
frequency is fed directly to the power
SWRS046
Page 17 of 92
CC1020
7.
Application Circuit
Very few external components are
required for the operation of CC1020. The
recommended application circuit is shown
in Figure 3. The external components are
described in Table 12 and values are
given in Table 13.
values shown in Table 13 can be used for
data rates up to 4.8 kBaud. Component
values for higher data rates are easily
found using the SmartRF® Studio
software.
Crystal
Input / output matching
An external crystal with two loading
capacitors (C4 and C5) is used for the
crystal oscillator. See section 19 on page
58 for details.
L1 and C1 is the input match for the
receiver. L1 is also a DC choke for
biasing. L2 and C3 are used to match the
transmitter to 50 Ω. Internal circuitry
makes it possible to connect the input and
output together and match the CC1020 to
50 Ω in both RX and TX mode. However, it
is recommended to use an external T/R
switch for optimum performance. See
section 14 on page 46 for details.
Component values for the matching
network are easily found using the
SmartRF® Studio software.
Additional filtering
Additional external components (e.g. RF
LC or SAW filter) may be used in order to
improve the performance in specific
applications. See section 14 on page 46
for further information.
Power supply decoupling and filtering
Power supply decoupling and filtering
must be used (not shown in the application
circuit). The placement and size of the
decoupling capacitors and the power
supply filtering are very important to
achieve the optimum performance for
Bias resistor
The precision bias resistor R1 is used to
set an accurate bias current.
narrowband
provides a reference design that should be
followed very closely.
applications.
Chipcon
PLL loop filter
The loop filter consists of two resistors (R2
and R3) and three capacitors (C6-C8). C7
and C8 may be omitted in applications
where high loop bandwidth is desired. The
Ref
C1
C3
Description
LNA input match and DC block, see page 46
PA output match and DC block, see page 46
Crystal load capacitor, see page 58
C4
C5
Crystal load capacitor, see page 58
C6
PLL loop filter capacitor
C7
C8
C60
L1
L2
PLL loop filter capacitor (may be omitted for highest loop bandwidth)
PLL loop filter capacitor (may be omitted for highest loop bandwidth)
Decoupling capacitor
LNA match and DC bias (ground), see page 46
PA match and DC bias (supply voltage), see page 46
Precision resistor for current reference generator
PLL loop filter resistor
R1
R2
R3
PLL loop filter resistor
R10
XTAL
PA output match, see page 46
Crystal, see page 58
Table 12. Overview of external components (excluding supply decoupling capacitors)
SWRS046
Page 18 of 92
CC1020
AVDD=3V
DVDD=3V
C6
AVDD=3V
R2
C7
R3
C8
R10
L2
24
23
22
21
20
19
18
17
1
2
3
4
5
VC
PCLK
PDI
Monopole
antenna
(50 Ohm)
AVDD
C60
C3
AVDD
PDO
LC Filter
DGND
DVDD
DGND
RF_OUT
DVDD=3V
CC1020
AVDD
RF_IN
AVDD=3V
AVDD=3V
6
T/R Switch
C1
7
8
AVDD
DCLK
DIO
R_BIAS
L1
R1
AVDD=3V
XTAL
C4
C5
Figure 3. Typical application and test circuit (power supply decoupling not shown)
Item
C1
C3
C4
C5
C6
C7
C8
C60
L1
433 MHz
868 MHz
915 MHz
10 pF, 5%, NP0, 0402
5.6 pF, 5%, NP0, 0402
22 pF, 5%, NP0, 0402
12 pF, 5%, NP0, 0402
220 nF, 10%, X7R, 0603
8.2 nF, 10%, X7R, 0402
2.2 nF, 10%, X7R, 0402
220 pF, 5%, NP0, 0402
33 nH, 5%, 0402
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
22 pF, 5%, NP0, 0402
12 pF, 5%, NP0, 0402
100 nF, 10%, X7R, 0603
3.9 nF, 10%, X7R, 0402
1.0 nF, 10%, X7R, 0402
220 pF, 5%, NP0, 0402
82 nH, 5%, 0402
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
22 pF, 5%, NP0, 0402
12 pF, 5%, NP0, 0402
100 nF, 10%, X7R, 0603
3.9 nF, 10%, X7R, 0402
1.0 nF, 10%, X7R, 0402
220 pF, 5%, NP0, 0402
82 nH, 5%, 0402
L2
22 nH, 5%, 0402
3.6 nH, 5%, 0402
3.6 nH, 5%, 0402
R1
82 kΩ, 1%, 0402
82 kΩ, 1%, 0402
82 kΩ, 1%, 0402
R2
1.5 kΩ, 5%, 0402
2.2 kΩ, 5%, 0402
2.2 kΩ, 5%, 0402
R3
4.7 kΩ, 5%, 0402
6.8 kΩ, 5%, 0402
6.8 kΩ, 5%, 0402
R10
XTAL
82 Ω, 5%, 0402
14.7456 MHz crystal,
16 pF load
82 Ω, 5%, 0402
14.7456 MHz crystal,
16 pF load
82 Ω, 5%, 0402
14.7456 MHz crystal,
16 pF load
Note: Items shaded vary for different frequencies. For 433 MHz, 12.5 kHz channel, a loop filter with
lower bandwidth is used to improve adjacent and alternate channel rejection.
Table 13. Bill of materials for the application circuit in Figure 3
Note:
The PLL loop filter component values in
Table 13 (R2, R3, C6-C8) can be used for
data rates up to 4.8 kBaud. The SmartRF®
Studio software provides component
values for other data rates using the
equations on page 50.
In the CC1020EMX reference design
LQG15HS series inductors from Murata
have been used. The switch is SW-456
from M/A-COM.
SWRS046
Page 19 of 92
CC1020
The LC filter in Figure 3 is inserted in the
TX path only. The filter will reduce the
emission of harmonics and the spurious
emissions in the TX path. An alternative is
to insert the LC filter between the antenna
and the T/R switch as shown in Figure 4.
The filter will reduce the emission of
harmonics and the spurious emissions in
the TX path as well as increase the
receiver selectivity. The sensitivity will be
slightly reduced due to the insertion loss of
the LC filter.
AVDD=3V
DVDD=3V
C6
AVDD=3V
R2
C7
R3
C8
R10
L2
24
23
22
21
20
19
18
17
1
VC
PCLK
2
Monopole
antenna
(50 Ohm)
AVDD
PDI
C60
C3
3
AVDD
PDO
4
DGND
DVDD
DGND
RF_OUT
DVDD=3V
5
LC Filter
CC1020
AVDD
RF_IN
AVDD=3V
AVDD=3V
6
T/R Switch
C1
7
8
AVDD
DCLK
DIO
R_BIAS
L1
R1
AVDD=3V
XTAL
C4
C5
Figure 4. Alternative application circuit (power supply decoupling not shown)
SWRS046
Page 20 of 92
CC1020
8.
Configuration Overview
separation, crystal oscillator reference
frequency
CC1020 can be configured to achieve
optimum performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:
• Power-down / power-up mode
• Crystal oscillator power-up / power-
down
• Data rate and data format (NRZ,
Manchester coded or UART interface)
• Synthesizer lock indicator mode
• Digital RSSI and carrier sense
• FSK / GFSK / OOK modulation
• Receive / transmit mode
• RF output power
• Frequency synthesizer key parameters:
RF output frequency, FSK frequency
8.1. Configuration Software
Chipcon provides users of CC1020 with a
software program, SmartRF® Studio
(Windows interface) that generates all
necessary CC1020 configuration data
based on the user’s selections of various
parameters. These hexadecimal numbers
will then be the necessary input to the
microcontroller for the configuration of
CC1020. In addition, the program will
provide the user with the component
values needed for the input/output
matching circuit, the PLL loop filter and the
LC filter.
Figure 5 shows the user interface of the
CC1020 configuration software.
Figure 5. SmartRF® Studio user interface
SWRS046
Page 21 of 92
CC1020
9.
Microcontroller Interface
The microcontroller pins connected to PDI,
PDO and PCLK can be used for other
purposes when the configuration interface
is not used. PDI, PDO and PCLK are high
impedance inputs as long as PSEL is not
activated (active low).
Used in a typical system, CC1020 will
interface to microcontroller. This
microcontroller must be able to:
a
• Program CC1020 into different modes
via the 4-wire serial configuration
interface (PDI, PDO, PCLK and PSEL)
PSEL has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up.
• Interface
to
the
bi-directional
synchronous data signal interface (DIO
and DCLK)
• Optionally, the microcontroller can do
data encoding / decoding
• Optionally, the microcontroller can
monitor the LOCK pin for frequency
lock status, carrier sense status or
other status information.
• Optionally, the microcontroller can read
back the digital RSSI value and other
status information via the 4-wire serial
interface
Signal interface
A bi-directional pin is usually used for data
(DIO) to be transmitted and data received.
DCLK providing the data timing should be
connected to a microcontroller input.
As an option, the data output in receive
mode can be made available on a
separate pin. See section 9.2 on page for
25 further details.
Configuration interface
The microcontroller interface is shown in
Figure 6. The microcontroller uses 3 or 4
I/O pins for the configuration interface
(PDI, PDO, PCLK and PSEL). PDO should
be connected to a microcontroller input.
PDI, PCLK and PSEL must be
microcontroller outputs. One I/O pin can
be saved if PDI and PDO are connected
together and a bi-directional pin is used at
the microcontroller.
PLL lock signal
Optionally, one microcontroller pin can be
used to monitor the LOCK signal. This
signal is at low logic level when the PLL is
in lock. It can also be used for carrier
sense and to monitor other internal test
signals.
PCLK
PDI
PDO
PSEL
(Optional)
Micro-
controller
DIO
DCLK
(Optional)
LOCK
Figure 6. Microcontroller interface
SWRS046
Page 22 of 92
CC1020
9.1. 4-wire Serial Configuration Interface
14. The clocking of the data on PDI is
done on the positive edge of PCLK. Data
should be set up on the negative edge of
PCLK by the microcontroller. When the
last bit, D0, of the 8 data-bits has been
loaded, the data word is loaded into the
internal configuration register.
CC1020 is configured via a simple 4-wire
SPI-compatible interface (PDI, PDO,
PCLK and PSEL) where CC1020 is the
slave. There are 8-bit configuration
registers, each addressed by a 7-bit
address. A Read/Write bit initiates a read
or write operation. A full configuration of
CC1020 requires sending 33 data frames of
16 bits each (7 address bits, R/W bit and 8
data bits). The time needed for a full
configuration depends on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 53 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.
The configuration data will be retained
during a programmed power down mode,
but not when the power supply is turned
off. The registers can be programmed in
any order.
The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back. CC1020 then
returns the data from the addressed
register. PDO is used as the data output
and must be configured as an input by the
microcontroller. The PDO is set at the
negative edge of PCLK and should be
sampled at the positive edge. The read
operation is illustrated in Figure 8.
During each write-cycle, 16 bits are sent
on the PDI-line. The seven most
significant bits of each data frame (A6:0)
are the address-bits. A6 is the MSB (Most
Significant Bit) of the address and is sent
as the first bit. The next bit is the R/W bit
(high for write, low for read). The 8 data-
bits are then transferred (D7:0). During
address and data transfer the PSEL
(Program SELect) must be kept low. See
Figure 7.
PSEL must be set high between each
read/write operation.
The timing for the programming is also
shown in Figure 7 with reference to Table
TSS
THS
TCL,min
TCH,min
THD
TSD
PCLK
Address
Write mode
Data byte
6
5
4
3
2
1
0
W
7
6
5
4
3
2
1
0
PDI
PDO
PSEL
Figure 7. Configuration registers write operation
SWRS046
Page 23 of 92
CC1020
TSS
THS
TCL,min
TCH,min
PCLK
PDI
Address
Read mode
6
5
4
3
2
1
0
R
Data byte
7
6
5
4
3
2
1
0
PDO
PSEL
TSH
Figure 8. Configuration registers read operation
Parameter Symbol
Min
Max
Unit
Conditions
PCLK, clock
frequency
FPCLK
10
MHz
PCLK low
pulse
duration
TCL,min
50
50
ns
ns
The minimum time PCLK must be low.
The minimum time PCLK must be high.
PCLK high
pulse
TCH,min
duration
PSEL setup
time
TSS
THS
TSH
TSD
THD
25
25
50
25
25
ns
ns
ns
ns
ns
The minimum time PSEL must be low before
positive edge of PCLK.
PSEL hold
time
The minimum time PSEL must be held low after
the negative edge of PCLK.
PSEL high
time
The minimum time PSEL must be high.
PDI setup
time
The minimum time data on PDI must be ready
before the positive edge of PCLK.
PDI hold time
The minimum time data must be held at PDI, after
the positive edge of PCLK.
Rise time
Fall time
Trise
Tfall
100
100
ns
ns
The maximum rise time for PCLK and PSEL
The maximum fall time for PCLK and PSEL
Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /
90% of VDD. The maximum load that this table is valid for is 20 pF.
Table 14. Serial interface, timing specification
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CC1020
9.2. Signal Interface
If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode.
The CC1020 can be used with NRZ (Non-
Return-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.
CC1020 can also synchronize the data from
the demodulator and provide the data
clock at DCLK. The data format is
controlled by the DATA_FORMAT[1:0] bits
in the MODEM register.
As an option, the data output can be made
available at a separate pin. This is done
by setting SEP_DI_DO
=
1
in the
INTERFACE register. Then, the LOCK pin
will be used as data output in synchronous
mode, overriding other use of the LOCK
pin.
CC1020 can be configured for three
different data formats:
Synchronous NRZ mode
Transparent
mode
In transmit mode DIO is used as data
input. The data is modulated at RF without
synchronization or encoding.
Asynchronous
UART
In transmit mode CC1020 provides the data
clock at DCLK and DIO is used as data
input. Data is clocked into CC1020 at the
rising edge of DCLK. The data is
modulated at RF without encoding.
In receive mode the raw data signal from
the demodulator is sent to the output
(DIO). No synchronization or decoding of
the signal is done in CC1020 and should be
done by the interfacing circuit.
In receive mode CC1020 performs the
synchronization and provides received
data clock at DCLK and data at DIO. The
data should be clocked into the interfacing
circuit at the rising edge of DCLK. See
Figure 9.
If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode. The DCLK pin is not active and can
be set to a high or low level by
DATA_FORMAT[0].
Synchronous Manchester encoded
mode
In transmit mode CC1020 provides the data
clock at DCLK and DIO is used as data
input. Data is clocked into CC1020 at the
rising edge of DCLK and should be in NRZ
format. The data is modulated at RF with
Manchester code. The encoding is done
by CC1020. In this mode the effective bit
rate is half the baud rate due to the
coding. As an example, 4.8 kBaud
Manchester encoded data corresponds to
2.4 kbps.
If SEP_DI_DO = 1 in the INTERFACE
register, the DCLK pin is the data output in
receive mode and the DIO pin is the data
input in transmit mode. In TX mode the
DCLK pin is not active and can be set to a
high or low level by DATA_FORMAT[0].
See Figure 11.
Manchester encoding and decoding
In the Synchronous Manchester encoded
mode CC1020 uses Manchester coding
when modulating the data. The CC1020
also performs the data decoding and
synchronization. The Manchester code is
based on transitions; a “0” is encoded as a
low-to-high transition, a “1” is encoded as
a high-to-low transition. See Figure 12.
In receive mode CC1020 performs the
synchronization and provides received
data clock at DCLK and data at DIO.
CC1020 performs the decoding and NRZ
data is presented at DIO. The data should
be clocked into the interfacing circuit at the
rising edge of DCLK. See Figure 10.
In synchronous NRZ or Manchester mode
the DCLK signal runs continuously both in
RX and TX unless the DCLK signal is
gated with the carrier sense signal or the
PLL lock signal. Refer to section 21 and
section 21.2 for more details.
The Manchester code ensures that the
signal has a constant DC component,
which is necessary in some FSK
demodulators. Using this mode also
ensures compatibility with CC400/CC900
designs.
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CC1020
Transmitter side:
DCLK
Clock provided by CC1020
DIO
Data provided by microcontroller
FSK modulating signal (NRZ),
internal in CC1020
“RF”
Receiver side:
Demodulated signal (NRZ),
internal in CC1020
“RF”
DCLK
DIO
Clock provided by CC1020
Data provided by CC1020
Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0)
Transmitter side:
DCLK
Clock provided by CC1020
DIO
Data provided by microcontroller
FSK modulating signal (Manchester
encoded), internal in CC1020
“RF”
Receiver side:
Demodulated signal (Manchester
encoded), internal in CC1020
“RF”
DCLK
DIO
Clock provided by CC1020
Data provided by CC1020
Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0)
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CC1020
Transmitter side:
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
DCLK
DIO
Data provided by UART (TXD)
FSK modulating signal,
internal in CC1020
“RF”
Receiver side:
Demodulated signal (NRZ),
internal in CC1020
“RF”
DCLK is used as data output
provided by CC1020.
Connect to UART (RXD)
DCLK
DIO
DIO is not used in receive mode. Used only
as data input in transmit mode
Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)
1
0 1 1 0 0 0 1 1 0 1
Tx
data
Time
Figure 12. Manchester encoding
10.
Data Rate Programming
The data rate (baud rate) is programmable
and depends on the crystal frequency and
MCLK_DIV2[1:0]
DIV2
00
01
10
11
1
2
4
8
the
programming of
the CLOCK
(CLOCK_A and CLOCK_B) registers.
The baud rate (B.R) is given by
Table 15. DIV2 for different settings of
MCLK_DIV2
fxosc
B.R. =
8 ⋅ (REF _ DIV +1) ⋅ DIV1⋅ DIV 2
MCLK_DIV1[2:0]
DIV1
2.5
3
000
001
010
011
100
101
110
111
where DIV1 and DIV2 are given by the
value of MCLK_DIV1 and MCLK_DIV2.
4
7.5
12.5
40
48
64
Table 17 shows some possible data rates
as a function of crystal frequency in
synchronous mode. In asynchronous
transparent UART mode any data rate up
to 153.6 kBaud can be used.
Table 16. DIV1 for different settings of
MCLK_DIV1
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CC1020
Data rate
[kBaud]
0.45
0.5
Crystal frequency [MHz]
4.9152
7.3728
X
9.8304
12.288
14.7456
17.2032
19.6608
X
X
X
0.6
0.9
1
1.2
1.8
2
2.4
3.6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
X
X
X
X
4.096
4.8
7.2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
8.192
9.6
14.4
16
16.384
19.2
28.8
32
32.768
38.4
57.6
64
65.536
76.8
115.2
128
153.6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 17. Some possible data rates versus crystal frequency
11.
Frequency Programming
Programming the frequency word in the
configuration registers sets the operation
frequency. There are two frequency words
registers, termed FREQ_A and FREQ_B,
which can be programmed to two different
frequencies. One of the frequency words
can be used for RX (local oscillator
frequency) and the other for TX
(transmitting carrier frequency) in order to
be able to switch very fast between RX
mode and TX mode. They can also be
used for RX (or TX) at two different
channels. The F_REG bit in the MAIN
register selects frequency word A or B.
The PLL output frequency is given by:
3
4
FREQ + 0.5 ⋅ DITHER
⎛
⎜
⎞
⎟
fc = fref
⋅
+
32768
⎝
⎠
in the frequency band 402 – 470 MHz, and
3
2
FREQ + 0.5 ⋅ DITHER
⎛
⎜
⎞
⎟
fc = fref
⋅
+
16384
⎝
⎠
in the frequency band 804 – 940 MHz.
The BANDSELECT bit in the ANALOG
register controls the frequency band used.
BANDSELECT = 0 gives 402 – 470 MHz,
and BANDSELECT = 1 gives 804 – 940
MHz.
The frequency word is located in
FREQ_2A:FREQ_1A:FREQ_0A
and
FREQ_2B:FREQ_1B:FREQ_0B for the
FREQ_A and FREQ_B word respectively.
The LSB of the FREQ_0 registers are
used to enable dithering, section 11.1.
The reference frequency is the crystal
oscillator clock frequency divided by
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CC1020
REF_DIV (3 bits in the CLOCK_A or
f0 = fc − fdev
CLOCK_B register), a number between 1
and 7:
f1 = fc + fdev
fxosc
fref
=
where fdev is set by the DEVIATION
register:
REF _ DIV +1
FSK frequency deviation is programmed in
the DEVIATION register. The deviation
programming is divided into a mantissa
fdev = fref ⋅TXDEV _ M ⋅ 2(TXDEV _ X −16)
in the frequency band 402 – 470 MHz and
(TXDEV_M[3:0])
(TXDEV_X[2:0]).
and
an
exponent
fdev = fref ⋅TXDEV _ M ⋅ 2(TXDEV _ X −15)
Generally REF_DIV should be as low as
possible but the following requirements
must be met
in the frequency band 804 – 940 MHz.
fc
OOK (On-Off Keying) is used if
TXDEV_M[3:0] = 0000.
9.8304 ≥ fref
>
[
MHz
]
256
The TX_SHAPING bit in the DEVIATION
register controls Gaussian shaping of the
modulation signal.
in the frequency band 402 – 470 MHz, and
fc
9.8304 ≥ fref
>
[MHz
]
512
In receive mode the frequency must be
programmed to be the LO frequency. Low
side LO injection is used, hence:
in the frequency band 804 – 940 MHz.
The PLL output frequency equations
above give the carrier frequency, fc , in
transmit mode (centre frequency). The two
FSK modulation frequencies are given by:
f
LO = fc − fIF
where fIF is the IF frequency (ideally 307.2
kHz).
11.1. Dithering
Spurious signals will occur at certain
frequencies depending on the division
ratios in the PLL. To reduce the strength of
these spurs, a common technique is to
use a dithering signal in the control of the
frequency dividers. Dithering is activated
by setting the DITHER bit in the FREQ_0
registers. It is recommended to use the
dithering in order to achieve the best
possible performance.
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CC1020
12.
Receiver
12.1. IF Frequency
The IF frequency is derived from the
crystal frequency as
Large offsets, however, from the nominal
IF frequency will give an un-symmetric
filtering (variation in group delay and
different attenuation) of the signal,
resulting in decreased sensitivity and
selectivity. See Application Note AN022
Crystal Frequency Selection for more
details.
fxoscx
fIF
=
8⋅(ADC _ DIV
[
2 : 0 +1)
]
where ADC_DIV[2:0] is set in the MODEM
register.
For IF frequencies other than 300 – 320
kHz and for high frequency deviation and
high data rates (typically ≥ 76.8 kBaud) the
analog filter must be bypassed by setting
FILTER_BYPASS = 1 in the FILTER
register. In this case the blocking
performance at 1 MHz and larger offsets
will be degraded.
The analog filter succeeding the mixer is
used for wideband and anti-alias filtering
which is important for the blocking
performance at 1 MHz and larger offsets.
This filter is fixed and centered on the
nominal IF frequency of 307.2 kHz. The
bandwidth of the analog filter is about 160
kHz.
The IF frequency is always the ADC clock
frequency divided by 4. The ADC clock
frequency should therefore be as close to
1.2288 MHz as possible.
Using crystal frequencies which gives an
IF frequency within 300 – 320 kHz means
that the analog filter can be used
(assuming low frequency deviations and
low data rates).
12.2. Receiver Channel Filter Bandwidth
In order to meet different channel spacing
requirements, the receiver channel filter
bandwidth is programmable. It can be
programmed from 9.6 to 307.2 kHz.
Manchester and NRZ mode 2·fm is then
equal to the programmed baud rate. The
equation for SBW can then be rewritten as
SBW = Baud rate + frequency separation
The minimum receiver channel filter
bandwidth depends on baud rate,
Furthermore, the frequency offset of the
transmitter and receiver must also be
considered. Assuming equal frequency
error in the transmitter and receiver (same
type of crystal) the total frequency error is:
frequency
tolerance.
separation
and
crystal
The signal bandwidth must be smaller
than the available receiver channel filter
bandwidth. The signal bandwidth (SBW)
can be approximated by (Carson’s rule):
f_error = ±2 · XTAL_ppm · f_RF
where XTAL_ppm is the total accuracy of
the crystal including initial tolerance,
temperature drift, loading and ageing.
F_RF is the RF operating frequency.
SBW = 2 · fm + 2 · frequency deviation
where fm is the modulating signal. In
Manchester
modulating
transmitting a continuous sequence of 0’s
(or 1’s). In NRZ mode the maximum
mode
signal
the
occurs
maximum
when
The minimum receiver channel filter
bandwidth (ChBW) can then be estimated
as
modulating
signal
occurs
when
ChBW > SBW + 2 · f_error
transmitting a 0-1-0 sequence. In both
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CC1020
The DEC_DIV[4:0] bits in the FILTER
register control the receiver channel filter
bandwidth. The 6 dB bandwidth is given
by:
different channel filter bandwidths than
given in Table 18.
There is a trade-off between selectivity as
well as sensitivity and accepted frequency
tolerance. In applications where larger
frequency drift is expected, the filter
bandwidth can be increased, but with
reduced adjacent channel rejection (ACR)
and sensitivity.
ChBW = 307.2 / (DEC_DIV + 1) [kHz]
where the IF frequency is set to 307.2
kHz.
In SmartRF® Studio the user specifies the
channel spacing and the channel filter
bandwidth is set according to Table 18.
Channel
spacing
[kHz]
12.5
25
Filter
bandwidth
[kHz]
12.288
19.2
FILTER.DEC_DIV
[4:0]
[decimal(binary)]
24 (11000b)
15 (01111b)
11 (01011b)
5 (00101b)
For narrowband systems with channel
spacings of 12.5 and 25 kHz the channel
filter bandwidth is 12.288 kHz and 19.2
kHz respectively to comply with ARIB STD
T-67 and EN 300 220.
50
100
25.6
51.2
150
102.4
2 (00010b)
200
153.6
1 (00001b)
500
307.2
0 (00000b)
Table 18. Channel filter bandwidths used
for the channel spacings defined in
SmartRF® Studio
For wideband systems (channel spacing of
50 kHz and above) it is possible to use
12.3. Demodulator, Bit Synchronizer and Data Decision
The block diagram for the demodulator,
data slicer and bit synchronizer is shown
in Figure 13. The built-in bit synchronizer
synchronizes the internal clock to the
incoming data and performs data
decoding. The data decision is done using
over-sampling and digital filtering of the
incoming signal. This improves the
reliability of the data transmission. Using
the synchronous modes simplifies the
data-decoding task substantially.
The digital data slicer in CC1020 uses an
average value of the minimum and
maximum frequency deviation detected as
the comparison level. The RXDEV_X[1:0]
and
RXDEV_M[3:0]
in
the
AFC_CONTROL register are used to set
the expected deviation of the incoming
signal. Once a shift in the received
frequency larger than the expected
deviation is detected, a bit transition is
recorded and the average value to be
used by the data slicer is calculated.
The recommended preamble is
a
‘010101…’ bit pattern. The same bit
pattern should also be used in Manchester
mode, giving a ‘011001100110…‘chip’
pattern. This is necessary for the bit
synchronizer to synchronize to the coding
correctly.
The minimum number of transitions
required to calculate a slicing level is 3.
That is, a 010 bit pattern (NRZ).
The actual number of bits used for the
averaging can be increased for better data
decision accuracy. This is controlled by
The data slicer does the bit decision.
Ideally the two received FSK frequencies
are placed symmetrically around the IF
frequency. However, if there is some
frequency error between the transmitter
and the receiver, the bit decision level
should be adjusted accordingly. In CC1020
this is done automatically by measuring
the two frequencies and use the average
value as the decision level.
the
SETTLING[1:0]
bits
in
the
AFC_CONTROL register. If RX data is
present in the channel when the RX chain
is turned on, then the data slicing estimate
will usually give correct results after 3 bit
transitions. The data slicing accuracy will
increase after this, depending on the
SETTLING[1:0] bits. If the start of
transmission occurs after the RX chain
has turned on, the minimum number of bit
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CC1020
transitions (or preamble bits) before
correct data slicing will depend on the
SETTLING[1:0] bits.
The internally calculated average FSK
frequency value gives a measure for the
frequency offset of the receiver compared
to the transmitter. This information can
also be used for an automatic frequency
control (AFC) as described in section
12.13.
The automatic data slicer average value
function can be disabled by setting
SETTLING[1:0] = 00. In this case a
symmetrical signal around the IF
frequency is assumed.
Average
filter
Bit
Frequency
detector
Data
filter
Data slicer
comparator
synchronizer
and data
Digital filtering
Decimator
decoder
Figure 13. Demodulator block diagram
12.4. Receiver Sensitivity versus Data Rate and Frequency Separation
The receiver sensitivity depends on the
channel filter bandwidth, data rate, data
format, FSK frequency separation and the
RF frequency. Typical figures for the
receiver sensitivity (BER = 10−3) are
shown in Table 19 and Table 20 for FSK.
For best performance, the frequency
deviation should be at least half the baud
rate in FSK mode.
The sensitivity is measured using the
matching network shown in the application
circuit in Figure 3, which includes an
external T/R switch.
Refer to Application Note AN029
CC1020/1021 AFC for plots of sensitivity
versus frequency offset.
Sensitivity [dBm]
Data rate
[kBaud]
Channel spacing
[kHz]
Deviation Filter BW
NRZ
mode
Manchester
mode
UART
mode
[kHz]
[kHz]
2.4 optimized sensitivity
2.4 optimized selectivity
12.5
12.5
25
9.6
12.288
19.2
25.6
51.2
102.4
153.6
307.2
-115
-112
-112
-110
-107
-104
-101
-96
-118
-114
-112
-111
-108
-104
-101
-97
-115
-112
-112
-110
-107
-104
-101
-96
± 2.025
± 2.025
± 2.475
± 4.95
± 9.9
± 19.8
± 36.0
± 72.0
4.8
9.6
19.2
38.4
76.8
153.6
50
100
150
200
500
Table 19. Typical receiver sensitivity as a function of data rate at 433 MHz, FSK
modulation, BER = 10−3, pseudo-random data (PN9 sequence)
Note: “Optimized selectivity” in Table 19 is relevant for systems targeting compliance with
ARIB STD T-67, 12.5 kHz channel spacing.
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CC1020
Sensitivity [dBm]
Data rate
[kBaud]
Channel spacing
[kHz]
Deviation Filter BW
NRZ
mode
Manchester
mode
UART
mode
[kHz]
[kHz]
2.4
4.8
9.6
19.2
38.4
76.8
153.6
12.5
25
50
100
150
200
500
12.288
19.2
25.6
-112
-111
-109
-107
-103
-99
-116
-112
-110
-107
-103
-100
-94
-112
-111
-109
-107
-103
-99
± 2.025
± 2.475
± 4.95
± 9.9
± 19.8
± 36.0
± 72.0
51.2
102.4
153.6
307.2
-94
-94
Table 20. Typical receiver sensitivity as a function of data rate at 868 MHz, FSK
modulation, BER = 10−3, pseudo-random data (PN9 sequence)
12.5. RSSI
P = 1.5·RSSI – 3·VGA_SETTING –
RSSI_Offset [dBm]
CC1020 has a built-in RSSI (Received
Signal Strength Indicator) giving a digital
value that can be read form the RSSI
register. The RSSI reading must be offset
and adjusted for VGA gain setting
The RSSI_Offset depends on the channel
filter bandwidth used due to different VGA
settings. Figure 14 and Figure 15 show
typical plots of RSSI reading as a function
of input power for different channel
spacings. See section 12.5 on page 33 for
(VGA_SETTING[4:0]
in
the
VGA3
register).
The digital RSSI value is ranging from 0 to
106 (7 bits).
a
list of channel filter bandwidths
corresponding to the various channel
spacings. Refer to Application Note AN030
CC1020/1021 RSSI for further details.
The RSSI reading is
a
logarithmic
measure of the average voltage amplitude
after the digital filter in the digital part of
the IF chain:
The following method can be used to
calculate the power P in dBm from the
RSSI readout values in Figure 14 and
Figure 15:
RSSI = 4 log2(signal amplitude)
The relative power is then given by RSSI x
1.5 dB in a logarithmic scale.
P = 1.5·[RSSI – RSSI_ref] + P_ref
where P is the output power in dBm for the
current RSSI readout value. RSSI_ref is
the RSSI readout value taken from
Figure 14 or Figure 15 for an input power
level of P_ref. Note that the RSSI reading
in decimal value changes for different
channel filter bandwidths.
The number of samples used to calculate
the average signal amplitude is controlled
by AGC_AVG[1:0] in the VGA2 register.
The RSSI update rate is given by:
f filter _ clock
fRSSI
=
[1:0]+1
2AGC _ AVG
The analog filter has a finite dynamic
range and is the reason why the RSSI
reading is saturated at lower channel
spacings. Higher channel spacing is
typically used for high frequency deviation
and data rates. The analog filter bandwidth
is about 160 kHz and is bypassed for high
frequency deviation and data rates and is
the reason why the RSSI reading is not
saturated for 200 kHz and 500 kHz
channel spacing in Figure 14 and Figure
15.
where AGC_AVG[1:0] is set in the VGA2
register and
.
f filter _ clock = 2⋅ChBW
Maximum VGA gain is programmed by the
VGA_SETTING[4:0] bits. The VGA gain is
programmed in approximately 3 dB/LSB.
The RSSI measurement can be referred to
the power (absolute value) at the RF_IN
pin by using the following equation:
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Page 33 of 92
CC1020
80
70
60
50
40
30
20
10
0
-125
-115
-105
-95
-85
-75
-65
-55
-45
-35
-25
Input power level [dBm]
12.5 kHz
25 kHz
50 kHz
100 kHz
150 kHz
200 kHz
500 kHz
Figure 14. Typical RSSI value vs. input power for some typical channel spacings, 433 MHz
80
70
60
50
40
30
20
10
0
-125
-115
-105
-95
-85
-75
-65
-55
-45
-35
-25
Input power level [dBm]
12.5 kHz
25 kHz
50 kHz
100 kHz
150 kHz
200 kHz
500 kHz
Figure 15. Typical RSSI value vs. input power for some typical channel spacings, 868 MHz
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CC1020
12.6. Image Rejection Calibration
10. Write XP-DX to PHASE_COMP register.
For perfect image rejection, the phase and
gain of the “I” and “Q” parts of the analog
RX chain must be perfectly matched. To
improve the image rejection, the “I” and
“Q” phase and gain difference can be fine-
tuned by adjusting the PHASE_COMP and
11. Wait at least 3 ms. Measure signal strength Y1
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
12. Write XP-2·DX to PHASE_COMP register.
13. Wait at least 3 ms. Measure signal strength Y0
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
14. Set AP = 2·(Y0-Y2+Y4) – (Y1+Y3).
15. If AP > 0 then
GAIN_COMP registers.
This allows
compensation for process variations and
other nonidealities. The calibration is done
set DP = ROUND( 7·DX·(2·(Y0-Y4)+Y1-
Y3) / (10·AP) )
else
by injecting
a
signal at the image
frequency, and adjusting the phase and
gain difference for minimum RSSI value.
if Y0+Y1 > Y3+Y4 then
set DP = DX
else
set DP = -DX.
16. If DP > DX then
During image rejection calibration, an
unmodulated carrier should be applied at
the image frequency (614.4 kHz below the
desired channel), No signal should be
present in the desired channel. The signal
level should be 50 – 60 dB above the
sensitivity in the desired channel, but the
optimum level will vary from application to
application. Too large input level gives
poor results due to limited linearity in the
analog IF chain, while too low input level
gives poor results due to the receiver
noise floor.
set DP = DX
else
if DP < -DX then set DP = -DX.
17. Set XP = XP+DP.
18. Write XP to PHASE_COMP register.
19. If XG+2·DX < 127 then
write XG+2·DX to GAIN_COMP register
else
write 127 to GAIN_COMP register.
20. Wait at least 3 ms. Measure signal strength Y4
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
21. Write XG+DX to GAIN_COMP register.
22. Wait at least 3 ms. Measure signal strength Y3
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
23. Write XG to GAIN_COMP register.
24. Wait at least 3 ms. Measure signal strength Y2
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
25. Write XG-DX to GAIN_COMP register.
26. Wait at least 3 ms. Measure signal strength Y1
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
27. Write XG-2·DX to GAIN_COMP register.
28. Wait at least 3 ms. Measure signal strength Y0
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
29. Set AG = 2·(Y0-Y2+Y4) – (Y1+Y3).
30. If AG > 0 then
For
best
RSSI
=
accuracy,
11 during image
use
AGC_AVG(1:0]
rejection calibration (RSSI value is
averaged over 16 filter output samples).
The RSSI register update rate then equals
the receiver channel bandwidth (set in
FILTER register) divided by 8, as the filter
output rate is twice the receiver channel
bandwidth. This gives the minimum
waiting time between RSSI register reads
(0.5 ms is used below). Chipcon
recommends
the
following
image
set DG = ROUND( 7·DX·(2·(Y0-Y4)+Y1-
Y3) / (10·AG) )
calibration procedure:
else
if Y0+Y1 > Y3+Y4 then
1. Define 3 variables: XP = 0, XG = 0 and DX = 64.
Go to step 3.
2. Set DX = DX/2.
3. Write XG to GAIN_COMP register.
4. If XP+2·DX < 127 then
set DG = DX
else
set DG = -DX.
31. If DG > DX then
set DG = DX
write XP+2·DX to PHASE_COMP register
else
else
if DG < -DX then set DG = -DX.
32. Set XG = XG+DG.
33. If DX > 1 then go to step 2.
Write XP to PHASE_COMP register and
XG to GAIN_COMP register.
write 127 to PHASE_COMP register.
5. Wait at least 3 ms. Measure signal strength Y4
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
6. Write XP+DX to PHASE_COMP register.
7. Wait at least 3 ms. Measure signal strength Y3
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
8. Write XP to PHASE_COMP register.
9. Wait at least 3 ms. Measure signal strength Y2
as filtered average of 8 reads from RSSI register
with 0.5 ms of delay between each RSSI read.
34.
If repeated calibration gives varying
results, try to change the input level or
increase the number of RSSI reads N. A
good starting point is N=8. As accuracy is
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CC1020
more important in the last fine-calibration
steps, it can be worthwhile to increase N
for each loop iteration.
in the FILTER register. In this case the
image rejection is degraded.
The image rejection is reduced for low
supply voltages (typically <2.5 V) when
operating in the 402 – 470 MHz frequency
range.
For high frequency deviation and high data
rates (typically ≥ 76.8 kBaud) the analog
filter succeeding the mixer must be
bypassed by setting FILTER_BYPASS = 1
12.7. Blocking and Selectivity
Figure 16 shows the blocking/selectivity at
433 MHz, 12.5 kHz channel spacing.
Figure 17 shows the blocking/selectivity at
868 MHz, 25 kHz channel spacing. The
blocking rejection is the ratio between a
modulated blocker (interferer) and
a
wanted signal 3 dB above the sensitivity
limit.
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
Blocker frequency offset [kHz]
Figure 16. Typical blocker rejection. Carrier frequency set to 434.3072 MHz (12.5 kHz
channel spacing, 12.288 kHz receiver channel filter bandwidth)
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CC1020
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
Blocker frequency offset [kHz]
Figure 17. Typical blocker rejection. Carrier frequency set to 868.3072 MHz (25 kHz
channel spacing, 19.2 kHz receiver channel filter bandwidth)
12.8. Linear IF Chain and AGC Settings
in the VGA4 register. Together, these two
values specify the signal strength limits
used by the AGC to adjust the VGA gain.
CC1020 is based on a linear IF chain
where the signal amplification is done in
an analog VGA (Variable Gain Amplifier).
The gain is controlled by the digital part of
the IF chain after the ADC (Analog to
Digital Converter). The AGC (Automatic
Gain Control) loop ensures that the ADC
operates inside its dynamic range by using
an analog/digital feedback loop.
To avoid unnecessary tripping of the VGA,
an extra hysteresis and filtering of the
RSSI samples can be added. The
AGC_HYSTERESIS bit in the VGA2
register enables this.
The time dynamics of the loop can be
altered by the VGA_BLANKING bit in the
ANALOG register, and VGA_FREEZE[1:0]
and VGA_WAIT[2:0] bits in the VGA1
register.
The maximum VGA gain is programmed
by the VGA_SETTING[4:0] in the VGA3
register. The VGA gain is programmed in
approximately 3 dB/LSB. The VGA gain
should be set so that the amplified thermal
noise from the front-end balance the
quantization noise from the ADC.
Therefore the optimum maximum VGA
gain setting will depend on the channel
filter bandwidth.
When VGA_BLANKING is activated, the
VGA recovery time from DC offset spikes
after a gain step is reduced.
VGA_FREEZE determines the time to hold
bit synchronization, VGA and RSSI levels
after one of these events occur:
A digital RSSI is used to measure the
signal strength after the ADC. The
CS_LEVEL[4:0] in the VGA4 register is
used to set the nominal operating point of
the gain control (and also the carrier sense
level). Further explanation can be found in
Figure 18.
•
•
•
RX power-up
The PLL has been out of lock
Frequency register setting is switched
between A and B
The VGA gain will be changed according
to a threshold set by the VGA_DOWN[2:0]
in the VGA3 register and the VGA_UP[2:0]
This feature is useful to avoid AGC
operation during start-up transients and to
ensure minimum dwell time using
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CC1020
1. Disable AGC and use maximum LNA2 gain by
writing BFh to the VGA2 register. Set minimum
VGA gain by writing to the VGA3 register with
VGA_SETTING = 0.
frequency hopping. This means that bit
synchronization can be maintained from
hop to hop.
2. Apply no RF input signal, and measure ADC noise
VGA_WAIT determines the time to hold
the present bit synchronization and RSSI
levels after changing VGA gain. This
feature is useful to avoid AGC operation
during the settling of transients after a
VGA gain change. Some transients are
expected due to DC offsets in the VGA.
floor by reading the RSSI register.
3. Apply no RF input signal, and write VGA3 register
with increasing VGA_SETTING value until the
RSSI register value is approximately 4 larger than
the value read in step 2. This places the front-end
noise floor around 6 dB above the ADC noise floor.
4. Apply an RF signal with strength equal the desired
carrier sense threshold. The RF signal should
preferably be modulated with correct Baud rate and
deviation. Read the RSSI register value, subtract 8,
and write to CS_LEVEL in the VGA4 register. Vary
the RF signal level slightly and check that carrier
At the sensitivity limit, the VGA gain is set
by VGA_SETTING. In order to optimize
selectivity, this gain should not be set
higher than necessary. The SmartRF®
Studio software gives the settings for
VGA1 – VGA4 registers. For reference,
the following method can be used to find
the AGC settings:
sense indication (bit
3 in STATUS register)
switches at the desired input level.
5. If desired, adjust the VGA_UP and VGA_DOWN
settings according to the explanation in Figure 18.
6. Enable AGC and select LNA2 gain change level.
Write 55h to VGA2 register if the resulting
VGA_SETTING>10. Otherwise, write 45h to VGA2.
Modify AGC_AVG in the above VGA2 value if
faster carrier sense and AGC settling is desired.
RSSI Level
(signal strength, 1.5dB/step)
Note that the AGC works with "raw" filter output signal
strength, while the RSSI readout value is compensated for
VGA gain changes by the AGC.
AGC decreases gain if above
this level (unless at minimum).
The AGC keeps the signal strength in this range. Minimize
VGA_DOWN for best selectivity, but leave some margin to
avoid frequent VGA gain changes during reception.
VGA_DOWN+3
AGC increases gain if below this
level (unless at maximum).
The AGC keeps the signal strength above carrier sense level
+ VGA_UP. Minimize VGA_UP for best selectivity, but
increase if first VGA gain reduction occurs too close to the
noise floor.
VGA_UP
Carrier sense is turned on here.
To set CS_LEVEL, subtract 8 from RSSI readout with RF
input signal at desired carrier sense level.
CS_LEVEL+8
0
Zero level depends on front-end settings and VGA_SETTING
value.
Figure 18. Relationship between RSSI, carrier sense level, and AGC settings CS_LEVEL,
VGA_UP and VGA_DOWN
12.9. AGC Settling
After turning on the RX chain, the following
occurs:
B) The AGC waits 16-48 FILTER_CLK
periods, depending on the VGA_WAIT
setting in the VGA1 register, for settling in
the analog parts and the digital channel
filter.
A) The AGC waits 16-128 ADC_CLK
(1.2288 MHz) periods, depending on the
VGA_FREEZE setting in the VGA1
register, for settling in the analog parts.
C) The AGC calculates the RSSI value as
the average magnitude over the next 2-16
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CC1020
FILTER_CLK periods, depending of the
AGC_AVG setting in the VGA2 register.
2-3 VGA gain changes should be
expected before the AGC has settled.
Increasing AGC_AVG increases the
settling time, but may be worthwhile if
there is the time in the protocol, and for
reducing false wake-up events when
setting the carrier sense close to the noise
floor.
D) If the RSSI value is higher than
CS_LEVEL+8, then the carrier sense
indicator is set (if CS_SET = 0). If the
RSSI value is too high according to the
CS_LEVEL, VGA_UP and VGA_DOWN
settings, and the VGA gain is not already
at minimum, then the VGA gain is reduced
and the AGC continues from B).
The AGC settling time depends on the
FILTER_CLK (= 2·ChBW). Thus, there is a
trade off between AGC settling time and
receiver sensitivity because the AGC
settling time can be reduced for data rates
lower than 76.8 kBaud by using a wider
receiver channel filter bandwidth (i.e.
larger ChBW).
E) If the RSSI value is too low according to
the CS_LEVEL and VGA_UP settings, and
the VGA gain is not already at maximum
(given by VGA_SETTING), then the VGA
gain is increased and the AGC continues
from B).
12.10. Preamble Length and Sync Word
The rules for choosing a good sync word
are as follows:
1. The sync word should be significantly
different from the preamble
2. A large number of transitions is good for
the bit synchronization or clock recovery.
Equal bits reduce the number of
transitions. The recommended sync word
has at the most 3 equal bits in a row.
3. Autocorrelation. The sync word should
not repeat itself, as this will increase the
likelihood for errors.
Using the register settings provided by the
SmartRF® Studio software, packet error
rates (PER) less than 0.5% can be
achieved when using 24 bits of preamble
and a 16 bit sync word (D391). Using a
preamble longer than 24 bits will improve
the PER.
When performing the PER measurements
described above the packet format
consisted of 10 bytes of random data, 2
bytes CRC and 1 dummy byte in addition
to the sync word and preamble at the start
of each package.
4. In general the first bit of sync should be
opposite of last bit in preamble, to achieve
one more transition.
For the test 1000 packets were sent 10
times. The transmitter was put in power
down between each packet. Any bit error
in the packet, either in the sync word, in
the data or in the CRC caused the packet
to be counted as a failed packet.
The recommended sync words for CC1020
are 2 bytes (D391), 3 bytes (D391DA) or 4
bytes (D391DA26) and are selected as the
best compromise of the above criteria.
12.11. Carrier Sense
The carrier sense signal is based on the
VGA_SETTING[4:0] sets the maximum
gain in the VGA. This value must be set so
that the ADC works with optimum dynamic
RSSI value and
a
programmable
threshold. The carrier sense function can
be used to simplify the implementation of a
CSMA (Carrier Sense Multiple Access)
medium access protocol.
range for
a
certain channel filter
bandwidth. The detected signal strength
(after the ADC) will therefore depend on
this setting.
Carrier
sense
threshold
level
is
programmed by CS_LEVEL[4:0] in the
VGA4 register and VGA_SETTING[4:0] in
the VGA3 register.
CS_LEVEL[4:0] sets the threshold for this
specific VGA_SETTING[4:0] value. If the
VGA_SETTING[4:0] is changed, the
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CC1020
CS_LEVEL[4:0]
must
be
changed
The carrier sense signal can be read as
the CARRIER_SENSE bit in the STATUS
register.
accordingly to maintain the same absolute
carrier sense threshold. See Figure 18 for
an explanation of the relationship between
RSSI, AGC and carrier sense settings.
The carrier sense signal can also be made
available at the LOCK pin by setting
LOCK_SELECT[3:0] = 0100 in the LOCK
register.
12.12. Automatic Power-up Sequencing
If SEQ_PSEL = 0 in the SEQUENCING
register, then the automatic power-up
CC1020 has a built-in automatic power-up
sequencing state machine. By setting the
CC1020 into this mode, the receiver can be
powered-up automatically by a wake-up
signal and will then check for a carrier
signal (carrier sense). If carrier sense is
not detected, it returns to power-down
mode. A flow chart for automatic power-up
sequencing is shown in Figure 19.
sequence is initiated by
a
negative
transition on the DIO pin (as long as
SEP_DI_DO = 1 in the INTERFACE
register).
Sequence timing is controlled through
RX_WAIT[2:0] and CS_WAIT[3:0] in the
SEQUENCING register.
The automatic power-up sequencing mode
is selected when PD_MODE[1:0] = 11 in
the MAIN register. When the automatic
power-up sequencing mode is selected,
the functionality of the MAIN register is
changed and used to control the
sequencing.
VCO and PLL calibration can also be done
automatically as a part of the sequence.
This is controlled through SEQ_CAL[1:0]
in the MAIN register. Calibration can be
done every time, every 16th sequence,
every 256th sequence, or never. See the
register description for details.
A
description of when to do, and how the
VCO and PLL self-calibration is done, is
given in section 15.2 on page 51.
By setting SEQ_PD = 1 in the MAIN
register, CC1020 is set in power down
mode. If SEQ_PSEL
=
1
in the
SEQUENCING register the automatic
power-up sequence is initiated by a
negative transition on the PSEL pin.
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CC1020
Power down
Turn on crystal oscillator/bias
Frequency synthesizer off
Receive chain off
Sequencing wake-up event
Crystal oscillator and bias off
Frequency synthesizer off
Receive chain off
(negative transition on
PSEL pin or DIO pin)
Crystal oscillator and bias on
Turn on frequency synthesizer
Receive chain off
Set
Optional calibration
Programmable: each time,
once in 16, or once in 256
Receive chain off
Wait for PLL
lock or timeout,
127 filter clocks
PLL timeout
SEQ_ERROR
flag in STATUS
register
PLL in lock
Optional waiting time before
turning on receive chain
Programmable:
32-256 ADC clocks
Crystal oscillator and bias on
Frequency synthesizer on
Turn on receive chain
Wait for
Carrier sense timeout
carrier sense or timeout
Programmable: 20-72
filter clocks
Carrier sense
Receive mode
Crystal oscillator and bias on
Frequency synthesizer on
Receive chain on
Sequencing power-down event
(Positive transition on SEQ_PD in MAIN register)
Figure 19. Automatic power-up sequencing flow chart
Notes to Figure 19:
Filter clock (FILTER_CLK):
f filter _ clock = 2⋅ChBW
ADC clock (ADC_CLK):
fxoscx
fADC
=
2 ⋅(ADC _ DIV
[
2 : 0 +1)
]
where ChBW is defined on page 30.
where ADC_DIV[2:0] is set in the MODEM
register.
12.13. Automatic Frequency Control
compensate for frequency offset between
transmitter and receiver.
CC1020 has a built-in feature called AFC
(Automatic Frequency Control) that can be
used to compensate for frequency drift.
The frequency offset is given by:
The average frequency offset of the
received signal (from the nominal IF
frequency) can be read in the AFC
register. The signed (2’s-complement) 8-
bit value AFC[7:0] can be used to
∆F = AFC·Baud rate / 16
The receiver can be calibrated against the
transmitter by changing the operating
frequency according to the measured
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CC1020
offset. The new frequency must be
calculated and written to the FREQ
register by the microcontroller. The AFC
can be used for an FSK/GFSK signal, but
not for OOK. Application Note AN029
CC1020/1021 AFC provides the procedure
and equations necessary to implement
AFC.
The AFC feature reduces the crystal
accuracy requirement.
12.14. Digital FM
It is possible to read back the
instantaneous IF from the FM demodulator
as a frequency offset from the nominal IF
frequency. This digital value can be used
kHz (Nyquist) and is determined by the
MODEM_CLK. The MODEM_CLK, which
is the sampling rate, equals 8 times the
baud rate. That is, the minimum baud rate,
which can be programmed, is 1 kBaud.
However, the incoming data will be filtered
in the digital domain and the 3-dB cut-off
frequency is 0.6 times the programmed
Baud rate. Thus, for audio the minimum
programmed Baud rate should be
approximately 7.2 kBaud.
to perform
a
pseudo analog FM
demodulation.
The frequency offset can be read from the
GAUSS_FILTER register and is a signed
8-bit value coded as 2-complement.
The instantaneous deviation is given by:
F = GAUSS_FILTER·Baud rate / 8
The
GAUSS_FILTER
resolution
decreases with increasing baud rate. A
accumulate and dump filter can be
implemented in the uC to improve the
The digital value should be read from the
register and sent to a DAC and filtered in
order to get an analog audio signal. The
internal register value is updated at the
MODEM_CLK rate. MODEM_CLK is
available at the LOCK pin when
LOCK_SELECT[3:0] = 1101 in the LOCK
register, and can be used to synchronize
the reading.
resolution.
Note
that
each
GAUSS_FILTER reading should be
synchronized to the MODEM_CLK. As an
example, accumulating 4 readings and
dividing the total by 4 will improve the
resolution by 2 bits.
Furthermore,
to
fully
utilize
the
GAUSS_FILTER dynamic range the
frequency deviation must be 16 times the
programmed baud rate.
For audio (300 – 4000 Hz) the sampling
rate should be higher than or equal to 8
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CC1020
13.
Transmitter
13.1. FSK Modulation Formats
The data modulator can modulate FSK,
which is a two level FSK (Frequency Shift
Keying), or GFSK, which is a Gaussian
filtered FSK with BT = 0.5. The purpose of
the GFSK is to make a more bandwidth
efficient system as shown in Figure 20.
The modulation and the Gaussian filtering
are done internally in the chip. The
TX_SHAPING bit in the DEVIATION
register enables the GFSK. GFSK is
recommended for narrowband operation.
Figure 21 and Figure 22 show typical eye
diagrams for 434 MHz and 868 MHz
operation respectively.
Figure 20. FSK vs. GFSK spectrum plot. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
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CC1020
Figure 21. FSK vs. GFSK eye diagram. 2.4 kBaud, NRZ, ±2.025 kHz frequency deviation
Figure 22. GFSK eye diagram. 153.6 kBaud, NRZ, ±79.2 kHz frequency deviation
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CC1020
13.2. Output Power Programming
The RF output power from the device is
programmable by the 8-bit PA_POWER
register. Figure 23 and Figure 24 shows
the output power and total current
use either the lower or upper 4-bits in the
register to control the power, as shown in
the figures. However, the output power
can be controlled in finer steps using all
the available bits in the PA_POWER
register.
consumption as
a
function of the
PA_POWER register setting. It is more
efficient in terms of current consumption to
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0
1
2
3
4
5
6
7
8
9
0A 0B 0C 0D 0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF
PA_POWER [hex]
Current Consumption
Output Power
Figure 23. Typical output power and current consumption, 433 MHz
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
0
1
2
3
4
5
6
7
8
9
0A 0B 0C 0D 0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF
PA_POWER [hex]
Current Consumption
Output Power
Figure 24. Typical output power and current consumption, 868 MHz
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CC1020
13.3. TX Data Latency
The transmitter will add a delay due to the
synchronization of the data with DCLK and
further clocking into the modulator. The
equivalent to at least 2 bits after the data
payload has been transmitted before
switching off the PA (i.e. before stopping
the transmission).
user should therefore add
a
delay
13.4. Reducing Spurious Emission and Modulation Bandwidth
Modulation bandwidth and spurious
emission are normally measured with the
PA continuously on and a repeated test
sequence.
PA ramping should then be used both
when switching the PA on and off. A linear
PA ramping sequence can be used where
register PA_POWER is changed from 00h
to 0Fh and then from 50h to the register
setting that gives the desired output power
(e.g. F0h for +10 dBm output power at 433
MHz operation). The longer the time per
PA ramping step the better, but setting the
total PA ramping time equal to 2 bit
periods is a good compromise between
performance and PA ramping time.
In cases where the modulation bandwidth
and spurious emission are measured with
the CC1020 switching from power down
mode to TX mode, a PA ramping
sequence could be used to minimize
modulation bandwidth and spurious
emission.
14.
Input / Output Matching and Filtering
When designing the impedance matching
network for the CC1020 the circuit must be
matched correctly at the harmonic
frequencies as well as at the fundamental
tone. A recommended matching network is
shown in Figure 25. Component values for
various frequencies are given in Table 21.
Component values for other frequencies
can be found using the SmartRF® Studio
software.
be measured and compared to the
response of the Chipcon reference design.
Refer to Figure 27 and Table 22 as well as
Figure 28 and Table 23.
The use of an external T/R switch reduces
current consumption in TX for high output
power levels and improves the sensitivity
in RX. A recommended application circuit
is available from the Chipcon web site
(CC1020EMX). The external T/R switch
can be omitted in certain applications, but
performance will then be degraded.
As can be seen from Figure 25 and Table
21, the 433 MHz network utilizes a T-type
filter, while the 868/915 MHz network has
a π-type filter topology.
The match can also be tuned by a shunt
capacitor array at the PA output
(RF_OUT). The capacitance can be set in
0.4 pF steps and used either in RX mode
or TX mode. The RX_MATCH[3:0] and
TX_MATCH[3:0] bits in the MATCH
register control the capacitor array.
It is important to remember that the
physical layout and the components used
contribute significantly to the reflection
coefficient, especially at the higher
harmonics. For this reason, the frequency
response of the matching network should
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CC1020
AVDD=3V
R10
ANTENNA
L2
C60
CC1020
L70
C72
L71
C3
RF_OUT
RF_IN
C71
C1
L1
T/R SWITCH
Figure 25. Input/output matching network
Item
433 MHz
868 MHz
915 MHz
C1
C3
C60
C71
C72
L1
10 pF, 5%, NP0, 0402
5.6 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
DNM
4.7 pF, 5%, NP0, 0402
33 nH, 5%, 0402
22 nH, 5%, 0402
47 nH, 5%, 0402
39 nH, 5%, 0402
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
82 nH, 5%, 0402
3.6 nH, 5%, 0402
5.1 nH, 5%, 0402
0 Ω resistor, 0402
82 Ω, 5%, 0402
47 pF, 5%, NP0, 0402
10 pF, 5%, NP0, 0402
220 pF, 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
8.2 pF 5%, NP0, 0402
82 nH, 5%, 0402
3.6 nH, 5%, 0402
5.1 nH, 5%, 0402
0 Ω resistor, 0402
82 Ω, 5%, 0402
L2
L70
L71
R10
82 Ω, 5%, 0402
Table 21. Component values for the matching network described in Figure 25 (DNM = Do
Not Mount).
Figure 26. Typical LNA input impedance, 200 – 1000 MHz
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CC1020
433 MHz
Figure 27. Typical optimum PA load impedance, 433 MHz. The frequency is swept from
300 MHz to 2500 MHz. Values are listed in Table 22
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
433
866
54
20
288
14
5
44
173
-563
-123
-66
1299
1732
2165
Table 22. Impedances at the first 5 harmonics (433 MHz matching network)
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CC1020
868 M H z
Figure 28: Typical optimum PA load impedance, 868/915 MHz. The frequency is swept
from 300 MHz to 2800 MHz. Values are listed in Table 23
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
868
915
15
20
24
35
18
22
44
45
1736
1830
2604
2745
1.5
1.7
3.2
3.6
Table 23. Impedances at the first 3 harmonics (868/915 MHz matching network)
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CC1020
15.
Frequency Synthesizer
15.1. VCO, Charge Pump and PLL Loop Filter
The VCO is completely integrated and
operates in the 1608 – 1880 MHz range. A
1) If the data rate is 4.8 kBaud or below
and the channel spacing is 12.5 kHz the
following loop filter components are
recommended:
frequency divider is used to get
a
frequency in the UHF range (402 – 470
and 804 – 940 MHz). The BANDSELECT
bit in the ANALOG register selects the
frequency band.
C6 = 220 nF
C7 = 8200 pF
C8 = 2200 pF
R2 = 1.5 kΩ
R3 = 4.7 kΩ
The VCO frequency is given by:
FREQ + 0.5 ⋅ DITHER
⎛
⎞
⎟
fVCO = fref ⋅ 3 +
⎜
2) If the data rate is 4.8 kBaud or below
and the channel spacing is different from
12.5 kHz the following loop filter
components are recommended:
8192
⎝
⎠
The VCO frequency is divided by 2 and by
4 to generate frequencies in the two
bands, respectively.
C6 = 100 nF
C7 = 3900 pF
C8 = 1000 pF
R2 = 2.2 kΩ
R3 = 6.8 kΩ
The VCO sensitivity (sometimes referred
to as VCO gain) varies over frequency and
operating conditions. Typically the VCO
sensitivity varies between 12 and 36
MHz/V. For calculations the geometrical
mean at 21 MHz/V can be used. The PLL
calibration (explained below) measures
the actual VCO sensitivity and adjusts the
charge pump current accordingly to
achieve correct PLL loop gain and
bandwidth (higher charge pump current
when VCO sensitivity is lower).
After calibration the PLL bandwidth is set
by the PLL_BW register in combination
with the external loop filter components
calculated above. The PLL_BW can be
found from
PLL_BW = 174 + 16 log2(fref /7.126)
where fref is the reference frequency (in
MHz). The PLL loop filter bandwidth
increases with increasing PLL_BW setting.
Note that in SmartRF® Studio PLL_BW is
fixed to 9E hex when the channel spacing
is set up for 12.5 kHz, optimized
selectivity.
The following equations can be used for
calculating PLL loop filter component
values, see Figure 3, for a desired PLL
loop bandwidth, BW:
C7 = 3037 (fref / BW2) –7
R2 = 7126 (BW / fref)
C6 = 80.75 (fref / BW2)
R3 = 21823 (BW / fref)
C8 = 839 (fref / BW2) –6
[pF]
[kΩ]
[nF]
[kΩ]
[pF]
After calibration the applied charge pump
current (CHP_CURRENT[3:0]) can be
read in the STATUS1 register. The charge
pump current is approximately given by:
Define a minimum PLL loop bandwidth as
BWmin
4
ICHP =16 ⋅ 2CHP _ CURRENT
[uA
]
=
80.75⋅ fref 220 . If BWmin
>
Baud rate/3 then set BW = BWmin and if
BWmin < Baud rate/3 then set BW = Baud
rate/3 in the above equations.
The combined charge pump and phase
detector gain (in A/rad) is given by the
charge pump current divided by 2π.
There are two special cases when using
the recommended 14.7456 MHz crystal:
The PLL bandwidth will limit the maximum
modulation frequency and hence data
rate.
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CC1020
15.2. VCO and PLL Self-Calibration
To compensate for supply voltage,
temperature and process variations, the
VCO and PLL must be calibrated. The
calibration is performed automatically and
sets the maximum VCO tuning range and
optimum charge pump current for PLL
stability. After setting up the device at the
operating frequency, the self-calibration
can be initiated by setting the
CAL_START bit in the CALIBRATE
register. The calibration result is stored
internally in the chip, and is valid as long
as power is not turned off. If large supply
voltage drops (typically more than 0.25 V)
or temperature variations (typically more
than 40oC) occur after calibration, a new
calibration should be performed.
To check that the PLL is in lock the user
should monitor the LOCK_CONTINUOUS
bit in the STATUS register. The
LOCK_CONTINUOUS bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0010.
There are separate calibration values for
the two frequency registers. However, dual
calibration is possible if all of the below
conditions apply:
•
•
The two frequencies A and B differ by
less than 1 MHz
Reference frequencies are equal
(REF_DIV_A[2:0] = REF_DIV_B[2:0]
in the CLOCK_A/CLOCK_B registers)
•
VCO
currents
are
equal
The nominal VCO control voltage is set by
the CAL_ITERATE[2:0] bits in the
CALIBRATE register.
(VCO_CURRENT_A[3:0]
VCO_CURRENT_B[3:0] in the VCO
register).
=
The CAL_COMPLETE bit in the STATUS
register indicates that calibration has
finished. The calibration wait time
(CAL_WAIT) is programmable and is
proportional to the internal PLL reference
frequency. The highest possible reference
frequency should be used to get the
The CAL_DUAL bit in the CALIBRATE
register controls dual or separate
calibration.
The
single
calibration
algorithm
(CAL_DUAL=0) using separate calibration
for RX and TX frequency is illustrated in
Figure 29. The same algorithm is
minimum
calibration
time.
It
is
recommended to use CAL_WAIT[1:0] = 11
in order to get the most accurate loop
bandwidth.
applicable
for
dual
calibration
if
CAL_DUAL=1. Application Note AN023
CC1020 MCU Interfacing, available from
the Chipcon web site, includes example
source code for single calibration.
Calibration
Reference frequency [MHz]
time [ms]
CAL_WAIT
1.8432
49 ms
60 ms
71 ms
109 ms
7.3728
12 ms
15 ms
18 ms
27 ms
9.8304
10 ms
11 ms
13 ms
20 ms
Chipcon
recommends
that
single
00
01
10
11
calibration be used for more robust
operation.
There is a small, but finite, possibility that
the PLL self-calibration will fail. The
calibration routine in the source code
should include a loop so that the PLL is re-
calibrated until PLL lock is achieved if the
PLL does not lock the first time. Refer to
CC1020 Errata Note 004.
Table 24. Typical calibration times
The CAL_COMPLETE bit can also be
monitored at the LOCK pin, configured by
LOCK_SELECT[3:0] = 0101, and used as
an interrupt input to the microcontroller.
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CC1020
Start single calibration
Write FREQ_A, FREQ_B, VCO,
CLOCK_A and CLOCK_B registers.
PLL_BW = 174 + 16log2(fref/7.126)
fref is the reference frequency (in
MHz)
Calibrate RX frequency register A
(to calibrate TX frequency register
B write MAIN register = D1h).
Register CALIBRATE = 34h
Write MAIN register = 11h:
RXTX=0, F_REG=0, PD_MODE=1,
FS_PD=0, CORE_PD=0, BIAS_PD=0,
RESET_N=1
Write CALIBRATE register = B4h
Start calibration
Wait for T≥100 us
Read STATUS register and wait until
CAL_COMPLETE=1
Read STATUS register and wait until
LOCK_CONTINUOUS=1
No
Calibration OK?
Yes
End of calibration
Figure 29. Single calibration algorithm for RX and TX
15.3. PLL Turn-on Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
turn-on time is the time needed for the PLL
to lock to the desired frequency when
going from power down mode (with the
crystal oscillator running) to TX or RX
mode. The PLL turn-on time depends on
the PLL loop filter bandwidth. Table 25
gives the PLL turn-on time for different
PLL loop filter bandwidths.
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CC1020
C6
[nF]
220
C7
[pF]
8200 2200
C8
[pF]
R2
[kΩ]
1.5
R3
[kΩ]
4.7
PLL turn-on time
Comment
[us]
3200
Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
100
56
15
3900 1000
2.2
3.3
5.6
6.8
10
18
2500
1400
1300
Up to 4.8 kBaud data rate, 25 kHz channel spacing
Up to 9.6 kBaud data rate, 50 kHz channel spacing
Up to 19.2 kBaud data rate, 100 kHz channel
spacing
2200
560
560
150
3.9
1.0
0.2
120
27
33
3.3
-
12
27
47
39
82
1080
950
Up to 38.4 kBaud data rate, 150 kHz channel
spacing
Up to 76.8 kBaud data rate, 200 kHz channel
spacing
Up to 153.6 kBaud data rate, 500 kHz channel
spacing
1.5
150
700
Table 25. Typical PLL turn-on time to within ±10% of channel spacing for different loop
filter bandwidths
15.4. PLL Lock Time versus Loop Filter Bandwidth
If calibration has been performed the PLL
lock time is the time needed for the PLL to
lock to the desired frequency when going
from RX to TX mode or vice versa. The
PLL lock time depends on the PLL loop
filter bandwidth. Table 26 gives the PLL
lock time for different PLL loop filter
bandwidths.
C6
C7
C8
R2
R3
PLL lock time
Comment
[nF]
[pF]
[pF]
[kΩ]
[kΩ]
[us]
1
2
3
220
100
56
8200 2200
3900 1000
1.5
2.2
3.3
5.6
12
4.7
6.8
10
900
180
270
140
70
1300 Up to 4.8 kBaud data rate, 12.5 kHz channel
spacing
640
400
140
75
830
490
230
180
55
Up to 4.8 kBaud data rate, 25 kHz channel
spacing
Up to 9.6 kBaud data rate, 50 kHz channel
spacing
Up to 19.2 kBaud data rate, 100 kHz channel
spacing
Up to 38.4 kBaud data rate, 150 kHz channel
spacing
2200
560
120
27
560
150
33
15
18
3.9
1.0
0.2
39
50
3.3
-
27
82
30
15
Up to 76.8 kBaud data rate, 200 kHz channel
spacing
1.5
47
150
14
14
28
Up to 153.6 kBaud data rate, 500 kHz channel
spacing
Table 26. Typical PLL lock time to within ±10% of channel spacing for different loop filter
bandwidths. 1) 307.2 kHz step, 2) 1 channel step, 3) 1 MHz step
16.
VCO and LNA Current Control
The VCO current is programmable and
should be set according to operating
frequency, RX/TX mode and output power.
FREQ_B
independently.
can
be
programmed
Recommended
settings
for
the
The bias currents for the LNA, mixer and
the LO and PA buffers are also
programmable. The FRONTEND and the
BUFF_CURRENT registers control these
currents.
VCO_CURRENT bits in the VCO register
are shown in the register overview and
also given by SmartRF® Studio. The VCO
current for frequency FREQ_A and
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CC1020
17.
Power Management
then be calibrated in both RX and TX
mode. After this is completed, the CC1020
is ready for use. See the detailed
procedure flowcharts in Figure 29 – Figure
31.
CC1020 offers great flexibility for power
management in order to meet strict power
consumption requirements in battery-
operated applications. Power down mode
is controlled through the MAIN register.
There are separate bits to control the RX
part, the TX part, the frequency
synthesizer and the crystal oscillator in the
MAIN register. This individual control can
be used to optimize for lowest possible
current consumption in each application.
Figure 30 shows a typical power-on and
initializing sequence for minimum power
consumption.
With reference to Application Note AN023
CC1020
MCU
Interfacing
Chipcon
recommends the following sequence:
After power up:
1) ResetCC1020
2) Initialize
3) WakeUpCC1020ToRX
4) Calibrate
Figure 31 shows a typical sequence for
activating RX and TX mode from power
5) WakeUpCC1020ToTX
6) Calibrate
down
mode
for
minimum
power
consumption.
After calibration is completed, enter TX
mode (SetupCC1020TX), RX mode
(SetupCC1020RX) or power down mode
(SetupCC1020PD)
Note that PSEL should be tri-stated or set
to a high level during power down mode in
order to prevent a trickle current from
flowing in the internal pull-up resistor.
From power-down mode to RX:
1) WakeUpCC1020ToRX
2) SetupCC1020RX
Application Note AN023 CC1020 MCU
Interfacing includes example source code
and is available from the Chipcon web
site.
From power-down mode to TX:
1) WakeUpCC1020ToTX
2) SetupCC1020TX
Chipcon recommends resetting the CC1020
(by clearing the RESET_N bit in the MAIN
register) when the chip is powered up
initially. All registers that need to be
configured should then be programmed
(those which differ from their default
values). Registers can be programmed
freely in any order. The CC1020 should
Switching from RX to TX mode:
1) SetupCC1020TX
Switching from TX to RX mode:
1) SetupCC1020RX
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CC1020
Power Off
Turn on power
Reset CC1020
MAIN: RX_TX=0, F_REG=0,
PD_MODE=1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
RESET_N=0
RESET_N=1
Program all necessary registers
except MAIN and RESET
Turn on crystal oscillator, bias
generator and synthesizer
successively
Calibrate VCO and PLL
MAIN: PD_MODE=1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
Power Down mode
Figure 30. Initialising sequence
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CC1020
*Time to wait depends
on the crystal frequency
and the load capacitance
Power Down mode
Turn on crystal oscillator core
MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1
Wait 1.2 ms*
Turn on bias generator. MAIN: BIAS_PD=0
Wait 150 us
RX
TX
RX or TX?
Turn on frequency synthesizer
Turn on frequency synthesizer
MAIN: RXTX=0, F_REG=0, FS_PD=0
MAIN: RXTX=1, F_REG=1, FS_PD=0
Wait until lock detected from LOCK pin
or STATUS register
Wait until lock detected from LOCK pin
or STATUS register
Turn on RX: MAIN: PD_MODE = 0
Turn on TX: MAIN: PD_MODE = 0
Set PA_POWER
TX mode
RX mode
Turn off RX/TX:
MAIN: PD_MODE = 1, FS_PD=1,
XOSC_PD=1, BIAS_PD=1
PA_POWER=00h
Power Down mode
Figure 31. Sequence for activating RX or TX mode
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CC1020
18.
On-Off Keying (OOK)
The data modulator can also provide OOK
(On-Off Keying) modulation. OOK is an
ASK (Amplitude Shift Keying) modulation
using 100% modulation depth. OOK
modulation is enabled in RX and in TX by
setting TXDEV_M[3:0] = 0000 in the
DEVIATION register. An OOK eye
diagram is shown in Figure 32.
must be 2 times the Baud rate (see Table
27). Manchester coding must always be
used for OOK.
Note that the automatic frequency control
(AFC) cannot be used when receiving
OOK, as it requires a frequency shift.
The AGC has a certain time-constant
determined by FILTER_CLK, which
depends on the IF filter bandwidth. There
is a lower limit on FILTER_CLK and hence
the AGC time constant. For very low data
rates the minimum time constant is too
fast and the AGC will increase the gain
when a “0” is received and decrease the
gain when a “1” is received. For this
reason the minimum data rate in OOK is
2.4 kBaud.
The data demodulator can also perform
OOK demodulation. The demodulation is
done by comparing the signal level with
the “carrier sense” level (programmed as
CS_LEVEL in the VGA4 register). The
signal is then decimated and filtered in the
data filter. Data decision and bit
synchronization are as for FSK reception.
In this mode AGC_AVG in the VGA2
register must be set to 3. The channel
bandwidth must be 4 times the Baud rate
for data rates up to 9.6 kBaud. For the
highest data rates the channel bandwidth
Typical figures for the receiver sensitivity
(BER = 10−3) are shown in Table 27 for
OOK.
Figure 32. OOK eye diagram. 9.6 kBaud
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CC1020
Sensitivity [dBm]
433 MHz 868 MHz
Manchester mode Manchester mode
Data rate
[kBaud]
Filter BW
[kHz]
2.4
4.8
9.6
19.2
38.4
76.8
153.6
9.6
19.2
38.4
51.2
102.4
153.6
307.2
-116
-113
-103
-102
-95
-92
-81
-107
-104
-101
-97
-94
-87
Table 27. Typical receiver sensitivity as a function of data rate at 433 and 868 MHz, OOK
modulation, BER = 10−3, pseudo-random data (PN9 sequence)
19.
Crystal Oscillator
The recommended crystal frequency is
14.7456 MHz, but any crystal frequency in
the range 4 – 20 MHz can be used. Using
a crystal frequency different from 14.7456
MHz might in some applications give
operation of the crystal. In addition,
loading capacitors (C4 and C5) for the
crystal are required. The loading capacitor
values depend on the total load
capacitance, CL, specified for the crystal.
The total load capacitance seen between
the crystal terminals should equal CL for
the crystal to oscillate at the specified
frequency.
degraded
performance.
Refer
to
Application
Note AN022
Crystal
Frequency Selection for more details on
the use of other crystal frequencies than
14.7456 MHz. The crystal frequency is
used as reference for the data rate (as
well as other internal functions) and in the
4 – 20 MHz range the frequencies 4.9152,
7.3728, 9.8304, 12.2880, 14.7456,
17.2032, 19.6608 MHz will give accurate
data rates as shown in Table 17 and an IF
frequency of 307.2 kHz. The crystal
frequency will influence the programming
of the CLOCK_A, CLOCK_B and MODEM
registers.
1
CL =
+ Cparasitic
1
1
+
C4 C5
The parasitic capacitance is constituted by
pin input capacitance and PCB stray
capacitance. Total parasitic capacitance is
typically 8 pF. A trimming capacitor may
be placed across C5 for initial tuning if
necessary.
An external clock signal or the internal
crystal oscillator can be used as main
frequency reference. An external clock
signal should be connected to XOSC_Q1,
while XOSC_Q2 should be left open. The
XOSC_BYPASS bit in the INTERFACE
register should be set to ‘1’ when an
external digital rail-to-rail clock signal is
used. No DC block should be used then. A
sine with smaller amplitude can also be
used. A DC blocking capacitor must then
be used (10 nF) and the XOSC_BYPASS
bit in the INTERFACE register should be
set to ‘0’. For input signal amplitude, see
section 4.5 on page 12.
The crystal oscillator circuit is shown in
Figure 33. Typical component values for
different values of CL are given in Table
28.
The crystal oscillator is amplitude
regulated. This means that a high current
is required to initiate the oscillations. When
the amplitude builds up, the current is
reduced to what is necessary to maintain
approximately 600 mVpp amplitude. This
ensures a fast start-up, keeps the drive
level to a minimum and makes the
oscillator insensitive to ESR variations. As
long
as
the
recommended
load
Using the internal crystal oscillator, the
crystal must be connected between the
XOSC_Q1 and XOSC_Q2 pins. The
oscillator is designed for parallel mode
capacitance values are used, the ESR is
not critical.
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CC1020
The initial tolerance, temperature drift,
aging and load pulling should be carefully
specified in order to meet the required
frequency separation, the software will
estimate the total bandwidth and compare
to the available receiver channel filter
bandwidth. The software will report any
contradictions and a more accurate crystal
will be recommended if required.
frequency
accuracy
in
a
certain
application. By specifying the total
expected frequency accuracy in SmartRF®
Studio together with data rate and
XOSC_Q1
XOSC_Q2
XTAL
C4
C5
Figure 33. Crystal oscillator circuit
Item
C4
CL= 12 pF
6.8 pF
CL= 16 pF
15 pF
CL= 22 pF
27 pF
C5
6.8 pF
15 pF
27 pF
Table 28. Crystal oscillator component values
20.
Built-in Test Pattern Generator
number of received ones. Note that the 9
first received bits should be discarded in
this case. Also note that one bit error will
generate 3 received ones.
The CC1020 has a built-in test pattern
generator that generates a PN9 pseudo
random sequence. The PN9_ENABLE bit
in the MODEM register enables the PN9
generator. A transition on the DIO pin is
required after enabling the PN9 pseudo
random sequence.
Transmitting only ones (DIO = 1), the BER
can be tested by counting the number of
received zeroes.
The PN9 pseudo random sequence is
defined by the polynomial x9 + x5 + 1.
The PN9 generator can also be used for
transmission of ‘real-life’ data when
measuring narrowband ACP (Adjacent
Channel Power), modulation bandwidth or
occupied bandwidth.
The PN9 sequence is ‘XOR’ed with the
DIO signal in both TX and RX mode as
shown in Figure 34. Hence, by transmitting
only zeros (DIO = 0), the BER (Bit Error
Rate) can be tested by counting the
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CC1020
Tx pseudo random sequence
Tx out (modulating signal)
Tx data (DIO pin)
XOR
8
7
6
5
4
3
2
1
0
XOR
Rx pseudo random sequence
Rx in (Demodulated Rx data)
8
7
6
5
4
3
2
1
0
XOR
XOR
Rx out (DIO pin)
Figure 34. PN9 pseudo random sequence generator in TX and RX mode
21.
Interrupt on Pin DCLK
21.1. Interrupt upon PLL Lock
In synchronous mode the DCLK pin on
CC1020 can be used to give an interrupt
signal to wake the microcontroller when
the PLL is locked.
logic 0. When this interrupt has been
detected write PD_MODE[1:0] = 00. This
will enable the DCLK signal.
This function can be used to wait for the
PLL to be locked before the PA is ramped
up in transmit mode. In receive mode, it
can be used to wait until the PLL is locked
before searching for preamble.
PD_MODE[1:0] in the MAIN register
should be set to 01. If DCLK_LOCK in the
INTERFACE register is set to 1 the DCLK
signal is always logic high if the PLL is not
in lock. When the PLL locks to the desired
frequency the DCLK signal changes to
21.2. Interrupt upon Received Signal Carrier Sense
In synchronous mode the DCLK pin on
CC1020 can also be used to give an
interrupt signal to the microcontroller when
the RSSI level exceeds a certain threshold
(carrier sense threshold). This function can
be used to wake or interrupt the
microcontroller when a strong signal is
received.
Gating the DCLK signal with the carrier
sense signal makes the interrupt signal.
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CC1020
This function should only be used in
receive mode and is enabled by setting
DCLK_CS = 1 in the INTERFACE register.
that the carrier sense signal is generated
earlier in the receive chain (i.e. before the
demodulator), causing it to be updated 2
bits before the corresponding data is
available on the DIO pin.
The DCLK signal is always logic high
unless carrier sense is indicated. When
carrier sense is indicated the DCLK starts
running. When gating the DCLK signal
with the carrier sense signal at least 2
dummy bits should be added after the data
payload in TX mode. The reason being
In transmit mode DCLK_CS must be set to
0. Refer to CC1020 Errata Note 002.
22.
PA_EN and LNA_EN Digital Output Pins
22.1. Interfacing an External LNA or PA
internal PA is turned on. Otherwise, the
EXT_PA_POL bit controls the PA_EN pin
directly. If EXT_LNA = 1, then the
LNA_EN pin will be activated when the
internal LNA is turned on. Otherwise, the
EXT_LNA_POL bit controls the LNA_EN
pin directly.
CC1020 has two digital output pins, PA_EN
and LNA_EN, which can be used to
control an external LNA or PA. The
functionality of these pins are controlled
through the INTERFACE register. The
outputs can also be used as general digital
output control signals.
These two pins can therefore also be used
as two general control signals, see section
22.2. In the Chipcon reference design
LNA_EN and PA_EN are used to control
the external T/R switch.
EXT_PA_POL and EXT_LNA_POL control
the active polarity of the signals.
EXT_PA and EXT_LNA control the
function of the pins. If EXT_PA = 1, then
the PA_EN pin will be activated when the
22.2. General Purpose Output Control Pins
The two digital output pins, PA_EN and
LNA_EN, can be used as two general
control signals by setting EXT_PA = 0 and
EXT_LNA = 0. The output value is then
set directly by the value written to
EXT_PA_POL and EXT_LNA_POL.
is controlled by LOCK_SELECT[3:0] in the
LOCK register. The LOCK pin is low when
LOCK_SELECT[3:0] = 0000, and high
when LOCK_SELECT[3:0] = 0001.
These features can be used to save I/O
pins on the microcontroller when the other
functions associated with these pins are
not used.
The LOCK pin can also be used as a
general-purpose output pin. The LOCK pin
22.3. PA_EN and LNA_EN Pin Drive
Figure 35 shows the PA_EN and LNA_EN
pin drive currents. The sink and source
currents have opposite signs but absolute
values are used in Figure 35.
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CC1020
1400
1200
1000
800
600
400
200
0
Voltage on PA_EN/LNA_EN pin [V]
source current, 3 V
sink current, 2.3 V
sink current, 3V
source current, 2.3 V
sink current, 3.6 V
source current, 3.6 V
Figure 35. Typical PA_EN and LNA_EN pin drive
23.
System Considerations and Guidelines
SRD regulations
properties for channel spacings down to
12.5 kHz.
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices)
for license free operation are allowed to
operate in the 433 and 868 – 870 MHz
bands in most European countries. In the
United States, such devices operate in the
260 – 470 and 902 – 928 MHz bands. A
summary of the most important aspects of
these regulations can be found in
Application Note AN001 SRD regulations
for license free transceiver operation,
available from the Chipcon web site.
Such narrowband performance normally
requires the use of external ceramic filters.
The CC1020 provides this performance as
a true single-chip solution with integrated
IF filters.
Japan and Korea have allocated several
frequency bands at 424, 426, 429, 447,
449 and 469 MHz for narrowband license
free operation. CC1020 is designed to
meet the requirements for operation in all
these
bands,
including
the
strict
Narrowband systems
requirements for narrowband operation
down to 12.5 kHz channel spacing.
CC1020 is specifically designed for
narrowband systems complying with ARIB
STD T-67 and EN 300 220. The CC1020
meets the strict requirements to ACP
(Adjacent Channel Power) and occupied
bandwidth for a narrowband transmitter.
To meet the ARIB STD T-67 requirements
a 3.0 V regulated voltage supply should be
used.
Due to on-chip complex filtering, the image
frequency is removed. An on-chip
calibration circuit is used to get the best
possible image rejection. A narrowband
preselector filter is not necessary to
achieve image rejection.
A unique feature in CC1020 is the very fine
frequency resolution. This can be used for
temperature compensation of the crystal if
the temperature drift curve is known and a
temperature sensor is included in the
For the receiver side, CC1020 gives very
good ACR (Adjacent Channel Rejection),
image frequency suppression and blocking
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CC1020
system. Even initial adjustment can be
performed using the frequency
High reliability systems
Using a SAW filter as a preselector will
improve the communication reliability in
harsh environments by reducing the
probability of blocking. The receiver
sensitivity and the output power will be
reduced due to the filter insertion loss. By
inserting the filter in the RX path only,
together with an external RX/TX switch,
only the receiver sensitivity is reduced and
output power is remained. The PA_EN
and LNA_EN pin can be configured to
control an external LNA, RX/TX switch or
power amplifier. This is controlled by the
INTERFACE register.
programmability. This eliminates the need
for an expensive TCXO and trimming in
some applications. For more details refer
to Application Note AN027 Temperature
Compensation available from the Chipcon
web site.
In less demanding applications, a crystal
with low temperature drift and low aging
could
be
used
without
further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C5)
could be used to set the initial frequency
accurately.
Frequency hopping spread spectrum
systems (FHSS)
The
frequency
offset
between
a
transmitter and receiver is measured in the
CC1020 and can be read back from the
AFC register. The measured frequency
offset can be used to calibrate the receiver
frequency using the transmitter as the
reference. For more details refer to
Application Note AN029 CC1020/1021
AFC available from the Chipcon web site.
Due to the very fast locking properties of
the PLL, the CC1020 is also very suitable
for frequency hopping systems. Hop rates
of 1-100 hops/s are commonly used
depending on the bit rate and the amount
of data to be sent during each
transmission. The two frequency registers
(FREQ_A and FREQ_B) are designed
such that the ‘next’ frequency can be
programmed while the ‘present’ frequency
is used. The switching between the two
frequencies is done through the MAIN
register. Several features have been
included to do the hopping without a need
to re-synchronize the receiver. For more
details refer to Application Note AN014
Frequency Hopping Systems available
from the Chipcon web site.
CC1020 also has the possibility to use
Gaussian shaped FSK (GFSK). This
spectrum-shaping
feature
improves
adjacent channel power (ACP) and
occupied bandwidth. In ‘true’ FSK systems
with abrupt frequency shifting, the
spectrum is inherently broad. By making
the frequency shift ‘softer’, the spectrum
can be made significantly narrower. Thus,
higher data rates can be transmitted in the
same bandwidth using GFSK.
In order to implement a frequency hopping
system with CC1020 do the following:
Low cost systems
Set the desired frequency, calibrate and
store the following register settings in non-
volatile memory:
As the CC1020 provides true narrowband
multi-channel performance without any
external filters, a very low cost high
performance system can be achieved. The
oscillator crystal can then be a low cost
crystal with 50 ppm frequency tolerance
using the on-chip frequency tuning
possibilities.
STATUS1[3:0]: CHP_CURRENT[3:0]
STATUS2[4:0]: VCO_ARRAY[4:0]
STATUS3[5:0]:VCO_CAL_CURRENT[5:0]
Repeat the calibration for each desired
frequency. VCO_CAL_CURRENT[5:0] is
not dependent on the RF frequency and
the same value can be used for all
frequencies.
Battery operated systems
In low power applications, the power down
mode should be used when CC1020 is not
being active. Depending on the start-up
time requirement, the oscillator core can
be powered during power down. See
section 17 on page 54 for information on
how effective power management can be
implemented.
When performing frequency hopping, write
the stored values to the corresponding
TEST1, TEST2 and TEST3 registers, and
enable override:
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CC1020
TEST1[3:0]: CHP_CO[3:0]
TEST2[4:0]: VCO_AO[4:0]
TEST2[5]: VCO_OVERRIDE
TEST2[6]: CHP_OVERRIDE
TEST3[5:0]: VCO_CO[5:0]
TEST3[6]: VCO_CAL_OVERRIDE
MAIN[6]). The channel 2 frequency can be
set by register FREQ_B which can be
written to while operating on channel 1.
The calibration data must be written to the
TEST1-3 registers after switching to the
next frequency. That is, when hopping to a
new channel write to register MAIN[6] first
and the test registers next. The PA should
be switched off between each hop and the
PLL should be checked for lock before
switching the PA back on after a hop has
been performed.
CHP_CO[3:0] is the register setting read
from CHP_CURRENT[3:0], VCO_AO[4:0]
is
VCO_ARRAY[4:0] and VCO_CO[5:0] is
the register setting read from
VCO_CAL_CURRENT[5:0].
the register setting read from
Note
that
the
override
bits
Assume channel 1 defined by register
FREQ_A is currently being used and that
CC1020 should operate on channel 2 next
(to change channel simply write to register
VCO_OVERRIDE, CHP_OVERRIDE and
VCO_CAL_OVERRIDE must be disabled
when performing a re-calibration.
24.
PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be
filled with metallization connected to
ground using several vias.
very important, especially for pins 23, 22,
20 and 18.
Each decoupling capacitor ground pad
should be connected to the ground plane
using a separate via. Direct connections
between neighboring power pins will
increase noise coupling and should be
avoided unless absolutely necessary.
The area under the chip is used for
grounding and must be connected to the
bottom ground plane with several vias. In
the Chipcon reference designs we have
placed 9 vias inside the exposed die
attached pad. These vias should be
“tented” (covered with solder mask) on the
component side of the PCB to avoid
migration of solder through the vias during
the solder reflow process.
The external components should ideally
be as small as possible and surface mount
devices are highly recommended.
Precaution should be used when placing
the microcontroller in order to avoid noise
interfering with the RF circuitry.
Each decoupling capacitor should be
placed as close as possible to the supply
pin it is supposed to decouple. Each
decoupling capacitor should be connected
to the power line (or power plane) by
separate vias. The best routing is from the
power line (or power plane) to the
decoupling capacitor and then to the
CC1020 supply pin. Supply power filtering is
A CC1020/1070DK Development Kit with
a fully assembled CC1020EMX Evaluation
Module is available. It is strongly advised
that this reference layout is followed very
closely in order to get the best
performance. The layout Gerber files are
available from the Chipcon web site.
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CC1020
25.
Antenna Considerations
difficult impedance matching because of
their very low radiation resistance.
CC1020 can be used together with various
types of antennas. The most common
antennas for short-range communication
are monopole, helical and loop antennas.
For low power applications the λ/4-
monopole antenna is recommended due
to its simplicity as well as providing the
best range.
Monopole
antennas
are
resonant
antennas with a length corresponding to
one quarter of the electrical wavelength
(λ/4). They are very easy to design and
can be implemented simply as a “piece of
wire” or even integrated onto the PCB.
The length of the λ/4-monopole antenna is
given by:
L = 7125 / f
Non-resonant monopole antennas shorter
than λ/4 can also be used, but at the
expense of range. In size and cost critical
applications such an antenna may very
well be integrated onto the PCB.
where f is in MHz, giving the length in cm.
An antenna for 868 MHz should be 8.2
cm, and 16.4 cm for 433 MHz.
The antenna should be connected as
close as possible to the IC. If the antenna
is located away from the input pin the
antenna should be matched to the feeding
transmission line (50 Ω).
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in
size critical applications. But helical
antennas tend to be more difficult to
optimize than the simple monopole.
For a more thorough background on
antennas, please refer to Application Note
AN003 SRD Antennas available from the
Chipcon web site.
Loop antennas are easy to integrate into
the PCB, but are less effective due to
26.
Configuration Registers
RESET, and should not be altered by the
user.
The configuration of CC1020 is done by
programming the 8-bit configuration
registers. The configuration data based on
selected system parameters are most
easily found by using the SmartRF® Studio
software. Complete descriptions of the
registers are given in the following tables.
After a RESET is programmed, all the
registers have default values. The TEST
registers also get default values after a
Chipcon recommends using the register
settings found using the SmartRF® Studio
software. These are the register settings
that Chipcon can guarantee across
temperature, voltage and process. Please
check the Chipcon web site for regularly
updates to the SmartRF® Studio software.
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CC1020
26.1. CC1020 Register Overview
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
Byte Name
Description
Main control register
Interface control register
Digital module reset register
Automatic power-up sequencing control register
Frequency register 2A
Frequency register 1A
Frequency register 0A
Clock generation register A
Frequency register 2B
Frequency register 1B
MAIN
INTERFACE
RESET
SEQUENCING
FREQ_2A
FREQ_1A
FREQ_0A
CLOCK_A
FREQ_2B
FREQ_1B
FREQ_0B
CLOCK_B
VCO
Frequency register 0B
Clock generation register B
VCO current control register
Modem control register
TX frequency deviation register
RX AFC control register
Channel filter / RSSI control register
VGA control register 1
VGA control register 2
VGA control register 3
VGA control register 4
Lock control register
Front end bias current control register
Analog modules control register
LO buffer and prescaler swing control register
MODEM
DEVIATION
AFC_CONTROL
FILTER
VGA1
VGA2
VGA3
VGA4
LOCK
FRONTEND
ANALOG
BUFF_SWING
BUFF_CURRENT LO buffer and prescaler bias current control register
PLL_BW
CALIBRATE
PA_POWER
MATCH
PHASE_COMP
GAIN_COMP
POWERDOWN
TEST1
PLL loop bandwidth / charge pump current control register
PLL calibration control register
Power amplifier output power register
Match capacitor array control register, for RX and TX impedance matching
Phase error compensation control register for LO I/Q
Gain error compensation control register for mixer I/Q
Power-down control register
Test register for overriding PLL calibration
Test register for overriding PLL calibration
Test register for overriding PLL calibration
Test register for charge pump and IF chain testing
Test register for ADC testing
Test register for VGA testing
Test register for VGA testing
Status information register (PLL lock, RSSI, calibration ready, etc.)
Status register for digital module reset
Received signal strength register
Average received frequency deviation from IF (can be used for AFC)
Digital FM demodulator register
Status of PLL calibration results etc. (test only)
Status of PLL calibration results etc. (test only)
Status of PLL calibration results etc. (test only)
Status of ADC signals (test only)
Status of channel filter “I” signal (test only)
Status of channel filter “Q” signal (test only)
Status of AGC (test only)
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
STATUS
RESET_DONE
RSSI
AFC
GAUSS_FILTER
STATUS1
STATUS2
STATUS3
STATUS4
STATUS5
STATUS6
STATUS7
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CC1020
MAIN Register (00h)
REGISTER
NAME
Default
Active
Description
value
MAIN[7]
MAIN[6]
RXTX
F_REG
-
-
-
-
RX/TX switch, 0: RX , 1: TX
Selection of Frequency Register,
0: Register A, 1: Register B
Power down mode
MAIN[5:4]
PD_MODE[1 :0]
-
-
0 (00): Receive Chain in power-down in TX, PA in power-down in
RX
1 (01): Receive Chain and PA in power-down in both TX and RX
2 (10): Individual modules can be put in power-down by
programming the POWERDOWN register
3 (11): Automatic power-up sequencing is activated (see below)
MAIN[3]
MAIN[2]
MAIN[1]
FS_PD
XOSC_PD
BIAS_PD
-
-
-
H
H
H
Power Down of Frequency Synthesizer
Power Down of Crystal Oscillator Core
Power Down of BIAS (Global Current Generator) and Crystal
Oscillator Buffer
MAIN[0]
RESET_N
-
L
Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11)
REGISTER
NAME
Default
Active
Description
value
MAIN[7]
MAIN[6]
MAIN[5 :4]
MAIN[3:2]
RXTX
F_REG
PD_MODE[1 :0]
SEQ_CAL[1:0]
-
-
-
-
-
-
H
-
Automatic power-up sequencing only works in RX (RXTX=0)
Selection of Frequency Register, 0: Register A, 1: Register B
Set PD_MODE[1:0]=3 (11) to enable sequencing
Controls PLL calibration before re-entering power-down
0: Never perform PLL calibration as part of sequence
1: Always perform PLL calibration at end of sequence
2: Perform PLL calibration at end of every 16th sequence
3: Perform PLL calibration at end of every 256th sequence
MAIN[1]
MAIN[0]
SEQ_PD
-
-
↑
↑1: Put the chip in power down and wait for start of new power-up
sequence
Reset, active low. Writing RESET_N low will write default values to
all other registers than MAIN. Bits in MAIN do not have a default
value and will be written directly through the configuration
interface. Must be set high to complete reset.
RESET_N
L
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CC1020
INTERFACE Register (01h)
REGISTER
NAME
Default
value
0
Active
H
Description
INTERFACE[7]
XOSC_BYPASS
Bypass internal crystal oscillator, use external clock
0: Internal crystal oscillator is used, or external sine wave fed
through a coupling capacitor
1: Internal crystal oscillator in power down, external clock
with rail-to-rail swing is used
INTERFACE[6]
SEP_DI_DO
0
H
Use separate pin for RX data output
0: DIO is data output in RX and data input in TX. LOCK pin
is available (Normal operation).
1: DIO is always input, and a separate pin is used for RX
data output (synchronous mode: LOCK pin, asynchronous
mode: DCLK pin).
If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING
register then negative transitions on DIO is used to start
power-up sequencing when PD_MODE=3 (power-up
sequencing is enabled).
INTERFACE[5]
INTERFACE[4]
DCLK_LOCK
DCLK_CS
0
0
H
H
Gate DCLK signal with PLL lock signal in synchronous mode
Only applies when PD_MODE = “01”
0: DCLK is always 1
1: DCLK is always 1 unless PLL is in lock
Gate DCLK signal with carrier sense indicator in
synchronous mode
Use when receive chain is active (in power-up)
Always set to 0 in TX mode.
0: DCLK is independent of carrier sense indicator.
1: DCLK is always 1 unless carrier sense is indicated
Use PA_EN pin to control external PA
0: PA_EN pin always equals EXT_PA_POL bit
1: PA_EN pin is asserted when internal PA is turned on
Use LNA_EN pin to control external LNA
0: LNA_EN pin always equals EXT_LNA_POL bit
1: LNA_EN pin is asserted when internal LNA is turned on
Polarity of external PA control
INTERFACE[3]
INTERFACE[2]
INTERFACE[1]
INTERFACE[0]
EXT_PA
EXT_LNA
0
0
0
0
H
H
H
H
EXT_PA_POL
EXT_LNA_POL
0: PA_EN pin is “0” when activating external PA
1: PA_EN pin is “1” when activating external PA
Polarity of external LNA control
0: LNA_EN pin is “0” when activating external LNA
1: LNA_EN pin is “1” when activating external LNA
Note: If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test
module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1
and TEST_MODE[2:0]=001.
RESET Register (02h)
REGISTER
NAME
Default
Active
Description
value
RESET[7]
RESET[6]
RESET[5]
RESET[4]
RESET[3]
ADC_RESET_N
AGC_RESET_N
GAUSS_RESET_N
AFC_RESET_N
0
0
0
0
0
L
L
L
L
L
Reset ADC control logic
Reset AGC (VGA control) logic
Reset Gaussian data filter
Reset AFC / FSK decision level logic
Reset modulator, bit synchronization logic and PN9
PRBS generator
BITSYNC_RESET_N
RESET[2]
RESET[1]
RESET[0]
SYNTH_RESET_N
SEQ_RESET_N
CAL_LOCK_RESET_N
0
0
0
L
L
L
Reset digital part of frequency synthesizer
Reset power-up sequencing logic
Reset calibration logic and lock detector
Note: For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be
used during normal operation.
Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant
digital clocks must be running for the resetting to complete. After writing to the RESET register, the user
should verify that all reset operations have been completed, by reading the RESET_DONE status
register (41h) until all bits equal 1.
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CC1020
SEQUENCING Register (03h)
REGISTER
NAME
Default
value
1
Active
H
Description
SEQUENCING[7]
SEQ_PSEL
Use PSEL pin to start sequencing
0: PSEL pin does not start sequencing. Negative
transitions on DIO starts power-up sequencing if
SEP_DI_DO=1.
1: Negative transitions on the PSEL pin will start power-
up sequencing
SEQUENCING[6:4]
RX_WAIT[2:0]
0
-
Waiting time from PLL enters lock until RX power-up
0: Wait for approx. 32 ADC_CLK periods (26 µs)
1: Wait for approx. 44 ADC_CLK periods (36 µs)
2: Wait for approx. 64 ADC_CLK periods (52 µs)
3: Wait for approx. 88 ADC_CLK periods (72 µs)
4: Wait for approx. 128 ADC_CLK periods (104 µs)
5: Wait for approx. 176 ADC_CLK periods (143 µs)
6: Wait for approx. 256 ADC_CLK periods (208 µs)
7: No additional waiting time before RX power-up
Waiting time for carrier sense from RX power-up
0: Wait 20 FILTER_CLK periods before power down
1: Wait 22 FILTER_CLK periods before power down
2: Wait 24 FILTER_CLK periods before power down
3: Wait 26 FILTER_CLK periods before power down
4: Wait 28 FILTER_CLK periods before power down
5: Wait 30 FILTER_CLK periods before power down
6: Wait 32 FILTER_CLK periods before power down
7: Wait 36 FILTER_CLK periods before power down
8: Wait 40 FILTER_CLK periods before power down
9: Wait 44 FILTER_CLK periods before power down
10: Wait 48 FILTER_CLK periods before power down
11: Wait 52 FILTER_CLK periods before power down
12: Wait 56 FILTER_CLK periods before power down
13: Wait 60 FILTER_CLK periods before power down
14: Wait 64 FILTER_CLK periods before power down
15: Wait 72 FILTER_CLK periods before power down
SEQUENCING[3:0]
CS_WAIT[3:0]
10
-
FREQ_2A Register (04h)
REGISTER
NAME
Default
value
131
Active
-
Description
FREQ_2A[7:0]
FREQ_A[22:15]
8 MSB of frequency control word A
FREQ_1A Register (05h)
REGISTER
NAME
Default
value
177
Active
-
Description
FREQ_1A[7:0]
FREQ_A[14:7]
Bit 15 to 8 of frequency control word A
FREQ_0A Register (06h)
REGISTER
NAME
Default
value
124
Active
Description
FREQ_0A[7:1]
FREQ_0A[0]
FREQ_A[6:0]
DITHER_A
-
H
7 LSB of frequency control word A
Enable dithering for frequency A
1
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CC1020
CLOCK_A Register (07h)
REGISTER
NAME
Default
value
2
Active
-
Description
CLOCK_A[7:5]
REF_DIV_A[2:0]
Reference frequency divisor (A):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
It is recommended to use the highest possible reference
clock frequency that allows the desired Baud rate.
Modem clock divider 1 (A):
0: Divide by 2.5
CLOCK_A[4:2]
MCLK_DIV1_A[2:0]
4
-
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
Modem clock divider 2 (A):
0: Divide by 1
CLOCK_A[1:0]
MCLK_DIV2_A[1:0]
0
-
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
FREQ_2B Register (08h)
REGISTER
NAME
Default
value
131
Active
-
Description
FREQ_2B[7:0]
FREQ_B[22:15]
8 MSB of frequency control word B
FREQ_1B Register (09h)
REGISTER
NAME
Default
value
189
Active
-
Description
FREQ_1B[7:0]
FREQ_B[14:7]
Bit 15 to 8 of frequency control word B
FREQ_0B Register (0Ah)
REGISTER
NAME
Default
value
124
Active
Description
FREQ_0B[7:1]
FREQ_0B[0]
FREQ_B[6:0]
DITHER_B
-
H
7 LSB of frequency control word B
Enable dithering for frequency B
1
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CC1020
CLOCK_B Register (0Bh)
REGISTER
NAME
Default
value
2
Active
-
Description
CLOCK_B[7:5]
REF_DIV_B[2:0]
Reference frequency divisor (B):
0: Not supported
1: REF_CLK frequency = Crystal frequency / 2
…
7: REF_CLK frequency = Crystal frequency / 8
Modem clock divider 1 (B):
0: Divide by 2.5
CLOCK_B[4:2]
MCLK_DIV1_B[2:0]
4
-
1: Divide by 3
2: Divide by 4
3: Divide by 7.5 (2.5·3)
4: Divide by 12.5 (2.5·5)
5: Divide by 40 (2.5·16)
6: Divide by 48 (3·16)
7: Divide by 64 (4·16)
Modem clock divider 2 (B):
0: Divide by 1
CLOCK_B[1:0]
MCLK_DIV2_B[1:0]
0
-
1: Divide by 2
2: Divide by 4
3: Divide by 8
MODEM_CLK frequency is FREF frequency divided by
the product of divider 1 and divider 2.
Baud rate is MODEM_CLK frequency divided by 8.
VCO Register (0Ch)
REGISTER
NAME
Default
value
Active
-
Description
VCO[7 :4]
VCO_CURRENT_A[3:0]
8
Control of current in VCO core for frequency A
0 : 1.4 mA current in VCO core
1 : 1.8 mA current in VCO core
2 : 2.1 mA current in VCO core
3 : 2.5 mA current in VCO core
4 : 2.8 mA current in VCO core
5 : 3.2 mA current in VCO core
6 : 3.5 mA current in VCO core
7 : 3.9 mA current in VCO core
8 : 4.2 mA current in VCO core
9 : 4.6 mA current in VCO core
10 : 4.9 mA current in VCO core
11 : 5.3 mA current in VCO core
12 : 5.6 mA current in VCO core
13 : 6.0 mA current in VCO core
14 : 6.4 mA current in VCO core
15 : 6.7 mA current in VCO core
Recommended setting: VCO_CURRENT_A=4
Control of current in VCO core for frequency B
The current steps are the same as for
VCO_CURRENT_A
VCO[3:0]
VCO_CURRENT_B[3:0]
8
-
Recommended setting: VCO_CURRENT_B=4
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CC1020
MODEM Register (0Dh)
REGISTER
NAME
-
Default
value
Active
Description
MODEM[7]
0
3
-
-
Reserved, write 0
ADC clock divisor
0: Not supported
MODEM[6:4]
ADC_DIV[2:0]
1: ADC frequency = XOSC frequency / 4
2: ADC frequency = XOSC frequency / 6
3: ADC frequency = XOSC frequency / 8
4: ADC frequency = XOSC frequency / 10
5: ADC frequency = XOSC frequency / 12
6: ADC frequency = XOSC frequency / 14
7: ADC frequency = XOSC frequency / 16
Note that the intermediate frequency should be as close
to 307.2 kHz as possible. ADC clock frequency is always
4 times the intermediate frequency and should therefore
be as close to 1.2288 MHz as possible.
Reserved, write 0
MODEM[3]
MODEM[2]
-
0
0
-
H
PN9_ENABLE
Enable scrambling of TX and RX with PN9 pseudo-
random bit sequence
0: PN9 scrambling is disabled
1: PN9 scrambling is enabled (x9+x5+1)
The PN9 pseudo-random bit sequence can be used for
BER testing by only transmitting zeros, and then
counting the number of received ones.
Modem data format
MODEM[1:0]
DATA_FORMAT[1:0]
0
-
0 (00): NRZ operation
1 (01): Manchester operation
2 (10): Transparent asynchronous UART operation, set
DCLK=0
3 (11): Transparent asynchronous UART operation, set
DCLK=1
DEVIATION Register (0Eh)
REGISTER
NAME
Default
value
Active
H
Description
DEVIATION[7]
TX_SHAPING
1
Enable Gaussian shaping of transmitted data
Recommended setting: TX_SHAPING=1
Transmit frequency deviation exponent
Transmit frequency deviation mantissa
DEVIATION[6 :4]
DEVIATION [3 :0]
TXDEV_X[2 :0]
TXDEV_M[3 :0]
6
8
-
-
Deviation in 402-470 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−16)
Deviation in 804-940 MHz band:
FREF ·TXDEV_M ·2(TXDEV_X−15)
On-off-keying (OOK) is used in RX/TX if TXDEV_M[3:0]=0
To find TXDEV_M given the deviation and TXDEV_X:
TXDEV_M = deviation·2(16−TXDEV_X)/FREF
in 402-470 MHz band,
TXDEV_M = deviation·2(15−TXDEV_X)/FREF
in 804-940 MHz band.
Decrease TXDEV_X and try again if TXDEV_M < 8.
Increase TXDEV_X and try again if TXDEV_M ≥ 16.
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CC1020
AFC_CONTROL Register (0Fh)
REGISTER
NAME
Default
value
2
Active
-
Description
AFC_CONTROL[7:6]
SETTLING[1:0]
Controls AFC settling time versus accuracy
0: AFC off; zero average frequency is used in demodulator
1: Fastest settling; frequency averaged over 1 0/1 bit pair
2: Medium settling; frequency averaged over 2 0/1 bit pairs
3: Slowest settling; frequency averaged over 4 0/1 bit pairs
Recommended setting: AFC_CONTROL=3 for higher
accuracy unless it is essential to have the fastest settling
time when transmission starts after RX is activated.
RX frequency deviation exponent
AFC_CONTROL[5:4]
AFC_CONTROL[3:0]
RXDEV_X[1:0]
RXDEV_M[3:0]
1
12
-
-
RX frequency deviation mantissa
Expected RX deviation should be:
Baud rate · RXDEV_M ·2(RXDEV_X−3) / 3
To find RXDEV_M given the deviation and RXDEV_X:
RXDEV_M = 3 · deviation ·2(3−RXDEV_X) / Baud rate
Decrease RXDEV_X and try again if RXDEV_M<8.
Increase RXDEV_X and try again if RXDEV_M≥16.
Note: The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100
kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation
for FSK and for GFSK at 100 kBaud data rate and above.
FILTER Register (10h)
REGISTER
NAME
Default
value
0
Active
H
Description
FILTER[7]
FILTER_BYPASS
Bypass analog image rejection / anti-alias filter. Set to 1 for
increased dynamic range at high Baud rates.
Recommended setting:
FILTER_BYPASS=0 below 76.8 kBaud,
FILTER_BYPASS=1 for 76.8 kBaud and up.
Number of extra bits to shift decimator input
(may improve filter accuracy and lower power consumption).
FILTER[6:5]
DEC_SHIFT[1:0]
0
-
Recommended settings:
DEC_SHIFT=0 when DEC_DIV ≤1 (receiver channel bandwidth
≥ 153.6 kHz),
DEC_SHIFT=1 when optimized sensitivity and 1< DEC_DIV <
24 (12.29 kHz < receiver channel bandwidth < 153.6 kHz),
DEC_SHIFT=2 when optimized selectivity and DEC_DIV ≥ 24
(receiver channel bandwidth ≤12.29 kHz)
FILTER[4:0]
DEC_DIV[4:0]
0
-
Decimation clock divisor
0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.
1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.
…
30: Decimation clock divisor = 31, 9.91 kHz channel filter BW.
31: Decimation clock divisor = 32, 9.6 kHz channel filter BW.
Channel filter bandwidth is 307.2 kHz divided by the decimation
clock divisor.
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CC1020
VGA1 Register (11h)
REGISTER
NAME
Default
value
1
Active
-
Description
VGA1[7 :6]
CS_SET[1:0]
Sets the number of consecutive samples at or above carrier
sense level before carrier sense is indicated (e.g. on LOCK
pin)
0: Set carrier sense after first sample at or above carrier sense
level
1: Set carrier sense after second sample at or above carrier
sense level
2: Set carrier sense after third sample at or above carrier
sense level
3: Set carrier sense after fourth sample at or above carrier
sense level
Increasing CS_SET reduces the number of “false” carrier
sense events due to noise at the expense of increased carrier
sense response time.
VGA1[5]
CS_RESET
1
-
Sets the number of consecutive samples below carrier sense
level before carrier sense indication (e.g. on lock pin) is reset
0: Carrier sense is reset after first sample below carrier sense
level
1: Carrier sense is reset after second sample below carrier
sense level
Recommended setting: CS_RESET=1 in order to reduce the
chance of losing carrier sense due to noise.
VGA1[4 :2]
VGA_WAIT[2 :0]
1
-
Controls how long AGC, bit synchronization, AFC and RSSI
levels are frozen after VGA gain is changed when frequency is
changed between A and B or PLL has been out of lock or after
RX power-up
0: Freeze operation for 16 filter clocks, 8/(filter BW) seconds
1: Freeze operation for 20 filter clocks, 10/(filter BW) seconds
2: Freeze operation for 24 filter clocks, 12/(filter BW) seconds
3: Freeze operation for 28 filter clocks, 14/(filter BW) seconds
4: Freeze operation for 32 filter clocks, 16/(filter BW) seconds
5: Freeze operation for 40 filter clocks, 20/(filter BW) seconds
6: Freeze operation for 48 filter clocks, 24/(filter BW) seconds
7: Freeze present levels unconditionally
VGA1[1:0]
VGA_FREEZE[1:0]
1
-
Controls the additional time AGC, bit synchronization, AFC
and RSSI levels are frozen when frequency is changed
between A and B or PLL has been out of lock or after RX
power-up
0: Freeze levels for approx. 16 ADC_CLK periods (13 µs)
1: Freeze levels for approx. 32 ADC_CLK periods (26 µs)
2: Freeze levels for approx. 64 ADC_CLK periods (52 µs)
3: Freeze levels for approx. 128 ADC_CLK periods (104 µs)
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CC1020
VGA2 Register (12h)
REGISTER
NAME
Default
value
0
Active
-
Description
VGA2[7]
LNA2_MIN
Minimum LNA2 setting used in VGA
0: Minimum LNA2 gain
1: Medium LNA2 gain
Recommended setting: LNA2_MIN=0 for best selectivity.
Maximum LNA2 setting used in VGA
0: Medium LNA2 gain
VGA2[6]
LNA2_MAX
1
3
-
-
1: Maximum LNA2 gain
Recommended setting: LNA2_MAX=1 for best sensitivity.
Selects at what VGA setting the LNA gain should be
changed
VGA2[5:4]
LNA2_SETTING[1:0]
0: Apply LNA2 change below min. VGA setting.
1: Apply LNA2 change at approx. 1/3 VGA setting (around
VGA setting 10).
2: Apply LNA2 change at approx. 2/3 VGA setting (around
VGA setting 19).
3: Apply LNA2 change above max. VGA setting.
Recommended setting:
LNA2_SETTING=0 if VGA_SETTING<10,
LNA2_SETTING=1 otherwise.
If LNA2_MIN=1 and LNA2_MAX=0, then the LNA2 setting is
controlled by LNA2_SETTING:
0: Between medium and maximum LNA2 gain
1: Minimum LNA2 gain
2: Medium LNA2 gain
3: Maximum LNA2 gain
VGA2[3]
VGA2[2]
AGC_DISABLE
0
1
H
H
Disable AGC
0: AGC is enabled
1: AGC is disabled (VGA_SETTING determines VGA gain)
Recommended setting: AGC_DISABLE=0 for good dynamic
range.
Enable AGC hysteresis
AGC_HYSTERESIS
0: No hysteresis. Immediate gain change for smallest
up/down step
1: Hysteresis enabled. Two samples in a row must indicate
gain change for smallest up/down step
Recommended setting: AGC_HYSTERESIS=1.
Sets how many samples that are used to calculate average
output magnitude for AGC/RSSI.
VGA2[1:0]
AGC_AVG[1:0]
1
-
0: Magnitude is averaged over 2 filter output samples
1: Magnitude is averaged over 4 filter output samples
2: Magnitude is averaged over 8 filter output samples
3: Magnitude is averaged over 16 filter output samples
Recommended setting: AGC_AVG=1.
For best AGC/RSSI accuracy AGC_AVG=3.
For automatic power-up sequencing, the AGC_AVG and
CS_SET values must be chosen so that carrier sense is
available in time to be detected before the chip re-enters
power-down.
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CC1020
VGA3 Register (13h)
REGISTER
NAME
Default
value
1
Active
-
Description
VGA3[7 :5]
VGA_DOWN[2:0]
Decides how much the signal strength must be above
CS_LEVEL+VGA_UP before VGA gain is decreased.
0: Gain is decreased 4.5 dB above CS_LEVEL+VGA_UP
1: Gain is decreased 6 dB above CS_LEVEL+VGA_UP
…
6: Gain is decreased 13.5 dB above CS_LEVEL+VGA_UP
7: Gain is decreased 15 dB above CS_LEVEL+VGA_UP
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
VGA setting to be used when receive chain is turned on
This is also the maximum gain that the AGC is allowed to use.
VGA3[4:0]
VGA_SETTING[4:0]
24
H
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
VGA4 Register (14h)
REGISTER
NAME
Default
value
1
Active
-
Description
VGA4[7 :5]
VGA_UP[2:0]
Decides the level where VGA gain is increased if it is not
already at the maximum set by VGA_SETTING.
0: Gain is increased when signal is below CS_LEVEL
1: Gain is increased when signal is below CS_LEVEL+1.5 dB
…
6: Gain is increased when signal is below CS_LEVEL+9 dB
7: Gain is increased when signal below CS_LEVEL+10.5 dB
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
Reference level for Received Signal Strength Indication
(carrier sense level) and AGC.
VGA4[4:0]
CS_LEVEL[4:0]
24
H
See Figure 18 on page 38 for an explanation of the
relationship between RSSI, AGC and carrier sense settings.
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CC1020
LOCK Register (15h)
REGISTER
NAME
Default
value
0
Active
-
Description
LOCK[7:4]
LOCK_SELECT[3:0]
Selection of signals to LOCK pin
0: Set to 0
1: Set to 1
2: LOCK_CONTINUOUS (active low)
3: LOCK_INSTANT (active low)
4: CARRIER_SENSE (RSSI above threshold, active low)
5: CAL_COMPLETE (active low)
6: SEQ_ERROR (active low)
7: FXOSC
8: REF_CLK
9: FILTER_CLK
10: DEC_CLK
11: PRE_CLK
12: DS_CLK
13: MODEM_CLK
14: VCO_CAL_COMP
15: F_COMP
LOCK[3]
LOCK[2]
WINDOW_WIDTH
LOCK_MODE
0
0
0
-
-
-
Selects lock window width
0: Lock window is 2 prescaler clock cycles wide
1: Lock window is 4 prescaler clock cycles wide
Recommended setting: WINDOW_WIDTH=0.
Selects lock detector mode
0: Counter restart mode
1: Up/Down counter mode
Recommended setting: LOCK_MODE=0.
LOCK[1:0]
LOCK_ACCURACY[1:0]
Selects lock accuracy (counter threshold values)
0: Declare lock at counter value 127, out of lock at value 111
1: Declare lock at counter value 255, out of lock at value 239
2: Declare lock at counter value 511, out of lock at value 495
3: Declare lock at counter value 1023, out of lock at value
1007
Note: Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator.
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CC1020
FRONTEND Register (16h)
REGISTER
NAME
Default
value
2
Active
-
Description
FRONTEND[7:6]
LNAMIX_CURRENT[1:0]
Controls current in LNA, LNA2 and mixer
Recommended setting: LNAMIX_CURRENT=1
Controls current in the LNA
FRONTEND[5:4]
LNA_CURRENT[1 :0]
1
-
Recommended setting: LNA_CURRENT=3.
Can be lowered to save power at the expense of
reduced sensitivity.
FRONTEND[3]
FRONTEND[2]
FRONTEND[1]
FRONTEND[0]
MIX_CURRENT
LNA2_CURRENT
SDC_CURRENT
LNAMIX_BIAS
0
0
0
1
-
-
-
-
Controls current in the mixer
Recommended setting:
MIX_CURRENT=1 at 426-464 MHz,
MIX_CURRENT=0 at 852-928 MHz.
Controls current in LNA 2
Recommended settings:
LNA2_CURRENT=0 at 426-464 MHz,
LNA2_CURRENT=1 at 852-928 MHz.
Controls current in the single-to-diff. Converter
Recommended settings:
SDC_CURRENT=0 at 426-464 MHz,
SDC_CURRENT=1 at 852-928 MHz.
Controls how front-end bias currents are generated
0: Constant current biasing
1: Constant Gm·R biasing (reduces gain variation)
Recommended setting: LNAMIX_BIAS=0.
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CC1020
ANALOG Register (17h)
REGISTER
NAME
Default
value
1
Active
-
Description
ANALOG[7]
ANALOG[6]
BANDSELECT
Frequency band selection
0: 402-470 MHz band
1: 804-940 MHz band
Lower LO DC level to mixers
0: High LO DC level to mixers
1: Low LO DC level to mixers
LO_DC
1
-
Recommended settings:
LO_DC=1 for 402-470 MHz,
LO_DC=0 for 804-940 MHz.
ANALOG[5]
ANALOG[4]
VGA_BLANKING
1
H
Enable analog blanking switches in VGA when
changing VGA gain.
0: Blanking switches are disabled
1: Blanking switches are turned on for approx.
0.8µs when gain is changed (always on if
AGC_DISABLE=1)
Recommended setting: VGA_BLANKING=0.
Selects short or long reset delay in phase
detector
PD_LONG
0
H
0: Short reset delay
1: Long reset delay
Recommended setting: PD_LONG=0.
Reserved, write 0
Boost PA bias current for higher output power
ANALOG[3]
ANALOG[2]
-
0
0
-
H
PA_BOOST
Recommended setting: PA_BOOST=1.
Overall bias current adjustment for VCO divider
and buffers
ANALOG[1:0]
DIV_BUFF_CURRENT[1:0]
3
-
0: 4/6 of nominal VCO divider and buffer current
1: 4/5 of nominal VCO divider and buffer current
2: Nominal VCO divider and buffer current
3: 4/3 of nominal VCO divider and buffer current
Recommended setting:
DIV_BUFF_CURRENT=3
BUFF_SWING Register (18h)
REGISTER
NAME
Default
value
Active
-
Description
BUFF_SWING[7:6]
PRE_SWING[1:0]
3
Prescaler swing.
0: 2/3 of nominal swing
1: 1/2 of nominal swing
2: 4/3 of nominal swing
3: Nominal swing
Recommended setting: PRE_SWING=0.
LO buffer swing, in RX (to mixers)
0: Smallest load resistance (smallest swing)
…
BUFF_SWING[5:3]
BUFF_SWING[2:0]
RX_SWING[2:0]
TX_SWING[2:0]
4
1
-
-
7: Largest load resistance (largest swing)
Recommended setting: RX_SWING=2.
LO buffer swing, in TX (to power amplifier driver)
0: Smallest load resistance (smallest swing)
…
7: Largest load resistance (largest swing)
Recommended settings:
TX_SWING=4 for 402-470 MHz,
TX_SWING=0 for 804-940 MHz.
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CC1020
BUFF_CURRENT Register (19h)
REGISTER
NAME
Default
value
1
Active
-
Description
BUFF_CURRENT[7:6]
PRE_CURRENT[1:0]
Prescaler current scaling
0: Nominal current
1: 2/3 of nominal current
2: 1/2 of nominal current
3: 2/5 of nominal current
Recommended setting: PRE_CURRENT=0.
LO buffer current, in RX (to mixers)
0: Minimum buffer current
…
BUFF_CURRENT[5:3]
BUFF_CURRENT[2:0]
RX_CURRENT[2:0]
TX_CURRENT[2:0]
4
5
-
-
7: Maximum buffer current
Recommended setting: RX_CURRENT=4.
LO buffer current, in TX (to PA driver)
0: Minimum buffer current
…
7: Maximum buffer current
Recommended settings:
TX_CURRENT=2 for 402-470 MHz,
TX_CURRENT=5 for 804-940 MHz.
PLL_BW Register (1Ah)
REGISTER
NAME
Default
Active
Description
value
PLL_BW[7:0]
PLL_BW[7:0]
134
-
Charge pump current scaling/rounding factor.
Used to calibrate charge pump current for the
desired PLL loop bandwidth. The value is given by:
PLL_BW = 174 + 16 log2(fref/7.126) where fref is the
reference frequency in MHz.
CALIBRATE Register (1Bh)
REGISTER
CALIBRATE[7]
CALIBRATE[6]
NAME
Default
value
0
Active
Description
CAL_START
CAL_DUAL
↑
↑ 1: Calibration started
0: Calibration inactive
0
0
H
Use calibration results for both frequency A and B
0: Store results in A or B defined by F_REG (MAIN[6])
1: Store calibration results in both A and B
Selects calibration wait time (affects accuracy)
0 (00): Calibration time is approx. 90000 F_REF periods
1 (01): Calibration time is approx. 110000 F_REF periods
2 (10): Calibration time is approx. 130000 F_REF periods
3 (11): Calibration time is approx. 200000 F_REF periods
CALIBRATE[5:4]
CAL_WAIT[1:0]
-
Recommended setting: CAL_WAIT=3 for best accuracy in
calibrated PLL loop filter bandwidth.
CALIBRATE[3]
CALIBRATE[2:0]
-
0
5
-
-
Reserved, write 0
Iteration start value for calibration DAC
CAL_ITERATE[2:0]
0 (000): DAC start value 1, VC<0.49 V after calibration
1 (001): DAC start value 2, VC<0.66 V after calibration
2 (010): DAC start value 3, VC<0.82 V after calibration
3 (011): DAC start value 4, VC<0.99 V after calibration
4 (100): DAC start value 5, VC<1.15 V after calibration
5 (101): DAC start value 6, VC<1.32 V after calibration
6 (110): DAC start value 7, VC<1.48 V after calibration
7 (111): DAC start value 8, VC<1.65 V after calibration
Recommended setting: CAL_ITERATE=4.
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CC1020
PA_POWER Register (1Ch)
REGISTER
NAME
Default
value
0
Active
-
Description
PA_POWER[7:4]
PA_HIGH [3:0]
Controls output power in high-power array
0: High-power array is off
1: Minimum high-power array output power
…
15: Maximum high-power array output power
Controls output power in low-power array
0: Low-power array is off
PA_POWER[3:0]
PA_LOW[3:0]
15
-
1: Minimum low-power array output power
…
15: Maximum low-power array output power
It is more efficient in terms of current consumption to use
either the lower or upper 4-bits in the PA_POWER
register to control the power.
MATCH Register (1Dh)
REGISTER
MATCH[7:4]
MATCH[3:0]
NAME
Default value
Active
Description
RX_MATCH[3:0]
TX_MATCH[3:0]
0
0
-
-
Selects matching capacitor array value for RX. Each
step is approximately 0.4 pF.
Selects matching capacitor array value for TX.
Each step is approximately 0.4 pF.
PHASE_COMP Register (1Eh)
REGISTER
NAME
Default
value
Active
-
Description
PHASE_COMP[7:0]
PHASE_COMP[7:0]
0
Signed compensation value for LO I/Q phase error.
Used for image rejection calibration.
−128: approx. −6.2° adjustment between I and Q phase
−1: approx. −0.02° adjustment between I and Q phase
0: approx. +0.02° adjustment between I and Q phase
127: approx. +6.2° adjustment between I and Q phase
GAIN_COMP Register (1Fh)
REGISTER
NAME
Default
Active
Description
value
GAIN_COMP[7:0]
GAIN_COMP[7:0]
0
-
Signed compensation value for mixer I/Q gain error. Used
for image rejection calibration.
−128: approx. −1.16 dB adjustment between I and Q gain
−1: approx. −0.004 dB adjustment between I and Q gain
0: approx. +0.004 dB adjustment between I and Q gain
127: approx. +1.16 dB adjustment between I and Q gain
POWERDOWN Register (20h)
REGISTER
NAME
Default
Active
Description
value
POWERDOWN[7]
POWERDOWN[6]
POWERDOWN[5]
PA_PD
VCO_PD
BUFF_PD
0
0
0
H
H
H
Sets PA in power-down when PD_MODE[1:0]=2
Sets VCO in power-down when PD_MODE[1:0]=2
Sets VCO divider, LO buffers and prescaler in power-down
when PD_MODE[1:0]=2
POWERDOWN[4]
POWERDOWN[3]
POWERDOWN[2]
POWERDOWN[1]
POWERDOWN[0]
CHP_PD
LNAMIX_PD
VGA_PD
FILTER_PD
ADC_PD
0
0
0
0
0
H
H
H
H
H
Sets charge pump in power-down when PD_MODE[1:0]=2
Sets LNA/mixer in power-down when PD_MODE[1:0]=2
Sets VGA in power-down when PD_MODE[1:0]=2
Sets image filter in power-down when PD_MODE[1:0]=2
Sets ADC in power-down when PD_MODE[1:0]=2
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CC1020
TEST1 Register (21h, for test only)
REGISTER
TEST1[7:4]
TEST1[3:0]
NAME
Default
value
4
Active
Description
CAL_DAC_OPEN[3:0]
CHP_CO[3:0]
-
-
Calibration DAC override value, active when
BREAK_LOOP=1
Charge pump current override value
13
TEST2 Register (22h, for test only)
REGISTER
TEST2[7]
TEST2[6]
TEST2[5]
TEST2[4:0]
NAME
Default
value
0
Active
Description
BREAK_LOOP
CHP_OVERRIDE
VCO_OVERRIDE
VCO_AO[4:0]
H
H
H
-
0: PLL loop closed
1: PLL loop open
0
0
0: use calibrated value
1: use CHP_CO[3:0] value
0: use calibrated value
1: use VCO_AO[4:0] value
VCO_ARRAY override value
16
TEST3 Register (23h, for test only)
REGISTER
NAME
Default
Active
Description
value
TEST3[7]
TEST3[6]
VCO_CAL_MANUAL
VCO_CAL_OVERRIDE
0
0
H
H
Enables “manual” VCO calibration (test only)
Override VCO current calibration
0: Use calibrated value
1: Use VCO_CO[5:0] value
VCO_CAL_OVERRIDE controls VCO_CAL_CLK if
VCO_CAL_MANUAL=1. Negative transitions are then
used to sample VCO_CAL_COMP.
TEST3[5:0]
VCO_CO[5:0]
6
-
VCO_CAL_CURRENT override value
TEST4 Register (24h, for test only)
REGISTER
NAME
Default
Active
Description
value
TEST4[7]
TEST4[6]
TEST4[5]
TEST4[4:3]
CHP_DISABLE
CHP_TEST_UP
CHP_TEST_DN
TM_IQ[1:0]
0
0
0
0
H
H
H
-
Disable normal charge pump operation
Force charge pump to output “up” current
Force charge pump to output “down” current
Value of differential I and Q outputs from mixer when
TM_ENABLE=1
0: I output negative, Q output negative
1: I output negative, Q output positive
2: I output positive, Q output negative
3: I output positive, Q output positive
Enable DC control of mixer output (for testing)
Connect analog test module to filter inputs
Connect analog test module to ADC inputs
TEST4[2]
TEST4[1]
TEST4[0]
TM_ENABLE
TF_ENABLE
TA_ENABLE
0
0
0
H
H
H
If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test
module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1
and TEST_MODE[2]=1.
TEST5 Register (25h, for test only)
REGISTER
NAME
Default
value
0
Active
H
Description
TEST5[7]
F_COMP_ENABLE
Enable frequency comparator output F_COMP from
phase detector
TEST5[6]
TEST5[5]
SET_DITHER_CLOCK
ADC_TEST_OUT
1
0
H
H
Enable dithering of delta-sigma clock
Outputs ADC samples on LOCK and DIO, while
ADC_CLK is output on DCLK
TEST5[4]
TEST5[3]
TEST5[2]
TEST5[1:0]
CHOP_DISABLE
SHAPING_DISABLE
VCM_ROT_DISABLE
ADC_ROTATE[1:0]
0
0
0
0
H
H
H
-
Disable chopping in ADC integrators
Disable ADC feedback mismatch shaping
Disable rotation for VCM mismatch shaping
Control ADC input rotation
0: Rotate in 00 01 10 11 sequence
1: Rotate in 00 10 11 01 sequence
2: Always use 00 position
3: Rotate in 00 10 00 10 sequence
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CC1020
TEST6 Register (26h, for test only)
REGISTER
NAME
Default
Active
Description
value
TEST6[7:4]
TEST6[3]
TEST6[2]
-
0
0
0
-
-
-
Reserved, write 0
Override VGA settings
Override value to first AC coupler in VGA
0: Approx. 0 dB gain
VGA_OVERRIDE
AC1O
1: Approx. −12 dB gain
TEST6[1:0]
AC2O[1:0]
0
-
Override value to second AC coupler in VGA
0: Approx. 0 dB gain
1: Approx. −3 dB gain
2: Approx. −12 dB gain
3: Approx. −15 dB gain
TEST7 Register (27h, for test only)
REGISTER
NAME
Default
Active
Description
value
TEST7[7:6]
TEST7[5:4]
TEST7[3:2]
TEST7[1:0]
-
0
0
0
0
-
-
-
-
Reserved, write 0
VGA1O[1:0]
VGA2O[1:0]
VGA3O[1:0]
Override value to VGA stage 1
Override value to VGA stage 2
Override value to VGA stage 3
STATUS Register (40h, read only)
REGISTER
STATUS[7]
STATUS[6]
NAME
Default
value
Active
Description
CAL_COMPLETE
SEQ_ERROR
-
H
H
Set to 0 when PLL calibration starts, and set to 1 when
calibration has finished
Set to 1 when PLL failed to lock during automatic power-
up sequencing
-
STATUS[5]
STATUS[4]
LOCK_INSTANT
LOCK_CONTINUOUS
-
-
H
H
Instantaneous PLL lock indicator
PLL lock indicator, as defined by LOCK_ACCURACY.
Set to 1 when PLL is in lock
STATUS[3]
STATUS[2]
STATUS[1]
STATUS[0]
CARRIER_SENSE
-
-
-
-
H
H
H
H
Carrier sense when RSSI is above CS_LEVEL
Logical level on LOCK pin
Logical level on DCLK pin
LOCK
DCLK
DIO
Logical level on DIO pin
RESET_DONE Register (41h, read only)
REGISTER
NAME
Default
Active
Description
value
RESET_DONE[7]
RESET_DONE[6]
RESET_DONE[5]
RESET_DONE[4]
RESET_DONE[3]
ADC_RESET_DONE
AGC_RESET_DONE
GAUSS_RESET_DONE
AFC_RESET_DONE
-
-
-
-
-
H
H
H
H
H
Reset of ADC control logic done
Reset of AGC (VGA control) logic done
Reset of Gaussian data filter done
Reset of AFC / FSK decision level logic done
Reset of modulator, bit synchronization logic
and PN9 PRBS generator done
Reset digital part of frequency synthesizer
done
BITSYNC_RESET_DONE
RESET_DONE[2]
SYNTH_RESET_DONE
-
H
RESET_DONE[1]
RESET_DONE[0]
SEQ_RESET_DONE
CAL_LOCK_RESET_DONE
-
-
H
H
Reset of power-up sequencing logic done
Reset of calibration logic and lock detector
done
RSSI Register (42h, read only)
REGISTER
NAME
Default
Active
Description
value
RSSI[7]
RSSI[6:0]
-
-
-
-
-
Not in use, will read 0
Received signal strength indicator.
RSSI[6:0]
The relative power is given by RSSI x 1.5 dB in a logarithmic
scale.
The VGA gain set by VGA_SETTING must be taken into
account. See page 41 for more details.
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CC1020
AFC Register (43h, read only)
REGISTER
NAME
Default
value
-
Active
-
Description
AFC[7 :0]
AFC[7:0]
Average received frequency deviation from IF. This 8-bit 2-
complement signed value equals the demodulator decision level
and can be used for AFC. The average frequency offset from the
IF frequency is ∆F = Baud rate · AFC / 16
GAUSS_FILTER Register (44h)
REGISTER
NAME
Default
value
Active
-
Description
GAUSS_FILTER[7 :0]
GAUSS_FILTER[7:0]
-
Readout of instantaneous IF frequency offset
from nominal IF. Signed 8-bit value.
∆F = Baud rate · GAUSS_FILTER / 8
STATUS1 Register (45h, for test only)
REGISTER
NAME
Default
Active
Description
value
STATUS1[7:4]
STATUS1[3:0]
CAL_DAC[3:0]
CHP_CURRENT[3:0]
-
-
-
-
Status vector defining applied Calibration DAC value
Status vector defining applied CHP_CURRENT value
STATUS2 Register (46h, for test only)
REGISTER
NAME
Default
Active
Description
value
STATUS2[7 :5]
CC1020_VERSION[2 :0]
-
-
CC1020 version code :
0 : Pre-production version
1: First production version
2-7: Reserved for future use
Status vector defining applied VCO_ARRAY
value
STATUS2[4:0]
VCO_ARRAY[4:0]
-
-
STATUS3 Register (47h, for test only)
REGISTER
STATUS3[7]
STATUS3[6]
NAME
Default
value
-
Active
Description
F_COMP
-
-
Frequency comparator output from phase
detector
Readout of VCO current calibration comparator.
VCO_CAL_COMP
-
Equals 1 if current defined by
VCO_CURRENT_A/B is larger than the VCO
core current
STATUS3[5:0]
VCO_CAL_CURRENT[5:0]
-
-
Status vector defining applied
VCO_CAL_CURRENT value
STATUS4 Register (48h, for test only)
REGISTER
NAME
Default
Active
Description
value
STATUS4[7:6]
STATUS4[5:3]
STATUS4[2:0]
ADC_MIX[1:0]
ADC_I[2:0]
ADC_Q[2:0]
-
-
-
-
-
-
Readout of mixer input to ADC
Readout of ADC “I” output
Readout of ADC “Q” output
STATUS5 Register (49h, for test only)
REGISTER
NAME
Default
value
-
Active
-
Description
STATUS5[7:0]
FILTER_I[7:0]
Upper bits of “I” output from channel filter
STATUS6 Register (4Ah, for test only)
REGISTER
NAME
Default
value
-
Active
-
Description
STATUS6[7 :0]
FILTER_Q[7 :0]
Upper bits of “Q” output from channel filter
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CC1020
STATUS7 Register (4Bh, for test only)
REGISTER
NAME
Default
Active
Description
value
STATUS7[7:5]
STATUS7[4:0]
-
-
-
-
-
Not in use, will read 0
Readout of offset between VGA_SETTING and
actual VGA gain set by AGC
VGA_GAIN_OFFSET[4:0]
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CC1020
27.
Package Description (QFN 32)
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CC1020
Quad Flat Pack – No Lead Package (QFN)
D
E
A
A1
e
b
L
D1
E1
P
QFN 32
Min
0.8
7.0 0.9
1.0
0.25
0.30
0.35
0.45
0.55
0.65
4.18
4.28
4.38
4.18
4.28
4.38
7.0
0.203
0.65
45°
Max
All dimensions in mm. Angles are in degrees.
Package is compliant with JEDEC: MO-220.
Note: Do not place a via underneath CC1020 at “pin #1 corner” as this pin is internally
connected to the exposed die attached pad, which is the main ground connection for the chip.
27.1. Package Marking
When contacting technical support with a chip-related question, please state the entire
marking information, not just the date code.
Standard leaded
0315123
0315 is the date code (year 03, week 15)
123 is the lot code
RoHS compliant Pb-free
A440123
440 is the date code (year 4, week 40)
123 is the lot code
A means RoHS compliant Pb-free
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CC1020
27.2. Recommended PCB Footprint for Package (QFN 32)
Note: The figure is an illustration only and not to scale. There are nine 14 mil (0.36 mm)
diameter via holes distributed symmetrically in the ground plane under the package. See also
the CC1020EMX reference design.
27.3. Package Thermal Properties
Thermal resistance
Air velocity
[m/s]
0
1
2
Rth,j-a [K/W]
21.4
18.9
17.0
27.4. Soldering Information
Recommended soldering profile for both standard leaded packages and Pb-free packages is
according to IPC/JEDEC J-STD-020C.
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CC1020
27.5. Plastic Tube Specification
QFN 7x7 mm antistatic tube.
Tube Specification
Package
QFN 32
Tube Width
8.5 ± 0.2 mm
Tube Height
2.2 +0.2/-0.1 mm
Tube Length
315 ± 1.25 mm
Units per Tube
43
27.6. Carrier Tape and Reel Specification
Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification
Package
QFN 32
Tape Width
16 mm
Component
Pitch
12 mm
Hole
Pitch
4 mm
Reel
Diameter
13”
Units per Reel
4000
28.
Ordering Information
Ordering part number
Description
MOQ
1123
CC1020-RTB1
CC1020, QFN32 package, RoHS compliant Pb-free assembly,
tubes with 43 pcs per tube, Single Chip RF Transceiver.
CC1020, QFN32 package, RoHS compliant Pb-free assembly,
T&R with 4000 pcs per reel, Single Chip RF Transceiver.
CC1020/1070 Development Kit, 433 MHz
43
1126
1115
1116
1158
CC1020-RTR1
4000
CC1020_1070DK-433
CC1020_1070DK-868/915
CC1020SK RoHS
1
1
1
CC1020/1070 Development Kit, 868/915 MHz
CC1020 Sample Kit, QFN32 package, RoHS compliant Pb-
free assembly, 5 pcs
MOQ = Minimum Order Quantity
T&R = tape and reel
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CC1020
29.
General Information
Document Revision History
Revision
Date
Description/Changes
1.4
November 2003 New improved image calibration routine.
Changes to preamble length and synchronization word for improved packet
error rate.
Included plot of blocking/selectivity.
Included data on PA_EN and LNA_EN pin drive.
Changes to Digital FM.
Changes to some of the electrical specification parameters.
Included data for intermodulation rejection
Changed “channel width” to “channel spacing”
Maximum power down current increased from 1 uA to 1.8 uA.
Update on preamble length and synchronization word for improved packet
error rate.
1.5
1.6
February 2004
December 2004 The various sections have been reorganized to improve readability
Added chapter numbering
Reorganized electrical specification section
Electrical specifications updated
Changes to sensitivity figures
Changes to TX spurious emission and harmonics figures
Changes to ACP figure at 868 MHz operation
Changes to current consumption figures in RX and TX mode and crystal
oscillator, bias and synthesizer mode
Changes to noise figure
Updates to section on input / output matching
Updates to section on VCO and PLL self-calibration
Updates to section on VCO, charge pump and PLL loop filter
Updates to section on receiver channel filter bandwidth
Updates to section on RSSI
Updates to section on image rejection calibration
Updates to section on preamble length and sync word
Description of OOK modulation and demodulation merged into one section
New bill of materials for operation at 433 MHz and 868/915 MHz
Added recommended PCB footprint for package (QFN 32)
Added information that there should be no via at “pin #1 corner” (section 27.2)
Added list of abbreviations
Changes to ordering information
1.7
1.8
October 2005
January 2006
RSSI dynamic range changed from 63 dB to 55 dB
Recommended CAL_ITERATE changed from 5 to 4
PLL timeout in “Automatic power-up sequencing flow chart” changed from
1024 filter clocks to 127 filter clocks
Calibration routine flow chart changed in accordance to CC1020 Errata Note
004
Added chapter on TX data latency
Updates to Ordering Information and Address Information
Product Status Definitions
Data Sheet Identification
Advance Information
Product Status
Planned or Under
Development
Definition
This data sheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
Engineering Samples This data sheet contains preliminary data, and
and First Production
supplementary data will be published at a later date.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
No Identification Noted
Obsolete
Full Production
This data sheet contains the final specifications.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
This data sheet contains specifications on a product
that has been discontinued by Chipcon. The data
sheet is printed for reference information only.
Not In Production
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CC1020
Disclaimer
Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However,
Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any
responsibility for the use of the described product; neither does it convey any license under its patent rights, or the
rights of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.
To the extent possible, major changes of product specifications and functionality will be stated in product specific
Errata Notes published at the Chipcon website. Customers are encouraged to sign up for the Developer’s Newsletter
for the most recent updates on products and support tools.
When a product is discontinued this will be done according to Chipcon’s procedure for obsolete products as
described in Chipcon’s Quality Manual. This includes informing about last-time-buy options. The Quality Manual can
be downloaded from Chipcon’s website.
Compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to
ensure that the system complies with regulations.
Trademarks
SmartRF® is a registered trademark of Chipcon AS. SmartRF® is Chipcon's RF technology platform with RF library
cells, modules and design expertise. Based on SmartRF® technology Chipcon develops standard component RF
circuits as well as full custom ASICs based on customer requirements and this technology.
All other trademarks, registered trademarks and product names are the sole property of their respective owners.
Life Support Policy
This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction
can reasonably be expected to result in significant personal injury to the user, or as a critical component in any life
support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting
from any improper use or sale.
© 2006, Chipcon AS. All rights reserved.
SWRS046
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相关型号：
CC107H004JAG
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VISHAY
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