CC1352R [TI]
具有 352kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M4F 多协议低于 1GHz 和 2.4GHz 无线 MCU;
| 型号： | CC1352R |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 352kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M4F 多协议低于 1GHz 和 2.4GHz 无线 MCU 无线 闪存 |
| 文件： | 总95页 (文件大小：3102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC1352R
ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
CC1352R SimpleLink™ 高性能多频带无线MCU
• 低功耗
– 宽电源电压范围：1.8V 至3.8V
1 特性
• 微控制器
– 有源模式RX：5.8mA（3.6V，868MHz）、
– 功能强大的48MHz Arm® Cortex®-M4F 处理器
– EEMBC CoreMark® 评分：148
– 352KB 系统内可编程闪存
– 256KB ROM，用于协议和库函数
– 8KB 缓存SRAM（也可作为通用RAM 提供）
– 80KB 超低泄漏SRAM。SRAM 通过奇偶校验得
到保护，从而确保高度可靠运行。
6.9mA（3.0V，2.4GHz）
– 有源模式TX (0dBm)：8.0mA（3.6V，
868MHz）、7.1mA（3.0V，2.4GHz）
– 有源模式TX (+14dBm)：24.9mA (868MHz)
– 有源模式MCU 48MHz (CoreMark)：
2.9 mA (60μA/MHz)
– 传感器控制器（低功耗模式、2MHz、运行无限
环路）：30.1μA
– 2 引脚cJTAG 和JTAG 调试
– 传感器控制器，有源模式，24MHz，运行无限循
环：808μA
– 支持无线(OTA) 升级
• 具有4KB SRAM 的超低功耗传感器控制器
– 待机：0.85μA（RTC 运行，80KB RAM 和
CPU 保持）
– 关断电流：150nA（发生外部事件时唤醒）
• 无线电部分
– 采样、存储和处理传感器数据
– 独立于系统CPU 运行
– 快速唤醒进入低功耗运行
• TI-RTOS、驱动程序、引导加载程序、低功耗
Bluetooth® 5.2 控制器和IEEE 802.15.4 MAC 嵌入
在ROM 中，优化了应用尺寸
– 多频带Sub-1GHz 和2.4GHz 射频收发器，兼容
低功耗蓝牙5.2 与早期LE 规范以及IEEE
802.15.4 PHY 和MAC
• 符合RoHS 标准的封装
– 3 线、2 线、1 线PTA 共存机制
– 出色的接收器灵敏度：
– 7mm × 7mm RGZ VQFN48（28 个GPIO）
• 外设
SimpleLink 远距离模式下为-121dBm
50kbps 时为-110dBm，蓝牙125kbps 时（LE
编码PHY）为-105dBm
– 数字外设可连接至任何GPIO
– 4 个32 位或8 个16 位通用计时器
– 12 位ADC、200ksps、8 通道
– 2 个具有内部基准DAC 的比较器
（1 个连续时间比较器、1 个超低功耗比较器）
– 可编程电流源
– 高达+14dBm (Sub-1GHz) 和+5dBm (2.4GHz)
的输出功率，具有温度补偿
– 适用于符合各项全球射频规范的系统
• ETSI EN 300 220 接收器类别1.5 和2、EN
300 328、EN 303 131、EN 303 204（欧
洲）
– 2 个异步收发器(UART)
– 2 个同步串行接口(SSI)（SPI、MICROWIRE
和TI）
– I2C 和I2S
• EN 300 440 类别2
– 实时时钟(RTC)
• FCC CFR47 第15 部分
– AES 128 位和256 位加密加速计
– ECC 和RSA 公钥硬件加速器
– SHA2 加速器（包括至SHA-512 的全套装）
– 真随机数发生器(TRNG)
– 电容式检测，最多8 通道
– 集成温度和电池监控器
• ARIB STD-T108 和STD-T66
– 支持广泛的标准
• 无线协议
– Thread、Zigbee®、低功耗Bluetooth® 5.2、
IEEE 802.15.4g、支持IPv6 的智能对象
(6LoWPAN)、MIOTY®、无线M-Bus、Wi-
SUN®、KNX RF、Amazon Sidewalk、专有系
统、SimpleLink™ TI 15.4-Stack
（Sub-1GHz），以及动态多协议管理器(DMM)
驱动程序。
• 外部系统
– 片上降压直流/直流转换器
– TCXO 支持
• 开发工具和软件
– CC1352R LaunchPad™ 开发套件
– SimpleLink™ CC13x2 和CC26x2 软件开发套
件(SDK)
– 用于简单无线电配置的SmartRF™ Studio
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS196
CC1352R
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ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
– 用于构建低功耗检测应用的Sensor Controller
– 智能仪表–水表、燃气表、电表和热量分配表
– 电网通信–无线通信–远距离传感器应用
– 其他替代能源–能量收集
• 工业运输–资产跟踪
Studio
2 应用
• 169、433、470 至510、868、902 至928 和2400
至2480MHz ISM 和SRD 系统，1 接收带宽低至
4kHz
• 工厂自动化和控制
• 医疗
• 电子销售终端(EPOS) –电子货架标签(ESL)
• 通信设备
• 楼宇自动化
– 楼宇安防系统–运动检测器、电子智能锁、门
窗传感器、车库门系统、网关
– HVAC –恒温器、无线环境传感器、HVAC 系
统控制器、网关
– 防火安全系统–烟雾和热量探测器、火警控制
面板(FACP)
– 有线网络–无线LAN 或Wi-Fi 接入点、边缘路
由器
• 个人电子产品
– 便携式电子产品–射频智能遥控器
– 家庭影院和娱乐–智能扬声器、智能显示器、
机顶盒
– 视频监控–IP 网络摄像头
– 升降机和自动扶梯–升降机和自动扶梯的电梯
主控板
– 联网外设–消费类无线模块、指点设备、键盘
– 游戏–电子玩具和机器人玩具
– 可穿戴设备（非医用）–智能追踪器、智能服
装
• 电网基础设施
3 说明
SimpleLink™ CC1352R 器件是一款多协议、多频带 Sub-1GHz 和 2.4GHz 无线微控制器 (MCU)，支持 Thread、
Zigbee®、低功耗 Bluetooth® 5.2、IEEE 802.15.4g、支持 IPv6 的智能对象 (6LoWPAN)、MIOTY®、Wi-SUN®、
专有系统（包括 Sub-1GHz 和 2.4GHz 的 TI 15.4-Stack）和通过动态多协议管理器 (DMM) 驱动程序实现的并发
多协议。该器件经过优化，可用于楼宇安防系统、HVAC、智能仪表、医疗、有线网络、便携式电子产品、家庭影
院和娱乐以及联网外设市场中的低功耗无线通信和高级检测。该器件的突出特性包括：
• 多频带器件，通过DMM 驱动程序支持面向Sub-1GHz 和2.4GHz 的并发多协议。
• SimpleLink™ CC13x2 和CC26x2 软件开发套件(SDK) 提供丰富灵活的协议栈支持。
• 对于Sub-1GHz，最大发送功耗为+14dBm（电流消耗为24.9mA）；对于2.4GHz，最大发送功耗为+5dBm
（电流消耗为9.6mA）。
• 具有0.85µA 的低待机电流（完全RAM 保持），从而延长无线应用的电池寿命。
• 支持工业温度，在85°C 下最低待机电流为5µA。
• 通过具有快速唤醒功能的可编程、自主式超低功耗传感器控制器CPU 实现高级检测。例如，传感器控制器能
够在1µA 系统电流下进行1Hz ADC 采样。
• 低SER（软错误率）FIT（时基故障），可延长运行寿命，不会对工业市场造成干扰，SRAM 奇偶校验功能始
终开启，可防止潜在辐射事件导致的损坏。
• 软件控制的专用无线电控制器(Arm® Cortex®-M0) 提供灵活的低功耗射频收发器功能，支持多个物理层和射频
标准。
• 出色的无线电敏感度(-121dBm) 和稳健性（选择性与阻断）性能，适用于SimpleLink™ 远距离模式。
CC1352R 器件是 SimpleLink™ MCU 平台的一部分，该平台包括 Wi-Fi®、低功耗蓝牙、Thread、Zigbee、
Sub-1GHz MCU 和主机 MCU，它们共用一个通用、易于使用的开发环境，其中包含单核软件开发套件 (SDK) 和
丰富的工具集。借助一次性集成的 SimpleLink™ 平台，可以将产品组合中的任何器件组合添加至您的设计中，从
而在设计要求变更时实现100% 的代码重用。如需更多信息，请访问SimpleLink™ MCU 平台。
器件信息
器件型号(1)
CC1352R1F3RGZ
封装尺寸（标称值）
封装
VQFN (48)
7.00mm × 7.00mm
(1) 如需所有可用器件的最新器件、封装和订购信息，请参阅节12 中的“封装选项附录”或访问TI 网站。
1
请参阅射频内核，了解有关支持的协议标准、调制格式和数据速率的其他详细信息。
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4 Functional Block Diagram
z
H
z
G
H
1
-
G
b
CC1352R
4
.
Su
2
RF Core
cJTAG
Main CPU
256KB
ROM
ADC
ADC
Arm® Cortex®-M4F
Processor
Up to
352KB
Flash
Digital PLL
with 8KB
Cache
DSP Modem
48 MHz
60 µA/MHz (3.6 V)
16KB
SRAM
Arm® Cortex®-M0
Processor
Up to
80KB
SRAM
ROM
with Parity
General Hardware Peripherals and Modules
Sensor Interface
I2C and I2S
4× 32-bit Timers
2× SSI (SPI)
Watchdog Timer
TRNG
ULP Sensor Controller
8-bit DAC
2× UART
12-bit ADC, 200 ks/s
32 ch. µDMA
28 GPIOs
2x Low-Power Comparator
SPI-I2C Digital Sensor IF
Temperature and
Battery Monitor
AES-256, SHA2-512
ECC, RSA
Capacitive Touch IF
RTC
Time-to-Digital Converter
LDO, Clocks, and References
Optional DC/DC Converter
4KB SRAM
图4-1. CC1352R Block Diagram
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Table of Contents
8.23 Zigbee and Thread - IEEE 802.15.4-2006 2.4
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagram –RGZ Package (Top View)..................7
7.2 Signal Descriptions –RGZ Package.........................8
7.3 Connections for Unused Pins and Modules................9
8 Specifications................................................................ 10
8.1 Absolute Maximum Ratings ..................................... 10
8.2 ESD Ratings ............................................................ 10
8.3 Recommended Operating Conditions ......................10
8.4 Power Supply and Modules ..................................... 11
8.5 Power Consumption - Power Modes ....................... 12
8.6 Power Consumption - Radio Modes ........................ 13
8.7 Nonvolatile (Flash) Memory Characteristics ............ 13
8.8 Thermal Resistance Characteristics ........................ 13
8.9 RF Frequency Bands ...............................................14
8.10 861 MHz to 1054 MHz - Receive (RX) ...................15
8.11 861 MHz to 1054 MHz - Transmit (TX) ................. 18
8.12 861 MHz to 1054 MHz - PLL Phase Noise
GHz (OQPSK DSSS1:8, 250 kbps) - TX ....................32
8.24 Timing and Switching Characteristics..................... 32
8.25 Peripheral Characteristics.......................................37
8.26 Typical Characteristics............................................45
9 Detailed Description......................................................70
9.1 Overview...................................................................70
9.2 System CPU............................................................. 70
9.3 Radio (RF Core)........................................................71
9.4 Memory.....................................................................73
9.5 Sensor Controller......................................................73
9.6 Cryptography............................................................ 75
9.7 Timers....................................................................... 76
9.8 Serial Peripherals and I/O.........................................77
9.9 Battery and Temperature Monitor............................. 77
9.10 µDMA......................................................................77
9.11 Debug......................................................................77
9.12 Power Management................................................78
9.13 Clock Systems........................................................ 79
9.14 Network Processor..................................................79
10 Application, Implementation, and Layout................. 80
10.1 Reference Designs................................................. 80
10.2 Junction Temperature Calculation...........................81
11 Device and Documentation Support..........................82
11.1 Tools and Software..................................................82
11.2 Documentation Support.......................................... 84
11.3 支持资源..................................................................85
11.4 Trademarks............................................................. 85
11.5 静电放电警告...........................................................85
11.6 术语表..................................................................... 85
12 Mechanical, Packaging, and Orderable
Wideband Mode ......................................................... 19
8.13 861 MHz to 1054 MHz - PLL Phase Noise
Narrowband Mode ......................................................20
8.14 359 MHz to 527 MHz - Receive (RX) .....................21
8.15 359 MHz to 527 MHz - Transmit (TX) ................... 23
8.16 359 MHz to 527 MHz - PLL Phase Noise .............. 24
8.17 143 MHz to 176 MHz - Receive (RX) .....................25
8.18 143 MHz to 176 MHz - Transmit (TX) .................. 26
8.19 143 MHz to 176 MHz - PLL Phase Noise .............. 26
8.20 Bluetooth Low Energy - Receive (RX) ................... 27
8.21 Bluetooth Low Energy - Transmit (TX) ...................30
8.22 Zigbee and Thread - IEEE 802.15.4-2006 2.4
Information.................................................................... 86
12.1 Packaging Information............................................ 86
GHz (OQPSK DSSS1:8, 250 kbps) - RX ................... 31
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5 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from November 19, 2020 to February 12, 2021 (from Revision H (November 2020) to
Revision I (February 2021))
Page
• 通篇更新为蓝牙5.2.............................................................................................................................................1
• 向节1，特性的“无线电部分”列表中添加了3 线、2 线和1 线PTA 共存机制............................................... 1
• Added PTA description in 节9.3, Radio (RF Core) ..........................................................................................71
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6 Device Comparison
表6-1. Device Family Overview
FLASH
(KB)
RAM
(KB)
DEVICE
RADIO SUPPORT
GPIO
PACKAGE SIZE
CC1312R
Sub-1 GHz
352
80
30
RGZ (7-mm × 7-mm VQFN48)
Multiprotocol
Sub-1 GHz
Bluetooth 5.2 Low Energy
Zigbee
CC1352P
CC1352R
352
80
26
28
RGZ (7-mm × 7-mm VQFN48)
Thread
2.4 GHz proprietary FSK-based formats
+20-dBm high-power amplifier
Multiprotocol
Sub-1 GHz
Bluetooth 5.2 Low Energy
Zigbee
352
80
RGZ (7-mm × 7-mm VQFN48)
Thread
2.4 GHz proprietary FSK-based formats
Bluetooth 5.2 Low Energy
2.4 GHz proprietary FSK-based formats
CC2642R
352
352
80
80
31
31
RGZ (7-mm × 7-mm VQFN48)
RTC (7-mm × 7-mm VQFN48)
CC2642R-Q1
Bluetooth 5.2 Low Energy
Multiprotocol
Bluetooth 5.2 Low Energy
Zigbee
CC2652R
352
352
80
80
31
31
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
Thread
2.4 GHz proprietary FSK-based formats
Multiprotocol
Bluetooth 5.2 Low Energy
Zigbee
CC2652RB
Thread
2.4 GHz proprietary FSK-based formats
Multiprotocol
Bluetooth 5.2 Low Energy
Zigbee
CC2652P
352
80
26
RGZ (7-mm × 7-mm VQFN48)
Thread
2.4 GHz proprietary FSK-based formats
+19.5-dBm high-power amplifier
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
CC1310
CC1350
Sub-1 GHz
32–128
16–20
10–31
10–31
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
Sub-1 GHz
Bluetooth 4.2 Low Energy
128
20
RGZ (7-mm × 7-mm VQFN48)
RHB (5-mm × 5-mm VQFN32)
RSM (4-mm × 4-mm VQFN32)
YFV (2.7-mm × 2.7-mm DSBGA34)
Bluetooth 5.1 Low Energy
2.4 GHz proprietary FSK-based formats
CC2640R2F
128
128
20
20
10–31
Bluetooth 5.1 Low Energy
2.4 GHz proprietary FSK-based formats
CC2640R2F-Q1
31
RGZ (7-mm × 7-mm VQFN48)
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7 Terminal Configuration and Functions
7.1 Pin Diagram –RGZ Package (Top View)
RF_P_2_4GHZ
RF_N_2_4GHZ
RF_P_SUB_1GHZ
RF_N_SUB_1GHZ
RX_TX
1
2
3
4
5
6
7
8
9
36 DIO_23
35 RESET_N
34 VDDS_DCDC
33 DCDC_SW
32 DIO_22
X32K_Q1
31 DIO_21
X32K_Q2
30 DIO_20
DIO_3
29 DIO_19
DIO_4
28 DIO_18
DIO_5 10
DIO_6 11
DIO_7 12
27 DIO_17
26 DIO_16
25 JTAG_TCKC
图7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in 图7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in 图7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30
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7.2 Signal Descriptions –RGZ Package
表7-1. Signal Descriptions –RGZ Package
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
33
23
8
DCDC_SW
DCOUPL
DIO_3
Power
Power
Output from internal DC/DC converter(1)
—
For decoupling of internal 1.27 V regulated digital-supply (2)
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Digital
GPIO
DIO_4
9
Digital
GPIO
DIO_5
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
Digital
GPIO, high-drive capability
DIO_6
Digital
GPIO, high-drive capability
DIO_7
Digital
GPIO, high-drive capability
DIO_8
Digital
GPIO
DIO_9
Digital
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
EGP
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
Digital
Digital
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
GND
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
Ground –exposed ground pad(3)
JTAG TMSC, high-drive capability
JTAG TCKC
—
24
25
35
—
I/O
I
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital
Digital
I
Digital
Reset, active low. No internal pullup resistor
Positive 2.4-GHz RF input signal to LNA during RX
Positive 2.4-GHz RF output signal from PA during TX
RF_P_2_4GHZ
RF_N_2_4GHZ
RF_P_SUB_1GHZ
1
2
3
RF
RF
RF
—
—
—
Negative 2.4-GHz RF input signal to LNA during RX
Negative 2.4-GHz RF output signal from PA during TX
Positive Sub-1 GHz RF input signal to LNA during RX
Positive Sub-1 GHz RF output signal from PA during TX
Negative Sub-1 GHz RF input signal to LNA during RX
Negative Sub-1 GHz RF output signal from PA during TX
RF_N_SUB_1GHZ
RX_TX
4
5
RF
RF
—
—
Optional bias pin for the RF LNA
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表7-1. Signal Descriptions –RGZ Package (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (4) (6)
VDDR
45
Power
Power
—
—
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (5) (6)
VDDR_RF
48
VDDS
44
13
22
34
46
47
6
Power
Power
Power
Power
Analog
Analog
Analog
Analog
1.8-V to 3.8-V main chip supply(1)
1.8-V to 3.8-V DIO supply(1)
—
—
—
—
—
—
—
—
VDDS2
VDDS3
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
X48M_N
X48M_P
X32K_Q1
X32K_Q2
1.8-V to 3.8-V DC/DC converter supply
48-MHz crystal oscillator pin 1
48-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
7
(1) For more details, see technical reference manual listed in 节11.2.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
7.3 Connections for Unused Pins and Modules
表7-2. Connections for Unused Pins
PREFERRED
FUNCTION
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE(1)
PRACTICE(1)
8–12
14–21
26–32
36–43
GPIO
DIO_n
NC or GND
NC
X32K_Q1
6
7
32.768-kHz crystal
NC or GND
NC
X32K_Q2
DCDC_SW
VDDS_DCDC
33
34
NC
NC
DC/DC converter(2)
VDDS
VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
VDDS(3)
Supply voltage
4.1
VDDS + 0.3, max 4.1
VDDR + 0.3, max 2.25
VDDS
V
V
V
Voltage on any digital pin(4)
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
Voltage scaling enabled
Vin
Voltage on ADC input Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
Input level, Sub-1 GHz RF pins
1.49
V
VDDS / 2.9
10 dBm
Input level, 2.4 GHz RF pins
5
dBm
°C
Tstg
Storage temperature
150
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIOs.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
All pins
All pins
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
105
3.8
UNIT
°C
Operating junction temperature(2)
–40
Operating supply voltage (VDDS)
1.8
2.1
V
Operating supply voltage (VDDS), boost mode
VDDR = 1.95 V
3.8
V
+14 dBm RF output power
Rising supply voltage slew rate
Falling supply voltage slew rate(1)
0
0
100
20
mV/µs
mV/µs
(1) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
(2) For thermal resistance characteristics refer to Thermal Resistance Characteristics. For application considerations, refer to Junction
Temperature.
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8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
1.1 -
1.55
VDDS Power-on-Reset (POR) threshold
V
VDDS Brown-out Detector (BOD) (1)
VDDS Brown-out Detector (BOD), before initial boot (2) Rising threshold
VDDS Brown-out Detector (BOD) (1)
Falling threshold
Rising threshold
1.77
1.70
1.75
V
V
V
(1) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V)
(2) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
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8.5 Power Consumption - Power Modes
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset
threshold
150
150
Reset and Shutdown
nA
Shutdown. No clocks running, no retention
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
0.85
µA
µA
µA
µA
µA
mA
Standby
without cache
retention
RTC running, CPU, 80KB RAM and (partial) register retention
XOSC_LF
0.99
2.78
2.92
590
Icore
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
Standby
with cache retention
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF
Supply Systems and RAM powered
RCOSC_HF
Idle
MCU running CoreMark at 48 MHz
RCOSC_HF
Active
2.89
(2)
Peripheral Current Consumption (1)
,
Peripheral power
domain
Delta current with domain enabled
82.3
5.5
Serial power domain Delta current with domain enabled
Delta current with power domain enabled,
clock enabled, RF core idle
RF Core
178.9
µDMA
Timers
I2C
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(5)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(4)
Delta current with clock enabled, module is idle(3)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
53.6
67.8
8.2
Iperi
µA
I2S
21.7
69.4
140.8
21.1
71.1
29.7
SSI
UART
CRYPTO (AES)
PKA
TRNG
Sensor Controller Engine Consumption
Active mode
24 MHz, infinite loop, VDDS = 3.0 V
2 MHz, infinite loop, VDDS = 3.0 V
808.5
30.1
ISCE
µA
Low-power mode
(1) Adds to core current Icore for each peripheral unit activated.
(2) Iperi is not supported in Standby or Shutdown modes.
(3) Only one UART running
(4) Only one SSI running
(5) Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.6 V with DC/DC enabled
unless otherwise noted.
Using boost mode (increasing VDDR up to 1.95 V), will increase system current by 15% (does not apply to TX +14 dBm
setting where this current is already included).
Relevant Icore and Iperi currents are included in below numbers.
PARAMETER
TEST CONDITIONS
TYP UNIT
Radio receive current, 868 MHz
5.8
6.9
mA
mA
Radio receive current, 2.44
GHz (BLE)
VDDS = 3.0 V
0 dBm output power setting
868 MHz
8.0
14.3
24.9
7.1
mA
mA
mA
mA
mA
Radio transmit current
Sub-1 GHz PA
+10 dBm output power setting
868 MHz
Radio transmit current
Boost mode, Sub-1 GHz PA
+14 dBm output power setting
868 MHz
Radio transmit current
2.4 GHz PA (BLE)
0 dBm output power setting, VDDS = 3.0 V
Radio transmit current
2.4 GHz PA (BLE)
+5 dBm output power setting
2440 MHz, VDDS = 3.0 V
9.6
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Flash sector size
8
KB
Supported flash erase cycles before failure, full bank(1)
30
60
k Cycles
k Cycles
(5)
Supported flash erase cycles before failure, single
sector(2)
Maximum number of write operations per row before
sector erase(3)
Write
Operations
83
Years at
105 °C
Flash retention
105 °C
11.4
Flash sector erase current
Flash sector erase time(4)
Flash write current
Average delta current
Zero cycles
10.7
10
mA
ms
mA
µs
Average delta current, 4 bytes at a time
4 bytes at a time
6.2
Flash write time(4)
21.6
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics
PACKAGE
RGZ
(VQFN)
48 PINS
23.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W(2)
°C/W(2)
RθJC(top)
13.3
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8.8 Thermal Resistance Characteristics (continued)
PACKAGE
RGZ
(VQFN)
THERMAL METRIC(1)
UNIT
48 PINS
8.0
RθJB
ψJT
Junction-to-board thermal resistance
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
7.9
ψJB
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
8.9 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
2360
1076
861
TYP
MAX
UNIT
2500
1315
1054
527
Frequency bands
431
MHz
359
439
287
351
143
176
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8.10 861 MHz to 1054 MHz - Receive (RX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Digital channel filter programmable
receive bandwidth
4
4000 kHz
Data rate step size
1.5
bps
Spurious emissions 25 MHz to 1 GHz 868 MHz
< -57
dBm
Conducted emissions measured according to ETSI EN
300 220
Spurious emissions 1 GHz to 13 GHz
< -47
dBm
IEEE 802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 100 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 868 MHz
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
BER = 10–2, 868 MHz(1)
dBm
dBm
dB
–110
10
Saturation limit
Selectivity, ±200 kHz
Selectivity, ±400 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±5 MHz
Blocking, ±10 MHz
44
48
dB
57
dB
61
dB
67
dB
76
dB
Image rejection (image compensation
enabled)
BER = 10–2, 868 MHz(1)
39
95
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
Starting from the sensitivity limit across the given
dynamic range
100 kbps, ±25 kHz Deviation, 2-GFSK, 137 kHz RX Bandwidth
Sensitivity 100 kbps
Selectivity, ±200 kHz
1% PER, 127 byte payload, 868 MHz
-104
31
dBm
dB
1% PER, 127 byte payload, 868 MHz. Wanted signal at
-96 dBm
1% PER, 127 byte payload, 868 MHz. Wanted signal at
-96 dBm
Selectivity, ±400 kHz
Co-channel rejection
37
-9
dB
dB
1% PER, 127 byte payload, 868 MHz. Wanted signal at
-79 dBm
200 kbps, ±50 kHz Deviation, 2-GFSK, 311 kHz RX Bandwidth
Sensitivity
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 915 MHz
dBm
dBm
–103
–103
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
Selectivity, ±400 kHz
Selectivity, ±800 kHz
Blocking, ±2 MHz
41
47
55
67
dB
dB
dB
dB
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
Blocking, ±10 MHz
500 kbps, ±190 kHz Deviation, 2-GFSK, 1150 kHz RX Bandwidth
Sensitivity 500 kbps
Selectivity, ±1 MHz
1% PER, 127 byte payload, 915 MHz
-94
14
dBm
dB
1% PER, 127 byte payload, 915 MHz. Wanted signal at
-88 dBm
1% PER, 127 byte payload, 915 MHz. Wanted signal at
-88 dBm
Selectivity, ±2 MHz
42
dB
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8.10 861 MHz to 1054 MHz - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1% PER, 127 byte payload, 915 MHz. Wanted signal at
-71 dBm
Co-channel rejection
-9
dB
1 Mbps, ±350 kHz Deviation, 2-GFSK, 2.2 MHz RX Bandwidth
Sensitivity
Sensitivity
BER = 10–2, 868 MHz
BER = 10–2, 915 MHz
-97
-96
dBm
dBm
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
Blocking, -10 MHz
43
26
54
48
dB
dB
dB
dB
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
BER = 10–2, 915 MHz. Wanted signal 3 dB above
sensitivity limit.
SimpleLink™ Long Range, 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity
2.5 kbps, BER = 10–2 , 868 MHz
5 kbps, BER = 10–2 , 868 MHz
2.5 kbps, BER = 10–2 , 868 MHz
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
2.5 kbps, BER = 10–2, 868 MHz(1)
-121
-120
10
dBm
dBm
dBm
dB
Sensitivity
Saturation limit
Selectivity, ±100 kHz
Selectivity, ±200 kHz
Selectivity, ±300 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±5 MHz
Blocking, ±10 MHz
49
50
dB
51
dB
63
dB
68
dB
78
dB
88
dB
Image rejection (image compensation
enabled)
2.5 kbps, BER = 10–2, 868 MHz(1)
Starting from the sensitivity limit
45
97
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit across the given
dynamic range
4.8 kbps, OOK, 39 kHz RX Bandwidth
Sensitivity
Sensitivity
BER = 10–2, 868 MHz, 38.9 kHz RX bandwidth
BER = 10–2, 915 MHz, 41.0 kHz RX bandwidth
-115
-115
dBm
dBm
Narrowband, 9.6 kbps, ±2.4 kHz Deviation, 2-GFSK, 17.1 kHz RX Bandwidth
Sensitivity
BER = 10–2, 868 MHz
-118
39
dBm
dB
BER = 10–2, 868 MHz. Wanted signal 3 dB above the
ETSI reference sensitivity limit (-104.6 dBm). Interferer
±20 kHz
Adjacent Channel Rejection
BER = 10–2, 868 MHz. Wanted signal 3 dB above the
ETSI reference sensitivity limit (-104.6 dBm). Interferer
±40 kHz
Alternate Channel Rejection
40
dB
BER = 10–2, 868 MHz. Wanted signal 3 dB above the
ETSI reference sensitivity limit (-104.6 dBm).
Blocking, ±1 MHz
Blocking, ±2 MHz
65
69
85
dB
dB
dB
BER = 10–2, 868 MHz. Wanted signal 3 dB above the
ETSI reference sensitivity limit (-104.6 dBm).
BER = 10–2, 868 MHz. Wanted signal 3 dB above the
ETSI reference sensitivity limit (-104.6 dBm).
Blocking, ±10 MHz
Wi-SUN
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8.10 861 MHz to 1054 MHz - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
50 kbps, ±12.5 kHz deviation, 2-GFSK, 868 MHz, 68 kHz
RX BW, 10% PER, 250 byte payload
Sensitivity
Sensitivity
Sensitivity
Sensitivity
-107
dBm
100 kbps, ±25 kHz deviation, 2-GFSK, 868 MHz, 135
kHz RX BW, 10% PER, 250 byte payload
-104
-102
-99
dBm
dBm
dBm
100 kbps, ±50 kHz deviation, 2-GFSK, 920.9 MHz, 196
kHz RX BW, 10% PER, 250 byte payload
200 kbps, ±100 kHz deviation, 2-GFSK, 920.8 MHz, 273
kHz RX BW, 10% PER, 250 byte payload
WB-DSSS, 30/60/120/240 kbps (480 ksps), ±195 kHz Deviation, 2-GFSK, 622 RX Bandwidth, FEC = 1:2, DSSS = 1:8/1:4/1:2/1:1
Sensitivity
30 kbps, BER = 10–2, 915 MHz
60 kbps, BER = 10–2, 915 MHz
120 kbps, BER = 10–2, 915 MHz
240 kbps, BER = 10–2, 915 MHz
240 kbps, BER = 10–2, 915 MHz
240 kbps, BER = 10–2, 915 MHz
240 kbps, BER = 10–2, 915 MHz
240 kbps, BER = 10–2, 915 MHz
-109
-108
-106
-105
49
dBm
dBm
dBm
dBm
dB
Sensitivity
Sensitivity
Sensitivity
Blocking ±1 MHz
Blocking ±2 MHz
Blocking ±5 MHz
Blocking ±10 MHz
53
dB
54
dB
65
dB
(1) Wanted signal 3 dB above the reference sensitivity limit according to ETSI EN 300 220 v. 3.1.1
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8.11 861 MHz to 1054 MHz - Transmit (TX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General parameters
VDDR = 1.95 V
Max output power, boost mode
Sub-1 GHz PA(2)
Minimum supply voltage (VDDS ) for
boost mode is 2.1 V
14
dBm
868 MHz and 915 MHz
Max output power,
Sub-1 GHz PA(2)
868 MHz and 915 MHz
868 MHz and 915 MHz
12
24
dBm
dB
Output power programmable range
Sub-1 GHz PA
+10 dBm setting
Over recommended temperature
operating range
Output power variation over temperature
Sub-1 GHz PA
±2
dB
dB
+14 dBm setting
Over recommended temperature
operating range
Output power variation over temperature
Boost mode, Sub-1 GHz PA
±1.5
Spurious emissions and harmonics
+14 dBm setting
ETSI restricted bands
< -54
< -36
< -30
dBm
dBm
dBm
Spurious emissions
30 MHz to 1 GHz
(excluding harmonics)
Sub-1 GHz PA, 868
+14 dBm setting
ETSI outside restricted bands
MHz (3)
1 GHz to 12.75 GHz
+14 dBm setting
measured in 1 MHz bandwidth (ETSI)
(outside ETSI restricted bands)
9.6 kbps, ±2.4 kHz deviation, 2-
GFSK, 20 kHz channel spacing. requirement). TxPower = 12.5 dBm. 868
Narrowband mode.
Adjacent channel (ETSI EN 300 220
Adjacent Channel
Power
-24
-31
dBm
dBm
MHz
9.6 kbps, ±2.4 kHz deviation, 2-
GFSK, 20 kHz channel
spacing. Narrowband mode.
Alternate channel (ETSI EN 300 220
requirement). TxPower = 12.5 dBm. 868
MHz
Alternate Channel
Power
30 MHz to 88 MHz
(within FCC restricted bands)
+14 dBm setting
+14 dBm setting
+14 dBm setting
< -56
< -52
< -50
dBm
dBm
dBm
88 MHz to 216 MHz
(within FCC restricted bands)
Spurious emissions
out-of-band
Sub-1 GHz PA, 915
216 MHz to 960 MHz
(within FCC restricted bands)
MHz (3)
960 MHz to 2390 MHz and above
2483.5 MHz (within FCC
restricted band)
+14 dBm setting
+14 dBm setting
<-42
dBm
dBm
1 GHz to 12.75 GHz
(outside FCC restricted bands)
< -40
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8.11 861 MHz to 1054 MHz - Transmit (TX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted. (1)
PARAMETER
TEST CONDITIONS
+14 dBm setting
MIN
TYP
MAX UNIT
Below 710 MHz
(ARIB T-108)
< -36
dBm
710 MHz to 900 MHz
(ARIB T-108)
+14 dBm setting
+14 dBm setting
+14 dBm setting
+14 dBm setting
+14 dBm setting
< -55
< -55
< -55
< -45
< -30
dBm
dBm
dBm
dBm
dBm
900 MHz to 915 MHz
(ARIB T-108)
Spurious emissions
out-of-band
Sub-1 GHz PA,
930 MHz to 1000 MHz
(ARIB T-108)
920.6/928 MHz (3)
1000 MHz to 1215 MHz
(ARIB T-108)
Above 1215 MHz
(ARIB T-108)
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
+14 dBm setting, 868 MHz
+14 dBm setting, 915 MHz
< -30
< -30
< -30
< -42
< -30
< -30
< -30
< -42
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
dBm
dBm
dBm
dBm
Harmonics
Sub-1 GHz PA
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.
(2) Output power is dependent on RF match. For dual-band devices in the CC13x2 platform, output power might be slightly reduced
depending on RF layout trade-offs.
(3) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±10 kHz offset
±100 kHz offset
±200 kHz offset
±400 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–74
–97
–107
–113
–120
–127
–141
Phase noise in the 868- and 915-MHz
bands
20 kHz PLL loop bandwidth
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
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8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±10 kHz offset
±100 kHz offset
±200 kHz offset
±400 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–93
–93
–94
Phase noise in the 868- and 915-MHz
bands
150 kHz PLL loop bandwith
–104
–121
–130
–140
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
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ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
8.14 359 MHz to 527 MHz - Receive (RX)
When measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
General Parameters
Spurious emissions 25 MHz to 1 GHz 433.92 MHz
TEST CONDITIONS
MIN
TYP
MAX UNIT
< -57
< -47
dBm
dBm
Conducted emissions measured according to ETSI EN
300 220
Spurious emissions 1 GHz to 13 GHz
IEEE 802.15.4, 50 kbps, ±25 kHz Deviation, 2-GFSK, 78 kHz RX Bandwidth
Sensitivity
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
dBm
dBm
dB
–110
10
Saturation limit
Selectivity, +200 kHz
Selectivity, -200 kHz
Selectivity, +400 kHz
Selectivity, -400 kHz
Blocking, +1 MHz
Blocking, -1 MHz
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
Blocking, -10 MHz
48
43
dB
53
dB
44
dB
60
dB
54
dB
62
dB
61
dB
75
dB
75
dB
Image rejection (image compensation
enabled)
BER = 10–2, 433.92 MHz(1)
44
95
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
Starting from the sensitivity limit across the given
dynamic range
200 kbps, ±50 kHz Deviation, 2-GFSK, 273 kHz RX Bandwidth
Sensitivity
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
BER = 10–2, 433.92 MHz(1)
dBm
dBm
dB
–104
10
Saturation limit
Selectivity, ±400 kHz
Blocking, ±1 MHz
Blocking, ±2 MHz
Blocking, ±10 MHz
48
51
dB
53
dB
68
dB
Image rejection (image compensation
enabled)
BER = 10–2, 433.92 MHz(1)
45
89
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
Starting from the sensitivity limit across the given
dynamic range
Narrowband, 4.8 kbps, ±2 kHz Deviation, 2-GFSK, 10.1 kHz RX Bandwidth
Sensitivity
BER = 10–2, 426.1 MHz
BER = 10–2, 426.1 MHz
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
dBm
dBm
dB
–120
10
Saturation limit
Selectivity, +12.5 kHz
Selectivity, -12.5 kHz
Selectivity, +25 kHz
Selectivity, -25 kHz
Blocking, +1 MHz
Blocking, -1 MHz
Blocking, +2 MHz
53
52
dB
53
dB
52
dB
70
dB
66
dB
72
dB
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8.14 359 MHz to 527 MHz - Receive (RX) (continued)
When measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
BER = 10–2, 426.1 MHz(1)
MIN
TYP
MAX UNIT
Blocking, -2 MHz
70
dB
dB
dB
Blocking, +10 MHz
Blocking, -10 MHz
BER = 10–2, 426.1 MHz(1)
BER = 10–2, 426.1 MHz(1)
84
84
Image rejection (image compensation
enabled)
BER = 10–2, 426.1 MHz(1)
44
102
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit
Starting from the sensitivity limit across the given
dynamic range
4.8 kbps, OOK, 34.1 kHz RX Bandwidth
Sensitivity
BER = 10–2, 433.92 MHz
-116
dBm
SimpleLink™ Long Range, 2.5/5 kbps (20 ksps), ±5 kHz Deviation, 2-GFSK, 34 kHz RX Bandwidth, FEC = 1:2, DSSS = 1:4/1:2
Sensitivity
2.5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
5 kbps, BER = 10–2, 433.92 MHz(1)
-121
-119
10
dBm
dBm
dBm
dB
Sensitivity
Saturation limit
Selectivity, +100 kHz
Selectivity, -100 kHz
Blocking, +1 MHz
Blocking, -1 MHz
Blocking, +2 MHz
Blocking, -2 MHz
Blocking, +10 MHz
Blocking, -10 MHz
55
53
dB
69
dB
65
dB
71
dB
70
dB
84
dB
84
dB
Image rejection (image compensation
enabled)
5 kbps, BER = 10–2, 433.92 MHz
Starting from the sensitivity limit
49
101
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit across the given
dynamic range
(1) Wanted signal 3 dB above sensitivity limit
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8.15 359 MHz to 527 MHz - Transmit (TX)
When measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements
are performed conducted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General parameters
Max output power,
Sub-1 GHz PA(2)
433.92 MHz, without BOOST (VDDR =
1.7 V)
13
24
dBm
dB
Output power programmable range
Sub-1 GHz PA
433.92 MHz, without BOOST (VDDR =
1.7 V)
+13 dBm setting. 433.92 MHz
Output power variation over temperature, Sub-1 GHz PA Over recommended temperature
operating range
±1.5
dB
Spurious emissions and harmonics
+10 dBm setting
ETSI restricted bands
< -54
< -36
< -30
dBm
dBm
dBm
Spurious emissions
30 MHz to 1 GHz
(excluding harmonics)
Sub-1 GHz PA, 433.92
MHz (3)
+10 dBm setting
ETSI outside restricted bands
1 GHz to 12.75 GHz
+10 dBm setting
measured in 1 MHz bandwidth (ETSI)
(outside ETSI restricted bands)
Outside the necessary requency
band
+10 dBm setting
< -26
dBm
(ARIB T-67)
710 MHz to 900 MHz
(ARIB T-67)
+10 dBm setting
< -55
< -55
< -55
< -45
< -30
< -36
< -30
< -30
< -30
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Spurious emissions
out-of-band
900 MHz to 915 MHz
(ARIB T-67)
+10 dBm setting
Sub-1 GHz PA, 429
MHz (3)
930 MHz to 1000 MHz
(ARIB T-67)
+10 dBm setting
1000 MHz to 1215 MHz
(ARIB T-67)
+10 dBm setting
Above 1215 MHz
(ARIB T-67)
+10 dBm setting
Harmonics
Sub-1 GHz PA
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
+13 dBm setting, 433 MHz
Harmonics
Sub-1 GHz PA
Harmonics
Sub-1 GHz PA
Harmonics
Sub-1 GHz PA
(1) Some combinations of frequency, data rate and modulation format requires use of external crystal load capacitors for regulatory
compliance. More details can be found in the device errata.
(2) Output power is dependent on RF match. For dual-band devices in the CC13x2 platform, output power might be slightly reduced
depending on RF layout trade-offs.
(3) Suitable for systems targeting compliance with EN 300 220, EN 303 131, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
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8.16 359 MHz to 527 MHz - PLL Phase Noise
When measured on the LAUNCHXL-CC1352P-4 reference design with Tc = 25 °C, VDDS = 3.0 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
-103
-101
-101
-106
-122
-133
-143
-86
MAX
UNIT
±10 kHz offset
±100 kHz offset
±200 kHz offset
±400 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase noise in the 429 MHz band
200 kHz PLL loop bandwidth
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
±10 kHz offset
±100 kHz offset
±200 kHz offset
±400 kHz offset
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
-108
-115
-122
-130
-137
-145
Phase noise in the 433 MHz band
20 kHz PLL loop bandwidth
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ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
8.17 143 MHz to 176 MHz - Receive (RX)
When measured on the CC1352EM-XS169-XS24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
General Parameters
Spurious emissions 25 MHz to 1 GHz 169.44375 MHz
TEST CONDITIONS
MIN
TYP
MAX UNIT
< -57
< -47
dBm
dBm
Conducted emissions measured according to ETSI EN
300 220
Spurious emissions 1 GHz to 13 GHz
WMBUS N-MODE, 4.8 kbps, ±2.4 kHz Deviation, 2-GFSK, 10 kHz RX Bandwidth
Sensitivity 4.8 kbps ± 2.4 kHz
Saturation limit
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
BER = 10–2, 169.40625 MHz
dBm
dBm
dB
–119
10
Selectivity, +12.5 kHz (1)
Selectivity, -12.5 kHz (1)
Selectivity, +25 kHz (1)
Selectivity, -25 kHz (1)
Blocking, +1 MHz (1)
Blocking, -1 MHz (1)
Blocking, +2 MHz (1)
Blocking, -2 MHz (1)
Blocking, +10 MHz (1)
Blocking, -10 MHz (1)
51
51
dB
52
dB
52
dB
73
dB
72
dB
77
dB
75
dB
86
dB
86
dB
Image rejection (image compensation
enabled) (1)
BER = 10–2, 169.40625 MHz
Starting from the sensitivity limit
46
91
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit across the given
dynamic range
WMBUS N-MODE, 2.4 kbps, ±2.4 kHz Deviation, 2-GFSK, 10 kHz RX Bandwidth
Sensitivity
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
BER = 10–2, 169.43125 MHz
dBm
dBm
dB
–121
10
Saturation limit
Selectivity, +12.5 kHz (1)
Selectivity, -12.5 kHz (1)
Selectivity, +25 kHz (1)
Selectivity, -25 kHz (1)
Blocking, +1 MHz (1)
Blocking, -1 MHz (1)
Blocking, +2 MHz (1)
Blocking, -2 MHz (1)
Blocking, +10 MHz (1)
Blocking, -10 MHz (1)
51
51
dB
52
dB
52
dB
74
dB
73
dB
78
dB
77
dB
88
dB
87
dB
Image rejection (image compensation
enabled) (1)
BER = 10–2, 169.43125 MHz
Starting from the sensitivity limit
50
92
±3
dB
dB
dB
RSSI dynamic range
RSSI accuracy
Starting from the sensitivity limit across the given
dynamic range
(1) Wanted signal 3 dB above sensitivity limit
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8.18 143 MHz to 176 MHz - Transmit (TX)
When measured on the CC1352EM-XS169-XS24 reference design with Tc = 25 °C, VDDS = 3.0 V with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General parameters
169.44375 MHz, without BOOST
(VDDR = 1.7 V), single ended
configuration.
Min output power,
Sub-1 GHz PA(1)
Min output power, Sub-1 GHz
PA(1)
-10
9
dBm
dBm
dBc
169.44375 MHz, without BOOST
(VDDR = 1.7 V), single ended
configuration.
Max output power, Sub-1 GHz PA(1)
0 dBm setting, 4.8 kbit/s, 169.44375
MHz, without BOOST (VDDR = 1.7 V),
single ended configuration.
Adjacent channel power Sub-1 GHz PA
-47
Spurious emissions and harmonics
0 dBm setting, ETSI restricted bands.
Measured in 100 kHz bandwidth
< -54
< -36
< -30
< -36
< -54
< -54
< -36
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Spurious emissions
30 MHz to 1 GHz
(excluding harmonics)
Sub-1 GHz PA, 433.92
0 dBm setting, ETSI outside restricted
bands
MHz (2)
1 GHz to 12.75 GHz
0 dBm setting, measured in 1 MHz
bandwidth (ETSI)
(outside ETSI restricted bands)
Harmonics
Sub-1 GHz PA
Second harmonic
Third harmonic
Fourth harmonic
Fifth harmonic
0 dBm setting, 169.44375 MHz
0 dBm setting, 169.44375 MHz
0 dBm setting, 169.44375 MHz
0 dBm setting, 169.44375 MHz
Harmonics
Sub-1 GHz PA
Harmonics
Sub-1 GHz PA
Harmonics
Sub-1 GHz PA
(1) Output power is dependent on RF match. For dual-band devices in the CC13x2 platform, output power might be slightly reduced
depending on RF layout trade-offs.
(2) Suitable for systems targeting compliance with EN 300 220.
8.19 143 MHz to 176 MHz - PLL Phase Noise
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V. PLL settings for
narrowband operation is used.
PARAMETER
TEST CONDITIONS
MIN
TYP
–108
–108
–110
-114
MAX
UNIT
±10 kHz offset
±100 kHz offset
±200 kHz offset
±400 kHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase noise in the 169 MHz band, 150
kHz PLL loop bandwidth
±1000 kHz offset
±2000 kHz offset
±10000 kHz offset
-131
–141
-150
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8.20 Bluetooth Low Energy - Receive (RX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
125 kbps (LE Coded)
Receiver sensitivity
Receiver saturation
TEST CONDITIONS
MIN
TYP
MAX UNIT
Differential mode. BER = 10–3
Differential mode. BER = 10–3
dBm
dBm
–105
>5
Difference between the incoming carrier
frequency and the internally generated carrier
frequency
Frequency error tolerance
kHz
> (–300 / 300)
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Data rate error tolerance
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
Selectivity, ±2 MHz(1)
Selectivity, ±3 MHz(1)
Selectivity, ±4 MHz(1)
ppm
ppm
dB
> (–320 / 240)
> (–125 / 125)
–1.5
Difference between incoming data rate and the
internally generated data rate (255-byte packets)
Wanted signal at –79 dBm, modulated interferer
in channel, BER = 10–3
Wanted signal at –79 dBm, modulated interferer
8 / 4.5(2)
dB
at ±1 MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer
44 / 39 (2)
46 / 44(2)
dB
at ±2 MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer
dB
at ±3 MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer
44 / 46(2)
dB
at ±4 MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer
at ≥±6 MHz, BER = 10–3
Selectivity, ±6 MHz(1)
48 / 44(2)
51 / 45(2)
39
dB
dB
dB
Wanted signal at –79 dBm, modulated interferer
at ≥±7 MHz, BER = 10–3
Selectivity, ±7 MHz
Wanted signal at –79 dBm, modulated interferer
Selectivity, Image frequency(1)
at image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co-
channel –1 MHz. Wanted signal at –79 dBm,
modulated interferer at ±1 MHz from image
frequency, BER = 10–3
Selectivity, Image frequency ±1
MHz(1)
4.5 / 44 (2)
dB
500 kbps (LE Coded)
Receiver sensitivity
Receiver saturation
Differential mode. BER = 10–3
Differential mode. BER = 10–3
dBm
dBm
–100
> 5
Difference between the incoming carrier
frequency and the internally generated carrier
frequency
Frequency error tolerance
kHz
> (–300 / 300)
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Data rate error tolerance
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
Selectivity, ±2 MHz(1)
Selectivity, ±3 MHz(1)
ppm
ppm
dB
> (–450 / 450)
> ( –175 / 175)
–3.5
Difference between incoming data rate and the
internally generated data rate (255-byte packets)
Wanted signal at –72 dBm, modulated interferer
in channel, BER = 10–3
Wanted signal at –72 dBm, modulated interferer
8 / 4(2)
dB
at ±1 MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer
44 / 37 (2)
46 / 46(2)
dB
at ±2 MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer
dB
at ±3 MHz, BER = 10–3
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8.20 Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal at –72 dBm, modulated interferer
Selectivity, ±4 MHz(1)
45 / 47(2)
dB
at ±4 MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer
at ≥±6 MHz, BER = 10–3
Selectivity, ±6 MHz(1)
46 / 45(2)
49 / 45(2)
37
dB
dB
dB
Wanted signal at –72 dBm, modulated interferer
at ≥±7 MHz, BER = 10–3
Selectivity, ±7 MHz
Wanted signal at –72 dBm, modulated interferer
Selectivity, Image frequency(1)
at image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co-
channel –1 MHz. Wanted signal at –72 dBm,
modulated interferer at ±1 MHz from image
frequency, BER = 10–3
Selectivity, Image frequency ±1
MHz(1)
4 / 46(2)
dB
1 Mbps (LE 1M)
Receiver sensitivity
Receiver saturation
Differential mode. BER = 10–3
Differential mode. BER = 10–3
dBm
dBm
–97
> 5
Difference between the incoming carrier
frequency and the internally generated carrier
frequency
Frequency error tolerance
kHz
> (–350 / 350)
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
ppm
dB
dB
dB
dB
dB
dB
dB
> ( –750 / 750)
–6
Wanted signal at –67 dBm, modulated interferer
in channel, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
7 / 4(2)
at ±1 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
Selectivity, ±2 MHz(1)
40 / 33(2)
36 / 41 (2)
36 / 45(2)
40
at ±2 MHz,BER = 10–3
Wanted signal at –67 dBm, modulated interferer
Selectivity, ±3 MHz(1)
at ±3 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
Selectivity, ±4 MHz(1)
at ±4 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
at ≥±5 MHz, BER = 10–3
Selectivity, ±5 MHz or more(1)
Selectivity, image frequency(1)
Wanted signal at –67 dBm, modulated interferer
33
at image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co-
channel –1 MHz. Wanted signal at –67 dBm,
modulated interferer at ±1 MHz from image
frequency, BER = 10–3
Selectivity, image frequency
±1 MHz(1)
4 / 41(2)
dB
Out-of-band blocking(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
dBm
dBm
dBm
–10
–18
–12
–2
Wanted signal at 2402 MHz, –64 dBm. Two
interferers at 2405 and 2408 MHz respectively, at
the given power level
Intermodulation
dBm
dBm
–42
Spurious emissions,
30 to 1000 MHz(4)
Measurement in a 50-Ωsingle-ended load.
< –59
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8.20 Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Spurious emissions,
1 to 12.75 GHz(4)
dBm
Measurement in a 50-Ωsingle-ended load.
< –47
RSSI dynamic range
RSSI accuracy
70
±4
dB
dB
2 Mbps (LE 2M)
Differential mode. Measured at SMA connector,
BER = 10–3
Receiver sensitivity
Receiver saturation
dBm
dBm
–92
Differential mode. Measured at SMA connector,
BER = 10–3
> 5
Difference between the incoming carrier
frequency and the internally generated carrier
frequency
Frequency error tolerance
kHz
> (–500 / 500)
Difference between incoming data rate and the
internally generated data rate (37-byte packets)
Data rate error tolerance
Co-channel rejection(1)
ppm
dB
> (–700 / 750)
–7
Wanted signal at –67 dBm, modulated interferer
in channel,BER = 10–3
Wanted signal at –67 dBm, modulated interferer
at ±2 MHz, Image frequency is at –2 MHz, BER =
10–3
Selectivity, ±2 MHz(1)
8 / 4(2)
dB
Wanted signal at –67 dBm, modulated interferer
Selectivity, ±4 MHz(1)
36 / 36 (2)
37 / 36(2)
4
dB
dB
dB
at ±4 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
Selectivity, ±6 MHz(1)
at ±6 MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer
Selectivity, image frequency(1)
at image frequency, BER = 10–3
Note that Image frequency + 2 MHz is the Co-
channel. Wanted signal at –67 dBm, modulated
interferer at ±2 MHz from image frequency, BER =
10–3
Selectivity, image frequency
±2 MHz(1)
–7 / 36(2)
dB
Out-of-band blocking(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
dBm
dBm
dBm
–16
–21
–15
–12
Wanted signal at 2402 MHz, –64 dBm. Two
interferers at 2408 and 2414 MHz respectively, at
the given power level
Intermodulation
dBm
–38
(1) Numbers given as I/C dB
(2) X / Y, where X is +N MHz and Y is –N MHz
(3) Excluding one exception at Fwanted / 2, per Bluetooth Specification
(4) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
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8.21 Bluetooth Low Energy - Transmit (TX)
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
5
MAX UNIT
dBm
General Parameters
Max output power,
2.4 GHz PA
Differential mode, delivered to a single-ended 50 Ωload through a balun
Differential mode, delivered to a single-ended 50 Ωload through a balun
Output power
programmable
range,
26
dB
2.4 GHz PA
Spurious emissions and harmonics
f < 1 GHz, outside restricted
dBm
dBm
dBm
< –36
< –54
< –55
bands
f < 1 GHz, restricted bands
ETSI
Spurious emissions,
2.4 GHz PA (1)
f < 1 GHz, restricted bands
FCC
+5 dBm setting
f > 1 GHz, including harmonics
Second harmonic
dBm
dBm
dBm
< –42
< –42
< –42
Harmonics,
2.4 GHz PA (1)
Third harmonic
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
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8.22 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
General Parameters
Receiver sensitivity
Receiver saturation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PER = 1%
PER = 1%
dBm
dBm
–100
> 5
Wanted signal at –82 dBm, modulated interferer at
±5 MHz, PER = 1%
Adjacent channel rejection
Alternate channel rejection
36
57
dB
dB
Wanted signal at –82 dBm, modulated interferer at
±10 MHz, PER = 1%
Wanted signal at –82 dBm, undesired signal is
IEEE 802.15.4 modulated channel, stepped through
all channels 2405 to 2480 MHz, PER = 1%
Channel rejection, ±15 MHz or
more
59
dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
57
63
63
66
60
60
63
65
dB
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
dB
Spurious emissions, 30 MHz to
1000 MHz(1)
dBm
dBm
ppm
ppm
Measurement in a 50-Ω single-ended load
Measurement in a 50-Ω single-ended load
–66
–53
Spurious emissions, 1 GHz to
12.75 GHz(1)
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Symbol rate error tolerance
> 350
> 1000
Difference between incoming symbol rate and the
internally generated symbol rate
RSSI dynamic range
RSSI accuracy
95
±4
dB
dB
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
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8.23 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
When measured on the CC1352REM-XD7793-XD24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Max output power, 2.4
GHz PA
5
dBm
dB
Differential mode, delivered to a single-ended 50-Ωload through a balun
Differential mode, delivered to a single-ended 50-Ωload through a balun
Output power
programmable range,
2.4 GHz PA
26
Spurious emissions and harmonics
f < 1 GHz, outside restricted
< -36
< -47
dBm
dBm
dBm
dBm
bands
f < 1 GHz, restricted bands
ETSI
Spurious emissions,
2.4 GHz PA (1) (2)
f < 1 GHz, restricted bands
FCC
< -55
+5 dBm setting
f > 1 GHz, including
harmonics
< –42
Second harmonic
Third harmonic
< -42
< -42
dBm
dBm
Harmonics,
2.4 GHz PA (1)
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector
magnitude,
2.4-GHz PA
+5 dBm setting
2
%
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
(2) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at 2480 MHz.
8.24 Timing and Switching Characteristics
8.24.1 Reset Timing
PARAMETER
MIN TYP
MAX UNIT
RESET_N low duration
1
µs
8.24.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
MCU, Reset to Active(1)
TEST CONDITIONS
MIN
TYP
850 - 3000
850 - 3000
160
MAX
UNIT
µs
MCU, Shutdown to Active(1)
MCU, Standby to Active
MCU, Active to Standby
MCU, Idle to Active
µs
µs
36
µs
14
µs
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value.
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8.24.3 Clock Specifications
8.24.3.1 48 MHz Clock Input (TCXO)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Clock frequency
48
MHz
TCXO clipped sine output
connected to pin X48M_P
through series capacitor
TCXO clipped sine output, peak-to-peak
0.8
1.7
V
TCXO with CMOS output, High input voltage TCXO with CMOS output
directly coupled to pin
TCXO with CMOS output, Low input voltage
X48M_P
1.3
0
VDDR
0.3
V
V
(1) Probing or otherwise stopping the TCXO while the DC/DC converter is enabled may cause permanent damage to the device.
(2) See CC13xx/CC26xx Hardware Configuration and PCB Design Considerations on how to add TCXO support
8.24.3.2 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
MAX
UNIT
Crystal frequency
48
MHz
Equivalent series resistance
6 pF < CL ≤9 pF
ESR
ESR
20
60
80
Ω
Equivalent series resistance
5 pF < CL ≤ 6 pF
Ω
Motional inductance, relates to the load capacitance that is used for the
crystal (CL in Farads)(5)
2
LM
CL
< 3 × 10–25 / CL
H
Crystal load capacitance(4)
Start-up time(2)
5
7(3)
9
pF
µs
200
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations. See the device errata for further details.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.24.3.3 48 MHz RC Oscillator (RCOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
%
Frequency
48
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Start-up time
±1
±0.25
5
%
µs
(1) Accuracy relative to the calibration source (XOSC_HF)
8.24.3.4 2 MHz RC Oscillator (RCOSC_MF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
µs
Calibrated frequency
Start-up time
2
5
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8.24.3.5 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
Crystal frequency
ESR
CL
Equivalent series resistance
Crystal load capacitance
100
12
6
7(1)
pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.24.3.6 32 kHz RC Oscillator (RCOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.8 (1)
50
MAX
UNIT
kHz
Calibrated frequency
Temperature coefficient.
ppm/°C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
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8.24.4 Synchronous Serial Interface (SSI) Characteristics
8.24.4.1 Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PARAMETER
NO.
MIN
TYP
MAX
UNIT
S1
tclk_per
tclk_high
tclk_low
SSIClk cycle time
SSIClk high time
SSIClk low time
12
65024 System Clocks (2)
S2(1)
S3(1)
0.5
0.5
tclk_per
tclk_per
(1) Refer to SSI timing diagrams 图8-1, 图8-2, and 图8-3
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
图8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
图8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
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S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
图8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
8.24.5 UART
8.24.5.1 UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
UART rate
3
MBaud
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8.25 Peripheral Characteristics
8.25.1 ADC
8.25.1.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample Rate
200
Offset
Internal 4.3 V equivalent reference(2)
Internal 4.3 V equivalent reference(2)
–0.24
7.14
>–1
±4
Gain error
DNL(4) Differential nonlinearity
INL
Integral nonlinearity
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
9.8
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
VDDS as reference, 200 kSamples/s, 9.6 kHz input
tone
10.1
ENOB Effective number of bits
Bits
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input
tone
11.1
Internal reference, voltage scaling disabled,
11.3
11.6
–65
–70
14-bit mode, 200 kSamples/s, 600 Hz input tone (5)
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone (5)
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
VDDS as reference, 200 kSamples/s, 9.6 kHz input
Total harmonic distortion tone
THD
dB
dB
dB
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input
tone
–72
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
63
Signal-to-noise
and
distortion ratio
VDDS as reference, 200 kSamples/s, 9.6 kHz input
tone
SINAD,
SNDR
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input
tone
68
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
73
VDDS as reference, 200 kSamples/s, 9.6 kHz input
tone
Spurious-free dynamic
range
SFDR
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input
tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Internal 4.3 V equivalent reference(2)
VDDS as reference
50
0.42
0.6
Clock Cycles
Current consumption
Current consumption
mA
mA
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8.25.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Equivalent fixed internal reference (input voltage
scaling enabled). For best accuracy, the ADC
conversion should be initiated through the TI-RTOS API
in order to include the gain/offset compensation factors
stored in FCFG1
Reference voltage
4.3(2) (3)
V
Fixed internal reference (input voltage scaling
disabled). For best accuracy, the ADC conversion
should be initiated through the TI-RTOS API in order to
include the gain/offset compensation factors stored in
FCFG1. This value is derived from the scaled value
(4.3 V) as follows:
Reference voltage
1.48
V
Vref = 4.3 V × 1408 / 4095
Reference voltage
Reference voltage
VDDS as reference, input voltage scaling enabled
VDDS as reference, input voltage scaling disabled
VDDS
V
V
VDDS /
2.82(3)
200 kSamples/s, voltage scaling enabled. Capacitive
input, Input impedance depends on sampling frequency
and sampling time
Input impedance
>1
MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings (see 节8.1) at all times
(4) No missing codes
(5) ADC_output = Σ(4n samples ) >> n, n = desired extra bits
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8.25.2 DAC
8.25.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
General Parameters
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
Bits
Any load, any VREF, pre-charge OFF, DAC charge-
pump ON
1.8
2.0
3.8
3.8
VDDS
Supply voltage
Clock frequency
External Load(4), any VREF, pre-charge OFF, DAC
charge-pump OFF
V
Any load, VREF = DCOUPL, pre-charge ON
Buffer ON (recommended for external load)
Buffer OFF (internal load)
2.6
16
16
3.8
250
FDAC
kHz
1000
VREF = VDDS, buffer OFF, internal load
13
13.8
20
Voltage output settling
time
1 / FDAC
VREF = VDDS, buffer ON, external capacitive load = 20
pF(3)
External capacitive load
External resistive load
Short circuit current
200
400
pF
MΩ
µA
10
VDDS = 3.8 V, DAC charge-pump OFF
VDDS = 3.0 V, DAC charge-pump ON
VDDS = 3.0 V, DAC charge-pump OFF
50.8
51.7
53.2
48.7
70.2
46.3
88.9
Max output impedance
ZMAX
Vref = VDDS, buffer ON, VDDS = 2.0 V, DAC charge-pump ON
kΩ
CLK 250 kHz
VDDS = 2.0 V, DAC charge-pump OFF
VDDS = 1.8 V, DAC charge-pump ON
VDDS = 1.8 V, DAC charge-pump OFF
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power
Differential nonlinearity
Clocked Comparator
±1
FDAC = 250 kHz
DNL
LSB(1)
LSB(1)
LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power
Differential nonlinearity
Clocked Comparator
±1.2
FDAC = 16 kHz
VREF = VDDS = 3.8 V
VREF = VDDS= 3.0 V
±0.64
±0.81
±1.27
±3.43
±2.88
±2.37
±0.78
±0.77
±3.46
±3.44
±4.70
±4.11
Offset error(2)
Load = Continuous Time
VREF = VDDS = 1.8 V
VREF = DCOUPL, pre-charge ON
Comparator
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF = VDDS = 3.0 V
Offset error(2)
Load = Low Power
VREF = VDDS= 1.8 V
VREF = DCOUPL, pre-charge ON
Clocked Comparator
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
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8.25.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±1.53
±1.71
±2.10
±6.00
±3.85
±5.84
±2.92
±3.06
±3.91
±7.84
±4.06
±6.94
0.03
3.62
0.02
2.86
0.01
1.71
0.01
1.21
1.27
2.46
0.01
1.41
0.03
3.61
0.02
2.85
0.01
1.71
0.01
1.21
1.27
2.46
0.01
1.41
VREF = VDDS = 3.8 V
VREF = VDDS = 3.0 V
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF =VDDS= 3.0 V
Max code output voltage
variation(2)
Load = Low Power
Clocked Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
Output voltage range(2)
Load = Continuous Time
Comparator
V
VREF = ADCREF, code 255
VREF = VDDS = 3.8 V, code 1
VREF = VDDS= 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS = 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
Output voltage range(2)
Load = Low Power
Clocked Comparator
V
VREF = ADCREF, code 255
External Load (Keysight 34401A Multimeter)
VREF = VDDS, FDAC = 250 kHz
±1
±1
±1
±1
INL
Integral nonlinearity
VREF = DCOUPL, FDAC = 250 kHz
VREF = ADCREF, FDAC = 250 kHz
VREF = VDDS, FDAC = 250 kHz
LSB(1)
LSB(1)
DNL
Differential nonlinearity
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8.25.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.20
±0.25
±0.45
±1.55
±1.30
±1.10
±0.60
±0.55
±0.60
±3.45
±2.10
±1.90
0.03
MAX
UNIT
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS = 1.8 V
Offset error
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS= 1.8 V
Max code output voltage
variation
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS = 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
3.61
0.02
2.85
0.02
Output voltage range
Load = Low Power
Clocked Comparator
1.71
V
0.02
1.20
1.27
2.46
0.02
VREF = ADCREF, code 255
1.42
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter
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8.25.3 Temperature and Battery Monitor
8.25.3.1 Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Accuracy
Accuracy
2
-40 °C to 0 °C
0 °C to 105 °C
±4.0
±2.5
3.6
°C
°C
Supply voltage coefficient(1)
°C/V
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.25.3.2 Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
25
1.8
3.8
Integral nonlinearity (max)
Accuracy
23
22.5
-32
-1
mV
mV
mV
%
VDDS = 3.0 V
Offset error
Gain error
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8.25.4 Comparators
8.25.4.1 Low-Power Clocked Comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Input voltage range
Clock frequency
0
VDDS
V
SCLK_LF
Using internal DAC with VDDS as reference
voltage, DAC code = 0 - 255
0.024 -
2.865
Internal reference voltage(1)
V
Measured at VDDS / 2, includes error from
internal DAC
Offset
±5
1
mV
Clock
Cycle
Decision time
Step from –50 mV to 50 mV
(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See 节8.25.2.1
8.25.4.2 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
Offset
Measured at VDDS / 2
±5
0.78
8.6
mV
µs
Decision time
Current consumption
Step from –10 mV to 10 mV
Internal reference
µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.25.5 Current Source
8.25.5.1 Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Current source programmable output range
(logarithmic range)
0.25 - 20
0.25
µA
µA
Resolution
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8.25.6 GPIO
8.25.6.1 GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.56
0.24
1.59
0.21
73
V
V
V
IOCURR = 1
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
µA
µA
GPIO pulldown current
19
IH = 1, transition voltage for input read as 0 →
1
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
GPIO input hysteresis
1.08
0.73
0.35
V
V
V
IH = 1, transition voltage for input read as 1 →
0
IH = 1, difference between 0 →1
and 1 →0 points
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.59
0.42
2.63
0.40
V
V
V
V
IOCURR = 1
Input mode, pullup enabled, Vpad = 0 V
282
110
µA
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →
1
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.97
1.55
0.42
V
V
V
IH = 1, transition voltage for input read as 1 →
0
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
TA = 25 °C
Lowest GPIO input voltage reliably interpreted
as a High
VIH
0.8*VDDS
V
Highest GPIO input voltage reliably interpreted
as a Low
VIL
0.2*VDDS
V
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8.26 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions for device limits. Values exceeding these limits are for reference only.
8.26.1 MCU Current
Active Current vs. VDDS
Running CoreMark, SCLK_HF = 48 MHz RCOSC
6
5.5
5
4.5
4
3.5
3
2.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D001
图8-4. Active Mode (MCU) Current vs.
Supply Voltage (VDDS)
Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC
12
10
8
6
4
2
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D006
图8-5. Standby Mode (MCU) Current vs.
Temperature
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Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC VDDS = 3.6 V
12
10
8
6
4
2
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
图8-6. Standby Mode (MCU) Current vs.
Temperature (VDDS = 3.6 V)
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8.26.2 RX Current
RX Current vs. Temperature
50 kbps, 868.3 MHz
8
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D008
图8-7. RX Current vs.
Temperature (50 kbps, 868.3 MHz)
RX Current vs. Temperature
50 kbps, 868.3 MHz, VDDS = 3.6 V
8
7.8
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D009
图8-8. RX Current vs.
Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V)
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RX Current vs. Temperature
BLE 1 Mbps, 2.44 GHz
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
6.5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D010
图8-9. RX Current vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
RX Current vs. VDDS
50 kbps, 868.3 MHz
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D012
图8-10. RX Current vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
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RX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D013
图8-11. RX Current vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
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8.26.3 TX Current
TX Current vs. Temperature
50 kbps, 868.3 MHz, +10 dBm
18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D014
图8-12. TX Current vs.
Temperature (50 kbps, 868.3 MHz)
TX Current vs. Temperature
50 kbps, 868.3 MHz, +10 dBm, VDDS = 3.6 V
18
17.7
17.4
17.1
16.8
16.5
16.2
15.9
15.6
15.3
15
14.7
14.4
14.1
13.8
13.5
13.2
12.9
12.6
12.3
12
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D015
图8-13. TX Current vs.
Temperature (50 kbps, 868.3 MHz, VDDS = 3.6 V)
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TX Current vs. Temperature
BLE 1 Mbps, 2.44 GHz, 0 dBm
9
8.85
8.7
8.55
8.4
8.25
8.1
7.95
7.8
7.65
7.5
7.35
7.2
7.05
6.9
6.75
6.6
6.45
6.3
6.15
6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D018
图8-14. TX Current vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
TX Current vs. VDDS
50 kbps, 868.3 MHz, +10 dBm
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
D022
图8-15. TX Current vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
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TX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D024
图8-16. TX Current vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
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表8-1 and 表8-2 show typical TX current and output power for different output power settings.
表8-1. Typical TX Current and Output Power (915 MHz, VDDS = 3.6 V)
CC1352R at 915 MHz, VDDS = 3.6 V (Measured on CC1352REM-XD7793-XD24)
txPower
0x013F
0xB224
0xA410
0x669A
0x3E92
0x3EDC
0x2CD8
0x26D4
0x20D1
0x1CCE
0x16CD
0x14CB
0x12CA
0x12C9
0x10C8
0x0AC4
0x0AC2
0x06C1
0x04C0
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
14
12.5
12
11
10
9
13.6
12
24.2
17.6
16.5
14.9
13.5
12.7
11.9
11
11.5
10.5
9.4
8.5
8
7.7
7
6.5
6
5.4
10.2
9.3
9
5
3.8
4
3.2
3
1.7
8.3
8
2
0.8
1
-0.3
-1.4
-8.6
-15.9
-22.3
-24.4
7.6
7.3
5.8
5.1
4.8
4.6
0
-5
-10
-15
-20
表8-2. Typical TX Current and Output Power (2.4 GHz, VDDS = 3.0 V)
CC1352R at 2.4 GHz, VDDS = 3.0 V (Measured on CC1352REM-XD7793-XD24)
txPower
0x7217
0x4E63
0x385D
0x3259
0x2856
0x2853
0x12D6
0x0ACF
0x06CA
0x04C6
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
5
4
4.4
3.0
9.6
8.9
8.3
7.9
7.5
7.1
6.1
5.5
5.1
4.8
3
1.8
2
0.7
1
-0.3
-1.5
-6.7
-11.5
-16.7
-22.7
0
-5
-10
-15
-20
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8.26.4 RX Performance
Sensitivity vs. Frequency
50 kbps
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
863
864
865
866
867
868
869
870
Frequency [MHz]
D026
图8-17. Sensitivity vs. Frequency (50 kbps, 868 MHz)
Sensitivity vs. Frequency
50 kbps
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
900
903
906
909
912
915
918
921
924
927
930
Frequency [MHz]
D027
图8-18. Sensitivity vs. Frequency (50 kbps, 915 MHz)
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Sensitivity vs. Frequency
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
D028
图8-19. Sensitivity vs. Frequency (BLE 1 Mbps, 2.44 GHz)
Sensitivity vs. Frequency
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps)
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
2.48
Frequency [GHz]
D029
图8-20. Sensitivity vs. Frequency (250 kbps, 2.44 GHz)
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Sensitivity vs. Temperature
50 kbps, 868.3 MHz
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D030
图8-21. Sensitivity vs. Temperature (50 kbps, 868.3 MHz)
Sensitivity vs. Temperature
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D031
图8-22. Sensitivity vs. Temperature (BLE 1 Mbps, 2.44 GHz)
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Sensitivity vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D032
图8-23. Sensitivity vs. Temperature (250 kbps, 2.44 GHz)
Sensitivity vs. VDDS
50 kbps, 868.3 MHz
-105
-106
-107
-108
-109
-110
-111
-112
-113
-114
-115
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D033
图8-24. Sensitivity vs. Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
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Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D034
图8-25. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz, DCDC Off
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D035
图8-26. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, DCDC Off)
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Sensitivity vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D036
图8-27. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz)
Selectivity vs. Frequency Offset
50 kbps, 868.3 MHz
80
60
40
20
0
-20
-10
-8
-6
-4
-2
0
2
4
6
8
10
Frequency [MHz]
D038
图8-28. Selectivity vs. Frequency Offset (50 kbps, 868.3 MHz)
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图8-29. PER vs. Level vs. Frequency (SimpleLink™ Long Range 5 kbps, 868 MHz)
图8-30. Narrowband, 9.6 kbps ±2.4 kHz deviation, 2-GFSK, 868 MHz, 17.1 kHz RX Bandwidth
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图8-31. Narrowband, 4.8 kbps ±2 kHz deviation, 2-GFSK, 426.1 MHz, 10.1 kHz RX Bandwidth
图8-32. Narrowband, WMBUS N-MODE, 2.4 kbps, 169 MHz
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8.26.5 TX Performance
Output Power vs. Temperature
50 kbps, 868.3 MHz, +14 dBm
14
13.8
13.6
13.4
13.2
13
12.8
12.6
12.4
12.2
12
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D039
图8-33. Output Power vs.
Temperature (50 kbps, 868.3 MHz)
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D041
图8-34. Output Power vs.
Temperature (BLE 1 Mbps, 2.44 GHz)
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Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D042
图8-35. Output Power vs.
Temperature (BLE 1 Mbps, 2.44 GHz, +5 dBm)
Output Power vs. VDDS
50 kbps, 868.3 MHz, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
D044
图8-36. Output Power vs.
Supply Voltage (VDDS) (50 kbps, 868.3 MHz)
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Output Power vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D046
图8-37. Output Power vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Output power vs. VDDS
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D048
图8-38. Output Power vs.
Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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Output Power vs. Frequency
50 kbps, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
863
864
865
866
867
868
869
870
Frequency [MHz]
D052
图8-39. Output Power vs.
Frequency (50 kbps, 868 MHz)
Output Power vs. Frequency
50 kbps, +14 dBm
14
13.9
13.8
13.7
13.6
13.5
13.4
13.3
13.2
13.1
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz]
D053
图8-40. Output Power vs.
Frequency (50 kbps, 915 MHz)
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Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
D058
图8-41. Output Power vs.
Frequency (BLE 1 Mbps, 2.44 GHz)
Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
D059
图8-42. Output Power vs.
Frequency (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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8.26.6 ADC Performance
ENOB vs. Input Frequency
11.4
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
11.1
10.8
10.5
10.2
9.9
9.6
0.2 0.3
0.5 0.7
1
2
3
4
5
6 7 8 10
20
30 40 50 70 100
Frequency [kHz]
D061
图8-43. ENOB vs.
Input Frequency
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference,
Fin = Fs / 10
10.2
10.15
10.1
10.05
10
9.95
9.9
9.85
9.8
1
2
3
4
5
6 7 8 10
20
30 40 50 70 100
200
Frequency [kHz]
D062
图8-44. ENOB vs.
Sampling Frequency
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INL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
1.5
1
0.5
0
-0.5
-1
-1.5
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
D064
图8-45. INL vs.
ADC Code
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
2.5
2
1.5
1
0.5
0
-0.5
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
D065
图8-46. DNL vs.
ADC Code
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ADC Accuracy vs. Temperature
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D066
图8-47. ADC Accuracy vs.
Temperature
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D067
图8-48. ADC Accuracy vs.
Supply Voltage (VDDS)
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9 Detailed Description
9.1 Overview
节4 shows the core modules of the CC1352R device.
9.2 System CPU
The CC1352R SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU) for safety-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
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9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that
interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF core offers a high level, command-based API
to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power and leaves more resources for the user application. Several signals are also
available to control external circuitry such as RF switches or range extenders autonomously.
Dual-band and multiprotocol solutions are enabled through time-sliced access of the radio, handled
transparently for the application through the TI-provided RF driver and dual-mode manager.
A Packet Traffic Arbitrator (PTA) scheme is available for the managed coexistence of BLE and a co-located 2.4-
GHz radio. This is based on 802.15.2 recommendations and common industry standards. The 3-wire
coexistence interface has multiple modes of operation, encompassing different use cases and number of lines
used for signaling. The radio acting as a slave is able to request access to the 2.4-GHz ISM band, and the
master to grant it. Information about the request priority and TX or RX operation can also be conveyed.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) updates while still using the same silicon.
备注
Not all combinations of features, frequencies, data rates, and modulation formats described in this
chapter are supported. Over time, TI can enable new physical radio formats (PHYs) for the device and
provides performance numbers for selected PHYs in the data sheet. Supported radio formats for a
specific device, including optimized settings to use with the TI RF driver, are included in the SmartRF
Studio tool with performance numbers of selected formats found in the Specifications section.
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9.3.1 Proprietary Radio Formats
The CC1352R radio can support a wide range of physical radio formats through a set of hardware peripherals
combined with firmware available in the device ROM, covering various customer needs for optimizing towards
parameters such as speed or sensitivity. This allows great flexibility in tuning the radio both to work with legacy
protocols as well as customizing the behavior for specific application needs.
表 9-1 gives a simplified overview of features of the various radio formats available in ROM. Other radio formats
may be available in the form of radio firmware patches or programs through the Software Development Kit (SDK)
and may combine features in a different manner, as well as add other features.
表9-1. Feature Support
SimpleLink™ Long
Feature
Main 2-(G)FSK Mode
High Data Rates
Low Data Rates
Range
Programmable preamble, sync word, and
CRC
Yes
Yes
Yes
No
Programmable receive bandwidth
Data / Symbol rate(3)
Yes
Yes
Yes (down to 4 kHz)
Yes
20 to 1000 kbps
≤2 Msps
≤100 ksps
≤20 ksps
2-(G)FSK
4-(G)FSK
2-(G)FSK
4-(G)FSK
Modulation format
2-(G)FSK
2-(G)FSK
Dual Sync Word
Carrier Sense (1) (2)
Preamble Detection(2)
Data Whitening
Digital RSSI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
CRC filtering
1:2
1:4
1:8
Direct-sequence spread spectrum (DSSS)
No
No
No
Forward error correction (FEC)
Link Quality Indicator (LQI)
No
No
No
Yes
Yes
Yes
Yes
Yes
(1) Carrier Sense can be used to implement HW-controlled listen-before-talk (LBT) and Clear Channel Assessment (CCA) for compliance
with such requirements in regulatory standards. This is available through the CMD_PROP_CS radio API.
(2) Carrier Sense and Preamble Detection can be used to implement sniff modes where the radio is duty cycled to save power.
(3) Data rates are only indicative. Data rates outside this range may also be supported. For some specific combinations of settings, a
smaller range might be supported.
9.3.2 Bluetooth 5.2 Low Energy
The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-sped 2-Mbps physical layer and
the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or
through a high-level Bluetooth API. The Bluetooth 5.2 PHY and part of the controller are in radio and system
ROM, providing significant savings in memory usage and more space available for applications.
The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times
the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers
significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.
Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application needs,
which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2
Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not
previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster
responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates.
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9.3.3 802.15.4 (Thread, Zigbee, 6LoWPAN)
Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2
Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN protocols. The
802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free protocol stacks for Thread
and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution.
9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-
system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both
storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by
default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in
memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always
initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically
used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by
the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,
which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that
can be used for initial programming of the device.
9.5 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary
power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby
significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable
state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power
• 2 MHz low-power mode enables lowest possible handling of digital sensors
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C
driver source code, which the System CPU application uses to control and exchange data with the Sensor
Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
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• Very low-power pulse counting (flow metering)
• Key scan
The peripherals in the Sensor Controller include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital
converter, and a comparator. The continuous time comparator in this block can also be used as a higher-
accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline
tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive
sensing.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be
triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI master with up to 6 MHz clock speed
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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9.6 Cryptography
The CC1352R device comes with a wide set of modern cryptography-related hardware accelerators, drastically
reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower
power and improves availability and responsiveness of the system because the cryptography operations runs in
a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The
hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available
for an application or stack:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P224, NIST-P256, NIST-P384, NIST-P521
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
• secp256r1
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• SHA2 based MACs
– HMAC with SHA224, SHA256, SHA384, or SHA512
• Block cipher mode of operation
– AESCCM
– AESGCM
– AESECB
– AESCBC
– AESCBC-MAC
• True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as
Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of
the TI SimpleLink SDK for the CC1352R device.
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9.7 Timers
A large selection of timers are available as part of the CC1352R device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the
Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the
RTC halts when a debugger halts the device.
• General Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each
edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or
periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as
well as for PWM output or waveform generation.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
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9.8 Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous
serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI modules support
configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-
rate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in 节 7. All digital peripherals can be connected to any
digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference Manual.
9.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC1352R device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and
respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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9.12 Power Management
To minimize power consumption, the CC1352R supports a number of power modes and power management
features (see 表9-2).
表9-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
Active
On
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Off
Off
Off
Off
No
No
Off
Off
Off
Off
No
No
Flash
Available
On
Off
SRAM
On
Retention
Duty Cycled
Partial
Full
Supply System
Register and CPU retention
SRAM retention
On
On
Full
Full
Full
Full
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
Off
Off
Off
Off
2 MHz medium-speed clock
(SCLK_MF)
RCOSC_MF
RCOSC_MF
Available
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
On
Available
Available
Available
Available
On
Off
Available
Available
Available
On
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Sensor Controller
Wake-up on RTC
Off
Wake-up on pin edge
Wake-up on reset pin
Brownout detector (BOD)
Power-on reset (POR)
Watchdog timer (WDT)
Available
On
On
On
Duty Cycled
On
Off
On
On
Off
Available
Available
Paused
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see 表9-2).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the
I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin
defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller
independently of the system CPU. This means that the system CPU does not have to wake up, for example to
perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would
otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,
control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be
controlled by the system CPU.
备注
The power, RF and clock management for the CC1352R device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC1352R software development kit (SDK). Therefore, TI highly
recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in
source code.
9.13 Clock Systems
The CC1352R device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the
internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal or TCXO.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator
(RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for
ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after
Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768
kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost.
9.14 Network Processor
Depending on the product configuration, the CC1352R device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
For general design guidelines and hardware configuration guidelines, refer to the CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC1352R
device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
Integrated matched filter-balun devices can be used both at sub-1 GHz frequencies and at 2.4 GHz for the low-
power RF outputs. Refer to the "Integrated Passive Component" section in CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations for further information.
CC1352REM-XD7793-
XD24 Design Files
The CC1352REM-XD7793-XD24 reference design provides schematic, layout and
production files for the characterization board used for deriving the performance
number found in this document.
LAUNCHXL-CC1352R1
Design Files
The CC1352R LaunchPad Design Files contain detailed schematics and layouts to
build application specific boards using the CC1352R device.
LAUNCHXL-CC1352P-4
Design Files
Detailed schematics and layouts for the multi-band CC1352P LaunchPad
evaluation board featuring 2.4 GHz RF matching optimized for 10 dBm operation
on the 20 dBm PA output and up to 13 dBm TX power at 433 MHz.
Sub-1 GHz and 2.4 GHz
The antenna kit allows real-life testing to identify the optimal antenna for your
Antenna Kit for LaunchPad application. The antenna kit includes 16 antennas for frequencies from 169 MHz
™ Development Kit and
SensorTag
to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad
development kits and SensorTags.
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10.2 Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T = ψ × P + T
case
(1)
(2)
(3)
J
JT
2. From board temperature:
T = ψ × P + T
board
J
JB
3. From ambient temperature:
T = R
× P + T
A
J
θJA
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in Thermal Resistance Characteristics.
Example:
Using 方程式 3, the temperature difference between ambient temperature and junction temperature is
calculated. In this example, we assume a simple use case where the radio is transmitting continuously at
10 dBm output power. Let us assume the ambient temperature is 85 °C and the supply voltage is 3.6 V. To
calculate P, we need to look up the current consumption for Tx at 85 °C in 节8.26. From the plot, we see that the
current consumption is 14.4 mA. This means that P is 14.4 mA × 3.6 V = 51.8 mW.
The junction temperature is then calculated as:
°C
T = 23.4
× 51.8mW + T = 1.2°C + T
A
(4)
W
J
A
As can be seen from the example, the junction temperature is 1.2 °C higher than the ambient temperature when
running continuous Tx at 85 °C and, thus, well within the recommended operating conditions.
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the peak
power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current
consumption.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Tools and Software
The CC1352R device is supported by a variety of software and hardware development tools.
Development Kit
CC1352R
LaunchPad™
Development Kit
The CC1352R LaunchPad™ Development Kit enables development of high-performance
wireless applications in the 863 - 930 MHz and 2.4 GHz frequency bands that benefit from
low-power operation. The kit features the CC1352R multi-band and multiprotocol
SimpleLink Wireless MCU. The kit works with the LaunchPad ecosystem, easily enabling
additional functionality like sensors, display, and more. The built-in EnergyTrace™ software
is an energy-based code analysis tool that measures and displays the application’s
energy profile and helps to optimize it for ultra-low power consumption.
Software
SimpleLink™
CC13x2-
CC26x2 SDK
The SimpleLink CC13x2-CC26x2 Software Development Kit (SDK) provides a complete
package for the development of wireless applications on the CC13x2 / CC26x2 family of
devices. The SDK includes a comprehensive software package for the CC1352R device,
including the following protocol stacks:
• Bluetooth Low Energy 4 and 5.2
• Thread (based on OpenThread)
• Zigbee 3.0
• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and
2.4 GHz
• EasyLink - a large set of building blocks for building proprietary RF software stacks
• Multiprotocol support - concurrent operation between stacks using the Dynamic
Multiprotocol Manager (DMM)
The SimpleLink CC13x2-CC26x2 SDK is part of TI’s SimpleLink MCU platform, offering a
single development environment that delivers flexible hardware, software and tool options for
customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit https://www.ti.com/simplelink.
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Development Tools
Code Composer
Studio™
Integrated
Development
Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available for
TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer
Studio™ Cloud
IDE
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
build CCS and Energia™ projects. After you have successfully built your project, you can
download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded
Workbench® for
Arm®
IAR Embedded Workbench® is a set of development tools for building and debugging
embedded system applications using assembler, C and C++. It provides a completely
integrated development environment that includes a project manager, editor, and build tools.
IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on
most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of
RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing and
debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device.
Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
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Sensor Controller
Studio
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller
peripheral. The tool generates a Sensor Controller Interface driver, which is a set of C
source files that are compiled into the System CPU application. These source files also
contain the Sensor Controller binary image and allow the System CPU application to control
and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
• Ready-to-use examples for several common use cases
• Full toolchain with built-in compiler and assembler for programming in a C-like
programming language
• Provides rapid development by using the integrated sensor controller task testing and
debugging functionality, including visualization of sensor data and verification of
algorithms
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.
UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free
of charge.
11.1.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired
and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible
hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
11.2 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC1352R. In the upper right corner, click on Alert me to register
and receive a weekly digest of any product information that has changed. For change details, review the revision
history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer
TI Resource Explorer
Software examples, libraries, executables, and documentation are available for your
device and development board.
Errata
CC1352R Silicon
Errata
The silicon errata describes the known exceptions to the functional specifications for
each silicon revision of the device and description on how to recognize a device
revision.
Application Reports
All application reports for the CC1352R device are found on the device product folder at: ti.com/product/
CC1352R/technicaldocuments.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLink™ Wireless
MCU TRM
The TRM provides a detailed description of all modules and
peripherals available in the device family.
Copyright © 2023 Texas Instruments Incorporated
84
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Product Folder Links: CC1352R
CC1352R
www.ti.com.cn
ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
SimpleLink™, SmartRF™, LaunchPad™, EnergyTrace™, Code Composer Studio™, and TI E2E™ are trademarks
of Texas Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH.
Arm®, Cortex®, and Arm Thumb® are registered trademarks of Arm Limited (or its subsidiaries).
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium.
Bluetooth® is a registered trademark of Bluetooth SIG Inc.
Zigbee® is a registered trademark of Zigbee Alliance Inc.
MIOTY® and Wi-SUN® are registered trademarks of Wi-SUN Alliance Inc.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Eclipse® is a registered trademark of Eclipse Foundation.
IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Windows® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: CC1352R
CC1352R
www.ti.com.cn
ZHCSHB9I –JANUARY 2018 –REVISED FEBRUARY 2021
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
86
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Product Folder Links: CC1352R
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC1352R1F3RGZR
CC1352R1F3RGZT
ACTIVE
VQFN
VQFN
RGZ
48
48
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 105
-40 to 105
CC1352
R1F3
Samples
Samples
ACTIVE
RGZ
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
CC1352
R1F3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC1352R1F3RGZR
CC1352R1F3RGZT
CC1352R1F3RGZT
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
48
48
48
2500
250
330.0
180.0
180.0
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
1.1
1.1
1.1
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC1352R1F3RGZR
CC1352R1F3RGZT
CC1352R1F3RGZT
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
48
48
48
2500
250
367.0
210.0
210.0
367.0
185.0
185.0
35.0
35.0
35.0
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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