CC2340R52E0RKPR_技术文档

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

CC2340R5 SimpleLink™ 低功耗Bluetooth ^®5.3 无线MCU

• 3×16 位和1×24 位通用计时器，支持正交解码模式

• 12 位ADC，使用外部基准时1.2MSPS，使用内部

基准时267ksps、高达12 个外部ADC 输入

• 1× 低功耗比较器

• 1 个异步收发器(UART)

• 1× SPI

• 1× I²C

1 特性

无线微控制器

• 经过优化的48MHz Arm^®Cortex^®-M0+ 处理器

• 512 KB 系统内可编程闪存

• 12KB ROM 用于引导加载程序和驱动程序

• 36 KB 超低泄漏SRAM。待机模式下完全RAM 保

持

• 与低功耗Bluetooth^®5.3 兼容的2.4GHz 射频收发

器

• 集成平衡-非平衡变压器

• 实时时钟(RTC)

• 集成温度和电池监控器

• 看门狗计时器

安全驱动工具

• 支持无线升级(OTA)

• 串行线调试(SWD)

• AES 128 位加密加速计

• 来自片上模拟噪声的随机数生成器

低功耗

开发工具和软件

• MCU 功耗：

• LP-EM-CC2340R5 LaunchPad 开发套件

• SimpleLink™ CC23xx 软件开发套件(SDK)

• 用于简单无线电配置的SmartRF™ Studio

• SysConfig 系统配置工具

– 2.6 mA 有源模式，CoreMark^®

– 53μA/MHz（运行CoreMark^®时）

– < 710nA 待机模式，RTC，36KB RAM

– 150nA 关断模式，引脚唤醒

• 无线电功耗：

工作温度范围

– RX：5.3 mA

– TX：5.1 mA（在0dBm 条件下）

– TX：< 11.0mA（在+8dBm 条件下）

• 片上降压直流/直流转换器

• 1.71V 至3.8V 单电源电压

• T_j：-40 至+125°C

无线协议支持

符合RoHS 标准的封装

• 低功耗Bluetooth® 5.3

• ZigBee® ¹

• SimpleLink™ TI 15.4-stack ¹

• 专有系统

• 5mm × 5mm RKP QFN40 (26 个GPIO)

• 4mm × 4mm RGE QFN24（12 个GPIO）²

高性能无线电

• -102dBm（在125kbps 低功耗Bluetooth® 下）

• -96.5dBm（在1Mbps 低功耗Bluetooth® 下）

• 高达+8dBm 的输出功率，具有温度补偿

法规遵从性

• 适用于符合以下标准的系统：

– EN 300 328（欧洲）

– FCC CFR47 第15 部分

– ARIB STD-T66（日本）

MCU 外设

• 多达26 个I/O 板

– 2 个IO 焊盘SWD，与GPIO 进行多路复用

– 2 个IO 焊盘LFXT，与GPIO 进行多路复用

– 多达22 个DIO（模拟或数字IO）

1

在未来的SDK 中提供

RGE (4.00mm x 4.00mm) 封装信息只是预发布版，可能会更改。

2

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

www.ti.com.cn

• 照明

– LED 灯具

– 照明控制–日光传感器、照明传感器、无线控

2 应用

• 医疗

– 居家医疗保健–血糖监测仪、血压监测仪、

CPAP 呼吸机、电子温度计

– 患者监护和诊断–医疗传感器贴片

– 个人护理和健身–电动牙刷、可穿戴健身和活

动监测仪

制

• 工厂自动化和控制

• 零售自动化和支付–电子销售终端

– 电子货架标签

• 通信设备

• 楼宇自动化

– 有线网络–无线LAN 或Wi-Fi 接入点、边缘路

由器

• 个人电子产品

– 楼宇安防系统–运动检测器、电子智能锁、门

窗传感器、车库门系统、网关

– HVAC –恒温器、无线环境传感器

– 防火安全系统–烟雾和热量探测器

– 视频监控–IP 网络摄像头

– 联网外设–消费类无线模块、指点设备、键盘

– 游戏–电子玩具和机器人玩具

– 可穿戴设备（非医用）–智能追踪器、智能服

装

3 说明

SimpleLink^™CC2340R5 器件是面向低功耗 Bluetooth® 5.3 和专有 2.4GHz 应用的 2.4GHz 无线微控制器

(MCU)。该器件针对低功耗无线通信进行了优化，并支持片上双映像无线下载 (OAD) 功能，¹适用于楼宇自动化

（无线传感器、照明控制、信标）、资产跟踪、医疗、零售 EPOS（电子销售终端）、ESL（电子货架标签）和

个人电子产品（玩具、HID、触控笔）市场。的突出特性包括：

• 支持Bluetooth ^®5 特性：高速模式(2Mbps PHY)、远距离（LE 编码125kbps 和500kbps PHY）、Privacy

1.2.1 和通道选择算法2，以及对Bluetooth ^®4.2 和早期低功耗规范的向后兼容性和支持。

• 完全合格的Bluetooth ^®5.3 软件协议栈（SimpleLink™ CC23xx 软件开发套件(SDK) 随附）。

• SimpleLink™ CC23xx 软件开发套件(SDK) ³

• 超低待机电流不到0.71μA 并具有RTC 操作和完全RAM 保持，可显著延长电池寿命，尤其是对于睡眠间隔

较长的应用。

• 集成平衡-非平衡变压器，可减少物料清单(BOM) 电路板布局布线

• 出色的无线电敏感度和稳健性（选择性与阻断）性能，适用于低功耗Bluetooth ^®（125kbps LE 编码PHY 且

集成平衡-非平衡变压器时为-102dBm）。

CC2340R5 器件是 SimpleLink™ MCU 平台的一部分，该平台包括 Wi-Fi^®、低功耗蓝牙、Thread、Zigbee、

Sub-1GHz MCU 和主机 MCU，它们共用一个通用、易于使用的开发环境，其中包含单核软件开发套件 (SDK) 和

丰富的工具集。借助一次性集成的 SimpleLink™ 平台，可以将产品组合中的任何器件组合添加至您的设计中，从

而在设计要求变更时实现100% 的代码重用。如需更多信息，请访问SimpleLink™ MCU 平台。

3

中的ZigBee® 协议栈支持将在未来的SDK 中提供

English Data Sheet: SWRS272

2

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CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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器件信息

封装

QFN24⁽²⁾

器件型号⁽¹⁾

封装尺寸（标称值）

4.00mm × 4.00mm

5.00mm × 5.00mm

CC2340R52E0RGER

CC2340R52E0RKPR

QFN40

(1) 如需所有可用器件的最新器件、封装和订购信息，请参阅节12 中的“封装选项附录”或访问TI 网站。

(2) RGE (4.00mm x 4.00mm) 封装信息只是预发布版，可能会发生变化。

4 功能方框图

48 MHz

HFXT

48 MHz

HFOSC

DC/DC

POR

BOD

Arm Cortex M0+ Processor

48 MHz

32.768 kHz

LFXT

32.768 kHz

LFOSC

Global LDO

2.4GHz Radio Transceiver

Radio Digital

B

A

L

2.4 GHz

50 Ω

RF RAM

U

N

ADC

Modem Accelerators

SWD

µDMA (8 channel)

System Buses

Timers

LGPT0-LGPT3

12-bit ADC

1.2 Msps

RTC

1x UART

1x SPI

512kB Flash

36kB SRAM

SYSTIM

System Timer

Low Power

Comparator

WDT

Temperature

Sensor

12kB System ROM

1x I2C

Battery

Monitor

AES-128

IOMUX | up to 26 GPIOs

图4-1. CC2340R5 方框图

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Product Folder Links: CC2340R5

English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

8.15 Bluetooth Low Energy - Transmit (TX)....................29

8.16 Proprietary Radio Modes........................................ 30

8.17 2.4 GHz RX/TX CW................................................ 31

8.18 Timing and Switching Characteristics..................... 31

8.19 Peripheral Characteristics.......................................33

9 Detailed Description......................................................42

9.1 Overview...................................................................42

9.2 System CPU............................................................. 42

9.3 Radio (RF Core)........................................................43

9.4 Memory.....................................................................43

9.5 Cryptography............................................................ 44

9.6 Timers....................................................................... 44

9.7 Serial Peripherals and I/O.........................................45

9.8 Battery and Temperature Monitor............................. 46

9.9 µDMA........................................................................46

9.10 Debug..................................................................... 46

9.11 Power Management................................................47

9.12 Clock Systems........................................................ 48

9.13 Network Processor..................................................48

10 Application, Implementation, and Layout................. 49

10.1 Reference Designs................................................. 49

10.2 Junction Temperature Calculation...........................50

11 Device and Documentation Support..........................51

11.1 Device Nomenclature..............................................51

11.2 Tools and Software..................................................51

11.3 Documentation Support.......................................... 54

11.4 支持资源..................................................................54

11.5 Trademarks............................................................. 54

11.6 静电放电警告...........................................................55

11.7 术语表..................................................................... 55

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................3

5 Revision History.............................................................. 4

6 Device Comparison.........................................................5

7 Pin Configuration and Functions...................................6

7.1 Pin Diagram –RKP Package (Top View).................. 6

7.2 Signal Descriptions –RKP Package......................... 7

7.3 Connections for Unused Pins and Modules –

RKP Package................................................................8

7.4 Pin Diagram –RGE Package (Preview)(Top

View)............................................................................. 9

7.5 Signal Descriptions –RGE Package (Preview).........9

7.6 Connections for Unused Pins and Modules –

RGE Package (Preview)............................................. 10

7.7 RKP and RGE Peripheral Pin Mapping.....................11

7.8 RKP and RGE Peripheral Signal Descriptions..........16

8 Specifications................................................................ 21

8.1 Absolute Maximum Ratings...................................... 21

8.2 ESD Ratings............................................................. 21

8.3 Recommended Operating Conditions.......................21

8.4 DCDC........................................................................21

8.5 Global LDO (GLDO)..................................................22

8.6 Power Supply and Modules...................................... 22

8.7 Battery Monitor..........................................................22

8.8 Temperature Sensor................................................. 22

8.9 Power Consumption - Power Modes........................ 23

8.10 Power Consumption - Radio Modes....................... 24

8.11 Nonvolatile (Flash) Memory Characteristics........... 24

8.12 Thermal Resistance Characteristics....................... 24

8.13 RF Frequency Bands..............................................25

8.14 Bluetooth Low Energy - Receive (RX).................... 26

Information.................................................................... 56

5 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

April 2023

*

Initial Release

4

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English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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6 Device Comparison

RADIO SUPPORT

PACKAGE SIZE

FLASH

(KB)

RAM +

GPIO

Device

Cache (KB)

CC1310

CC1311R3

CC1311P3

CC1312R

CC1312R7

CC1352R

CC1352P

CC1352P7

X

32-128

352

704

352

704

512

16-20 + 8 10-30

X

32 + 8

80 + 8

144 + 8

80 + 8

144 + 8

36

22-30

26

X

30

X

30

X

28

X

26

X

CC2340R5^{(1) (2)}

12-26

,

X

CC2640R2F

CC2642R

X

128

352

704

352

704

352

20 + 8

80 + 8

32 + 8

80 + 8

144 + 8

80 + 8

144 + 8

80 + 8

10-31

31

X

CC2642R-Q1

CC2651R3

CC2651P3

CC2652R

31

X

23-31

22-26

31

X

CC2652RB

CC2652R7

CC2652P

31

X

26

CC2652P7

CC2662R-Q1

26

31

(1) ZigBee and Thread support enabled by future software update

(2) Information for the RGE (4.00 mm x 4.00 mm) package is preview only and subject to change.

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English Data Sheet: SWRS272

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ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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7 Pin Configuration and Functions

7.1 Pin Diagram –RKP Package (Top View)

VDDR

DIO8

1

2

3

4

5

6

7

8

9

30 DCDC

29 DIO5_A2

28 VDDD

DIO9

DIO10

DIO11

DIO12

DIO13

VDDS

DIO14

27 DIO4_X32N

26 DIO3_X32P

25 RSTN

24 DIO2_A3

23 DIO1_A4

22 DIO0_A5

21 DIO25_A6

DIO15 10

图7-1. RKP (5-mm × 5-mm) Pinout, 0.4-mm Pitch (Top View)

The following I/O pins marked in 图7-1 in bold have high-drive capabilities:

• Pin 6, DIO12

• Pin 11, DIO16_SWDIO

• Pin 12, DIO17_SWDCK

• Pin 13, DIO18

• Pin 14, DIO19

• Pin 20, DIO24_A7

The following I/O pins marked in 图7-1 in italics have analog capabilities:

• Pin 15, DIO20_A11

• Pin 16, DIO21_A10

• Pin 18, DIO22_A9

• Pin 19, DIO23_A8

• Pin 20, DIO24_A7

• Pin 21, DIO25_A6

• Pin 22, DIO0_A5

• Pin 23, DIO1_A4

• Pin 24, DIO2_A3

• Pin 29, DIO5_A2

• Pin 32, DIO6, A1

• Pin 33, DIO7_A0

English Data Sheet: SWRS272

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7.2 Signal Descriptions –RKP Package

表7-1. Signal Descriptions –RKP Package

I/O

TYPE

DESCRIPTION

NAME

NO.

Ground –exposed ground pad⁽¹⁾

EGP

GND

—

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO^{(2) (3) (4)}

VDDR

1

Power

DIO8

2

I/O

Digital

GPIO

DIO9

3

GPIO

DIO10

DIO11

DIO12

DIO13

VDDS

DIO14

DIO15

4

Digital

GPIO

5

Digital

GPIO

6

Digital

GPIO, high-drive capability

GPIO

7

Digital

8

Power

1.71-V to 3.8-V DIO supply⁽⁵⁾

—

9

I/O

Digital

GPIO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Digital

GPIO

DIO16_SWDIO

DIO17_SWDCK

DIO18

Digital

GPIO, SWD interface: mode select or SWDIO, high-drive capability

GPIO, SWD interface: clock, high-drive capability

GPIO, high-drive capability

GPIO, analog capability

1.71-V to 3.8-V DIO supply⁽⁵⁾

GPIO, analog capability

GPIO, Analog capability, high-drive capability

GPIO, analog capability

Reset, active low. No internal pullup resistor

GPIO, 32-kHz crystal oscillator pin 1, Optional TCXO input

GPIO, 32-kHz crystal oscillator pin 2

Digital

DIO19

Digital

DIO20_A11

DIO21_A10

VDDS

Digital or Analog

Power

—

I/O

I

DIO22_A9

DIO23_A8

DIO24_A7

DIO25_A6

DIO0_A5

Digital or Analog

Digital

DIO1_A4

DIO2_A3

RSTN

DIO3_X32P

DIO4_X32N

I/O

Digital or Analog

For decoupling of internal 1.28-V regulated core-supply. Connect

an external 1 μF decoupling capacitor.⁽²⁾

VDDD

28

Power

—

DIO5_A2

DCDC

29

30

31

32

33

I/O

Digital or Analog

Power

GPIO, analog capability

Switching node of internal DC/DC converter⁽⁵⁾

1.71-V to 3.8-V analog supply⁽⁵⁾

GPIO, analog capability

—

VDDS

Power

DIO6_A1

DIO7_A0

I/O

Digital or Analog

GPIO, analog capability

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO. Connect an external 10 μF

decoupling capacitor.^{(2) (3) (4)}

VDDR

34

Power

—

X48P

X48N

NC

35

36

37

38

Analog

48-MHz crystal oscillator pin 1

48-MHz crystal oscillator pin 2

No Connect

—

VDDS

Power

1.71-V to 3.8-V analog supply⁽⁵⁾

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Product Folder Links: CC2340R5

English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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表7-1. Signal Descriptions –RKP Package (continued)

I/O

TYPE

DESCRIPTION

NAME

ANT

NO.

39

I/O

RF

2.4 GHz TX, RX

RF Ground

RFGND

40

RFGND

—

(1) EPG is the only non-RF ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB)

is imperative for proper device operation.

(2) Do not supply external circuitry from this pin.

(3) VDDR pins 1 and 34 must be tied together on the PCB.

(4) Output from internal DC/DC and LDO is trimmed to 1.5 V.

(5) For more details, see the technical reference manual listed in 节11.3.

7.3 Connections for Unused Pins and Modules –RKP Package

表7-2. Connections for Unused Pins –RKP Package

PREFERRED

FUNCTION

SIGNAL NAME

PIN NUMBER

ACCEPTABLE PRACTICE⁽¹⁾

PRACTICE⁽¹⁾

2–7

9–10

13–14

GPIO (digital)

DIOn

NC, GND, or VDDS

NC

DIO16_SWDIO

DIO17_SWDCK

11

12

NC, GND, or VDDS

GND or VDDS

SWD

15–16

18–24

29

GPIO (digital or analog)

32.768-kHz crystal

DIOn_Am

NC, GND, or VDDS

NC or GND

NC

32–33

DIO3_X32P

DIO4_X32N

DCDC

26

27

30

NC

DC/DC converter⁽²⁾

VDDS

8, 17, 31, 38

VDDS

(1) NC = No connect

(2) When the DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected and

the 10 μF DCDC capacitor must be kept on the VDDR net.

English Data Sheet: SWRS272

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7.4 Pin Diagram –RGE Package (Preview)(Top View)

ANT

VDDR

DIO8

1

2

3

4

5

6

18 VDDS

17 DCDC

16 VDDD

DIO11

DIO12

DIO13

15 DIO4_X32N

14 DIO3_X32P

13 RSTN

图7-2. RGE (4-mm × 4-mm) Pinout, 0.4-mm Pitch (Preview)(Top View)

The following I/O pins marked in 图7-2 in bold have high-drive capabilities:

• Pin 5, DIO12

• Pin 7, DIO16_SWDIO

• Pin 8, DIO17_SWDCK

• Pin 12, DIO24_A7

The following I/O pins marked in 图7-2 in italics have analog capabilities:

• Pin 9, DIO20_A11

• Pin 10, DIO21_A10

• Pin 12, DIO24_A7

• Pin 19, DIO6_A1

7.5 Signal Descriptions –RGE Package (Preview)

表7-3. Signal Descriptions –RGE Package

I/O

TYPE

DESCRIPTION

NAME

EGP

NO.

Ground –exposed ground pad⁽¹⁾

GND

RF

—

ANT

1

I/O

2.4 GHz TX, RX

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO^{(2) (3) (4)}

VDDR

2

Power

—

DIO8

3

4

I/O

Digital

GPIO

DIO11

GPIO

DIO12

5

Digital

GPIO, high-drive capability

DIO13

6

Digital

GPIO

DIO16_SWDIO

DIO17_SWDCK

DIO20_A11

DIO21_A10

7

Digital

GPIO, SWD interface: mode select or SWDIO, high-drive capability

GPIO, SWD interface: clock, high-drive capability

GPIO, analog capability

8

Digital

9

Digital or Analog

10

GPIO, analog capability

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Product Folder Links: CC2340R5

English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

www.ti.com.cn

表7-3. Signal Descriptions –RGE Package (continued)

I/O

TYPE

DESCRIPTION

1.71-V to 3.8-V DIO supply⁽⁵⁾

NAME

NO.

11

VDDS

Power

—

I/O

I

DIO24_A7

RSTN

12

13

14

15

Digital or Analog

Digital

GPIO, Analog capability, high-drive capability

Reset, active low. No internal pullup resistor

DIO3_X32P

DIO4_X32N

I/O

Digital or Analog

GPIO, 32-kHz crystal oscillator pin 1, Optional TCXO input

GPIO, 32-kHz crystal oscillator pin 2

For decoupling of internal 1.28-V regulated core-supply. Connect

an external 1 μF decoupling capacitor.⁽²⁾

VDDD

16

Power

—

DCDC

17

18

19

Power

Switching node of internal DC/DC converter⁽⁵⁾

1.71-V to 3.8-V analog supply⁽⁵⁾

GPIO, analog capability

—

VDDS

DIO6_A1

I/O

Digital or Analog

Internal supply, must be powered from the internal DC/DC

converter or the internal LDO. Connect an external 10 μF

decoupling capacitor.^{(2) (3) (4)}

VDDR

20

Power

—

X48P

X48N

GND

21

22

23

24

Analog

GND

48-MHz crystal oscillator pin 1

48-MHz crystal oscillator pin 2

Ground

—

VDDS

Power

1.71-V to 3.8-V analog supply⁽⁵⁾

(1) EPG is the main ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is

imperative for proper device operation.

(2) Do not supply external circuitry from this pin.

(3) VDDR pins 2 and 20 must be tied together on the PCB.

(4) Output from internal DC/DC and LDO is trimmed to 1.5 V.

(5) For more details, see technical reference manual listed in 节11.3.

7.6 Connections for Unused Pins and Modules –RGE Package (Preview)

表7-4. Connections for Unused Pins –RGE Package

PREFERRED

FUNCTION

SIGNAL NAME

PIN NUMBER

ACCEPTABLE PRACTICE⁽¹⁾

PRACTICE⁽¹⁾

GPIO (digital)

DIOn

NC, GND, or VDDS

NC

3–6

DIO16_SWDIO

DIO17_SWDCK

7

8

GND or VDDS

SWD

9–10

12

19

GPIO (digital or analog)

32.768-kHz crystal

DIOn_Am

NC, GND, or VDDS

NC or GND

NC

DIO3_X32P

DIO4_X32N

DCDC

14

15

17

NC

DC/DC converter⁽²⁾

VDDS

11, 18, 24

VDDS

(1) NC = No connect

(2) Whenthe DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected and

the 10 μF DCDC capacitor must be kept on the VDDR net.

English Data Sheet: SWRS272

10

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7.7 RKP and RGE Peripheral Pin Mapping

表7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping

PIN NO.

PIN NAME

SIGNAL NAME

SIGNAL TYPE⁽¹⁾PIN MUX ENCODING

SIGNAL DIRECTION

QFN24

QFN40

2

1

VDDR

GPIO8

N/A

0

1

2

3

4

5

7

0

1

3

0

1

2

3

0

1

2

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

5

7

N/A

0

1

2

3

4

N/A

I/O

O

—

SPI0SCLK

UART0RTS

T1C0N

I2C0SDA

T0C0N

DTB3

3

2

DIO8

I/O

O

I/O

O

GPIO9

I/O

O

3

4

DIO9

T3C0

I/O

—

LRFD3

GPIO10

LPCO

O

I/O

O

DIO10

T2PE

O

T3C0N

GPIO11

SPI0CSN

T1C2N

T0C0

O

I/O

O

4

5

6

5

6

7

DIO11

DIO12

DIO13

I/O

O

LRFD0

SPI0POCI

DTB9

O

I/O

O

GPIO12

SPI0POCI

SPI0PICO

UART0RXD

T1C1

I/O

I

O

I2C0SDA

DTB13

I/O

O

GPIO13

SPI0POCI

SPI0PICO

UART0TXD

T0C0N

T1F

I/O

O

DTB4

O

8

9

VDDS

DIO14

VDDS

N/A

I/O

O

—

GPIO14

T3C2

T1C2N

LRFD5

T1F

I/O

O

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表7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)

PIN NO.

PIN NAME

SIGNAL NAME

SIGNAL TYPE⁽¹⁾PIN MUX ENCODING

SIGNAL DIRECTION

QFN24

QFN40

GPIO15

UART0RXD

T2C0N

0

I/O

I

1

10

11

DIO15

I/O

—

2

O

CKMIN

3

0

1

2

I

GPIO16

SPI0PICO

UART0RXD

I2C0SDA

T1C2

I/O

I

DIO16_SWD

IO

7

I/O

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

7

0

1

2

4

7

0

1

2

3

4

5

6

7

I/O

O

T1C0N

O

DTB10

O

GPIO17

SPI0SCLK

UART0TXD

I2C0SCL

T1C1N

I/O

O

DIO17_SWD

CK

8

12

I/O

O

T0C2

O

DTB11

O

GPIO18

T3C0

I/O

O

LPCO

O

13

14

DIO18

DIO19

I/O

—

UART0TXD

SPI0SCLK

DTB12

O

I/O

O

GPIO19

T3C1

I/O

O

T2PE

O

—

SPI0PICO

DTB8

I/O

O

GPIO20

LPCO

I/O

O

UART0TXD

UART0RXD

T1C0

O

I

9

15

DIO20_A11

I/O

O

SPI0POCI

ADC11

I/O

I

DTB14

O

English Data Sheet: SWRS272

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表7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)

PIN NO.

PIN NAME

SIGNAL NAME

SIGNAL TYPE⁽¹⁾PIN MUX ENCODING

SIGNAL DIRECTION

QFN24

QFN40

GPIO21

UART0CTS

T1C1N

0

1

2

I/O

I

O

T0C1

3

O

10

16

DIO21_A10

I/O

SPI0POCI

LRFD1

4

I/O

O

5

6

7

ADC10/LPC+

DTB15

I

O

11

17

18

VDDS

N/A

0

1

2

3

6

7

0

1

3

6

0

1

2

3

4

5

6

7

0

1

2

3

6

0

1

2

3

6

0

1

2

3

4

5

6

N/A

I/O

O

—

GPIO22

T2C0

UART0RXD

T3C1N

I

DIO22_A9

I/O

—

O

ADC9

I

DTB1

O

GPIO23

T2C1

I/O

O

19

DIO23_A8

I/O

—

T3C2N

O

ADC8/LPC+/LPC-

GPIO24

SPI0SCLK

T1C0

I

I/O

O

T3C0

O

12

20

DIO24_A7

I/O

T0PE

O

I2C0SCL

ADC7/LPC+/LPC-

DTB5

I/O

I

O

GPIO25

SPI0POCI

I2C0SCL

T2C2N

I/O

O

21

22

DIO25_A6

DIO0_A5

I/O

—

ADC6

I

GPIO0

I/O

O

SPI0CSN

I2C0SDA

T3C2

ADC5

I

GPIO1

I/O

O

T3C1

LRFD7

O

23

DIO1_A4

T1F

I/O

O

—

UART0RTS

ADC4

O

I

DTB2

O

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表7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)

PIN NO.

PIN NAME

SIGNAL NAME

SIGNAL TYPE⁽¹⁾PIN MUX ENCODING

SIGNAL DIRECTION

QFN24

QFN40

GPIO2

T0PE

0

1

I/O

O

24

25

DIO2_A3

RTSN

T2C1N

UART0CTS

ADC3

I/O

2

3

O

—

I

6

I

13

RSTN

N/A

0

N/A

I/O

I

—

GPIO3

LFCI

1

T0C1N

LRFD0

T3C1

2

O

3

O

14

26

DIO3_X32P

I/O

4

O

T1C2

5

O

LFXT_P

DTB7

6

I

7

O

GPIO4

T0C2N

UART0TXD

LRFD1

SPI0PICO

T0C2

0

I/O

O

1

2

O

3

O

15

27

DIO4_X32N

4

I/O

O

5

LFXT_N

DTB8

6

I

7

O

16

28

29

VDDD

N/A

0

N/A

I/O

O

—

GPIO5

T2C2

1

DIO5_A2

I/O

—

LRFD6

ADC2

3

O

6

I

17

18

30

31

DCDC

VDDS

DCDC

N/A

0

N/A

I/O

O

—

VDDS

GPIO6

SPI0CSN

I2C0SCL

T1C2

1

2

3

19

32

DIO6_A1

I/O

LRFD2

UART0TXD

ADC1/AREF+

DTB6

4

O

5

O

6

I

7

O

GPIO7

T3C1

0

I/O

O

1

33

DIO7_A0

I/O

—

LRFD4

ADC0/AREF-

VDDR

3

O

6

I

20

21

22

34

35

36

VDDR

X48P

X48N

N/A

—

X48P

X48N

English Data Sheet: SWRS272

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表7-5. RKP (QFN40) and RGE (QFN24) Peripheral Pin Mapping (continued)

PIN NO.

PIN NAME

SIGNAL NAME

SIGNAL TYPE⁽¹⁾PIN MUX ENCODING

SIGNAL DIRECTION

QFN24

QFN40

37

NC

VDDS

ANT

NC

VDDS

ANT

N/A

—

24

1

—

38

39

40

RFGND

—

GND_TAB

(1) Signal Types: I = Input, O = Output, I/O = Input or Output.

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7.8 RKP and RGE Peripheral Signal Descriptions

表7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions

Pin No.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

QFN24 QFN40

ADC11

9

15

16

18

19

20

21

22

23

24

29

32

33

32

33

26

27

35

36

10

HP ADC channel 11 input

ADC10

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

AREF+

AREF-

X32P

10

HP ADC channel 10 input

HP ADC channel 9 input

HP ADC channel 8 input

HP ADC channel 7 input

ADC channel 6 input

—

12

—

19

ADC

I/O

I

ADC channel 5 input

ADC channel 4 input

ADC channel 3 input

ADC channel 2 input

HP ADC channel 1 input

HP ADC channel 0 input

—

19

ADC external voltage reference, positive terminal

ADC external voltage reference, negative terminal

32-kHz crystal oscillator pin 1, Optional TCXO input

32-kHz crystal oscillator pin 2

ADC Reference

I/O

I

—

14

15

21

22

I/O

I

X32N

X48P

48-MHz crystal oscillator pin 1

—

Clock

X48N

CKMIN

48-MHz crystal oscillator pin 2

I/O

TDC or HFOSC tracking loop reference clock input

—

Low frequency clock input (LFXT bypass clock from

pin)

LFCI

14

26

I/O

I

4

—

9

Comparator

LPCO

13

15

16

19

20

19

20

I/O

O

Low power comparator output

10

LPC+

LPC-

Low power comparator positive input terminal

Lower power comparator negative input terminal

—

Comparator

Input

12

I/O

I

—

12

English Data Sheet: SWRS272

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FUNCTION

表7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)

Pin No.

SIGNAL

SIGNAL NAME

DESCRIPTION

TYPE

DIRECTION

QFN24 QFN40

DTB3

3

4

2

Digital test bus output 3

DTB9

5

Digital test bus output 9

Digital test bus output 0

Digital test bus output 4

Digital test bus output 10

Digital test bus output 11

Digital test bus output 12

Digital test bus output 13

Digital test bus output 1

Digital test bus output 2

Digital test bus output 14

Digital test bus output 5

Digitial test bus output 15

Digital test bus output 7

Digital test bus output 8

Digital test bus output 6

DTB0

14

7

—

6

DTB4

DTB10

DTB11

DTB12

DTB13

DTB1

7

11

12

13

6

8

—

5

Digital Test Bus

I/O

O

18

23

15

20

16

26

27

32

2

—

9

DTB2

DTB14

DTB5

12

10

14

15

19

3

DTB15

DTB7

DTB8

DTB6

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

3

—

4

5

6

7

9

—

7

10

11

12

13

14

15

16

18

19

20

21

22

23

24

26

27

29

32

33

8

—

9

GPIO

I/O

General-purpose input or output

10

—

12

—

14

15

—

19

—

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表7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)

Pin No.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

QFN24 QFN40

8

12

20

21

32

2

12

I2C0SCL

I/O

I²C clock data

—

19

3

I²C

5

6

I2C0SDA

I²C data

7

11

22

3

—

4

LRFD3

LRFD0

LRFD5

LRFD1

LRF digital ouptut 3

LRF digital output 0

LRF digital output 5

LRF digital output 1

5

14

26

9

—

10

15

16

27

23

29

32

33

1

LRF Digital

Output

I/O

O

LRFD7

LRFD6

LRFD2

LRFD4

LRF digital output 7

LRF digital output 6

LRF digital output 2

LRF digital output 4

—

19

—

2

VDDR

Internal supply

—

20

34

8

—

11

18

24

17

31

38

VDDS

VDDD

1.71-V to 3.8V DIO supply

—

Power

For decoupling of internal 1.28-V regulated core-

supply.

16

28

DCDC

RSTN

ANT

17

13

1

30

25

39

40

Switching node of internal DC/DC converter

Global main device reset (active low)

50 ohm RF port

—

Reset

RF

RF Ground

RFGND

RF Ground reference

—

English Data Sheet: SWRS272

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FUNCTION

表7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)

Pin No.

SIGNAL

SIGNAL NAME

DESCRIPTION

TYPE

DIRECTION

QFN24 QFN40

3

8

2

12

13

20

5

SPI0SCLK

I/O

SPI clock

SPI POCI

—

12

4

5

6

7

SPI0POCI

9

15

16

21

5

10

SPI

—

4

SPI0CSN

SPI0PICO

22

32

6

I/O

SPI chip select

SPI PICO

—

19

5

6

7

11

14

27

11

12

5

—

15

7

SWDIO

SWDCK

T0C0

I/O

I

JTAG/SWD TCK. Reset default pinout.

JTAG/SWD TMS. Reset default pinout.

Capture/compare Output-0 from Timer-0

Capture/compare Output-1 from Timer-0

SWD

8

4

T0C1

10

8

16

12

27

15

20

6

I/O

T0C2

Capture/compare Output-2 from Timer-0

15

9

T1C0

T1C1

Capture/compare Output-0 from Timer-1

Capture/compare Output-1 from Timer-1

12

5

I/O

7

11

26

32

18

19

29

3

T1C2

14

19

Capture/compare Output-2 from Timer-1

Timers -

Capture/

Compare

T2C0

T2C1

T2C2

Capture/compare Output-0 from Timer-2

Capture/compare Output-1 from Timer-2

Capture/compare Output-2 from Timer-2

—

12

T3C0

13

20

14

23

26

33

9

Capture/compare Output-0 from Timer-3

—

14

I/O

T3C1

T3C2

Capture/compare Output-1 from Timer-3

Capture/compare Output-2 from Timer-3

—

22

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表7-6. RKP (QFN40) and RGE (QFN24) Peripheral Signal Descriptions (continued)

Pin No.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

DESCRIPTION

QFN24 QFN40

3

6

2

7

Complementary compare/PWM Output-0 from

Timer-0

T0C0N

Complementary compare/PWM Output-1 from

Timer-0

I/O

O

T0C1N

T0C2N

14

15

26

27

Complementary compare/PWM Output-2 from

Timer-0

3

7

2

11

12

16

5

Complementary compare/PWM Output-0 from

Timer-1

T1C0N

T1C1N

T1C2N

8

Complementary compare/PWM Output-1 from

Timer-1

I/O

O

10

4

Timers -

Complementary

Capture/

Complementary compare/PWM Output-2 from

Timer-1

9

—

Compare

Complementary compare/PWM Output-0 from

Timer-2

T2C0N

T2C1N

T2C2N

T3C0N

T3C1N

T3C2N

10

24

21

4

—

Complementary compare/PWM Output-1 from

Timer-2

Complementary compare/PWM Output-2 from

Timer-2

Complementary compare/PWM Output-0 from

Timer-3

Complementary compare/PWM Output-1 from

Timer-3

18

19

I/O

O

Complementary compare/PWM Output-2 from

Timer-3

—

6

7

Timers - Fault

input

T1F

9

I

Fault input for Timer-1

—

12

23

4

T2PE

T0PE

I/O

O

Prescaler event ouput from Timer-2

Prescaler eveny ouput from Timer-0

14

20

24

7

Timers -

Prescaler Event

—

6

8

12

13

15

27

32

6

—

9

UART0TXD

UART0RXD

I/O

O

UART0 TX data

15

19

5

UART

10

11

15

18

16

24

2

—

7

I

UART0 RX data

9

—

10

UART0CTS

UART0RTS

I/O

I

UART0 clear-to-send input (active low)

UART0 request-to-send (active low)

—

3

O

23

—

English Data Sheet: SWRS272

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

0

MAX UNIT

VDDS

Supply voltage

4.1

V

Voltage on any digital pin⁽³⁾

Voltage on crystal oscillator pins X48P and X48N

Voltage on ADC input

VDDS + 0.3, max 4.1

1.24

VDDS

5

V

V_{in_adc}

V

Input level, RF pins

dBm

°C

T_stg

Storage temperature

150

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground, unless otherwise noted.

(3) Including analog capable DIOs.

8.2 ESD Ratings

VALUE

±1000

±250

UNIT

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

All pins

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

125

3.8

100

1

UNIT

°C

Operating ambient temperature^{(1) (2)}

–40

Operating junction temperature^{(1) (2)}

°C

–40

Operating supply voltage (VDDS)

Rising supply voltage slew rate

Falling supply voltage slew rate⁽³⁾

1.71

0

V

mV/µs

0

(1) Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime.

(2) For thermal resistance details, refer to Thermal Resistance Characteristics table in this document.

(3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 10-µF VDDS input capacitor must be used

to ensure compliance with this slew rate.

8.4 DCDC

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V with DCDC enabled unless otherwise

noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDS supply voltage for DCDC operation ^{(1) (2)}

2.2

3.0

3.8

V

(1) When the supply voltage drops below the DCDC operation min voltage, the device smoothly transitions to use GLDO regulator on-

chip.

(2) A 10µH inductor and a 10µF load capacitor is recommended at VDDR pin.

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English Data Sheet: SWRS272

CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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8.5 Global LDO (GLDO)

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDS supply voltage for GLDO operation ⁽¹⁾

1.71

3.0

3.8

V

(1) A 10 µF capacitor is recommended at VDDR pin.

8.6 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDDS_BOD

Untrimmed brownout rising threshold

Trimmed brownout rising threshold ⁽¹⁾

Trimmed brownout falling threshold ⁽¹⁾

POR

Before initial boot ⁽¹⁾

1.67

1.68

1.67

V

power-on reset power-up level

power-on reset power-down level

1.5

V

1.45

(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RSTN pin.

8.7 Battery Monitor

Measured on the CC2340R5 reference design with T_c= 25 °C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

V

Resolution

Range

22

1.7

3.8

Accuracy

VDDS = 3.0 V

30

mV

8.8 Temperature Sensor

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Accuracy

-40 °C to 85 °C

±10 ⁽¹⁾

°C

(1) Raw output from register.

English Data Sheet: SWRS272

22

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8.9 Power Consumption - Power Modes

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, DCDC enabled, GLDO disabled, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

TYP

UNIT

Core Current Consumption with DCDC

I_core

Active

Idle

MCU running CoreMark from Flash at 48 MHz

2.6

mA

MCU running CoreMark from Flash at 48MHz

53 µA / MHz

Supply Systems and RAM powered, flash disabled, DMA disabled

Supply Systems and RAM powered, flash disabled, DMA enabled

Supply Systems and RAM powered, flash enabled, DMA disabled

Supply Systems and RAM powered, flash enabled, DMA enabled

780

µA

Idle

810

1100

1200

Idle

RTC running, 36kB RAM retention

LFOSC, DCDC recharge current setting (ipeak = 1)

I_core

Standby

0.71

0.74

µA

RTC running, 36kB RAM retention

LFXT, DCDC recharge current setting (ipeak = 1)

I_core

Core Current consumption with GLDO

I_core

Active

Idle

MCU running CoreMark from Flash at 48 MHz

4.1

1170

1230

1490

1665

mA

µA

Supply Systems and RAM powered, flash disabled, DMA disabled

Supply Systems and RAM powered, flash disabled, DMA enabled

Supply Systems and RAM powered, flash enabled, DMA disabled

Supply Systems and RAM powered, flash enabled, DMA enabled

Idle

RTC running, 36kB RAM retention

LFOSC, default GLDO recharge current setting

I_core

Standby

1.1

µA

RTC running, 36kB RAM retention

LFXT default GLDO recharge current setting

1.15

Reset, Shutdown Current Consumption

I_core

Reset

Reset. RSTN pin asserted or VDDS below power-on-reset threshold

150

nA

Shutdown measured in steady state. No clocks running, no retention, IO

wakeup enabled

Shutdown

Peripheral Current Consumption

I_peri

RF

Delta current, clock enabled, RF subsystem idle

Delta current with clock enabled, module is idle, one LGPT timer

Delta current with clock enabled, module is idle

40

2.4

µA

Timers

I2C

10.6

3.4

SPI

UART

24.5

3.8

CRYPTO (AES)

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CC2340R5

ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

www.ti.com.cn

8.10 Power Consumption - Radio Modes

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V with DCDC enabled unless otherwise

noted.

PARAMETER

TEST CONDITIONS

TYP UNIT

I_RX

Radio receive current

Radio transmit current

2440 MHz, 1 Mbps, GFSK, system bus off ⁽¹⁾

2440 MHz, 1 Mbps, GFSK, DCDC OFF, system bus off ⁽¹⁾

5.3

9

mA

-8 dBm output power setting

2440 MHz system bus off ⁽¹⁾

I_TX

4.0

5.1

8.8

7.7

8.9

10.7

19

mA

Radio transmit current

0 dBm output power setting

2440 MHz system bus off ⁽¹⁾

0 dBm output power setting

2440 MHz DCDC OFF, system bus off ⁽¹⁾

+4 dBm output power setting

2440 MHz system bus off ⁽¹⁾

+6 dBm output power setting

2440 MHz system bus off ⁽¹⁾

+8 dBm output power setting

2440 MHz system bus off ⁽¹⁾

+8 dBm output power setting

2440 MHz DCDC OFF, system bus off ⁽¹⁾

(1) System bus off refers to device idle mode, DMA disabled, flash disabled

8.11 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and V_DDS= 3.0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Flash sector size

2

KB

Supported flash erase cycles before failure, full bank^{(1) (2)}

Supported flash erase cycles before failure, single sector⁽³⁾

30

60

k Cycles

Maximum number of write operations per row before sector

erase⁽⁴⁾

Write

Operations

83

Flash retention

105 °C

125 °C

11.4

10

Years

mA

Flash retention

Flash sector erase current

Flash sector erase time⁽⁵⁾

Flash write current

Flash write time⁽⁵⁾

Average delta current

1.2

2.2

1.7

7.7

0 erase cycles

ms

Average delta current, full sector at a time

full sector at a time, 0 erase cycles

mA

µs

(1) A full bank erase is counted as a single erase cycle on each sector

(2) Aborting flash during erase or program modes is not a safe operation.

(3) Up to 16 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k

cycles

(4) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per

write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum

number of write operations per row is reached.

(5) This number is dependent on Flash aging and increases over time and erase cycles

8.12 Thermal Resistance Characteristics

PACKAGE

THERMAL

METRIC

RKP

(VQFN)

RGE

(VQFN)

THERMAL METRIC

UNIT ⁽¹⁾

40 PINS

31.8

24 PINS

40.1

R_θJA

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

℃/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

23.1

30.5

12.7

17.2

0.3

0.4

ψ_JT

English Data Sheet: SWRS272

24

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PACKAGE

THERMAL

METRIC

RKP

(VQFN)

RGE

THERMAL METRIC

UNIT ⁽¹⁾

(VQFN)

40 PINS

12.7

24 PINS

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

17.1

3.4

ψ_JB

℃/W

R_θJC(bot)

3.3

(1) °C/W = degrees Celsius per watt.

8.13 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

MIN

TYP

MAX

UNIT

MHz

Frequency bands

2360

2510

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8.14 Bluetooth Low Energy - Receive (RX)

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled

unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All

measurements are performed conducted.

PARAMETER

125 kbps (LE Coded)

Receiver sensitivity

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BER = 10^–3

dBm

–102

Receiver saturation

5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

> (–122/ 122) ⁽¹⁾

> (–90 / 90) ⁽¹⁾

–6

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽²⁾

Selectivity, ±1 MHz⁽²⁾

Selectivity, ±2 MHz⁽²⁾

Selectivity, ±3 MHz⁽²⁾

Selectivity, ±4 MHz⁽²⁾

Selectivity, ±6 MHz⁽²⁾

Selectivity, ±7 MHz

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Wanted signal at –79 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±1

9 / 5 ⁽³⁾

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±2

44 / 31 ⁽³⁾

47 / 42 ⁽³⁾

49 / 45 ⁽³⁾

52 / 48 ⁽³⁾

54 / 49 ⁽³⁾

31

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±3

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±4

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ≥±6

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ≥±7

dB

MHz, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at

Selectivity, Image frequency⁽²⁾

dB

image frequency, BER = 10^–3

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –79 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽²⁾

5 / 42 ⁽³⁾

dB

500 kbps (LE Coded)

Receiver sensitivity

Receiver saturation

BER = 10^–3

dBm

–99

5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

> (–122 / 122) ⁽¹⁾

> (–90/ 90) ⁽¹⁾

> (–90 / 90) ⁽¹⁾

–4.5

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽²⁾

Selectivity, ±1 MHz⁽²⁾

Selectivity, ±2 MHz⁽²⁾

Selectivity, ±3 MHz⁽²⁾

Selectivity, ±4 MHz⁽²⁾

Selectivity, ±6 MHz⁽²⁾

Selectivity, ±7 MHz

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Wanted signal at –72 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±1

9 / 5 ⁽³⁾

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±2

42 / 31 ⁽³⁾

45 / 41 ⁽³⁾

46 / 42 ⁽³⁾

50 / 45 ⁽³⁾

51 / 46 ⁽³⁾

31

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±3

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±4

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ≥±6

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ≥±7

dB

MHz, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at

Selectivity, Image frequency⁽²⁾

dB

image frequency, BER = 10^–3

English Data Sheet: SWRS272

26

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When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled

unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All

measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –72 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽²⁾

5 / 41 ⁽³⁾

dB

1 Mbps (LE 1M)

Receiver sensitivity

Receiver saturation

BER = 10^–3

dBm

–96.5

5

Difference between the incoming carrier frequency and

the internally generated carrier frequency

> (–225 /225) ⁽¹⁾

> (–750 / 750) ⁽¹⁾

–6

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽²⁾

Selectivity, ±1 MHz⁽²⁾

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±1

7 / 5 ⁽³⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±2

Selectivity, ±2 MHz⁽²⁾

39 / 28 ⁽³⁾

44 / 38 ⁽³⁾

47 / 35 ⁽³⁾

40

dB

MHz,BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±3

Selectivity, ±3 MHz⁽²⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±4

Selectivity, ±4 MHz⁽²⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ≥±5

Selectivity, ±5 MHz or more⁽²⁾

Selectivity, image frequency⁽²⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at

28

dB

image frequency, BER = 10^–3

Note that Image frequency + 1 MHz is the Co- channel –

1 MHz. Wanted signal at –67 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±1 MHz⁽²⁾

5 / 38 ⁽³⁾

dB

Out-of-band blocking⁽⁴⁾

Out-of-band blocking

30 MHz to 2000 MHz

dBm

–10

–2

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz (excluding VCO frequency)

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2405 and 2408 MHz respectively, at the given power

level

Intermodulation

dBm

–37

Spurious emissions,

30 to 1000 MHz⁽⁵⁾

dBm

Measurement in a 50-Ωsingle-ended load.

< –59

< –47

Spurious emissions,

1 to 12.75 GHz⁽⁵⁾

RSSI dynamic range ⁽⁶⁾

RSSI accuracy

70

±4

1

dB

RSSI resolution

2 Mbps (LE 2M)

Receiver sensitivity

Receiver saturation

Measured at SMA connector, BER = 10^–3

dBm

–92

2

Difference between the incoming carrier frequency and

the internally generated carrier frequency

> (–225 / 225) ⁽¹⁾

> (–1050 / 1050) ⁽¹⁾

–8

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽²⁾

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel,BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±2

MHz, Image frequency is at –2 MHz, BER = 10^–3

Selectivity, ±2 MHz⁽²⁾

Selectivity, ±4 MHz⁽²⁾

9 / 5 ⁽³⁾

dB

Wanted signal at –67 dBm, modulated interferer at ±4

40 / 32 ⁽³⁾

MHz, BER = 10^–3

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When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled

unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All

measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Wanted signal at –67 dBm, modulated interferer at ±6

Selectivity, ±6 MHz⁽²⁾

46 / 40 ⁽³⁾

dB

MHz, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at

Selectivity, image frequency⁽²⁾

5

dB

image frequency, BER = 10^–3

Note that Image frequency + 2 MHz is the Co-channel.

Wanted signal at –67 dBm, modulated interferer at ±2

MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±2 MHz⁽²⁾

–8 / 32 ⁽³⁾

Out-of-band blocking⁽⁴⁾

Out-of-band blocking

30 MHz to 2000 MHz

dBm

–10

–12

–10

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz (excluding VCO frequency)

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2408 and 2414 MHz respectively, at the given power

level

Intermodulation

dBm

–38

(1) Exceeding Bluetooth specification

(2) Numbers given as I/C dB

(3) X / Y, where X is +N MHz and Y is –N MHz

(4) Excluding one exception at F_wanted/ 2, per Bluetooth Specification

(5) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2

(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)

(6) The device will saturate at -30dB.

English Data Sheet: SWRS272

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8.15 Bluetooth Low Energy - Transmit (TX)

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled

unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All

measurements are performed conducted.

PARAMETER

General Parameters

Max output power

TEST CONDITIONS

MIN

TYP

MAX UNIT

8

dBm

dB

Delivered to a single-ended 50-Ωload through integrated balun

Output power

programmable range

28

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8.16 Proprietary Radio Modes

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled unless

otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements

are performed conducted.

PARAMETER

2 Mbps GFSK (HID), 320 kHz deviation

Receiver sensitivity

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PER = 30.8%, Payload 37 bytes

-89

dBm

English Data Sheet: SWRS272

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8.17 2.4 GHz RX/TX CW

When measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with DCDC enabled

unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All

measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Spurious emissions and harmonics

f < 1 GHz, outside restricted bands

dBm

< –36

< –54

< –55

< –42

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

Spurious emissions⁽¹⁾

Harmonics ⁽¹⁾

+8 dBm setting

Third harmonic

(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2

(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

8.18 Timing and Switching Characteristics

8.18.1 Reset Timing

PARAMETER

MIN

TYP

MAX

UNIT

RSTN low duration

1

µs

8.18.2 Wakeup Timing

Measured over operating free-air temperature with V_DDS= 3.0 V (unless otherwise noted). The times listed here do not

include any software overhead (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GLDO default charge current setting,

VDDR capacitor fully charged ⁽²⁾

MCU, Reset/Shutdown to Active⁽¹⁾

350-450

µs

MCU, Standby to Active (ready to execute

code from flash). DCDC ON, default

recharge current configuration

MCU, Standby to Active

33-43 ⁽³⁾

33-50 ⁽³⁾

MCU, Standby to Active (ready to execute

code from flash). GLDO ON, default

recharge current configuration

µs

MCU, Idle to Active

Flash enabled in idle mode

Flash disabled in idle mode

3

µs

14

(1) Wakeup time includes device ROM bootcode execution time. The wakeup time is dependent on remaining charge on VDDR capacitor

when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again.

(2) This is the best case reset/shutdown to active time (including ROM bootcode operation), for the specified GLDO charge current setting

considering the VDDR capacitor is fully charged and is not discharged during the reset and shutdown events; that is, when the device

is in reset / shutdown modes for only a very short period of time

(3) Depending on VDDR capacitor voltage level.

8.18.3 Clock Specifications

8.18.3.1 48 MHz Crystal Oscillator (HFXT)

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽⁴⁾

PARAMETER

MIN

TYP

MAX

UNIT

Crystal frequency

48

MHz

Equivalent series resistance

6 pF < C_L≤9 pF

ESR

20

60

Ω

Equivalent series resistance

5 pF < C_L≤ 6 pF

ESR

C_L

80

9

Ω

Crystal load capacitance⁽¹⁾

3

7⁽²⁾

pF

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ZHCSSA2B –APRIL 2023 –REVISED MAY 2023

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Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽⁴⁾

PARAMETER

MIN

TYP

MAX

UNIT

Start-up

time ⁽³⁾

Until clock is qualified

200

µs

(1) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with

certain regulations.

(2) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed

through software in the Customer Configuration section (CCFG).

(3) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.

(4) Tai-Saw TZ3908AAAO43 has been validated for CC2340R5 design.

8.18.3.2 48 MHz RC Oscillator (HFOSC)

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

MHz

%

Frequency

48

Uncalibrated frequency accuracy

Calibrated frequency accuracy ⁽¹⁾

±3

±0.25

%

(1) Accuracy relative to the calibration source (HFXT)

8.18.3.3 32 kHz Crystal Oscillator (LFXT)

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

kHz

pF

Crystal frequency

32.768

Supported crystal load capacitance

ESR

6

12

30

100

kΩ

8.18.3.4 32 kHz RC Oscillator (LFOSC)

Measured on the CC2340R5 reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

32.768 ⁽¹⁾

±600

MAX

UNIT

kHz

Calibrated frequency

Temperature coefficient.

ppm/°C

(1) When using LFOSC as source for the low frequency system clock (LFCLK), the accuracy of the LFCLK-derived Real Time Clock

(RTC) can be improved by measuring LFOSC relative to HFXT and compensating for the RTC tick speed. This functionality is available

through the TI-provided Power driver.

English Data Sheet: SWRS272

32

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8.19 Peripheral Characteristics

8.19.1 UART

8.19.1.1 UART Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

UART rate

3

MBaud

8.19.2 SPI

8.19.2.1 SPI Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Primary Mode

1.71 < VDDS < 3.8

12

fSCLK

1/tsclk

Secondary Mode

2.7 < VDDS < 3.8

SPI clock frequency

8

MHz

%

Secondary Mode

VDDS < 2.7

7

DC_SCKSCK Duty Cycle

45

50

55

8.19.2.2 SPI Controller Mode

Over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ns

t_{SCLK_H/}

(t_SPI/2) -

1

(t_SPI/2) +

1

SCLK High or Low time

t_SPI/2

L

t_CS.LEADCS lead-time, CS active to clock

1

SCLK

CS lag time, Last clock to CS

t_CS.LAG

inactive

CS access time, CS active to

PICO data out

t_CS.ACC

1

SCLK

CS disable time, CS inactive to

t_CS.DIS

PICO high inpedance

t_VALID.C

PICO output data valid time⁽¹⁾

SCLK edge to PICO valid,C_L= 20 pF

C_L= 20 pF

13

ns

O

t_HD.COPICO output data hold time⁽²⁾

0

(1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge

(2) Specifies how long data on the output is valid after the output changing SCLK clock edge

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8.19.2.3 SPI Timing Diagrams - Controller Mode

CS

(inverted)

t_{CS, LEAD}

CS

1 / f_SPI

t_{CS, LAG}

SCLK

(SPO = 0)

t_{SCLK_H/L}

SCLK

(SPO = 1)

t_SU,CI

t_HD,CI

POCI

PICO

t_HD,CO

t_VALID,CO

t_{CS, DIS}

t_{CS, ACC}

Controller Mode, SPH = 0

图8-1. SPI Timing Diagram - Controller Mode, SPH = 0

CS

(inverted)

t_{CS, LEAD}

CS

1 / f_SPI

t_{CS, LAG}

SCLK

(SPO = 0)

t_{SCLK_H/L}

SCLK

(SPO = 1)

t_SU,CI

t_HD,CI

t_{CS, ACC}

POCI

PICO

t_HD,CO

t_VALID,CO

t_{CS, DIS}

Controller Mode, SPH = 1

图8-2. SPI Timing Diagram - Controller Mode, SPH = 1

8.19.2.4 SPI Peripheral Mode

Over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_CS.LEADCS lead-time, CS active to clock

1

SCLK

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Over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CS lag time, Last clock to CS

inactive

t_CS.LAG

t_CS.ACC

t_CS.DIS

1

SCLK

CS access time, CS active to

POCI data out

VDDS = 3.3V

VDDS = 1.8V

VDDS = 3.3V

VDDS = 1.8V

56

70

56

70

ns

CS access time, CS active to

POCI data out

CS disable time, CS inactive to

POCI high inpedance

CS disable time, CS inactive to

POCI high inpedance

t_SU.PI

t_HD.PI

PICO input data setup time

PICO input data hold time

30

0

ns

t_VALID.P

POCI output data valid time⁽¹⁾

SCLK edge to POCI valid,C_L= 20 pF, 3.3V (4)

50

65

ns

O

t_VALID.P

POCI output data valid time⁽¹⁾

POCI output data hold time⁽²⁾

SCLK edge to POCI valid,C_L= 20 pF, 1.8V (4)

C_L= 20 pF

ns

O

t_HD.PO

0

(1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge

(2) Specifies how long data on the output is valid after the output changing SCLK clock edge

8.19.2.5 SPI Timing Diagrams - Peripheral Mode

CS

(inverted)

t_{CS, LEAD}

CS

1 / f_SPI

t_{CS, LAG}

SCLK

(SPO = 0)

t_{SCLK_H/L}

SCLK

(SPO = 1)

t_SU,PI

t_HD,PI

PICO

POCI

t_HD,PO

t_VALID,PO

t_{CS, DIS}

t_{CS, ACC}

Peripheral Mode, SPH = 0

图8-3. SPI Timing Diagram - Peripheral Mode, SPH = 0

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CS

(inverted)

t_{CS, LEAD}

CS

1 / f_SPI

t_{CS, LAG}

SCLK

(SPO = 0)

t_{SCLK_H/L}

SCLK

(SPO = 1)

t_SU,PI

t_HD,PI

PICO

t_HD,PO

t_VALID,PO

t_{CS, DIS}

t_{CS, ACC}

POCI

Peripheral Mode, SPH = 1

图8-4. SPI Timing Diagram - Peripheral Mode, SPH = 1

8.19.3 I²C

8.19.3.1 I2C

Over operating free-air temperature range (unless otherwise noted)

PARAMETERS

TEST CONDITIONS

MIN

0

TYP

MAX

UNIT

kHz

µs

f_SCL

SCL clock frequency

400

t_HD,STAHold time (repeated) START

f_SCL= 100kHz

f_SCL> 100kHz

4.0

0.6

µs

Setup time for a repeated

t_SU,STA

START

f_SCL= 100kHz

f_SCL> 100kHz

4.7

0.6

µs

Setup time for a repeated

t_SU,STA

START

t_HD,DATData hold time

0

100

4.0

0.6

µs

t_SU,DATData setup time

t_SU,STOSetup time for STOP

f_SCL= 100kHz

f_SCL> 100kHz

Bus free time between STOP

and START conditions

t_BUF

f_SCL= 100kHz

f_SCL> 100kHz

4.7

1.3

50

µs

ns

Bus free time between STOP

and START conditions

t_BUF

Pulse duration of spikes

t_SP

supressed by input deglitch filter

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8.19.3.2 I²C Timing Diagram

t_SU,STA

t_BUF

t_HD,STA

SDA

tt_LOW

t

tt_HIGHt

t_SP

SCL

t_HD,DAT

t_SU,STO

t_SU,DAT

图8-5. I²C Timing Diagram

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MAX UNIT

8.19.4 GPIO

8.19.4.1 GPIO DC Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

T_A= 25 °C, V_DDS= 1.8 V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

39.08

9.815

65.84

20.71

1.105

0.752

108.9

39.96

µA

V

GPIO pulldown current

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 →1

IH = 1, transition voltage for input read as 1 →0

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

0.9145

0.5891

1.277

0.9146

V

IH = 1, difference between 0 →1

and 1 →0 points

GPIO input hysteresis

0.2559

0.3534

0.4401

V

T_A= 25 °C, V_DDS= 3.0 V

GPIO VOH at 10 mA load

high-drive GPIOs only, max drive setting

standard drive GPIOs

2.466

2.516

V

GPIO VOL at 10 mA load

0.2527

0.1985

GPIO VOH at 2 mA load

GPIO VOL at 2 mA load

standard drive GPIOs

T_A= 25 °C, V_DDS= 3.8 V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

169.5

60.08

1.757

1.262

261.5

109.7

1.983

1.515

392.7

171.6

2.27

µA

V

GPIO pulldown current

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 →1

IH = 1, transition voltage for input read as 1 →0

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

1.791

V

IH = 1, difference between 0 →1

and 1 →0 points

GPIO input hysteresis

T_A= 25 °C

0.3961

0.4689

0.5405

V

Lowest GPIO input voltage reliably interpreted as a

High

VIH

0.8*V_DDS

V

Highest GPIO input voltage reliably interpreted as a

Low

VIL

0.2*V_DDS

8.19.5 ADC

8.19.5.1 Analog-to-Digital Converter (ADC) Characteristics

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽²⁾Performance numbers require use of offset and gain adjustements in

software by TI-provided ADC drivers.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC Power Supply and Input Range Conditions

V_(Ax)

Analog input voltage range

All ADC analog input pins Ax

0

VDDS

V

RES = 0x0 (12Bit mode), Fs = 1.2MSPS, Internal reference

OFF (ADCREF_EN = 0), VeREF+ = VDDS

I_(ADC)

480

365

single-

ended

mode

Operating supply current

into VDDS terminal

μA

RES = 0x0 (12Bit mode), Fs = 266ksps, Internal reference ON

(ADCREF_EN = 0), ADCREF = 2.5V

Input capacitance into a

single terminal

C_{I GPIO}

R_{I GPIO}

5

7

1

pF

Input MUX ON-resistance

0.5

kΩ

ADC Switching Characteristics

ADC sampling frequency

F_SADC

ADCREF_EN = 1, RES = 0x0 (12-bit), VDDS = 1.71V to

VDDSmax

when using the internal ADC

REF

267¹

308¹

400¹

1.2¹

ksps

Msps

reference voltage

ADC sampling frequency

F_SADC

ADCREF_EN = 1, RES = 0x1 (10-bit), VDDS = 1.71V to

VDDSmax

when using the internal ADC

REF

reference voltage

ADC sampling frequency

F_SADC

ADCREF_EN = 1, RES = 0x2 (8-bit), VDDS = 1.71V to

VDDSmax

when using the internal ADC

REF

reference voltage

ADC sampling frequency

F_SEXTR

ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x0 (12-bit), VDDS

= 1.71V to VDDSmax

when using the external ADC

EF

reference voltage

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T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽²⁾Performance numbers require use of offset and gain adjustements in

software by TI-provided ADC drivers.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC sampling frequency

when using the external ADC

reference voltage

F_SEXTR

EF

ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x1 (10-bit), VDDS

= 1.71V to VDDSmax

1.33¹

Msps

ADC sampling frequency

when using the external ADC

reference voltage

F_SEXTR

EF

ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x2 (8-bit), VDDS

= 1.71V to VDDSmax

1.6 ¹

Msps

N_CONVER

Clock cycles for conversion

Sampling time

RES = 0x0 (12-bit)

RES = 0x1 (10-bit)

RES = 0x2 (8-bit)

14

12

9

cycles

ns

T

N_CONVER

T

N_CONVER

T

RES = 0x0 (12-bit), R_S= 25 Ω, C_pext= 10 pF. +/- 0.5 LSB

settling

t_Sample

250

20

Sample time required when

Vsupply/3 channel is

selected

t_VSUPPLY/

µs

3(sample)

ADC Linearity Parameters

Integral linearity error (INL)

for single-ended inputs

E_I

12-bit Mode, V_R+= VeREF+ = VDDS, VDDS=1.71-->3.8

+/- 2

+/- 1

1.98

LSB

Differential linearity error

(DNL)

E_D

E_O

12-bit Mode, External reference, V_R+= VeREF+ =

VDDS, VDDS=1.71-->3.8

Offset error

E_O

E_G

Offset error

Gain error

12-bit Mode, Internal reference, V_R+= ADCREF = 2.5V

External Reference, V_R+= VeREF+ = VDDS , VDD= 1.71-->3.8

Internal reference, V_R+= ADCREF = 2.5V

1.02

+/- 2

LSB

+/- 40

ADC Dynamic Parameters

ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =

0x2 (8-bit)

ENOB

Effective number of bits

8

9.9

bit

ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =

0x1 (10-bit)

Effective number of bits

ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =

0x0 (12-bit)

11.2

ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x2

(8-bit)

8

ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V} , RES = 0x1

(10-bit)

9.6

ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0

(12-bit)

ENOB

SINAD

Effective number of bits

10.4

bit

dB

VDDS reference, RES = 0x0 (12-bit)

11.2

Signal-to-noise and distortion ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES =

ratio 0x0 (12-bit)

69.18

Signal-to-noise and distortion ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0

64.37

69.18

SINAD

dB

ratio

(12-bit)

Signal-to-noise and distortion

ratio

VDDS reference, RES = 0x0 (12-bit)

ADC External Reference

Positive external reference

voltage input

ADCREF_EN=0, ADC reference sourced from external

reference pin (VeREF+)

EXTREF

1.4

VDDS

0

V

Negative external reference ADCREF_EN=0, ADC reference sourced from external

voltage input reference pin (VeREF-)

ADC Temperature Diode, Supply Monitor

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T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.⁽²⁾Performance numbers require use of offset and gain adjustements in

software by TI-provided ADC drivers.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC

Internal

Input:

V_supplyvoltage divider

V_SUPPLY/ accuracy for supply

ADC input channel: Vsupply monitor

+/- 1

%

3

monitoring

Accurac

y

ADC

Internal V_supplyvoltage divider current

ADC input channel Vsupply monitor. V_supply=VDDS=3.3V

ADC reference sourced from VDDS

10

µA

Input:

consumption

I_{Vsupply / 3}

ADC Internal and VDDS Reference

VDDSR Positive ADC reference

VDDS

1.4

V

EF

voltage

ADCREF_EN = 1, ADCREF_VSEL = 0, VDDS = 1.71V -

VDDSmax

ADCRE Internal ADC Reference

F

Voltage

ADCREF_EN = 1, ADCREF_VSEL = 1, VDDS = 2.7V -

VDDSmax

2.5

Operating supply current into

I_ADCREFVDDA terminal with internal

reference ON

ADCREF_EN = 1, VDDA = 1.7V to VDDAmax, ADCREF_VSEL

= {0,1}

80

2

µA

µs

Internal ADC Reference

t_ON

ADCREF_EN = 1

Voltage power on-time

(1) Measured with 48MHz HFOSC

(2) Using IEEE Std 1241-2010 for terminology and test methods

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8.19.6 Comparators

8.19.6.1 Ultra-low power comparator

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range

0

V_DDS

V

KHz

Clock frequency

Voltage Divider Accuracy

Offset

32

98

Input voltage range is between VDDS/4 and VDDS

Measured at V_DDS/ 2 (Errors seen when using two external inputs )

Step from –50 mV to 50 mV

%

+/- 27.3

1

mV

Decision time

3

Clock Cycle

COMP_LP disable →enable, VIN+, VIN- from pins,

Overdrive ≥20 mV

Comparator enable time

Current consumption

70

µs

Including using VDDS/2 as internal reference at VIN- comparator

terminal

270

nA

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9 Detailed Description

9.1 Overview

节4 shows the core modules of the CC2340R5 device.

9.2 System CPU

The CC2340R5 SimpleLink^™Wireless MCU contains an Arm^®Cortex^®-M0+ system CPU, which runs the

application, the protocol stacks, and the radio. The Cortex-M0+ processor is built on a highly area and power

optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers

exceptional energy efficiency through a small but powerful instruction set and extensively optimized design,

providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor offers

multiple benefits to developers including:

• Ultra-low power, energy efficient operation

• Deterministic, high-performance interrupt handling for time-critical applications

• Upward compatibility with the Cortex-M processors family

The Cortex-M0+ processor provides the excellent performance expected of a modern 32- bit architecture core,

with higher code density than other 8-bit and 16-bit microcontrollers. Its features include the following:

• ARMv6-M architecture optimized for small-footprint embedded applications

• Subset of Arm Thumb/Thumb-2 mixed 16- and 32-bit instructions delivers the high performance expected of

a 32-bit Arm

• Single-cycle multiply instruction

• VTOR supporting offset of the vector table base address

• Serial Wire debug with HW break-point comparators

• Ultra-low-power consumption with integrated sleep modes

• SysTick timer

• 48 MHz operation

• 0.99 DMIPS/MHz

Additionally, the CC2340Rx devices are compatible with all ARM tools and software.

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9.3 Radio (RF Core)

The low-power RF Core (LRF) implements a high performance and highly flexible RF sub system containing RF

and baseband circuitry in addition to a software defined digital radio (LRFD). LRFD provides a high-level,

command-based API to the main CPU and handles all of the timing critical and low-level details of many different

radio PHYs. Several signals are also available to control external circuitry such as RF switches or range

extenders autonomously.

The software-defined modem is not programmable by customers but is instead loaded with pre-compiled images

provided in the radio driver in the SimpleLink^™CC23xx software development kit (SDK). This mechanism allows

the radio platform to be updated for support of future versions of standards with over-the-air (OTA) updates while

still using the same silicon. LRFD stores the code images in the RF SRAM and does not make use of any ROM

memory, thus image loading from NV memory only occurs once after boot and also, no patching is required

when exiting power modes.

9.3.1 Bluetooth 5.3 Low Energy

The RF Core offers full support for Bluetooth 5.3 Low Energy, including the high-speed 2 Mbps physical layer

and the 500 kbps and 125 kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.3 stack or

through a high-level Bluetooth API.

The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times

the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers

significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.

Bluetooth 5.3 also enables unparalleled flexibility for adjustment of speed and range based on application needs,

which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2

Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not

previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster

responses, richer engagement, and longer battery life. Bluetooth 5.3 enables fast, reliable firmware updates.

9.3.2 802.15.4 (Thread and Zigbee)

Through a dedicated IEEE radio API, the RF sub-system supports the 2.4-GHz IEEE 802.15.4-2011 physical

layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread and Zigbee protocols. TI also provides

royalty-free protocol stacks for Thread and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end

solution.

9.4 Memory

The 512 KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-system

programmable and erasable. A special flash memory sector must contain a Customer Configuration section

(CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done

through the ccfg.c source file that is included in all TI provided examples.

The ultra-low leakage system static 36 KB RAM (SRAM) can be used for both storage of data and execution of

code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode

power consumption numbers. System SRAM is always initialized to zeroes upon code execution during boot.

The ROM includes device bootcode firmware handling initial device trimming operations, security configurations

and device lifecycle management. The ROM also contains a serial (SPI and UART) bootloader that can be used

for initial programming of the device.

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9.5 Cryptography

The CC2340R5 device comes with AES-128 cryptography hardware accelerator, reducing code footprint and

execution time for cryptographic operations. It also has the benefit of being lower power and improves availability

and responsiveness of the system because the cryptography operations run in a background hardware thread.

The AES hardware accelerators supports the following block cipher modes and message authentication codes:

• AES ECB encrypt

• AES CBC encrypt

• AES CTR encrypt/decrypt

• AES CBC-MAC

• AES GCM

• AEC CCM (uses a combination of CTR + CBC-MAC hardware via software drivers)

The AES hardware accelerator can be fed with plaintext/ciphertext from either CPU or using DMA. Sustained

throughput of one 16 byte ECB block per 23 cycles is possible corresponding to > 30 Mbps.

The CC2340R5 device supports Random Number Generation (RNG) using on-chip analog noise as the non-

deterministic noise source for the purpose of generating a seed for a cryptographically secure counter

deterministic random bit generator (CTR-DRBG) that in turn is used to generate random numbers for keys,

initialization vectors (IVs), and other random number requirements. Hardware acceleration of AES CTR-DRBG is

supported.

The CC2340R5 device includes a complete SHA 256 library in ROM, reducing the code footprint of the

application. Uses cases may include generating digests for use in digital signature algorithms, data integrity

checks, and password storage.

Together with a large selection of open-source cryptography libraries provided with the Software Development

Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform.

9.6 Timers

A large selection of timers are available as part of the CC2340R5 device. These timers are:

• Real-Time Clock (RTC)

The RTC is a 67-bit, 2-channel timer running on the LFCLK system clock. The RTC is active in STANDBY

and ACTIVE power states. When the device enters the RESET or SHUTDOWN state the RTC is reset.

The RTC accumulates time elapsed since reset on each LFCLK. The RTC counter is incremented by LFINC

at a rate of 32.768 kHz. LFINC indicates the period of LFCLK in μs, with an additional granularity of 16

fractional bits.

The counter can be read from two 32-bit registers. RTC.TIME8U has a range of approximately 9.5 hours with

an LSB representing 8 microseconds. RTC.TIME524M has a range of approximately 71.4 years with an LSB

representing 524 milliseconds.

There is hardware synchronization between the system timer (SYSTIM) and the RTC so that the multi-

channel and higher resolution SYSTIM remain in synchronization with the RTC’s time base.

The RTC has two channels: one compare channel and one capture channel and is capable of waking the

device out of the standby power state. The RTC compare channel is typically used only by system software

and only during the standby power state.

• System Timer (SYSTIM)

The SYSTIM is a 34-bit, 5-channel wrap-around timer with a per-channel selectable 32b slice with either a 1

us resolution and 1h11m35s range or 250 ns resolution and 17m54s range. All channels support both capture

and single-shot compare (posting an event) operation. One channel is reserved for system software, three

channels are reserved for radio software and one channel is freely available to user applications.

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For software convenience a hardware synchronization mechanism automatically ensures that the RTC and

SYSTIM share a common time base (albeit with different resolutions/spans). Another software convenience

feature is that SYSTIM qualifies any submitted compare values so that the timer channel will immediately

trigger if the submitted event is in the immediate past (4.294s with 1 us resolution and 1.049s with 250 ns

resolution).

• General Purpose Timers (LGPT)

The CC2340R5 device provides four LGPTs with 3 × 16 bit timers and 1× 24 bit timer, all running on up to 48

MHz. The LGPTs support a wide range of features such as:

– 3 capture/compare channels

– One-shot or periodic counting

– Pulse width modulation (PWM)

– Time counting between edges and edge counting

– Input filter implemented on each of the channels for all timers

– IR generation feature available on Timer-0

– Dead band feature available on Timer-1

The timer capture/compare and PWM signals are connected to IOs via IO controller module (IOC) and the

internal timer event connections to CPU, DMA and other peripherals are via the event fabric, which allows the

timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. Two LGPTs (2× 16 bit

timers) supports quadrature decoder mode to enable buffered decoding of quadrature-encoded sensor

signals. The LGPTs are available in device Active and Idle power modes.

表9-1. Timer Comparison

Feature

Timer 0

Timer 1

Timer 2

Timer 3

Counter Width

Quadrature Decoder

Park Mode on Fault

16-bit counter width

24-bit counter width

Yes

No

Yes

No

Yes

Programmable Dead-

Band Insertion

• Watchdog timer

The watchdog timer is used to regain control if the system operates incorrectly due to software errors. Upon

counter expiry, the watchdog timer resets the device when periodic monitoring of the system components and

tasks fails to verify proper functionality. The watchdog timer runs on a 32 kHz clock rate and operates in

device active, idle, and standby modes and cannot be stopped once enabled.

9.7 Serial Peripherals and I/O

The CC2340R5 device provides 1xUART, 1xSPI and 1xI2C serial peripherals

The SPI module supports both SPI controller and peripheral up to 12 MHz with configurable phase and polarity.

The UART module implement universal asynchronous receiver and transmitter functions. They support flexible

baud-rate generation up to a maximum of 3 Mbps and IRDA SIR mode of operation.

The I2C module is used to communicate with devices compatible with the I²C standard. The I²C interface can

handle 100 kHz and 400 kHz operation, and can serve as both controller and target.

The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals

to be assigned to I/O pins in a fixed manner over DIOs. All digital I/Os are interrupt and wake-up capable, have a

programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge

(configurable). When configured as an output, pins can function as either push-pull, open-drain, or open source.

Some GPIOs have high-drive capabilities, which are marked in bold in 节7.

For more information, see the CC23xx SimpleLink™ Wireless MCU Technical Reference Manual.

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9.8 Battery and Temperature Monitor

A combined temperature and battery voltage monitor is available in the CC2340R5 device. The battery and

temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and

respond to changes in environmental conditions as needed. The module contains window comparators to

interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can

also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.

9.9 µDMA

The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload

data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available

bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA

controller has dedicated channels for each supported on-chip module and can be programmed to automatically

perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller include the following (this is not an exhaustive list):

• Channel operation of up to 8 channels, with 6 channels having dedicated peripheral interface and 2 channels

having ability to be triggered via configurable events.

• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral

• Data sizes of 8, 16, and 32 bits

• Ping-pong mode for continuous streaming of data

9.10 Debug

On-chip debug is supported through the serial wire debug (SWD) interface, which is an ARM bi-directional 2-wire

protocol that communicates with the JTAG Test Access Port (TAP) controller and allows for complete debug

functionality. SWD is fully compatible with Texas Instruments' XDS family of debug probes.

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9.11 Power Management

To minimize power consumption, the CC2340R5 supports a number of power modes and power management

features (see 表9-2).

表9-2. Power Modes

SOFTWARE CONFIGURABLE POWER MODES ⁽¹⁾

RESET PIN

MODE

HELD

ACTIVE

Active

On

IDLE

Off

STANDBY

Off

SHUTDOWN

CPU

Off

No

Off

No

Off

Flash

Available

On

Off

SRAM

On

Retention

Off

Radio

Available

On

Available

On

Supply System

CPU register retention

SRAM retention

Duty Cycled

Full ⁽²⁾

Full

48 MHz high-speed clock

(HFCLK)

HFXT

Duty Cycled

Off

LFXT or

LFOSC

LFXT or

LFOSC

32 kHz low-speed clock (LFCLK)

Peripherals

LFXT or LFOSC

IOC, BATMON,

RTC, LPCOMP

Available

Wake-up on RTC

N/A

Available

On

Available

On

Off

Available

On

Off

On

Off

On

Off

Wake-up on pin edge

Wake-up on reset pin

Brownout detector (BOD)

Power-on reset (POR)

Watchdog timer (WDT)

On

Duty Cycled

On

Off

On

Available

Off

(1) “Available”indicates that the specific IP or feature can be enabled by user application in the corresponding device operating modes.

“On”indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the

corresponding device operating mode. “Off”indicates that the specific IP or feature is turned off and not available for the user

application in the corresponding device operating mode.

(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode

In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power

consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU..

In Idle mode the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active.

Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on state of the DMA and debug

subsystem.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or

comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the

device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up

again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby

mode.

In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with

the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from

shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in

this way and reset-by-reset pin or power-on reset, or thermal shutdown reset, by reading the reset status

register. The only state retained in this mode are the latched I/O state, 3V register bank, and the flash memory

contents.

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备注

The power, RF and clock management for the CC2340R5 device require specific configuration and

handling by software for optimized performance. This configuration and handling is implemented in the

TI-provided drivers that are part of the CC2340R5 software development kit (SDK). Therefore, TI

highly recommends using this software framework for all application development on the device. The

complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source

code.

9.12 Clock Systems

The CC2340R5 device has the following internal system clocks.

The 48 MHz HFCLK is used as the main system (MCU and peripherals) clock. This is driven by the internal 48

MHz RC Oscillator (HFOSC), which can track its accuracy against an external 48 MHz crystal (HFXT). Radio

operation requires an external 48 MHz crystal.

The 32.768 kHz LFCLK is used as the internal low-frequency system clock. It is used for the RTC, the watchdog

timer (if enabled in standby power mode), and to synchronize the radio timer before or after Standby power

mode. LFCLK can be driven by the internal 32.8 kHz RC Oscillator (LFOSC), a 32.768 kHz watch-type crystal, or

clock input in LFXT bypass mode. When using a crystal or the internal RC oscillator, the device can output the

32 kHz LFCLK signal to other devices, thereby reducing the overall system cost.

9.13 Network Processor

Depending on the product configuration, the CC2340R5 device can function as a wireless network processor

(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as

a system-on-chip (SoC - with the application and protocol stack running on the system CPU inside the device).

In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,

the application must be written according to the application framework supplied with the wireless protocol stack.

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10 Application, Implementation, and Layout

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Reference Designs

The following reference designs should be followed closely when implementing designs using the CC2340R5

device.

Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator

components, as well as ground connections for all of these.

LP-EM-CC2340R5 Design

Files

The CC2340R5 LaunchPad Design Files contain detailed schematics and

layouts to build application specific boards using the CC2340R5 device.

Sub-1 GHz and 2.4 GHz

The antenna kit allows real-life testing to identify the optimal antenna for your

Antenna Kit for LaunchPad™ application. The antenna kit includes 16 antennas for frequencies from 169 MHz

Development Kit and

SensorTag

to 2.4 GHz, including:

• PCB antennas

• Helical antennas

• Chip antennas

• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz

The antenna kit includes a JSC cable to connect to the Wireless MCU

LaunchPad Development Kits and SensorTags.

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10.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating

conditions. For more details, see Semiconductor and IC Package Thermal Metrics.

There are two recommended ways to derive the junction temperature from other measured temperatures:

1. From package temperature:

T = ψ × P + T

case

(1)

(2)

J

JT

2. From board temperature:

T = ψ × P + T

board

J

JB

P is the power dissipated from the device and can be calculated by multiplying current consumption with supply

voltage. Thermal resistance coefficients are found in Thermal Resistance Characteristics.

Example:

Using Equation 1, the temperature difference between the top of the case and junction temperature is calculated.

In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm output

power. Let us assume we want to maintain a junction temperature of 85 °C and the supply voltage is 3 V. To

calculate P, look up the current consumption for Tx at 85 °C in the Junction Temperature Calculation. From the

plot, we see that the current consumption is 7.8 mA. This means that P is 7.8 mA × 3 V = 23.4 mW.

The maximum case temperature is then calculated as:

°C

T

< T − 0.4

× 23.4mW = 84.991°C

(3)

W

case

j

For various application use cases current consumption for other modules may have to be added to calculate the

appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral

modules may be enabled, and so on. Typically, the easiest way to find the peak current consumption, and thus

the peak power dissipation in the device, is to measure as described in the Measuring CC13xx and CC26xx

Current Consumption application report.

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11 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed as follows.

11.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-

code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, X is in preview;

therefore, an X prefix/identification is assigned).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Production devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, RHB).

For orderable part numbers of devices in the RHB (5-mm x 5-mm) package type, see the Package Option

Addendum of this document, the Device Information in 节 3, the TI website (www.ti.com), or contact your TI

sales representative.

CC2340 R 5 2 E 0 RKP R

R = Large Reel

PREFIX

X = Experimental Device

Blank = Qualified Device

PACKAGE

RKP = 5 mm x 5 mm QFN

DEVICE

SimpleLink™ Bluetooth® 5.3

Low Energy Wireless MCU

PRODUCT REVISION

CONFIGURATION

R = Regular (+8 dBm)

TEMPERATURE

E = 125 °C Ambient

SRAM SIZE

2 = 36KB

FLASH SIZE

5 = 512KB

图11-1. Device Nomenclature

11.2 Tools and Software

The CC2340R5 device is supported by a variety of software and hardware development tools.

Development Kit

CC2340R5

LaunchPad™

Development Kit

The CC2340R5 LaunchPad ^™Development Kit enables development of high-

performance wireless applications that benefit from low-power operation. The kit features

the CC2340R5 SimpleLink Wireless MCU, which allows you to quickly evaluate and

prototype 2.4-GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee and

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Thread, plus combinations of these. The kit works with the LaunchPad ecosystem, easily

enabling additional functionality like sensors, display and more.

Software

SimpleLink™

CC23xx software

development kit

(SDK)

The SimpleLink CC23xx software development kit (SDK) provides a complete package for

the development of wireless applications on the CC23xx family of devices. The SDK

includes a comprehensive software package for the CC2340R5 device, including the

following protocol stacks:

• Bluetooth Low Energy 4 and 5.3

The SimpleLink CC23xx SDK is part of TI’s SimpleLink MCU platform, offering a single

development environment that delivers flexible hardware, software and tool options for

customers developing wired and wireless applications. For more information about the

SimpleLink MCU Platform, visit https://www.ti.com/simplelink.

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Development Tools

Code Composer

Studio^™Integrated

Development

Code Composer Studio is an integrated development environment (IDE) that supports TI's

Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a

suite of tools used to develop and debug embedded applications. It includes an optimizing

C/C++ compiler, source code editor, project build environment, debugger, profiler, and

many other features. The intuitive IDE provides a single user interface taking you through

each step of the application development flow. Familiar tools and interfaces allow users to

get started faster than ever before. Code Composer Studio combines the advantages of the

Eclipse^®software framework with advanced embedded debug capabilities from TI resulting

in a compelling feature-rich development environment for embedded developers.

Environment (IDE)

CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace^™

software (application energy usage profiling). A real-time object viewer plugin is available

for TI-RTOS, part of the SimpleLink SDK.

Code Composer Studio is provided free of charge when used in conjunction with the XDS

debuggers included on a LaunchPad Development Kit.

Code Composer

Studio™ Cloud

IDE

Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and

build CCS and Energia™ projects. After you have successfully built your project, you can

download and run on your connected LaunchPad. Basic debugging, including features like

setting breakpoints and viewing variable values is now supported with CCS Cloud.

IAR Embedded

Workbench^®for

Arm^®

IAR Embedded Workbench^®is a set of development tools for building and debugging

embedded system applications using assembler, C and C++. It provides a completely

integrated development environment that includes a project manager, editor, and build

tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,

including XDS110, IAR I-jet^™and Segger J-Link^™. A real-time object viewer plugin is

available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on

most software examples provided as part of the SimpleLink SDK.

A 30-day evaluation or a 32 KB size-limited version is available through iar.com.

SmartRF™ Studio

SmartRF™ Studio is a Windows^®application that can be used to evaluate and configure

SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of

RF systems to easily evaluate the radio at an early stage in the design process. It is

especially useful for generation of configuration register values and for practical testing and

debugging of the RF system. SmartRF Studio can be used either as a standalone

application or together with applicable evaluation boards or debug probes for the RF

device. Features of the SmartRF Studio include:

• Link tests - send and receive packets between nodes

• Antenna and radiation tests - set the radio in continuous wave TX and RX states

• Export radio configuration code for use with the TI SimpleLink SDK RF driver

• Custom GPIO configuration for signaling and control of external switches

CCS UniFlash

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.

UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free

of charge.

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11.2.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired

and wireless Arm^®MCUs (System-on-Chip) in a single software development environment. Delivering flexible

hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software

development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.

11.3 Documentation Support

To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate

to the device product folder (CC2340R5). In the upper right corner, click on Alert me to register and receive a

weekly digest of any product information that has changed. For change details, review the revision history

included in any revised document.

The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as

follows.

TI Resource Explorer

Software examples, libraries, executables, and documentation are available for your

device and development board.

Errata

CC2340R5 Silicon

Errata

The silicon errata describes the known exceptions to the functional specifications for

each silicon revision of the device and description on how to recognize a device

revision.

Application Reports

All application reports for the CC2340R5 device are found on the device product folder (CC2340R5).

Technical Reference Manual (TRM)

CC23xx SimpleLink™ Wireless MCU

TRM

The TRM provides a detailed description of all modules and

peripherals available in the device family.

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

SimpleLink^™, LaunchPad^™, Code Composer Studio^™, EnergyTrace^™, and TI E2E^™are trademarks of Texas

Instruments.

I-jet^™is a trademark of IAR Systems AB.

J-Link^™is a trademark of SEGGER Microcontroller Systeme GmbH.

Arm^®and Cortex^®are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Bluetooth^®is a registered trademark of Bluetooth SIG.

CoreMark^®is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.

Wi-Fi^®is a registered trademark of Wi-Fi Alliance.

Eclipse^®is a registered trademark of Eclipse Foundation.

IAR Embedded Workbench^®is a registered trademark of IAR Systems AB.

Windows^®is a registered trademark of Microsoft Corporation.

所有商标均为其各自所有者的财产。

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11.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RKP 40

5 x 5, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4229305/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RKP0040B

PLASTIC QUAD FLATPACK- NO LEAD

5.1

4.9

A

B

PIN 1 INDEX AREA

5.1

4.9

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.6

3.4

(0.1) TYP

11

20

36X 0.4

10

21

41

SYMM

4X

3.6

0.25

0.15

30

40X

1

0.1

C A B

C

PIN1 ID

(OPTIONAL)

40

31

0.05

SYMM

0.5

0.3

40X

4219083/A 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RKP0040B

PLASTIC QUAD FLATPACK- NO LEAD

2X (4.8)

3.5)

SYMM

(

40X (0.6)

40X (0.2)

40

31

1

30

36X (0.4)

SYMM

2X

(4.8)

2X (0.6)

2X (0.9)

21

10

(R 0.05) TYP

(Ø 0.2) VIA

11

20

TYP

2X (0.9283)

2X (0.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

SOLDERMASK

EXPOSED

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

NON- SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219083/A 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

.

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RKP0040B

PLASTIC QUAD FLATPACK- NO LEAD

2X (4.8)

SYMM

9X

1)

(

40X (0.6)

40X (0.2)

40

31

1

30

36X (0.4)

SYMM

2X

(4.8)

2X

(1.2)

21

10

(R 0.05) TYP

11

20

2X (1.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

74% PRINTED COVERAGE BY AREA

SCALE: 15X

4219083/A 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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