CC2500 [TI]
Single Chip Low Cost Low Power RF Transceiver; 单芯片低成本低功耗RF收发器
| 型号： | CC2500 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single Chip Low Cost Low Power RF Transceiver |
| 文件： | 总76页 (文件大小：1064K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC2500
CC2500
Single Chip Low Cost Low Power RF Transceiver
Applications
• 2400-2483.5 MHz ISM/SRD band systems
• Consumer Electronics
• Wireless audio
• Wireless keyboard and mouse
• Wireless game controllers
Product Description
controlled via an SPI interface. In a typical
system, the CC2500 will be used together with
a microcontroller and a few additional passive
components.
CC2500 is based on Chipcon’s SmartRF®04
technology in 0.18 µm CMOS.
The CC2500 is a low cost true single chip 2.4
GHz transceiver designed for very low power
wireless applications. The circuit is intended
for the ISM (Industrial, Scientific and Medical)
and SRD (Short Range Device) frequency
band at 2400-2483.5 MHz.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kbps. The
communication range can be increased by
enabling a Forward Error Correction option,
which is integrated in the modem.
CC2500 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication and wake-on-radio.
The main operating parameters and the 64-
byte transmit/receive FIFOs of CC2500 can be
Key Features
•
Small size (QLP 4x4 mm package, 20
pins)
True single chip 2.4 GHz RF transceiver
Frequency range: 2400-2483.5 MHz
High sensitivity (–101 dBm at 10 kbps, 1%
packet error rate)
Programmable data rate up to 500 kbps
Low current consumption (13.3 mA in RX,
250 kbps, input 30 dB above sensitivity
limit)
Programmable output power up to +1 dBm
Excellent receiver selectivity and blocking
performance
•
•
Suitable for frequency hopping systems
due to a fast settling frequency synthesizer
Optional Forward Error Correction with
interleaving
Separate 64-byte RX and TX data FIFOs
Efficient SPI interface: All registers can be
programmed with one “burst” transfer
Digital RSSI output
Suited for systems compliant with EN 300
328 and EN 300 440 class 2 (Europe),
CFR47 Part 15 (US), and ARIB STD-T66
(Japan)
Wake-on-radio functionality for automatic
low-power RX polling
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Very
few
external
components:
Many powerful digital features allow a
high-performance RF system to be made
using an inexpensive microcontroller
Integrated analog temperature sensor
Lead-free “green“ package
Completely on-chip frequency synthesizer,
no external filters or RF switch needed
Programmable baseband modem
Ideal for multi-channel operation
Configurable packet handling hardware
•
•
•
•
•
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 1 of 77
CC2500
Features (continued from front page)
compatibility
communication protocols
with
existing
radio
•
Flexible support for packet oriented
systems: On chip support for sync word
detection, address check, flexible packet
length and automatic CRC handling.
Programmable channel filter bandwidth
2-FSK, GFSK and MSK supported
OOK supported
Automatic Frequency Compensation can
be used to align the frequency synthesizer
to received centre frequency
•
•
Programmable Carrier Sense indicator
Programmable Preamble Quality Indicator
for detecting preambles and improved
protection against sync word detection in
random noise
Support for automatic Clear Channel
Assessment (CCA) before transmitting (for
listen-before-talk systems)
•
•
•
•
•
•
Support for per-package Link Quality
Indication
•
•
Optional automatic whitening and de-
whitening of data
Support for asynchronous transparent
receive/transmit mode for backwards
Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK
ADC
AFC
AGC
AMR
ASK
BER
CCA
CRC
CS
Binary Frequency Shift Keying
Analog to Digital Converter
Automatic Frequency Offset Compensation
Automatic Gain Control
Automatic Meter Reading
Amplitude Shift Keying
MSK
NA
Minimum Shift Keying
Not Applicable
PA
Power Amplifier
PCB
PD
Printed Circuit Board
Power Down
PER
PLL
Packet Error Rate
Bit Error Rate
Phase Locked Loop
Power-on Reset
Clear Channel Assessment
Cyclic Redundancy Check
Carrier Sense
POR
PQI
Preamble Quality Indicator
Preamble Quality Threshold
RC Oscillator
PQT
RCOSC
RF
DC
Direct Current
EIRP
ESR
FEC
FIFO
FHSS
FSK
GFSK
IF
Equivalent Isotropic Radiated Power
Equivalent Series Resistance
Forward Error Correction
First-In-First-Out
Radio Frequency
RSSI
RX
Received Signal Strength Indicator
Receive, Receive Mode
Surface Aqustic Wave
Signal to Noise Ratio
Serial Peripheral Interface
To Be Defined
SAW
SNR
SPI
Frequency Hopping Spread Spectrum
Frequency Shift Keying
Gaussian shaped Frequency Shift Keying
Intermediate Frequency
Listen Before Transmit
TBD
TX
Transmit, Transmit Mode
Voltage Controlled Oscillator
Wake on Radio, Low power polling
Crystal Oscillator
LBT
LNA
LO
VCO
WOR
XOSC
XTAL
Low Noise Amplifier
Local Oscillator
LQI
Link Quality Indicator
Crystal
MCU
Microcontroller Unit
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 2 of 77
CC2500
Table Of Contents
APPLICATIONS...........................................................................................................................................1
PRODUCT DESCRIPTION.........................................................................................................................1
KEY FEATURES ..........................................................................................................................................1
FEATURES (CONTINUED FROM FRONT PAGE)................................................................................2
ABBREVIATIONS........................................................................................................................................2
TABLE OF CONTENTS ..............................................................................................................................3
1
2
3
ABSOLUTE MAXIMUM RATINGS..............................................................................................6
OPERATING CONDITIONS ..........................................................................................................6
GENERAL CHARACTERISTICS..................................................................................................6
4
ELECTRICAL SPECIFICATIONS................................................................................................7
CURRENT CONSUMPTION .....................................................................................................................7
RF RECEIVE SECTION...........................................................................................................................8
RF TRANSMIT SECTION ......................................................................................................................10
CRYSTAL OSCILLATOR.......................................................................................................................10
LOW POWER RC OSCILLATOR............................................................................................................11
FREQUENCY SYNTHESIZER CHARACTERISTICS...................................................................................11
ANALOG TEMPERATURE SENSOR .......................................................................................................12
DC CHARACTERISTICS .......................................................................................................................12
POWER-ON RESET ..............................................................................................................................12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
PIN CONFIGURATION.................................................................................................................13
CIRCUIT DESCRIPTION .............................................................................................................15
APPLICATION CIRCUIT.............................................................................................................15
CONFIGURATION OVERVIEW.................................................................................................17
CONFIGURATION SOFTWARE.................................................................................................18
4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...........................................19
6
7
8
9
10
10.1 CHIP STATUS BYTE ............................................................................................................................20
10.2 REGISTER ACCESS ..............................................................................................................................21
10.3 COMMAND STROBES ..........................................................................................................................22
10.4 FIFO ACCESS .....................................................................................................................................22
10.5 PATABLE ACCESS............................................................................................................................22
11
MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ...................................23
11.1 CONFIGURATION INTERFACE..............................................................................................................23
11.2 GENERAL CONTROL AND STATUS PINS ..............................................................................................23
11.3 OPTIONAL RADIO CONTROL FEATURE ...............................................................................................23
12
13
14
DATA RATE PROGRAMMING...................................................................................................24
RECEIVER CHANNEL FILTER BANDWIDTH .......................................................................24
DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION............................25
14.1 FREQUENCY OFFSET COMPENSATION.................................................................................................25
14.2 BIT SYNCHRONIZATION......................................................................................................................25
14.3 BYTE SYNCHRONIZATION...................................................................................................................25
15
PACKET HANDLING HARDWARE SUPPORT .......................................................................25
15.1 DATA WHITENING..............................................................................................................................26
15.2 PACKET FORMAT................................................................................................................................26
15.3 PACKET FILTERING IN RECEIVE MODE...............................................................................................27
15.4 CRC CHECK .......................................................................................................................................28
15.5 PACKET HANDLING IN TRANSMIT MODE............................................................................................28
15.6 PACKET HANDLING IN RECEIVE MODE ..............................................................................................28
16
MODULATION FORMATS..........................................................................................................29
16.1 FREQUENCY SHIFT KEYING................................................................................................................29
16.2 MINIMUM SHIFT KEYING....................................................................................................................29
16.3 AMPLITUDE MODULATION .................................................................................................................29
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 3 of 77
CC2500
17
RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION .....................30
17.1 SYNC WORD QUALIFIER.....................................................................................................................30
17.2 PREAMBLE QUALITY THRESHOLD (PQT)...........................................................................................30
17.3 RSSI...................................................................................................................................................30
17.4 CARRIER SENSE (CS)..........................................................................................................................31
17.5 CLEAR CHANNEL ASSESSMENT (CCA) ..............................................................................................32
17.6 LINK QUALITY INDICATOR (LQI).......................................................................................................32
18
FORWARD ERROR CORRECTION WITH INTERLEAVING ..............................................33
18.1 FORWARD ERROR CORRECTION (FEC)...............................................................................................33
18.2 INTERLEAVING ...................................................................................................................................33
19
RADIO CONTROL.........................................................................................................................34
19.1 POWER-ON START-UP SEQUENCE......................................................................................................35
19.2 CRYSTAL CONTROL............................................................................................................................35
19.3 VOLTAGE REGULATOR CONTROL.......................................................................................................35
19.4 ACTIVE MODES ..................................................................................................................................35
19.5 WAKE ON RADIO (WOR)...................................................................................................................36
19.6 TIMING ...............................................................................................................................................37
19.7 RX TERMINATION TIMER ...................................................................................................................37
20
21
22
DATA FIFO .....................................................................................................................................38
FREQUENCY PROGRAMMING.................................................................................................39
VCO ..................................................................................................................................................40
22.1 VCO AND PLL SELF-CALIBRATION ...................................................................................................40
23
24
25
26
VOLTAGE REGULATORS ..........................................................................................................40
OUTPUT POWER PROGRAMMING .........................................................................................40
SELECTIVITY GRAPHS ..............................................................................................................42
CRYSTAL OSCILLATOR.............................................................................................................44
26.1 REFERENCE SIGNAL ...........................................................................................................................44
27
28
29
EXTERNAL RF MATCH ..............................................................................................................45
GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................45
ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................47
29.1 ASYNCHRONOUS OPERATION..............................................................................................................47
29.2 SYNCHRONOUS SERIAL OPERATION ....................................................................................................47
30
SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................47
30.1 SRD REGULATIONS............................................................................................................................47
30.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS.....................................................................47
30.3 DATA BURST TRANSMISSIONS............................................................................................................48
30.4 CONTINUOUS TRANSMISSIONS ...........................................................................................................48
30.5 CRYSTAL DRIFT COMPENSATION .......................................................................................................48
30.6 SPECTRUM EFFICIENT MODULATION..................................................................................................48
30.7 LOW COST SYSTEMS ..........................................................................................................................49
30.8 BATTERY OPERATED SYSTEMS ..........................................................................................................49
30.9 INCREASING OUTPUT POWER .............................................................................................................49
31
CONFIGURATION REGISTERS.................................................................................................49
31.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ..........54
31.2 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE ........69
31.3 STATUS REGISTER DETAILS.................................................................................................................70
32
PACKAGE DESCRIPTION (QLP 20)..........................................................................................73
32.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20).....................................................................74
32.2 PACKAGE THERMAL PROPERTIES ........................................................................................................74
32.3 SOLDERING INFORMATION..................................................................................................................74
32.4 TRAY SPECIFICATION..........................................................................................................................74
32.5 CARRIER TAPE AND REEL SPECIFICATION ...........................................................................................75
33
34
ORDERING INFORMATION.......................................................................................................75
GENERAL INFORMATION.........................................................................................................75
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 4 of 77
CC2500
34.1 DOCUMENT HISTORY .........................................................................................................................75
34.2 PRODUCT STATUS DEFINITIONS .........................................................................................................75
34.3 DISCLAIMER .......................................................................................................................................76
34.4 TRADEMARKS.....................................................................................................................................76
34.5 LIFE SUPPORT POLICY ........................................................................................................................76
35
ADDRESS INFORMATION..........................................................................................................77
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 5 of 77
CC2500
1
Absolute Maximum Ratings
Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.
Caution!
ESD
sensitive
device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
Parameter
Min
Max
3.6
Units
Condition
Supply voltage
–0.3
V
V
All supply pins must have the same voltage
Voltage on any digital pin
–0.3
VDD+0.3
max 3.6
2.0
Voltage on the pins RF_P, RF_N
and DCOUPL
–0.3
V
Voltage ramp-up rate
Input RF level
120
+10
150
260
kV/µs
dBm
°C
Storage temperature range
Solder reflow temperature
–50
T = 10 s
°C
Table 1: Absolute Maximum Ratings
2
Operating Conditions
The operating conditions for CC2500 are listed Table 2 in below.
Parameter
Min
–40
1.8
Max
85
Unit
°C
Condition
Operating temperature
Operating supply voltage
3.6
V
All supply pins must have the same voltage
Table 2: Operating Conditions
3
General Characteristics
Parameter
Min
2400
1.2
Typ
Max
2483.5
500
Unit
MHz
kbps
Condition/Note
Frequency range
Data rate
Modulation formats supported:
(Shaped) MSK (also known as differential offset
QPSK) up to 500 kbps
2-FSK up to 500 kbps
GFSK and OOK (up to 250 kbps)
Optional Manchester encoding (halves the data rate).
Table 3: General Characteristics
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 6 of 77
CC2500
4
Electrical Specifications
4.1 Current Consumption
Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.
Parameter
Min
Typ
Max
Unit Condition
Current consumption in
power down modes
400
nA
nA
µA
µA
µA
Voltage regulator to digital part off, register values retained
(SLEEP state)
900
92
Voltage regulator to digital part off, register values retained, low-
power RC oscillator running (SLEEP state with WOR enabled)
Voltage regulator to digital part off, register values retained,
XOSC running (SLEEP state with MCSM0.OSC_FORCE_ONset)
157
1.4
Voltage regulator to digital part on, all other modules in power
down (XOFF state)
Current consumption
Automatic RX polling once each second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kbps data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level.
17
Same as above, but with signal in channel above carrier sense
level, 1.9 ms RX timeout, and no preamble/sync word found.
µA
µA
0.9
Automatic RX polling every 15th second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kbps data rate,
PLL calibration every 4th wakeup. Average current with signal in
channel below carrier sense level.
37
Same as above, but with signal in channel above carrier sense
level, 14 ms RX timeout, and no preamble/sync word found.
µA
1.5
mA Only voltage regulator to digital part and crystal oscillator running
(IDLE state)
7.4
mA Only the frequency synthesizer running (after going from IDLE
until reaching RX or TX states, and frequency calibration states)
Current consumption,
RX states
15.3
12.8
15.4
12.9
18.8
15.7
16.6
13.3
19.6
17.0
mA Receive mode, 2.4 kbps, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 2.4 kbps, input 30 dB above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 10 kbps, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 10 kbps, input 30 dB above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 250 kbps, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 0
mA Receive mode, 250 kbps, input 30 dB above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 0
mA Receive mode, 250 kbps reduced current, input at sensitivity
limit, MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 250 kbps reduced current, input 30 dB above
sensitivity limit, MDMCFG2.DEM_DCFILT_OFF= 1
mA Receive mode, 500 kbps, input at sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 0
mA Receive mode, 500 kbps, input 30 dB above sensitivity limit,
MDMCFG2.DEM_DCFILT_OFF= 0
Current consumption,
TX states
11.1
15.1
mA Transmit mode, –12 dBm output power
mA Transmit mode, -6 dBm output power
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 7 of 77
CC2500
Parameter
Min
Typ
21.2
21.5
Max
Unit Condition
mA Transmit mode, 0 dBm output power
mA Transmit mode, 1.5 dBm output power
Table 4: Current Consumption
4.2 RF Receive Section
Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.
Parameter
Min Typ
Max
Unit Condition/Note
kHz User programmable. The bandwidth limits are proportional
Digital channel filter
bandwidth
58
812
to crystal frequency (given values assume a 26.0 MHz
crystal).
2.4 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF= 1
(2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)
Receiver sensitivity
–104
dBm The sensitivity can be improved to typically –106 dBm by
setting MDMCFG2.DEM_DCFILT_OFF= 0 . The typical
current consumption is in this case 17.0 mA at sensitivity
llimit.
Saturation
–13
23
dBm
Adjacent channel
rejection
dB
Desired channel 3 dB above the sensitivity limit. 250 kHz
channel spacing
Alternate channel
rejection
31
dB
Desired channel 3 dB above the sensitivity limit. 250 kHz
channel spacing
See Figure 17 for plot of selectivity versus frequency offset
10 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF= 1
(2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)
Receiver sensitivity
–99
dBm The sensitivity can be improved to typically –101 dBm by
setting MDMCFG2.DEM_DCFILT_OFF= 0 . The typical
current consumption is in this case 17.3 mA at sensitivity
llimit.
Saturation
–9
18
dBm
Adjacent channel
rejection
dB
Desired channel 3 dB above the sensitivity limit. 250 kHz
channel spacing
Alternate channel
rejection
25
dB
Desired channel 3 dB above the sensitivity limit. 250 kHz
channel spacing
See Figure 18 for plot of selectivity versus frequency offset
250 kbps data rate, MDMCFG2.DEM_DCFILT_OFF= 0
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity
Saturation
–89
–13
21
dBm
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 750 kHz
channel spacing
Alternate channel
rejection
30
dB
Desired channel 3 dB above the sensitivity limit. 750 kHz
channel spacing
See Figure 19 for plot of selectivity versus frequency offset
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 8 of 77
CC2500
Parameter
Min Typ
Max
Unit Condition/Note
250 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF= 1
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity
Saturation
–87
–13
21
dBm
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 750 kHz
channel spacing
Alternate channel
rejection
30
dB
Desired channel 3 dB above the sensitivity limit. 750 kHz
channel spacing
See Figure 20 for plot of selectivity versus frequency offset
500 kbps data rate, MDMCFG2.DEM_DCFILT_OFF= 0
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity
Saturation
–82
–18
14
dBm
dBm
dB
Adjacent channel
rejection
Desired channel 3 dB above the sensitivity limit. 1 MHz
channel spacing
Alternate channel
rejection
25
dB
Desired channel 3 dB above the sensitivity limit. 1 MHz
channel spacing
See Figure 21 for plot of selectivity versus frequency offset
General
Selectivity at 10 MHz
offset
47
52
54
dB
dB
dB
Desired channel at –80 dBm. Compliant with ETSI EN 300
440 class 2 receiver requirements.
Selectivity at 20 MHz
offset
Desired channel at –80 dBm. Compliant with ETSI EN 300
440 class 2 receiver requirements.
Selectivity at 50 MHz
offset
Desired channel at –80 dBm. Compliant with ETSI EN 300
440 class 2 receiver requirements.
Spurious emissions
25 MHz – 1 GHz
Above 1 GHz
–57
–47
dBm
dBm
Table 5: RF Receive Parameters
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 9 of 77
CC2500
4.3 RF Transmit Section
Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurements were performed using the CC2500EM reference
design.
Parameter
Min
Typ
Max Unit Condition/Note
Differential impedance as seen from the RF-port (RF_P and
Differential load
impedance
80 + j74
Ω
RF_N) towards the antenna. Follow the CC2500EM
reference design available from Chipcon’s website.
Output power,
highest setting
+1
dBm Output power is programmable and is available across the
entire frequency band
Delivered to a 50 Ω single-ended load via Chipcon
reference design RF matching network.
Output power,
lowest setting
–30
dBm Output power is programmable and is available across the
entire frequency band
Delivered to a 50 Ω single-ended load via Chipcon
reference design RF matching network.
Spurious emissions
25 MHz – 1 GHz
–36 dBm
–54 dBm
47-74, 87.5-118, 174-
230, 470-862 MHz
1800-1900 MHz
–47
dBm Restricted band in Europe
At 2·RF and 3·RF
–41 dBm Restricted bands in USA
–30 dBm
Otherwise above 1
GHz
Table 6: RF Transmit Parameters
4.4 Crystal Oscillator
Tc = 25°C, VDD = 3.0 V if nothing else stated.
Parameter
Min
Typ
26
Max
Unit
MHz
ppm
Condition/Note
Crystal frequency
Tolerance
26
27
±40
This is the total tolerance including a) initial tolerance, b) crystal
loading, c) aging and d) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.
ESR
100
Ω
Start-up time
300
µs
Measured on Chipcon’s CC2500EM reference design.
Table 7: Crystal Oscillator Parameters
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 10 of 77
CC2500
4.5 Low Power RC Oscillator
Typical performance is for Tc = 25°C @ VDD = 3.0 V if nothing else is stated. The values in the table are simulated results
and will be updated in later versions of the data sheet.
Parameter
Min
Typ
Max
Unit
kHz
Condition/Note
Calibrated frequency
34.6
34.7
36
Calibrated RC Oscillator frequency is XTAL
frequency divided by 750
Frequency accuracy after
calibration
+0.3
-10
%
Temperature coefficient
Supply voltage coefficient
Initial calibration time
+0.4
+3
2
Frequency drift when temperature changes
after calibration
% / °C
% / V
ms
Frequency drift when supply voltage changes
after calibration
When the RC Oscillator is enabled, calibration
is continuously done in the background as long
as the crystal oscillator is running.
Wake-up period
58e-6
59650
Seconds Programmable, dependent on XTAL frequency
Table 8: RC Oscillator Parameters
4.6 Frequency Synthesizer Characteristics
Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.
Parameter
Min
Typ
Max
Unit
Condition/Note
Programmed
frequency resolution
397
FXOSC
/
412
Hz
26-27 MHz crystal.
216
Synthesizer frequency
tolerance
±40
ppm
Given by crystal used. Required accuracy (including
temperature and aging) depends on frequency band and
channel bandwidth / spacing.
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
RF carrier phase noise
PLL turn-on / hop time
–78
–78
–81
–90
dBc/Hz @ 50 kHz offset from carrier
dBc/Hz @ 100 kHz offset from carrier
dBc/Hz @ 200 kHz offset from carrier
dBc/Hz @ 500 kHz offset from carrier
dBc/Hz @ 1 MHz offset from carrier
dBc/Hz @ 2 MHz offset from carrier
dBc/Hz @ 5 MHz offset from carrier
dBc/Hz @ 10 MHz offset from carrier
–100
–108
–116
–127
90
Time from leaving the IDLE state until arriving in the RX,
µs
FSTXON or TX state, when not performing calibration.
Crystal oscillator running.
PLL RX/TX and
TX/RX settling time
10
Settling time for the 1xIF frequency step from RX to TX,
and vice versa.
µs
PLL calibration time
18739
0.72
XOSC
cycles
Calibration can be initiated manually, or automatically
before entering or after leaving RX/TX.
0.69
0.72
ms
Min/typ/max time is for 27/26/26 MHz crystal frequency.
Table 9: Frequency Synthesizer Parameters
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 11 of 77
CC2500
4.7 Analog Temperature Sensor
The characteristics of the analog temperature sensor are listed in Table 10 below. Note that it is
necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE
state.
Parameter
Min
Typ
Max
Unit
Condition/Note
0.660
0.755
0.859
0.958
1.056
2.54
V
V
V
V
V
Output voltage at –40°C
Output voltage at 0°C
Output voltage at +40°C
Output voltage at +80°C
Output voltage at +120°C
Temperature coefficient
mV/°C Fitted from –20°C to +80°C
Error in calculated
temperature, calibrated
0
°C
From –20°C to +80°C when using 2.54 mV / °C,
after 1-point calibration at room temperature
Current consumption
0.3
mA
increase when enabled
Table 10: Analog Temperature Sensor Parameters
4.8 DC Characteristics
The DC Characteristics of CC2500 are listed in Table 11 below.
Tc = 25°C if nothing else stated.
Digital Inputs/Outputs
Logic "0" input voltage
Logic "1" input voltage
Logic "0" output voltage
Logic "1" output voltage
Logic "0" input current
Logic "1" input current
Min
Max
0.7
Unit
V
Condition
0
VDD-0.7
0
VDD
0.5
VDD
–1
V
V
For up to 4 mA output current
For up to 4 mA output current
Input equals 0V
VDD-0.3
NA
V
µA
µA
NA
1
Input equals VDD
Table 11: DC Characteristics
4.9 Power-On Reset
When the power supply complies with the requirements in Table 12 below, proper Power-On-
Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state
until transmitting an SRESstrobe over the SPI interface. See Section 19.1 on page 35 for further
details.
Parameter
Min
Typ
Max
Unit
Condition/Note
Power ramp-up time
Power off time
5
ms
ms
From 0 V until reaching 1.8 V
1
Minimum time between power-on and power-off.
Table 12: Power-On Reset Requirements
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 12 of 77
CC2500
5
Pin Configuration
20 19 18 17 16
SCLK 1
SO (GDO1) 2
GDO2 3
15 AVDD
14 AVDD
13 RF_N
12 RF_P
11 AVDD
DVDD 4
DCOUPL 5
GND
Exposed die
attach pad
6
7
8
9 10
Figure 1: Pinout top view
Note: The exposed die attach pad must be connected to a solid ground plane as this is the main
ground connection for the chip.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 13 of 77
CC2500
Pin # Pin name
Pin type
Description
1
Digital Input
Serial configuration interface, clock input
SCLK
2
Digital Output
Serial configuration interface, data output.
Optional general output pin when CSnis high
Digital output pin for general use:
SO
(GDO1)
3
Digital Output
GDO2
•
•
•
•
•
Test signals
FIFO status signals
Clear Channel Indicator
Clock output, down-divided from XOSC
Serial output RX data
4
Power (Digital)
Power (Digital)
1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
DVDD
5
1.6 - 2.0 V digital power supply output for decoupling.
DCOUPL
NOTE: This pin is intended for use with the CC2500 only. It can not be
used to provide supply voltage to other devices.
6
Digital I/O
Digital output pin for general use:
GDO0
•
•
•
•
•
•
Test signals
(ATEST)
FIFO status signals
Clear Channel Indicator
Clock output, down-divided from XOSC
Serial output RX data
Serial input TX data
Also used as analog test I/O for prototype/production testing
Serial configuration interface, chip select
7
Digital Input
Analog I/O
CSn
8
Crystal oscillator pin 1, or external clock input
1.8 - 3.6 V analog power supply connection
Crystal oscillator pin 2
XOSC_Q1
9
Power (Analog)
Analog I/O
AVDD
10
XOSC_Q2
11
Power (Analog)
RF I/O
1.8 - 3.6 V analog power supply connection
AVDD
12
Positive RF input signal to LNA in receive mode
Positive RF output signal from PA in transmit mode
Negative RF input signal to LNA in receive mode
Negative RF output signal from PA in transmit mode
1.8 - 3.6 V analog power supply connection
RF_P
13
RF I/O
RF_N
14
Power (Analog)
Power (Analog)
Ground (Analog)
Analog I/O
AVDD
15
1.8 - 3.6 V analog power supply connection
Analog ground connection
AVDD
16
GND
17
External bias resistor for reference current
Power supply connection for digital noise isolation
Ground connection for digital noise isolation
Serial configuration interface, data input
RBIAS
18
Power (Digital)
Ground (Digital)
Digital Input
DGUARD
19
GND
20
SI
Table 13: Pinout overview
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 14 of 77
CC2500
6
Circuit Description
RADIO CONTROL
ADC
LNA
SCLK
ADC
SO (GDO1)
SI
RF_P
RF_N
FREQ
SYNTH
0
CSn
90
GDO0 (ATEST)
GDO2
PA
RC OSC
BIAS
XOSC
RBIAS
XOSC_Q1 XOSC_Q2
Figure 2: CC2500 simplified block diagram
phase shifter for generating the I and Q LO
signals to the down-conversion mixers in
receive mode.
A simplified block diagram of CC2500 is shown
in Figure 2.
CC2500
features a low-IF receiver. The
A crystal is to be connected to XOSC_Q1 and
XOSC_Q2. The crystal oscillator generates the
reference frequency for the synthesizer, as
well as clocks for the ADC and the digital part.
received RF signal is amplified by the low-
noise amplifier (LNA) and down-converted in
quadrature (I and Q) to the intermediate
frequency (IF). At IF, the I/Q signals are
digitised by the ADCs. Automatic gain control
(AGC), fine channel filtering, demodulation
bit/packet synchronization is performed
digitally.
A 4-wire SPI serial interface is used for
configuration and data buffer access.
The digital baseband includes support for
channel configuration, packet handling and
data buffering.
The transmitter part of CC2500 is based on
direct synthesis of the RF frequency.
The frequency synthesizer includes
a
completely on-chip LC VCO and a 90 degrees
7
Application Circuit
Only a few external components are required
for using the CC2500. The recommended
application circuit is shown in Figure 3. The
external components are described in Table
14, and typical values are given in Table 15.
Note that the PCB antenna alternative
indicated in Figure 3 is preliminary and subject
to changes. Performance for the PCB antenna
alternative will be included in future revisions
of this data sheet.
Bias resistor
The bias resistor R171 is used to set an
accurate bias current.
Balun and RF matching
C122, C132, L121 and L131 form a balun that
converts the differential RF signal on CC2500
to a single-ended RF signal (C121 and C131
are also needed for DC blocking). Together
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 15 of 77
CC2500
with an appropriate LC network, the balun
components also transform the impedance to
match a 50 Ω antenna (or cable). Component
values for the RF balun and LC network are
easily found using the SmartRF® Studio
software. Suggested values are listed in Table
15.
Power supply decoupling
The power supply must be properly decoupled
close to the supply pins. Note that decoupling
capacitors are not shown in the application
circuit. The placement and the size of the
decoupling capacitors are very important to
achieve the optimum performance. Chipcon
provides a reference design that should be
followed closely.
Crystal
The crystal oscillator uses an external crystal
with two loading capacitors (C81 and C101).
See Section 26 on page 44 for details.
Component
C51
Description
Decoupling capacitor for on-chip voltage regulator to digital part
Crystal loading capacitors, see Section 26 on page 44 for details
RF balun DC blocking capacitors
C81/C101
C121/C131
C122/C132
C123/C124
L121/L131
L122
RF balun/matching capacitors
RF LC filter/matching capacitors
RF balun/matching inductors (inexpensive multi-layer type)
RF LC filter inductor (inexpensive multi-layer type)
Resistor for internal bias current reference
R171
XTAL
26-27 MHz crystal, see Section 26 on page 44 for details
Table 14: Overview of external components (excluding supply decoupling capacitors)
1.8V-3.6V power supply
R171
SI
Antenna
(50 Ohm)
SCLK
1 SCLK
AVDD 15
AVDD 14
RF_N 13
RF_P 12
AVDD 11
L131
SO
2 SO (GDO1)
3 GDO2
(GDO1)
GDO2
(optional)
C131
C121
C132
CC2500
4 DVDD
DIE ATTACH PAD:
L122
C123
L121
C122
C124
5 DCOUPL
C51
GDO0
(optional)
CSn
Alternative:
Folded dipole PCB
antenna (no external
components needed)
XTAL
C81
C101
Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 16 of 77
CC2500
Component
C51
Value
100 nF ±10%, 0402 X5R
C81
27 pF ±5%, 0402 NP0
C101
C121
C122
C123
C124
C131
C132
L121
27 pF ±5%, 0402 NP0
100 pF ±5%, 0402 NP0
1.0 pF ±0.25 pF, 0402 NP0
1.8 pF ±0.25 pF, 0402 NP0
1.5 pF ±0.25 pF, 0402 NP0
100 pF ±5%, 0402 NP0
1.0 pF ±0.25 pF, 0402 NP0
1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
56 kΩ ±1%, 0402
L122
L131
R171
XTAL
26.0 MHz surface mount crystal
Table 15: Bill Of Materials for the application circuit
In the CC2500EM reference design LQG-15
series inductors from Murata have been used.
Measurements have been performed with
multi-layer inductors from other manufacturers
(e.g. Würth) and the measurement results
were the same as when using the Murata part.
8
Configuration Overview
CC2500 can be configured to achieve optimum
performance for many different applications.
Configuration is done using the SPI interface.
The following key parameters can be
programmed:
•
•
•
•
Packet radio hardware support
Forward Error Correction with interleaving
Data Whitening
Wake-On-Radio (WOR)
•
•
•
•
•
•
•
•
•
Power-down / power up mode
Crystal oscillator power-up / power-down
Receive / transmit mode
RF channel selection
Data rate
Modulation format
RX channel filter bandwidth
RF output power
Data buffering with separate 64-byte
receive and transmit FIFOs
Details of each configuration register can be
found in Section 31, starting on page 49.
Figure 4 shows a simplified state diagram that
explains the main CC2500 states, together with
typical usage and current consumption. For
detailed information on controlling the CC2500
state machine, and a complete state diagram,
see Section 19, starting on page 34.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 17 of 77
CC2500
Lowest power mode. Most
register values are retained.
Typ. current consumption
400nA, or 900nA when
wake-on-radio (WOR) is
enabled.
Sleep
SPWD or wake-on-radio (WOR)
SIDLE
Default state when the radio is not
receiving or transmitting. Typ.
current consumption: 1.5mA.
CSn=0
Idle
SXOFF
CSn=0
SCAL
Used for calibrating frequency
synthesizer upfront (entering
receive or transmit mode can
then be done quicker).
Transitional state. Typ. current
consumption: 7.4mA.
All register values are
retained. Typ. current
consumption; 0.16mA.
Manual freq.
synth. calibration
Crystal
oscillator off
SRX or STX or SFSTXON or wake-on-radio (WOR)
Frequency
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state. Typ. current consumption: 7.4mA.
synthesizer startup,
optional calibration,
settling
SFSTXON
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the
STX command strobe.Typ.
current consumption: 7.4mA.
Frequency
synthesizer on
STX
SRX or wake-on-radio (WOR)
STX
TXOFF_MODE=01
SFSTXON or RXOFF_MODE=01
Typ. current consumption:
11.1mA at -12dBm output,
15.1mA at -6dBm output,
21.2mA at 0dBm output.
Typ. current consumption:
from 13.3mA (strong
input signal) to 16.3mA
(weak input sgnal).
STX or RXOFF_MODE=10
SRX or TXOFF_MODE=11
Transmit mode
Receive mode
TXOFF_MODE=00
RXOFF_MODE=00
Optional transitional state. Typ.
current consumption: 7.4mA.
In FIFO-based modes,
In FIFO-based modes,
transmission is turned off
and this state entered if the
TX FIFO becomes empty in
the middle of a packet. Typ.
current consumption: 1.5mA.
reception is turned off and
this state entered if the RX
FIFO overflows. Typ. current
consumption: 1.5mA.
TX FIFO
underflow
Optional freq.
synth. calibration
RX FIFO
overflow
SFTX
SFRX
Idle
Figure 4: Simplified state diagram, with typical usage and current consumption at 250 kbps
data rate and MDMCFG2.DEM_DCFILT_OFF = 1 (reduced current)
9
Configuration Software
CC2500 can be configured using the SmartRF®
Studio software, available for download from
http://www.chipcon.com. The SmartRF® Studio
software is highly recommended for obtaining
optimum register settings, and for evaluating
performance and functionality. A screenshot of
the SmartRF® Studio user interface for CC2500
is shown in Figure 5.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 18 of 77
CC2500
Figure 5: SmartRF® Studio user interface
10 4-wire Serial Configuration and Data Interface
will be cancelled. The timing for the address
and data transfer on the SPI interface is
shown in Figure 6 with reference to Table 16.
CC2500 is configured via a simple 4-wire SPI-
compatible interface (SI, SO, SCLK and CSn)
where CC2500 is the slave. This interface is
also used to read and write buffered data. All
address and data transfer on the SPI interface
is done most significant bit first.
When CSn goes low, the MCU must wait until
CC2500 SO pin goes low before starting to
transfer the header byte. This indicates that
the voltage regulator has stabilized and the
crystal is running. Unless the chip was in the
SLEEP or XOFF states, the SOpin will always
go low immediately after taking CSnlow.
All transactions on the SPI interface start with
a header byte containing a read/write bit, a
burst access bit and a 6-bit address.
During address and data transfer, the CSnpin
(Chip Select, active low) must be kept low. If
CSn goes high during the access, the transfer
Figure 7 gives a brief overview of different
register access types possible.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 19 of 77
CC2500
tsp
tch
tcl
tsd
thd
tns
SCLK:
CSn:
Write to register:
X
A6
S6
A5
S5
A4
S4
A3
S3
A2
A1
S1
A0
S0
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D 0
W
X
0
W
W
W
W
W
W
W
SI
S7
S2
S7
S6
S5
S4
S3
S2
S1
S0
S7
Hi-Z
Hi-Z
Hi-Z
SO
Read from register:
X
A6
S6
A5
S5
A4
S4
A3
S3
A2
S2
A1
S1
A0
S0
X
1
SI
S7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D 0
R
Hi-Z
R
R
R
R
R
R
R
SO
Figure 6: Configuration registers write and read operations (A6 is the “burst” bit)
Parameter
Description
Min
Max
Units
FSCLK
tsp,pd
tsp
0
10
MHz
SCLKfrequency
TBD
TBD
-
-
µs
CSnlow to positive edge on SCLK, in power-down mode
ns
CSnlow to positive edge on SCLK, in active mode
tch
tcl
Clock high
50
50
-
-
ns
ns
ns
ns
ns
Clock low
-
trise
tfall
tsd
Clock rise time
TBD
TBD
-
Clock rise time
-
TBD
Setup data to positive edge on SCLK
thd
tns
TBD
TBD
-
-
ns
ns
Hold data after positive edge on SCLK
Negative edge on SCLKto CSnhigh.
Table 16: SPI interface timing requirements
CSn:
Command strobe(s):
ADDR
ADDR
ADDR
...
DATA
DATA
strobe
strobe strobe
ADDR
DATA
ADDR
ADDR
reg
DATA
...
Read or write register(s):
reg
reg
ADDR
DATA
DATA
n+1
Read or write consecutive registers (burst):
Read or write n+1 bytes from/to RF FIFO:
Combinations:
...
...
reg n
n
n+2
ADDR
DATA
DATA
DATA
DATA
DATA
byte n
FIFO
byte 0
byte 1
byte 2
byte n-1
ADDR
DATA ADDR
ADDR
DATA ADDR
ADDR
DATA
DATA
byte 1
...
reg
strobe
reg
strobe
FIFO
byte 0
Figure 7: Register access types
10.1 Chip Status Byte
When the header byte, data byte or command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC2500 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYnsignal; this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYnsignal indicates that the crystal is
running and the regulated digital supply
voltage is stable.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 20 of 77
CC2500
The last four bits (3:0) in the status byte con-
tains FIFO_BYTES_AVAILABLE. For read
operations, the FIFO_BYTES_AVAILABLE
field contains the number of bytes available for
reading from the RX FIFO. For write
operations, the FIFO_BYTES_AVAILABLE
field contains the number of bytes free for
Bits 6, 5 and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel
configuration should only be updated when the
chip is in this state. The RX state will be active
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
writing
into
the
TX
FIFO.
When
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 17 gives a status byte summary.
Bits Name
Description
7
CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4
STATE[2:0]
Indicates the current main state machine mode
Value State
Description
000
IDLE
Idle state
(Also reported for some transitional states instead
of SETTLING or CALIBRATE)
001
010
011
RX
Receive mode
Transmit mode
TX
FSTXON
Frequency synthesizer is on, ready to start
transmitting
100
101
110
CALIBRATE
Frequency synthesizer calibration is running
PLL is settling
SETTLING
RXFIFO_OVERFLOW
RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX
111
TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with
SFTX
3:0
FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO
(depends on the read/write-bit). If FIFO_BYTES_AVAILABLE=15, there are 15 or
more bytes in RX FIFO or 49 or less bytes in the TX FIFO.
Table 17: Status byte summary
10.2 Register Access
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit in the address header. The address
sets the start address in an internal address
counter. This counter is incremented by one
each new byte (every 8 clock pulses). The
burst access is either a read or a write access
and must be terminated by setting CSnhigh.
The configuration registers of the CC2500 are
located on SPI addresses from 0x00to 0x2F.
Table 35 on page 51 lists all configuration
registers. The detailed description of each
register is found in Section 31.1, starting on
page 54. All configuration registers can be
both written to and read. The read/write bit
controls if the register should be written to or
read. When writing to registers, the status byte
is sent on the SOpin each time a header byte
or data byte is transmitted on the SI pin.
When reading from registers, the status byte is
sent on the SOpin each time a header byte is
transmitted on the SIpin.
For register addresses in the range 0x30-
0x3D, the “burst” bit is used to select between
status registers and command strobes (see
below). The status registers can only be read.
Burst read is not available for status registers,
so they must be read one at a time.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 21 of 77
CC2500
10.3 Command Strobes
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free before writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted to the SI pin, the status
byte received concurrently on the SO pin will
indicate that one byte is free in the TX FIFO.
Command Strobes may be viewed as single
byte instructions to CC2500. By addressing a
Command Strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 14
command strobes are listed in Table 34 on
page 50.
The transmit FIFO may be flushed by issuing a
SFTX command strobe. Similarly, a SFRX
command strobe will flush the receive FIFO. A
SFTX or SFRX command strobe can only be
issued in the IDLE, TXFIFO_UNDERLOW or
RXFIFO_OVERFLOW state. Both FIFOs are
flushed when going to the SLEEP state.
The command strobe registers are accessed
in the same way as for a register write
operation, but no data is transferred. That is,
only the R/W bit (set to 0), burst access (set to
0) and the six address bits (in the range 0x30
through 0x3D) are written. A command strobe
may be followed by any other SPI access
without pulling CSn high. The command
strobes are executed immediately, with the
exception of the SPWDand the SXOFFstrobes
that are executed when CSngoes high.
10.5 PATABLE Access
The 0x3E address is used to access the
PATABLE, which is used for selecting PA
power control settings. The SPI expects up to
eight data bytes after receiving the address.
By programming the PATABLE, controlled PA
power ramp-up and ramp-down can be
achieved. See Section 0 on page 40 for output
power programming details.
When writing command strobes, the status
byte is sent on the SOpin.
10.4 FIFO Access
The PATABLE is an 8-byte table that defines
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit
value FREND0.PA_POWER). The table is
written and read from the lowest setting (0) to
the highest (7), one byte at a time. An index
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts
at zero.
The 64-byte TX FIFO and the 64-byte RX
FIFO are accessed through the 0x3F address.
When the read/write bit is zero, the TX FIFO is
accessed, and the RX FIFO is accessed when
the read/write bit is one.
The TX FIFO is write-only, while the RX FIFO
is read-only.
The burst bit is used to determine if FIFO
access is single byte or a burst access. The
single byte access method expects address
with burst bit set to zero and one data byte.
After the data byte a new address is expected;
hence, CSncan remain low. The burst access
method expects one address byte and then
consecutive data bytes until terminating the
access by setting CSnhigh.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The read/write bit controls whether
the access is a write access (R/W=0) or a read
access (R/W=1).
The following header bytes access the FIFOs:
•
•
•
•
0x3F: Single byte access to TX FIFO
0x7F: Burst access to TX FIFO
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
0xBF: Single byte access to RX FIFO
0xFF: Burst access to RX FIFO
Note that the content of the PATABLE is lost
when entering the SLEEP state, except for the
first byte (index 0).
When writing to the TX FIFO, the status byte
(see Section 10.1) is output for each new data
byte on SO, as shown in Figure 6. This status
byte can be used to detect TX FIFO underflow
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 22 of 77
CC2500
11 Microcontroller Interface and Pin Configuration
IDLE state, the PTEST register should be
restored to its default value (0x7F).
In a typical system, CC2500 will interface to a
microcontroller. This microcontroller must be
able to:
• Program CC2500 into different modes,
• Read and write buffered data
11.3 Optional Radio Control Feature
The CC2500 has an optional way of controlling
the radio, by reusing SI, SCLK and CSn from
the SPI interface. This feature allows for a
simple three-pin control of the major states of
the radio: SLEEP, IDLE, RX and TX.
• Read back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLKand CSn).
This optional functionality is enabled with the
MCSM0.PIN_CTRL_ENconfiguration bit.
11.1 Configuration Interface
The microcontroller uses four I/O pins for the
SPI configuration interface (SI, SO, SCLK and
CSn). The SPI is described in Section 10 on
page 19.
State changes are commanded as follows:
When CSn is high the SI and SCLK is set to
the desired state according to Table 18. When
CSn goes low the state of SI and SCLK is
latched and a command strobe is generated
internally according to the control coding. It is
only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SIand SCLKare set to
RX and CSntoggles. When CSnis low the SI
and SCLKhas normal SPI functionality.
11.2 General Control and Status Pins
The CC2500 has two dedicated configurable
pins and one shared pin that can output
internal status information useful for control
software. These pins can be used to generate
interrupts on the MCU. See Section 28 on
page 45 for more details on the signals that
can be programmed. The dedicated pins are
called GDO0 and GDO2. The shared pin is the
SOpin in the SPI interface. The default setting
for GDO1/SO is 3-state output. By selecting
any other of the programming options the
GDO1/SOpin will become a generic pin. When
CSn is low, the pin will always function as a
normal SOpin.
All pin control command strobes are executed
immediately, except the SPWDstrobe, which is
delayed until CSngoes high.
CSn SCLK SI
Function
Chip unaffected by
SCLK/SI
1
X
X
0
0
1
1
0
1
Generates SPWDstrobe
Generates STXstrobe
Generates SIDLEstrobe
Generates SRXstrobe
SPI mode (wakes up into
↓
↓
↓
↓
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX
data input pin while in transmit mode.
0
1
SPI
mode
SPI
0
The GDO0pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0pin with an external ADC,
mode IDLE if in SLEEP/XOFF)
Table 18: Optional pin control coding
the
temperature
can
be
calculated.
Specifications for the temperature sensor are
found in Section 4.7 on page 12.
The temperature sensor output is only
available when the frequency synthesizer is
enabled (e.g. the MANCAL, FSTXON, RX and
TX states). It is necessary to write 0xBF to the
PTEST register to use the analog temperature
sensor in the IDLE state. Before leaving the
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 23 of 77
CC2500
12 Data Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
The data rate can be set from 1.2 kbps to 500
kbps with the minimum step size of:
by
the
MDMCFG3.DRATE_M
and
the
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
Data rate
start
Typical
data rate
Data rate
stop
Data rate
step size
0.8 kbps
1.2/2.4
kbps
3.17 kbps
0.0062 kbps
(
256 + DRATE _ M
)
⋅ 2DRATE _ E
RDATA
=
⋅ fXOSC
3.17 kbps
6.35 kbps
12.7 kbps
25.4 kbps
50.8 kbps
101.6 kbps
203.1 kbps
406.3 kbps
4.8 kbps
9.6 kbps
6.35 kbps
12.7 kbps
25.4 kbps
50.8 kbps
101.6 kbps
203.1 kbps
406.3 kbps
500 kbps
0.0124 kbps
0.0248 kbps
0.0496 kbps
0.0992 kbps
0.1984 kbps
0.3967 kbps
0.7935 kbps
1.5869 kbps
228
19.6 kbps
38.4 kbps
76.8 kbps
153.6 kbps
250 kbps
500 kbps
The following approach can be used to find
suitable values for a given data rate:
RDATA ⋅ 220
⎢
⎥
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
DRATE _ E = log
⎢
2
fXOSC
⎢
⎣
⎥
⎦
RDATA ⋅ 228
fXOSC ⋅ 2DRATE _ E
DRATE _ M =
− 256
Table 19: Data rate step size
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
use DRATE_M=0.
13 Receiver Channel Filter Bandwidth
In order to meet different channel width
requirements, the receiver channel filter is
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers
control the receiver channel filter bandwidth,
which scales with the crystal oscillator
frequency. The following formula gives the
relation between the register settings and the
channel filter bandwidth:
MDMCFG4.
MDMCFG4.CHANBW_E
00 01 10 11
812 406 203 102
CHANBW_M
00
01
10
11
650 325 162
541 270 135
464 232 116
81
68
58
Table 20: Channel filter bandwidths [kHz]
(assuming a 26 MHz crystal)
fXOSC
BWchannel
=
8⋅(4 + CHANBW_ M )·2CHANBW_ E
Above 300 kHz bandwidth, however, the
sensitivity and blocking performance may be
somewhat degraded. For best performance,
the channel filter bandwidth should be
selected so that the signal bandwidth occupies
at most 80% of the channel filter bandwidth.
The channel centre tolerance due to crystal
accuracy should also be subtracted from the
signal bandwidth. The following example
illustrates this:
The CC2500 supports the following channel
filter bandwidths:
With the channel filter bandwidth set to 600
kHz, the signal should stay within 80% of 600
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 24 of 77
CC2500
kHz, which is 480 kHz. Assuming 2.44 GHz
frequency and ±20 ppm frequency uncertainty
for both the transmitting device and the
receiving device, the total frequency
uncertainty is ±40 ppm of 2.44 GHz, which is
±98 kHz. If the whole transmitted signal
bandwidth is to be received within 480 kHz,
the transmitted signal bandwidth should be
maximum 480 kHz–2·98 kHz, which is 284
kHz.
14 Demodulator, Symbol Synchronizer and Data Decision
14.3 Byte Synchronization
Byte synchronization is achieved by
CC2500 contains an advanced and highly
configurable demodulator. Channel filtering
and frequency offset compensation is
performed digitally. To generate the RSSI level
(see Section 17.3 for more information) the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
a
continuous sync word search. The sync word
is a 16 or 32 bit configurable field that is
automatically inserted at the start of the packet
by the modulator in transmit mode. The
demodulator uses this field to find the byte
boundaries in the stream of bits. The sync
word will also function as a system identifier,
since only packets with the correct predefined
sync word will be received. The sync word
detector correlates against the user-configured
16-bit sync word. The correlation threshold
can be set to 15/16 bits match or 16/16 bits
match. The sync word can be further qualified
14.1 Frequency Offset Compensation
When using FSK, GFSK or MSK modulation,
the demodulator will compensate for the offset
between the transmitter and receiver
frequency, within certain limits, by estimating
the centre of the received data. This value is
available in the FREQEST status register.
Writing the value from FREQEST into
using
the
preamble
quality
indicator
mechanism described below and/or a carrier
sense condition. The sync word is
programmed with SYNC1and SYNC0.
FSCTRL0.FREQOFF
synthesizer is
the
frequency
adjusted
automatically
In order to make false detections of sync
according to the estimated frequency offset.
words less likely,
a
mechanism called
Note that frequency offset compensation is not
supported for OOK modulation.
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
See Section 17.2 on page 30 for more details.
14.2 Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 12 on
page 24. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.
15 Packet Handling Hardware Support
The CC2500 has built-in hardware support for
•
A two byte Synchronization Word. Can be
duplicated to give a 4-byte sync word.
(Recommended).
Optionally whiten the data with a PN9
sequence.
Optionally Interleave and Forward Error
Code the data.
Optionally compute and add a CRC
checksum over the data field.
packet oriented radio protocols.
In transmit mode, the packet handler will add
the following elements to the packet stored in
the TX FIFO:
•
•
•
•
A programmable number of preamble
bytes. 4 preamble bytes is recommended.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 25 of 77
CC2500
In receive mode, the packet handling support
will de-construct the data packet:
Setting PKTCTRL0.WHITE_DATA=1 is recom-
mended for all uses, except when over-the-air
compatibility with other systems is needed.
•
•
•
•
•
Preamble detection.
Sync word detection.
15.2 Packet Format
Optional one byte address check.
Optionally compute and check CRC.
Optionally append two status bytes (see
Table 21 and Table 22) with RSSI value,
Link Quality Indication and CRC status.
The format of the data packet can be
configured and consists of the following items:
•
•
•
Preamble
Synchronization word
Length byte or constant programmable
packet length
Bit
Field name
Description
•
•
•
Optional address byte
Payload
Optional 2 byte CRC
7:0
RSSI
RSSI value
Table 21: Received packet status byte 1
(first byte appended after the data)
The preamble pattern is an alternating
sequence of ones and zeros (01010101…).
The minimum length of the preamble is
programmable. When enabling TX, the
modulator will start transmitting the preamble.
When the programmed number of preamble
bytes has been transmitted, the modulator will
send the sync word and then data from the TX
FIFO if data is available. If the TX FIFO is
empty, the modulator will continue to send
preamble bytes until the first byte is written to
the TX FIFO. The modulator will then send the
sync word and then the data bytes. The
number of preamble bytes is programmed with
the MDMCFG1.NUM_PREAMBLEvalue.
Bit
Field name
Description
7
CRC_OK
1: CRC for received data OK (or
CRC disabled)
0: CRC error in received data
6:0
LQI
The Link Quality Indicator
estimates how easily a received
signal can be demodulated
Table 22: Received packet status byte 2
(second byte appended after the data)
Note that register fields that control the packet
handling features should only be altered when
CC2500 is in the IDLE state.
The synchronization word is a two-byte value
set in the SYNC1 and SYNC0 registers. The
sync word provides byte synchronization of the
incoming packet. A one-byte sync word can be
emulated by setting the SYNC1 value to the
preamble pattern. It is also possible to emulate
15.1 Data Whitening
From a radio perspective, the ideal over the air
data are random and DC free. This results in
the smoothest power distribution over the
occupied bandwidth. This also gives the
regulation loops in the receiver uniform
operation conditions (no data dependencies).
a
32
bit
sync
word
by
using
MDMCFG2.SYNC_MODE=3 or 7. The sync word
will then be repeated twice.
CC2500 supports both fixed packet length
protocols and variable packet length protocols.
Variable or fixed packet length mode can be
used for packet up to 255 bytes. For longer
packets, infinite packet length mode must be
used.
Real world data often contain long sequences
of zeros and ones. Performance can then be
improved by whitening the data before
transmitting, and de-whitening in the receiver.
With CC2500, this can be done automatically
by setting PKTCTRL0.WHITE_DATA=1. All
data, except the preamble and the sync word,
are then XOR-ed with a 9-bit pseudo-random
(PN9) sequence before being transmitted. At
the receiver end, the data are XOR-ed with the
same pseudo-random sequence. This way, the
whitening is reversed, and the original data
appear in the receiver.
Fixed packet length mode is selected by
setting PKTCTRL0.LENGTH_CONFIG=0. The
desired packet length is set by the PKTLEN
register. The packet length is defined as the
payload data, excluding the length byte and
the optional automatic CRC. In variable length
mode, PKTCTRL0.LENGTH_CONFIG=1, the
packet length is configured by the first byte
after the sync word. The PKTLEN register is
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 26 of 77
CC2500
used to set the maximum packet length
allowed in RX. Any packet received with a
length byte with a value greater than PKTLEN
will be discarded.
By utilizing the infinite packet length option,
arbitrary packet length is available. At the start
of the packet, the infinite mode must be active.
When less than 256 bytes remains of the
packet, the MCU sets the PKTLEN register to
mod(length, 256), disables infinite packet
length and activates fixed length packets.
When the internal byte counter reaches the
PKTLEN value, the transmission or reception
ends. Automatic CRC appending/checking can
be used (by setting PKTCTRL0.CRC_ENto 1).
With PKTCTRL0.LENGTH_CONFIG=2, the
packet length is set to infinite and transmission
and reception will continue until turned off
manually. The infinite mode can be turned off
while a packet is being transmitted or received.
As described in the next section, this can be
used to support packet formats with different
length configuration than natively supported by
CC2500.
When for example a 454-byte packet is to be
transmitted, the MCU does the following:
•
•
Set PKTCTRL0.LENGTH_CONFIG=2 (10).
15.2.1 Arbitrary Length Field Configuration
Pre-program the PKTLEN register to
mod(454,256)=198.
The fixed length field can be reprogrammed
during receive and transmit. This opens the
possibility to have a different length field
configuration than supported for variable
length packets. At the start of reception, the
packet length is set to a large value. The MCU
reads out enough bytes to interpret the length
field in the packet. Then the PKTLEN value is
set according to this value. The end of packet
will occur when the byte counter in the packet
handler is equal to the PKTLEN register. Thus,
the MCU must be able to program the correct
length, before the internal counter reaches the
packet length.
•
Transmit at least 198 bytes, for example
by filling the 64-byte TX FIFO four times
(256 bytes transmitted).
•
•
Set PKTCTRL0.LENGTH_CONFIG=0 (00).
The transmission ends when the packet
counter reaches 198.
A
total of
256+198=454 bytes are transmitted.
Optional data whitening
Legend:
Optionally FEC encoded/decoded
Optional CRC-16 calculation
Inserted automatically in TX,
processed and removed in RX.
Optional user-provided fields processed in TX,
processed but not removed in RX.
Preamble bits
(1010...1010)
Data field
Unprocessed user data (apart from FEC
and/or whitening)
8
8
8 x n bits
16/32 bits
8 x n bits
16 bits
bits bits
Figure 8: Packet format
15.3 Packet Filtering in Receive Mode
0xFF
broadcast
addresses
when
PKTCTRL1.ADR_CHK=11. If the received
address matches a valid address, the packet is
received and written into the RX FIFO. If the
address match fails, the packet is discarded
and receive mode restarted (regardless of the
MCSM1.RXOFF_MODEsetting).
CC2500 supports three different packet-filtering
criteria: address filtering, maximum length
filtering and CRC filtering.
15.3.1 Adress Filtering
Setting PKTCTRL1.ADR_CHK to any other
value than zero enables the packet address
filter. The packet handler engine will compare
the destination address byte in the packet with
the programmed node address in the ADDR
register and the 0x00 broadcast address when
PKTCTRL1.ADR_CHK=10 or both 0x00 and
15.3.2 Maximum Length Filtering
In the variable packet length mode the
PKTLEN.PACKET_LENGTH register value is
used to set the maximum allowed packet
length. If the received length byte has a larger
value than this, the packet is discarded and
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 27 of 77
CC2500
receive mode restarted (regardless of the
15.5 Packet Handling in Transmit Mode
MCSM1.RXOFF_MODEsetting).
The payload that is to be transmitted must be
written into the TX FIFO. The first byte written
must be the length byte when variable packet
length is enabled. The length byte has a value
equal to the payload of the packet (including
the optional address byte). If fixed packet
length is enabled, then the first byte written to
the TX FIFO is interpreted as the destination
address, if this feature is enabled in the device
that receives the packet.
15.3.3 CRC Filtering
The filtering of a packet when CRC check fails
is enabled with PKTCTRL1.CRC_AUTOFLUSH.
The CRC auto flush function will flush the
entire RX FIFO if the CRC check fails. After
auto flushing the RX FIFO, the next state
depends on the MCSM1.RXOFF_MODEsetting.
When using the auto flush function, the
maximum packet length is 63 bytes in variable
packet length mode and 64 bytes in fixed
packet length mode. Note that the maximum
allowed packet length is reduced by two bytes
The modulator will first send the programmed
number of preamble bytes. If data is available
in the TX FIFO, the modulator will send the
two-byte (optionally 4-byte) sync word and
then the payload in the TX FIFO. If CRC is
enabled, the checksum is calculated over all
the data pulled from the TX FIFO and the
result is sent as two extra bytes at the end of
the payload data.
when
PKTCTRL1.APPEND_STATUS
is
enabled, to make room in the RX FIFO for the
two status bytes appended at the end of the
packet. Since the entire RX FIFO is flushed
when the CRC check fails, the previously
received packet must be read out of the FIFO
before receiving the current packet. The MCU
must not read from the current packet until the
CRC has been checked as OK.
If whitening is enabled, the length byte,
payload data and the two CRC bytes will be
whitened. This is done before the optional
FEC/Interleaver stage. Whitening is enabled
by setting PKTCTRL0.WHITE_DATA=1.
15.4 CRC Check
If FEC/Interleaving is enabled, the length byte,
payload data and the two CRC bytes will be
scrambled by the interleaver, and FEC
encoded before being modulated.
It is possible to read back the CRC status in 2
different ways:
1) Set PKTCTRL1.APPEND_STATUS=1 and
read the CRC_OK flag in the MSB of the
second byte appended to the RX FIFO after
the packet data. This requires double buffering
of the packet, i.e. the entire packet content of
the RX FIFO must be completely read out
before it is possible to check whether the CRC
indication is OK or not.
15.6 Packet Handling in Receive Mode
In receive mode, the demodulator and packet
handler will search for a valid preamble and
the sync word. When found, the demodulator
has obtained both bit and byte synchronism
and will receive the first payload byte.
2) To avoid reading the whole RX FIFO,
If FEC/Interleaving is enabled, the FEC
decoder will start to decode the first payload
byte. The interleaver will de-scramble the bits
before any other processing is done to the
data.
another
solution
is
to
use
the
PKTCTRL1.CRC_AUTOFLUSH feature. If this
feature is enabled, the entire RX FIFO will be
flushed if the CRC check fails. If
GDOx_CFG=0x06 the GDOx pin will be
asserted when a sync word is found. The
GDOx pin will be de-asserted at the end of the
packet. When the latter occurs the MCU
should read the number of bytes in the RX
FIFO from the RXBYTES.NUM_RXBYTES
status register. If RXBYTES.NUM_RXBYTES=0
the CRC check failed and the FIFO was
flushed. If RXBYTES.NUM_RXBYTES>0 the
CRC check was OK and data can be read out
of the FIFO.
If whitening is enabled, the data will be de-
whitened at this stage.
When variable packet length is enabled, the
first byte is the length byte. The packet handler
stores this value as the packet length and
receives the number of bytes indicated by the
length byte. If fixed packet length is used, the
packet handler will accept the programmed
number of bytes.
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 28 of 77
CC2500
enabled, the packet handler computes CRC
and matches it with the appended CRC
checksum.
At the end of the payload, the packet handler
will optionally write two extra packet status
bytes that contain CRC status, link quality
indication and RSSI value.
16 Modulation Formats
16.2 Minimum Shift Keying
CC2500 supports amplitude, frequency and
phase shift modulation formats. The desired
When using MSK1, the complete transmission
(preamble, sync word and payload) will be
MSK modulated.
modulation
format
is
set
in
the
MDMCFG2.MOD_FORMAT register.
Optionally, the data stream can be Manchester
coded by the modulator and decoded by the
demodulator. This option is enabled by setting
Phase shifts are performed with a constant
transition time. This means that the rate of
change for the 180-degree transition is twice
that of the 90-degree transition.
MDMCFG2.MANCHESTER_EN=1.
Manchester
encoding is not supported at the same time as
using the FEC/Interleaver option. Manchester
coding can be used with the 2-ary modulation
formats (2-FSK, GFSK, OOK and MSK).
The fraction of a symbol period used to
change the phase can be modified with the
DEVIATN.DEVIATION_M setting. This is
equivalent to changing the shaping of the
symbol. Setting DEVIATN.DEVIATION_M=7
will generate a standard shaped MSK signal.
16.1 Frequency Shift Keying
2-FSK can optionally be shaped by
Gaussian filter with BT=1, producing a GFSK
modulated signal.
a
The MSK modulation format implemented in
CC2500
inverts the sync word and data
compared to e.g. signal generators.
The frequency deviation is programmed with
the DEVIATION_M and DEVIATION_E values
in the DEVIATN register. The value has an
exponent/mantissa form, and the resultant
deviation is given by:
16.3 Amplitude Modulation
The supported amplitude modulation On-Off
Keying (OOK) simply turns on or off the PA to
modulate 1 and 0 respectively.
fxosc
fdev
=
⋅(8 + DEVIATION _ M )⋅2DEVIATION _ E
217
1
Identical to offset QPSK with half-sine
shaping (data coding may differ)
The symbol encoding is shown in Table 23.
Format
Symbol
Coding
2-FSK/GFSK
‘0’
‘1’
– Deviation
+ Deviation
Table 23: Symbol encoding for FSK
modulation
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 29 of 77
CC2500
17 Received Signal Qualifiers and Link Quality Information
PKTCTRL1.PQT. A threshold of 4·PQT for this
counter is used to gate sync word detection.
By setting the value to zero, the preamble
quality qualifier of the sync word is disabled.
CC2500 has several qualifiers that can be used
to increase the likelihood that a valid sync
word is detected.
A “Preamble Quality Reached” flag can also
be observed on one of the GDO pins and in
17.1 Sync Word Qualifier
If sync word detection in RX is enabled in
register MDMCFG2 the CC2500 will not start
filling the RX FIFO and perform the packet
filtering described in Section 15.3 before a
valid sync word has been detected. The sync
the
status
register
bit
PKTSTATUS.PQT_REACHED. This flag asserts
when the received signal exceeds the PQT.
17.3 RSSI
word
qualifier
mode
is
set
by
MDMCFG2.SYNC_MODE and is summarized in
Table 24. Carrier sense in Table 24 is
described in Section 17.4.
The RSSI value is an estimate of the signal
level in the current channel. This value is
based on the current gain setting in the RX
chain and the measured signal level in the
channel.
MDMCFG2.
Sync word qualifier mode
In RX mode, the RSSI value can be read
continuously from the RSSI status register,
until the demodulator detects a sync word
(when sync word detection is enabled). At that
point, the RSSI readout value is frozen until
the next time the chip enters the RX state. The
RSSI value is in dB with ½dB resolution.
SYNC_MODE
000
001
010
011
100
No preamble/sync
15/16 sync word bits detected
16/16 sync word bits detected
30/32 sync word bits detected
No preamble/sync, carrier sense
above threshold
If PKTCTRL1.APPEND_STATUS is enabled, a
snapshot of the RSSI during the first 8 bytes of
the packet is automatically added to the end of
each received packet.
101
110
111
15/16 + carrier sense above threshold
16/16 + carrier sense above threshold
30/32 + carrier sense above threshold
The RSSI value read from the RSSI status
register is a 2’s complement number. The
following procedure can be used to convert the
RSSI reading to an absolute power level
(RSSI_dBm).
Table 24: Sync word qualifier mode
17.2 Preamble Quality Threshold (PQT)
1) Read the RSSI status register
The Preamble Quality Threshold (PQT) sync-
word qualifier adds the requirement that the
received sync word must be preceded with a
preamble with a quality above a programmed
threshold.
2) Convert the reading from a hexadecimal
number to a decimal number (RSSI_dec)
3) If RSSI_dec ≥ 128 then RSSI_dBm =
(RSSI_dec - 256)/2 – RSSI_offset
Another use of the preamble quality threshold
is as a qualifier for the optional RX termination
timer. See Section 19.7 on page 37 for details.
4) Else if RSSI_dec < 128 then RSSI_dBm =
(RSSI_dec)/2 – RSSI_offset
The preamble quality estimator increases an
internal counter by one each time a bit is
received that is different from the previous bit,
and decreases the counter by 4 each time a
bit is received that is the same as the last bit.
The counter saturates at 0 and 31. The
threshold is configured with the register field
Table 25 gives typical values for the
RSSI_offset.
Figure 9 shows typical plots of RSSI reading
as a function of input power level for different
data rates.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 30 of 77
CC2500
Data rate
2.4 kbps
10 kbps
RSSI_offset (decimal)
71
69
72
72
250 kbps
500 kbps
Table 25: Typical RSSI_offset values
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
-110.0
-120.0
-120 -110 -100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input power [dBm]
2.4 kbps
10 kbps
250 kbps
250 kbps, reduced current
500 kbps
Figure 9: Typical RSSI value vs. input power level for some typical data rates
17.4 Carrier Sense (CS)
search to be performed. The signal can also
be observed on one of the GDO pins and in
the status register bit PKTSTATUS.CS.
The Carrier Sense flag is used as a sync word
qualifier and for CCA. The CS flag can be set
based on two conditions, which can be
individually adjusted:
Other uses of Carrier Sense include the TX-If-
CCA function (see Section 17.5 on page 32)
and the optional fast RX termination (see
Section 19.7 on page 37).
•
CS is asserted when the RSSI is above a
programmable absolute threshold, and de-
asserted when RSSI is below the same
threshold (with hysteresis).
CS can be used to avoid interference from e.g.
WLAN.
•
CS is asserted when the RSSI has
increased with a programmable number of
dB from one RSSI sample to the next, and
de-asserted when RSSI has decreased
with the same number of dB. This setting
is not dependent on the absolute signal
level and is thus useful to detect signals in
environments with a time varying noise
floor.
17.4.1 CS Absolute Threshold
The absolute threshold related to the RSSI
value is given by:
THRRSSI = MAGN _TARGET +
CARRIER _ SENSE _ ABS _THR −GAINMAX
The maximum possible gain can be reduced
using the AGCCTRL2.MAX_LNA_GAIN and
AGCCTRL2.MAX_DVGA_GAIN register fields.
CARRIER_SENSE_ABS_THR is programmable
in 1 dB steps from -7 dB to + 7dB. Table 26
and Table 27 show the RSSI readout values
Carrier Sense (CS) can be used as a sync
word qualifier that requires the signal level to
be higher than the threshold for a sync word
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 31 of 77
CC2500
at the CS threshold at 2.4 kbps and 250 kbps
data rate respectively. The default
CARRIER_SENSE_ABS_THR = 0 (0 dB) and
MAGN_TARGET = 3 (33 dB) have been used.
level in the channel into the demodulator.
Increasing this value reduces the headroom
for blockers, and therefore close-in selectivity.
17.4.2 CS relative threshold
The relative threshold detects sudden changes
in the measured signal level. This setting is not
dependent on the absolute signal level and is
thus useful to detect signals in environments
with a time varying noise floor. The register
field AGCCTRL1.CARRIER_SENSE_REL_THR
is used to enable/disable relative CS, and to
select threshold of 6 dB, 10 dB or 14 dB RSSI
change
MAX_DVGA_GAIN[1:0]
00
-99
-97
01
-93
10
11
-81.5
-78.5
-76
000
001
-87
-85
-82
-80
-78
-76
-73
-70
-90.5
-87
010 -93.5
011 -91.5
100 -90.5
-86
-74
-84
-72.5
-70
101
-88
-82.5
17.5 Clear Channel Assessment (CCA)
110 -84.5 -78.5
111 -82.5 -76
-67
The Clear Channel Assessment is used to
indicate if the current channel is free or busy.
The current CCA state is viewable on any of
the GDO pins.
-64
Table 26: Typical RSSI value in dBm at CS
threshold with default MAGN_TARGET at 2.4
kbps
MCSM1.CCA_MODE selects the mode to use
when determining CCA.
When the STXor SFSTXONcommand strobe is
given while CC2500 is in the RX state, the TX
state is only entered if the clear channel
requirements are fulfilled. The chip will
otherwise remain in RX. This feature is called
TX if CCA.
MAX_DVGA_GAIN[1:0]
00
01
10
-84
11
-78.5
-77.5
-75
000
-96
-90
-89
-87
-85
-82
001 -94.5
010 -92.5
-83
-81
Four CCA requirements can be programmed:
011
-91
-78.5
-76
-73
•
•
•
•
Always (CCA disabled, always goes to TX)
If RSSI is below threshold
100 -87.5
-70
101
110
111
-85
-83
-78
-79.5 -73.5 -67.5
Unless currently receiving a packet
-76.5 -70.5
-72 -66
-65
-60
Both the above (RSSI below threshold and
not currently receiving a packet)
Table 27: Typical RSSI value in dBm at CS
threshold with default MAGN_TARGET at
250 kbps
17.6 Link Quality Indicator (LQI)
The Link Quality Indicator is a metric of the
current quality of the received signal. If
PKTCTRL1.APPEND_STATUS is enabled, the
value is automatically appended to the end of
each received packet. The value can also be
read from the LQI status register. The LQI is
calculated over the 64 symbols following the
sync word (first 8 packet bytes for 2-ary
modulation). LQI is best used as a relative
measurement of the link quality, since the
value is dependent on the modulation format.
If the threshold is to be set high, e.g. only
signals with good strength are wanted, the
threshold should be adjusted upwards by first
reducing the MAX_LNA_GAIN value and then
the MAX_DVGA_GAIN value. This will reduce
power consumption in the receiver front end,
since the highest gain settings are avoided.
The MAGN_TARGET setting is a compromise
between blocker tolerance/selectivity and
sensitivity. The value sets the desired signal
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 32 of 77
CC2500
18 Forward Error Correction with Interleaving
18.1 Forward Error Correction (FEC)
18.2 Interleaving
Data received through radio channels will
often experience burst errors due to
interference and time-varying signal strengths.
In order to increase the robustness to errors
spanning multiple bits, interleaving is used
when FEC is enabled. After de-interleaving, a
continuous span of errors in the received
stream will become single errors spread apart.
CC2500 has built in support for Forward Error
Correction (FEC). To enable this option, set
MDMCFG1.FEC_EN to 1. FEC is employed on
the data field and CRC word in order to reduce
the gross bit error rate when operating near
the sensitivity limit. Redundancy is added to
the transmitted data in such a way that the
receiver can restore the original data in the
presence of some bit errors.
CC2500 employs matrix interleaving, which is
illustrated in Figure 10. The on-chip
interleaving and de-interleaving buffers are 4 x
4 matrices. In the transmitter, the data bits are
written into the rows of the matrix, whereas the
bit sequence to be transmitted is read from the
columns of the matrix and fed to the rate ½
convolutional coder. Conversely, in the
receiver, the received symbols are written into
the columns of the matrix, whereas the data
passed onto the convolutional decoder is read
from the rows of the matrix.
The use of FEC allows correct reception at a
lower SNR, thus extending communication
range. Alternatively, for a given SNR, using
FEC decreases the bit error rate (BER). As the
packet error rate (PER) is related to BER by:
PER = 1− (1− BER)packet _ length
a lower BER can be used to allow longer
packets, or a higher percentage of packets of
a given length, to be transmitted successfully.
Finally, in realistic ISM radio environments,
transient and time-varying phenomena will
produce occasional errors even in otherwise
good reception conditions. FEC will mask such
errors and, combined with interleaving of the
coded data, even correct relatively long
periods of faulty reception (burst errors).
When FEC and interleaving is used, the
amount of data transmitted over the air must
be a multiple of the size of the interleaver
buffer (two bytes). In addition, at least one
extra byte is required for trellis termination.
The packet control hardware therefore
automatically inserts one or two extra bytes at
the end of the packet, so that the total length
of the data to be interleaved is an even
number. Note that these extra bytes are
invisible to the user, as they are removed
before the received packet enters the RX
FIFO.
The FEC scheme adopted for CC2500 is
convolutional coding, in which n bits are
generated based on k input bits and the m
most recent input bits, forming a code stream
able to withstand a certain number of bit errors
between each coding state (the m-bit window).
The convolutional coder is a rate 1/2 code with
a constraint length of m=4. The coder codes
one input bit and produces two output bits;
hence, the effective data rate is halved.
Due to the implementation of the FEC and
interleaver, the data to be interleaved must be
at least two bytes. One byte long fixed length
packets without CRC is therefore not
supported when FEC/interleaving is enabled.
1) Storing coded
data
2) Transmitting
interleaved data
3) Receiving
interleaved data
4) Passing on data
to decoder
TX
RX
Data
Data
Transmitter
Receiver
Figure 10: General principle of matrix interleaving
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 33 of 77
CC2500
19 Radio Control
SIDLE
SPWD
| SWOR
SLEEP
0
CAL_COMPLETE
MANCAL
3,4,5
IDLE
1
CSn = 0
| WOR
SXOFF
SCAL
CSn = 0
XOFF
2
SRX
| STX | SFSTXON | WOR
FS_WAKEUP
6,7
FS_AUTOCAL = 01
&
SRX
| STX | SFSTXON | WOR
FS_AUTOCAL = 00 | 10 | 11
&
CALIBRATE
8
SRX
| STX | SFSTXON | WOR
CAL_COMPLETE
SETTLING
9,10,11
SFSTXON
FSTXON
18
STX
SRX
| WOR
STX
SFSTXON
|
RXOFF_MODE = 01
TXOFF_MODE=01
RXTX_SETTLING
21
STX
|
RXOFF_MODE = 10
( STX
| SFSTXON ) & CCA
|
RXOFF_MODE = 01 | 10
TX
19,20
RX
13,14,15
TXOFF_MODE = 10
RXOFF_MODE = 11
SRX
| TXOFF_MODE = 11
TXRX_SETTLING
16
RXOFF_MODE = 00
&
FS_AUTOCAL = 10 | 11
TXOFF_MODE = 00
&
FS_AUTOCAL = 10 | 11
TXFIFO_UNDERFLOW
RXFIFO_OVERFLOW
CALIBRATE
12
TXOFF_MODE = 00
RXOFF_MODE = 00
&
FS_AUTOCAL = 00 | 01
&
FS_AUTOCAL = 00 | 01
TX_UNDERFLOW
22
RX_OVERFLOW
17
SFTX
SFRX
IDLE
1
Figure 11: Complete radio control state diagram
shown in Figure 4 on page 13. The complete
radio control state diagram is shown in Figure
11. The numbers refer to the state number
readable in the MARCSTATE status register.
This register is primarily for test purposes.
CC2500 has a built-in state machine that is
used to switch between different operation
states (modes). The change of state is done
either by using command strobes or by
internal events such as TX FIFO underflow.
A simplified state diagram, together with
typical usage and current consumption, is
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 34 of 77
CC2500
19.1 Power-On Start-Up Sequence
XOSC will be turned off when CSnis released
(goes high). The XOSC will be automatically
turned on again when CSngoes low. The state
machine will then go to the IDLE state. The SO
pin on the SPI interface must be zero before
the SPI interface is ready to be used; as
described in Section 19 on page 20.
When the power supply is turned on, the
system must be reset. One of the following two
sequences must be followed: Automatic
power-on reset (POR) or manual reset.
19.1.1 Automatic POR
If the XOSC is forced on, the crystal will
always stay on even in the SLEEP state.
A power-on reset circuit is included in the
CC2500. The minimum requirements stated in
Section 4.9 must be followed for the power-on
reset to function properly. The internal power-
up sequence is completed when CHIP_RDYn
goes low. CHIP_RDYn is observed on the SO
pin after CSn is pulled low. See Section 10.1
for more details on CHIP_RDYn.
Crystal oscillator start-up time depends on
crystal ESR and load capacitances. The
electrical specification for the crystal oscillator
can be found in Section 4.4 on page 10.
19.3 Voltage Regulator Control
The voltage regulator to the digital core is
controlled by the radio controller. When the
chip enters the SLEEP state, which is the state
with the lowest current consumption, this
regulator is disabled. This occurs after CSn is
released when a SPWD command strobe has
been sent on the SPI interface. The chip is
now in the SLEEP state. Setting CSnlow again
will turn on the regulator and crystal oscillator
and make the chip enter the IDLE state.
19.1.2 Manual Reset
The other global reset possibility on CC2500 is
the SRES command strobe. By issuing this
strobe, all internal registers and states are set
to the default, idle state. The manual power-up
sequence is as follows (see Figure 12):
•
Set SCLK=1 and SI=0, to avoid potential
problems with pin control mode (see
Section 11.3 on page 23).
When wake on radio is enabled, the WOR
module will control the voltage regulator as
described in Section 19.5.
•
•
•
Strobe CSnlow / high.
Hold CSnhigh for at least 40 µs.
Pull CSn low and wait for SO to go low
(CHIP_RDYn).
19.4 Active Modes
CC2500 has two active modes: receive and
transmit. These modes are activated directly
by the MCU by using the SRX and STX
command strobes, or automatically by Wake
on Radio.
•
•
Issue the SRESstrobe on the SI line.
When SO goes low again, reset is
complete and the chip is in the IDLE state.
40µs
The frequency synthesizer must be calibrated
regularly. CC2500 has one manual calibration
option (using the SCAL strobe), and three
automatic calibration options, controlled by the
MCSM0.FS_AUTOCALsetting:
CSn
SO
Unknown/ don't care
SRES done
•
•
•
Calibrate when going from IDLE to
either RX or TX (or FSTXON)
Figure 12: Power-on reset with SRES
Calibrate when going from either RX
or TX to IDLE
19.2 Crystal Control
The crystal oscillator (XOSC) is either
automatically controlled or always on, if
MCSM0.XOSC_FORCE_ONis set.
Calibrate every fourth time when going
from either RX or TX to IDLE
The calibration takes a constant number of
XOSC cycles (see Table 28 for timing details).
In the automatic mode, the XOSC will be
turned off if the SXOFF or SPWD command
strobes are issued; the state machine then
goes to XOFF or SLEEP respectively. This
can only be done from the IDLE state. The
When RX is activated, the chip will remain in
receive mode until a packet is successfully
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 35 of 77
CC2500
received or the RX termination timer expires
(see Section 19.7). Note: the probability that a
false sync word is detected can be reduced by
using PQT, CS, maximum sync word length
and sync word qualifier mode as describe in
Section 17. After a packet is successfully
received the radio controller will then go to the
state indicated by the MCSM1.RXOFF_MODE
setting. The possible destinations are:
IDLE state when the timer expires. After a
programmable time in RX, the chip goes back
to SLEEP, unless a packet is received. See
Section 19.7 for details on how the timeout
works.
CC2500 can be set up to signal the MCU that a
packet has been received by using the GDO
pins. If
a
packet is received, the
MCSM1.RXOFF_MODE
will determine the
•
•
IDLE
behaviour at the end of the received packet.
When the MCU has read the packet, it can put
the chip back into SLEEP with the SWORstrobe
from the IDLE state. The FIFO will lose its
contents in the SLEEP state.
FSTXON: Frequency synthesizer on
and ready at the TX frequency.
Activate TX with STX.
•
•
TX: Start sending preambles
The WOR timer has two events, Event 0 and
Event 1. In the SLEEP state with WOR
activated, reaching Event 0 will turn the digital
regulator and start the crystal oscillator. Event
1 follows Event 0 after a programmed timeout.
RX: Start search for a new packet
Similarly, when TX is active the chip will
remain in the TX state until the current packet
has been successfully transmitted. Then the
state will change as indicated by the
MCSM1.TXOFF_MODE setting. The possible
destinations are the same as for RX.
The time between two consecutive Event 0 is
programmed with a mantissa value given by
WOREVT1.EVENT0 and WOREVT0.EVENT0,
and
an
exponent
value
set
by
WORCTRL.WOR_RES. The equation is:
The MCU can manually change the state from
RX to TX and vice versa by using the
command strobes. If the radio controller is
currently in transmit and the SRX strobe is
used, the current transmission will be ended
and the transition to RX will be done.
750
tEvent0
=
⋅ EVENT0⋅ 25⋅WOR _ RES
fXOSC
If the radio controller is in RX when the STX or
SFSTXONcommand strobes are used, the “TX
if clear channel” function will be used. If the
channel is not clear, the chip will remain in RX.
The MCSM1.CCA_MODE setting controls the
conditions for clear channel assessment. See
Section 17.5 on page 32 for details.
The Event 1 timeout is programmed with
WORCTRL.EVENT1. Figure 13 shows the
timing relationship between Event 0 timeout
and Event 1 timeout.
Rx timeout
The SIDLE command strobe can always be
used to force the radio controller to go to the
IDLE state.
State: SLEEP IDLE
RX
Event1
SLEEP
IDLE
RX
Event0
Event0
Event1
t
tEvent0
19.5 Wake On Radio (WOR)
tEvent0
The optional Wake on Radio (WOR)
functionality enables CC2500 to periodically
wake up from deep sleep and listen for
incoming packets without MCU interaction.
tEvent1
tEvent1
Figure 13: Event 0 and Event 1 relationship
When WOR is enabled, the CC2500 will go to
the SLEEP state when CSn is released after
the SWOR command strobe has been sent on
the SPI interface. The RC oscillator must be
enabled before the WOR strobe can be used,
as it is the clock source for the WOR timer.
The on-chip timer will get CC2500 back into the
19.5.1 RC Oscillator and Timing
The frequency of the low-power RC oscillator
used for the WOR functionality varies with
temperature and supply voltage. In order to
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 36 of 77
CC2500
keep the frequency as accurate as possible,
the RC oscillator will be calibrated whenever
possible, which is when the XOSC is running
and the chip is not in the SLEEP state. When
the power and XOSC is enabled, the clock
used by the WOR timer is a divided XOSC
clock. When the chip goes to the sleep state,
the RC oscillator will use the last valid
calibration result. The frequency of the RC
oscillator is locked to the main crystal
frequency divided by 750.
The main use for this functionality is wake-on-
radio (WOR), but it may be useful for other
applications. The termination timer starts when
in RX state. The timeout is programmable with
the MCSM2.RX_TIME setting. When the timer
expires, the radio controller will check the
condition for staying in RX; if the condition is
not met, RX will terminate. After the timeout,
the condition will be checked continuously.
The programmable conditions are:
•
MCSM2.RX_TIME_QUAL=0:
receive if sync word has been found
Continue
19.6 Timing
•
MCSM2.RX_TIME_QUAL=1:
receive if sync word has been found or
preamble quality is above threshold (PQT)
Continue
The radio controller controls most timing in
CC2500, such as synthesizer calibration, PLL
lock and RT/TX turnaround times. Timing from
IDLE to RX and IDLE to TX is constant,
dependent on the auto calibration setting.
RX/TX and TX/RX turnaround times are
constant. The calibration time is constant
18739 clock periods. Table 28 shows timing in
crystal clock cycles for key state transitions.
If the system can expect the transmission to
have started when enabling the receiver, the
MCSM2.RX_TIME_RSSIfunction can be used.
The radio controller will then terminate RX if
the first valid carrier sense sample indicates
no carrier (RSSI below threshold). See Section
17.4 on page 31 for details on Carrier Sense.
Power on time and XOSC start-up times are
variable, but within the limits stated in Table 7.
Note that in a frequency hopping spread
spectrum or a multi-channel protocol the
calibration time can be reduced from 721 µs to
approximately 150 µs. This is explained in
Section 30.2.
For OOK modulation, lack of carrier sense is
only considered valid after eight symbol
periods. Thus, the MCSM2.RX_TIME_RSSI
function can be used in OOK mode when the
distance between “1” symbols is 8 or less.
If RX terminates due to no carrier sense when
the MCSM2.RX_TIME_RSSI function is used,
or if no sync word was found when using the
MCSM2.RX_TIME timeout function, the chip
will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
Otherwise, the MCSM1.RXOFF_MODE setting
determines the state to go to when RX ends.
Description
XOSC
periods
26 MHz
crystal
Idle to RX, no calibration
Idle to RX, with calibration
Idle to TX/FSTXON, no calibration
Idle to TX/FSTXON, with calibration
TX to RX switch
2298
~21037
2298
~21037
560
88.4 µs
809 µs
88.4 µs
809 µs
21.5 µs
9.6 µs
Note that in wake-on-radio (WOR) mode, the
WOR state is cleared in the latter case. This
means that the chip will not automatically go
back to SLEEP again, even if e.g. the address
field in the packet did not match. It is therefore
recommended to always wake up the
microcontroller on sync word detection when
using WOR mode. This can be done by
selecting output signal 6 (see Table 33 on
page 46) on one of the programmable GDO
RX to TX switch
250
RX or TX to IDLE, no calibration
RX or TX to IDLE, with calibration
Manual calibration
2
0.1 µs
~18739
~18739
721 µs
721 µs
Table 28: State transition timing
19.7 RX Termination Timer
output
pins,
and
programming
the
CC2500 has optional functions for automatic
termination of RX after a programmable time.
microcontroller to wake up on an edge-
triggered interrupt from this GDO pin.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 37 of 77
CC2500
20 Data FIFO
the corresponding thresholds for the RX and
TX FIFOs. The threshold value is coded in
opposite directions for the RX FIFO and TX
FIFO. This gives equal margin to the overflow
and underflow conditions when the threshold
is reached.
The CC2500 contains two 64 byte FIFOs, one
for received data and one for data to be
transmitted. The SPI interface is used to read
from the RX FIFO and write to the TX FIFO.
Section 10.4 contains details on the SPI FIFO
access. The FIFO controller will detect
overflow in the RX FIFO and underflow in the
TX FIFO.
A flag will assert when the number of bytes in
the FIFO is equal to or higher than the
programmed threshold. The flag is used to
generate the FIFO status signals that can be
viewed on the GDO pins (see Section 28 on
page 45).
When writing to the TX FIFO it is the
responsibility of the MCU to avoid TX FIFO
overflow. A TX FIFO overflow will result in an
error in the TX FIFO content.
Figure 15 shows the number of bytes in both
the RX FIFO and TX FIFO when the threshold
flag toggles, in the case of FIFO_THR=13.
Figure 14 shows the flag as the respective
FIFO is filled above the threshold, and then
drained below.
Likewise, when reading the RX FIFO the MCU
must avoid reading the RX FIFO past its
empty value, since an RX FIFO underflow will
result in an error in the data read out of the RX
FIFO.
The chip status byte that is available on the SO
pin while transferring the SPI address contains
the fill grade of the RX FIFO if the address is a
read operation and the fill grade of the TX
FIFO is the address is a write operation.
Section 10.1 on page 20 contains more details
on this.
NUM_RXBYTES
53 54 55 56 57 56 55 54 53
GDO
NUM_TXBYTES
6
7
8
9
10
9
8
7
6
GDO
The number of bytes in the RX FIFO and TX
FIFO can also be read from the status
Figure 14: FIFO_THR=13 vs. number of bytes
in FIFO (GDOx_CFG=0x00 in Rx and
GDOx_CFG=0x02 in Tx)
registers
TXBYTES.NUM_TXBYTES
receiving data while reading the last byte in
the RX FIFO, the RX FIFO pointer is not
updated, resulting in a duplication of the last
byte read.
RXBYTES.NUM_RXBYTES
respectively.
and
If
FIFO_THR
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Bytes in TX FIFO
Bytes in RX FIFO
61
57
53
49
45
41
37
33
29
25
21
17
13
9
4
To avoid this problem one should never empty
the RX FIFO before the last byte of the packet
is received. The following software fix can be
used:
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
1. Read RXBYTES.NUM_RXBYTES
2. If RXBYTES.NUM_RXBYTES
<
packet
length, read RXBYTES.NUM_RXBYTES-1
bytes from the FIFO
3. Repeat until RXBYTES.NUM_RXBYTES =
number of remaining bytes of the packet
4. Read the remaining bytes from the FIFO
5
1
The 4-bit FIFOTHR.FIFO_THRsetting is used
to program threshold points in the FIFOs.
Table 29 lists the 16 FIFO_THR settings and
Table 29: FIFO_THRsettings and the
corresponding FIFO thresholds
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 38 of 77
CC2500
Overflow
margin
FIFO_THR=13
56 bytes
FIFO_THR=13
Underflow
margin
8 bytes
RXFIFO
TXFIFO
Figure 15: Example of FIFOs at threshold
21 Frequency Programming
The base or start frequency is set by the 24 bit
frequency word located in the FREQ2, FREQ1
and FREQ0 registers. This word will typically
be set to the centre of the lowest channel
frequency that is to be used.
The frequency programming in CC2500 is
designed to minimize the programming
needed in a channel-oriented system.
To set up a system with channel numbers, the
desired channel spacing is programmed with
the
MDMCFG0.CHANSPC_M
and
The desired channel number is programmed
with the 8-bit channel number register,
CHANNR.CHAN, which is multiplied by the
channel offset. The resultant carrier frequency
is given by:
MDMCFG1.CHANSPC_E registers. The channel
spacing registers are mantissa and exponent
respectively.
fXOSC
216
fcarrier
=
⋅
(
FREQ + CHAN ⋅
(
256 + CHANSPC _ M
)
⋅2CHANSPC _ E−2 ))
Note that the SmartRF® Studio software
automatically calculates the optimum
FSCTRL1.FREQ_IF register setting based on
channel spacing and channel filter bandwidth.
With a 26 MHz crystal the maximum channel
spacing is 405 kHz. To get e.g. 1 MHz channel
spacing one solution is to use 333 kHz
channel spacing and select each third channel
in CHANNR.CHAN.
If any frequency programming register is
altered when the frequency synthesizer is
running, the synthesizer may give an
undesired response. Hence, the frequency
programming should only be updated when
the radio is in the IDLE state.
The preferred IF frequency is programmed
with the FSCTRL1.FREQ_IF register. The IF
frequency is given by:
fXOSC
fIF =
⋅ FREQ _ IF
210
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 39 of 77
CC2500
22 VCO
The VCO is completely integrated on-chip.
The calibration can be initiated automatically
or manually. The synthesizer can be
automatically calibrated each time the
synthesizer is turned on, or each time the
synthesizer is turned off. This is configured
with the MCSM0.FS_AUTOCAL register setting.
In manual mode, the calibration is initiated
when the SCAL command strobe is activated
in the IDLE mode.
22.1 VCO and PLL Self-Calibration
The VCO characteristics will vary with
temperature and supply voltage changes, as
well as the desired operating frequency. In
order to ensure reliable operation, CC2500
includes frequency synthesizer self-calibration
circuitry. This calibration should be done
regularly, and must be performed after turning
on power and before using a new frequency
(or channel). The number of XOSC cycles for
completing the PLL calibration is given in
Table 28 on page 37.
Note that the calibration values are maintained
in sleep mode, so the calibration is still valid
after waking up from sleep mode (unless
supply voltage or temperature has changed
significantly).
23 Voltage Regulators
If the chip is programmed to enter power-down
mode, (SPWDstrobe issued), the power will be
turned off after CSngoes high. The power and
crystal oscillator will be turned on again when
CSngoes low.
CC2500 contains several on-chip linear voltage
regulators, which generate the supply voltage
needed by low-voltage modules. These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that the absolute maximum ratings and
required pin voltages in Table 1 and Table 13
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
The voltage regulator output should only be
used for driving the CC2500.
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before using the serial
interface (setup time is given in Table 16).
24 Output Power Programming
The RF output power level from the device has
two levels of programmability, as illustrated in
Figure 16. Firstly, the special PATABLE
register can hold up to eight user selected
output power settings. Secondly, the 3-bit
The power ramping at the start and at the end
of a packet can be turned off by setting
FREND0.PA_POWER
to zero and then
program the desired output power to index
zero in the PATABLE.
FREND0.PA_POWER
value
selects
the
Table 31 contains recommended PATABLE
settings for various output levels and
frequency bands. See Section 10.5 on page
22 for PATABLEprogramming details.
PATABLE entry to use. This two-level
functionality provides flexible PA power ramp
up and ramp down at the start and end of
transmission. All the PA power settings in the
PATABLE from index
FREND0.PA_POWERvalue are used.
0
up to the
PATABLE must be programmed in burst mode
if you want to write to other entries than
PATABLE[0].
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 40 of 77
CC2500
PATABLE(7)[7:0]
PATABLE(6)[7:0]
PATABLE(5)[7:0]
PATABLE(4)[7:0]
PATABLE(3)[7:0]
PATABLE(2)[7:0]
PATABLE(1)[7:0]
PATABLE(0)[7:0]
The PA uses this
setting.
Settings 0 to PA_POWER are
used during ramp-up at start of
transmission and ramp-down at
end of transmission, and for
ASK/OOK modulation.
Index into PATABLE(7:0)
The SmartRF® Studio software
should be used to obtain optimum
PATABLE settings for various
output powers.
e.g 6
PA_POWER[2:0]
in FREND0 register
Figure 16: PA_POWER and PATABLE
Output power,
typical [dBm]
Current consumption,
Default power setting
typical [mA]
0xC6
-11.8
11.1
Table 30: Output power and current consumption for default PATABLE setting
Output power,
typical, +25°C, 3.0 V [dBm]
PATABLE
value
Current consumption,
typical [mA]
(–55 or less)
–30
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
0x00
0x50
0x44
0xC0
0x84
0x81
0x46
0x93
0x55
0x8D
0xC5
0x97
0x6E
0x7F
0xA9
0xBB
0xFE
0xFF
8.4
9.9
9.7
10.2
10.1
10.0
10.1
11.7
10.8
12.2
11.1
12.2
14.1
15.1
16.2
17.7
21.2
21.5
–6
–4
–2
0
1.5
Table 31: Optimum PATABLE settings for various output power levels (subject to changes)
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 41 of 77
CC2500
25 Selectivity Graphs
Figure 17 to Figure 21 show the typical selectivity performance (adjacent and alternate rejection).
50
40
30
20
10
0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-10
Frequency offset [MHz]
Figure 17: Typical selectivity at 2.4 kbps. IF frequency is 273.9 kHz.
MDMCFG2.DEM_DCFILT_OFF= 1
40
35
30
25
20
15
10
5
0
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-5
-10
Frequency offset [MHz]
Figure 18: Typical selectivity at 10 kbps. IF frequency is 273.9 kHz.
MDMCFG2.DEM_DCFILT_OFF= 1
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 42 of 77
CC2500
50
40
30
20
10
0
-3
-2
-1
0
1
2
3
-10
-20
Frequency offset [MHz]
Figure 19: Typical selectivity at 250 kbps. IF frequency is 177.7 kHz.
MDMCFG2.DEM_DCFILT_OFF= 0
50
40
30
20
10
0
-3
-2
-1
0
1
2
3
-10
-20
Frequency offset [MHz]
Figure 20: Typical selectivity at 250 kbps. IF frequency is 457 kHz.
MDMCFG2.DEM_DCFILT_OFF= 1
35
30
25
20
15
10
5
0
-3
-2
-1
0
1
2
3
-5
-10
-15
-20
Frequency offset [MHz]
Figure 21: Typical selectivity at 500 kbps. IF frequency is 307.4 kHz.
MDMCFG2.DEM_DCFILT_OFF= 0
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 43 of 77
CC2500
26 Crystal Oscillator
A crystal in the frequency range 26-27 MHz
must be connected between the XOSC_Q1
and XOSC_Q2 pins. The oscillator is designed
for parallel mode operation of the crystal. In
addition, loading capacitors (C81 and C101)
for the crystal are required. The loading
capacitor values depend on the total load
capacitance, CL, specified for the crystal. The
total load capacitance seen between the
crystal terminals should equal CL for the
crystal to oscillate at the specified frequency.
The crystal oscillator is amplitude regulated.
This means that a high current is used to start
up the oscillations. When the amplitude builds
up, the current is reduced to what is necessary
to maintain approximately 0.4Vpp signal
swing. This ensures a fast start-up, and keeps
the drive level to a minimum. The ESR of the
crystal should be within the specification in
order to ensure a reliable start-up (see Section
4.4 on page 10).
The initial tolerance, temperature drift, aging
and load pulling should be carefully specified
in order to meet the required frequency
accuracy in a certain application. By specifying
the total expected frequency accuracy in
SmartRF® Studio together with data rate and
frequency deviation, the software calculates
the total bandwidth and compares this to the
chosen receiver channel filter bandwidth. The
software reports any contradictions, and a
more accurate crystal is recommended if
required.
1
CL =
+ Cparasitic
1
1
+
C81 C101
The parasitic capacitance is constituted by pin
input capacitance and PCB stray capacitance.
Total parasitic capacitance is typically 2.5 pF.
The crystal oscillator circuit is shown in Figure
22. Typical component values for different
values of CL are given in Table 32.
XOSC_Q1
XOSC_Q2
XTAL
C81
C101
Figure 22: Crystal oscillator circuit
Component
C81
CL= 10 pF
CL=13 pF
22 pF
CL=16 pF
27 pF
15 pF
15 pF
C101
22 pF
27 pF
Table 32: Crystal oscillator component values
26.1 Reference Signal
The chip can alternatively be operated with a
reference signal from 26 to 27 MHz instead of
a crystal. This input clock can either be a full-
swing digital signal (0 V to VDD) or a sine
wave of maximum 1 V peak-peak amplitude.
The reference signal must be connected to the
XOSC_Q1 input. The sine wave must be
connected to XOSC_Q1 using serial
capacitor. The XOSC_Q2 line must be left un-
connected. C81 and C101 can be omitted
when using a reference signal.
a
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 44 of 77
CC2500
27 External RF Match
The balanced RF input and output of CC2500
share two common pins and are designed for
a simple, low-cost matching and balun network
on the printed circuit board. The receive- and
transmit switching at the CC2500 front-end is
controlled by a dedicated on-chip function,
eliminating the need for an external RX/TX-
switch.
Although CC2500 has
a
balanced RF
input/output, the chip can be connected to a
single-ended antenna with few external low
cost capacitors and inductors.
The
passive
matching/filtering
network
connected to CC2500 should have the following
differential impedance as seen from the RF-
port (RF_P and RF_N) towards the antenna:
A few passive external components combined
with the internal RX/TX switch/termination
circuitry ensures match in both RX and TX
mode.
Zout = 80 + j74 Ω
28 General Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1 and
GDO2 are general control pins configured with
The default value for GDO0 is a 135-141 kHz
clock output (XOSC frequency divided by 192).
Since the XOSC is turned on at power-on-
reset, this can be used to clock the MCU in
systems with only one crystal. When the MCU
is up and running, it can change the clock
frequency by writing to IOCFG0.GDO0_CFG.
IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG
and IOCFG2.GDO3_CFG respectively. Table
33 shows the different signals that can be
monitored on the GDO pins. These signals can
be used as an interrupt to the MCU. GDO1 is
the same pin as the SO pin on the SPI
interface, thus the output programmed on this
pin will only be valid when CSn is high. The
default value for GDO1 is 3-stated, which is
useful when the SPI interface is shared with
other devices.
An on-chip analog temperature sensor is
enabled by writing the value 128 (0x80h) to the
IOCFG0.GDO0_CFG register. The voltage on
the GDO0 pin is then proportional to
temperature. See Section 4.7 on page 12 for
temperature sensor specifications.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 45 of 77
CC2500
GDO0_CFG[5:0]
GDO1_CFG[5:0] Description
GDO2_CFG[5:0]
Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR. De-asserts when RX FIFO is drained
below RXFIFO_THR.
Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR or the end of packet is reached. De-
asserts when RX FIFO is empty.
Associated to the TX FIFO: Asserts when the TX FIFO is filled above TXFIFO_THR. De-asserts when the TX FIFO is
below TXFIFO_THR.
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below
TXFIFO_THR.
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
Reserved
Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A) Lock detector output
Serial Clock. Synchronous to the data in synchronous serial mode.
11 (0x0B)
Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK when GDOx_INV=0.
Serial Synchronous Data Output (DO). Used for synchronous serial mode. The MCU must read DO on the rising edge
of SERIAL_CLK when GDOx_INV=0. Data is set up on the falling edge by CC2500.
12 (0x0C)
13 (0x0D) Serial transparent Data Output. Used for asynchronous serial mode.
14 (0x0E) Carrier sense. High if RSSI level is above threshold.
15 (0x0F) Reserved
16 (0x10) Reserved – used for test.
17 (0x11) Reserved – used for test.
18 (0x12) Reserved – used for test.
19 (0x13) Reserved – used for test.
20 (0x14) Reserved – used for test.
21 (0x15) Reserved – used for test.
22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
24 (0x18) Reserved – used for test.
25 (0x19) Reserved – used for test.
26 (0x1A) Reserved – used for test.
27 (0x1B) PA_PD. PA is enabled when 0, in power-down when 1. Can be used to control external PA or RX/TX switch.
28 (0x1C) LNA_PD. LNA is enabled when 0, in power-down when 1. Can be used to control external LNA or RX/TX switch.
29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.
30 (0x1E) Reserved – used for test.
31 (0x1F) Reserved – used for test.
32 (0x20) Reserved – used for test.
33 (0x21) Reserved – used for test.
34 (0x22) Reserved – used for test.
35 (0x23) Reserved – used for test.
36 (0x24) Reserved – used for test.
37 (0x25) Reserved – used for test.
38 (0x26) Reserved – used for test.
39 (0x27) Reserved – used for test.
40 (0x28) Reserved – used for test.
41 (0x29) CHIP_RDY
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved with _INV signal)
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36) CLK_XOSC/8
55 (0x37) CLK_XOSC/12
56 (0x38) CLK_XOSC/16
57 (0x39) CLK_XOSC/24
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192
Table 33: GDO signal selection
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 46 of 77
CC2500
29 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have
been included in the CC2500 to provide
backward compatibility with previous Chipcon
products and other existing RF communication
systems. For new systems, it is recommended
to use the built-in packet handling features, as
they can give more robust communication,
significantly offload the microcontroller and
simplify software development.
The CC2500 modulator samples the level of the
asynchronous input 8 times faster than the
programmed data rate. The timing requirement
for the asynchronous stream is that the error in
the bit period must be less than one eighth of
the programmed data rate.
29.2 Synchronous serial operation
Setting
PKTCTRL0.PKT_FORMAT
to
1
enables synchronous serial operation mode. In
the synchronous serial operation mode, data is
transferred on a two wire serial interface. The
CC2500 provides a clock that is used to set up
new data on the data input line or sample data
on the data output line. Data input (TX data) is
the GDO0 pin. This pin will automatically be
configured as an input when TX is active. The
data output pin can be any of the GDO pins;
this is set by the IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG
fields.
29.1 Asynchronous operation
For backward compatibility with systems
already using the asynchronous data transfer
from other Chipcon products, asynchronous
transfer is also included in CC2500. When
asynchronous transfer is enabled, several of
the support mechanisms for the MCU that are
included in CC2500 will be disabled, such as
packet handling hardware, buffering in the
FIFO and so on. The asynchronous transfer
mode does not allow the use of the data
whitener, interleaver and FEC.
Preamble and sync word insertion/detection
may or may not be active, dependent on the
sync mode set by the MDMCFG2.SYNC_MODE.
If preamble and sync word is disabled, all
other packet handler features and FEC should
also be disabled. The MCU must then handle
preamble and sync word insertion and
detection in software. If preamble and sync
word insertion/detection is left on, all packet
handling features and FEC can be used. The
CC2500 will insert and detect the preamble and
sync word and the MCU will only provide/get
the data payload. This is equivalent to the
recommended FIFO operation mode.
Only 2-FSK, GFSK and OOK are supported for
asynchronous transfer.
Setting
PKTCTRL0.PKT_FORMAT
to
3
enables asynchronous transparent (serial)
mode.
In TX, the GDO0pin is used for data input (TX
data). Data output can be GDO0, GDO1 or
GDO2.
The MCU must control start and stop of
transmit and receive with the STX, SRX and
SIDLEstrobes.
30 System considerations and Guidelines
30.1 SRD Regulations
GHz band, available from the Chipcon
website.
International regulations and national laws
regulate the use of radio receivers and
transmitters. Short Range Devices (SRDs) for
license free operation are allowed to operate
in the 2.45 GHz bands worldwide. The most
important regulations are EN 300 440 and EN
300 328 (Europe), FCC CFR47 part 15.247
and 15.249 (USA), and ARIB STD-T66
(Japan). A summary of the most important
aspects of these regulations can be found in
Application Note AN032 SRD regulations for
license-free transceiver operation in the 2.4
Please note that compliance with regulations
is
dependent
on
complete
system
performance. It is the customer’s responsibility
to ensure that the system complies with
regulations.
30.2 Frequency Hopping and Multi-
Channel Systems
The 2.400 – 2.4835 GHz band is shared by
many systems both in industrial, office and
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 47 of 77
CC2500
home
environments.
It
is
therefore
30.3 Data Burst Transmissions
recommended to use frequency hopping
spread spectrum (FHSS) or a multi-channel
protocol because the frequency diversity
makes the system more robust with respect to
interference from other systems operating in
the same frequency band. FHSS also combats
multipath fading.
The high maximum data rate of CC2500 opens
up for burst transmissions. A low average data
rate link (say 10 kbps), can be realized using a
higher over-the-air data rate. Buffering the
data and transmitting in bursts at high data
rate (say 500 kbps) will reduce the time in
active mode, and hence also reduce the
average current consumption significantly.
Reducing the time in active mode will reduce
the likelihood of collisions with other systems,
e.g. WLAN.
CC2500 is highly suited for FHSS or multi-
channel systems due to its agile frequency
synthesizer and effective communication
interface. Using the packet handling support
and data buffering is also beneficial in such
systems as these features will significantly
offload the host controller.
30.4 Continuous Transmissions
In data streaming applications the CC2500
opens up for continuous transmissions at 500
kbps effective data rate. As the modulation is
done with an I/Q up-converter with LO I/Q-
signals coming from a closed loop PLL, there
is no limitation in the length of a transmission.
(Open loop modulation used in some
transceivers often prevents this kind of
continuous data streaming and reduces the
effective data rate.)
Charge pump current, VCO current and VCO
capacitance array calibration data is required
for each frequency when implementing
frequency hopping for CC2500. There are 3
ways of obtaining the calibration data from the
chip:
1) Frequency hopping with calibration for each
hop. The PLL calibration time is approximately
720 µs.
2) Fast frequency hopping without calibration
for each hop can be done by calibrating each
frequency at startup and saving the resulting
FSCAL3, FSCAL2and FSCAL1 register values
in MCU memory. Between each frequency
hop, the calibration process can then be
replaced by writing the FSCAL3, FSCAL2 and
FSCAL1 register values corresponding to the
next RF frequency. The PLL turn on time is
approximately 90 µs.
30.5 Crystal Drift Compensation
The CC2500 has a very fine frequency
resolution (see Table 9). This feature can be
used to compensate for frequency offset and
drift.
The frequency offset between an ‘external’
transmitter and the receiver is measured in the
CC2500 and can be read back from the
FREQEST status register as described in
Section 14.1. The measured frequency offset
can be used to calibrate the frequency using
the ‘external’ transmitter as the reference. That
is, the received signal of the device will match
the receiver’s channel filter better. In the same
way the centre frequency of the transmitted
signal will match the ‘external’ transmitter’s
signal.
3) Run calibration on a single frequency at
startup. Next write 0hex to FSCAL3[5:4] to
disable the charge pump calibration. After
writing to FSCAL3[5:4] strobe SRX (or STX)
with MCSM0.FS_AUTOCAL = 1 for each new
frequency hop. That is, VCO current and VCO
capacitance calibration is done but not charge
pump current calibration. When charge pump
current calibration is disabled the calibration
time is reduced from approximately 720 µs to
approximately 150 µs.
30.6 Spectrum Efficient Modulation
There is a trade off between blanking time and
memory space needed for storing calibration
data in non-volatile memory. Solution 2) above
gives the shortest blanking interval, but
requires more memory space to store
CC2500 also has the possibility to use
Gaussian shaped FSK (GFSK). This
spectrum-shaping feature improves adjacent
channel
power
(ACP)
and
occupied
bandwidth. In ‘true’ FSK systems with abrupt
frequency shifting, the spectrum is inherently
broad. By making the frequency shift ‘softer’,
the spectrum can be made significantly
narrower. Thus, higher data rates can be
calibration
values.
Solution
3)
gives
approximately 570 µs smaller blanking interval
than solution 1).
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 48 of 77
CC2500
transmitted in the same bandwidth using
GFSK.
30.8 Battery Operated Systems
In low power applications, the SLEEP state
with the crystal oscillator core switched off
should be used when the CC2500 is not active.
It is possible to leave the crystal oscillator core
running in the SLEEP state if start-up time is
critical.
30.7 Low Cost Systems
As the CC2500 provides 500 kbps multi-
channel performance without any external
filters, a very low cost system can be made.
The WOR functionality should be used in low
power applications.
A differential antenna will eliminate the need
for a balun, and the DC biasing can be
achieved in the antenna topology, see Figure
3.
30.9 Increasing Output Power
A HC-49 type SMD crystal is used in the
CC2500EM reference design. Note that the
crystal package strongly influences the price.
In a size constrained PCB design a smaller,
but more expensive, crystal may be used.
In some applications it may be necessary to
extend the link range. Adding an external
power amplifier is the most effective way of
doing this.
The power amplifier should be inserted
between the antenna and the balun, and two
T/R switches are needed to disconnect the PA
in RX mode. See Figure 23.
Antenna
Filter
PA
Balun
CC2500
T/R switch
T/R switch
Figure 23. Block diagram of CC2500 usage with external power amplifier
31 Configuration Registers
registers are for test purposes only, and need
not be written for normal operation of CC2500.
The configuration of CC2500 is done by
programming 8-bit registers. The configuration
data based on selected system parameters
are most easily found by using the SmartRF®
Studio software. Complete descriptions of the
registers are given in the following tables. After
chip reset, all the registers have default values
as shown in the tables.
There are also 12 Status registers, which are
listed in Table 36. These registers, which are
read-only, contain information about the status
of CC2500.
The two FIFOs are accessed through one 8-bit
register. Write operations write to the TX FIFO,
while read operations read from the RX FIFO.
There are 14 Command Strobe Registers,
listed in Table 34. Accessing these registers
will initiate the change of an internal state or
mode. There are 47 normal 8-bit Configuration
Registers, listed in Table 35. Many of these
During the address transfer and while writing
to a register or the TX FIFO, a status byte is
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 49 of 77
CC2500
returned. This status byte is described in Table
17 on page 21.
read/write bits on the top. Note that the burst
bit has different meaning for base addresses
above and below 0x2F.
Table 37 summarizes the SPI address space.
The address to use is given by adding the
base address to the left and the burst and
Address
Strobe
Name
Description
0x30
0x31
SRES
Reset chip.
SFSTXON
Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
0x32
0x33
SXOFF
SCAL
Turn off crystal oscillator.
Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in IDLE
state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
0x34
0x35
SRX
STX
Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.
In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36
0x38
0x39
SIDLE
SWOR
SPWD
Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5.
Enter power down mode when CSngoes high.
0x3A
0x3B
SFRX
SFTX
Flush the RX FIFO buffer. Only issue in IDLE, TXFIFO_UNDERFLOW or RXFIFO_OVERFLOW
states.
Flush the TX FIFO buffer. Only issue in IDLE, TXFIFO_UNDERFLOW or RXFIFO_OVERFLOW
states.
0x3C
0x3D
SWORRST Reset real time clock.
SNOP No operation. May be used to pad strobe commands to two bytes for simpler software.
Table 34: Command Strobes
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 50 of 77
CC2500
Preserved in
SLEEP state
Details on
page number
Address
Register
Description
Yes
Yes
Yes
54
GDO2output pin configuration
GDO1output pin configuration
0x00
0x01
IOCFG2
IOCFG1
54
54
GDO0output pin configuration
RX FIFO and TX FIFO thresholds
Sync word, high byte
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
IOCFG0
FIFOTHR
SYNC1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
55
55
55
55
56
57
57
57
58
58
58
58
58
59
59
60
61
61
62
62
63
64
64
64
65
66
66
66
67
67
67
68
68
68
68
69
69
69
69
69
69
70
70
70
SYNC0
Sync word, low byte
PKTLEN
Packet length
PKTCTRL1 Packet automation control
PKTCTRL0 Packet automation control
ADDR
CHANNR
FSCTRL1
FSCTRL0
FREQ2
Device address
Channel number
Frequency synthesizer control
Frequency synthesizer control
Frequency control word, high byte
Frequency control word, middle byte
Frequency control word, low byte
FREQ1
FREQ0
MDMCFG4 Modem configuration
MDMCFG3 Modem configuration
MDMCFG2 Modem configuration
MDMCFG1 Modem configuration
MDMCFG0 Modem configuration
DEVIATN
MCSM2
Modem deviation setting
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Frequency Offset Compensation configuration
Bit Synchronization configuration
AGC control
MCSM1
MCSM0
FOCCFG
BSCFG
AGCTRL2
AGCTRL1
AGCTRL0
AGC control
AGC control
WOREVT1 High byte Event 0 timeout
WOREVT0 Low byte Event 0 timeout
WORCTRL Wake On Radio control
FREND1
FREND0
FSCAL3
FSCAL2
FSCAL1
FSCAL0
RCCTRL1
RCCTRL0
FSTEST
PTEST
Front end RX configuration
Front end TX configuration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
Frequency synthesizer calibration
RC oscillator configuration
RC oscillator configuration
Frequency synthesizer calibration control
Production test
No
AGCTEST
TEST2
AGC test
No
Various test settings
No
TEST1
Various test settings
No
TEST0
Various test settings
No
Table 35: Configuration Registers Overview
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 51 of 77
CC2500
Address
Register
PARTNUM
VERSION
FREQEST
LQI
Description
Details on page number
70
70
70
71
71
71
72
72
72
72
72
72
0x30 (0xF0)
0x31 (0xF1)
0x32 (0xF2)
0x33 (0xF3)
0x34 (0xF4)
0x35 (0xF5)
0x36 (0xF6)
0x37 (0xF7)
0x38 (0xF8)
0x39 (0xF9)
0x3A (0xFA)
0x3B (0xFB)
Part number for CC2500
Current version number
Frequency Offset Estimate
Demodulator estimate for Link Quality
Received signal strength indication
Control state machine state
RSSI
MARCSTATE
WORTIME1
WORTIME0
PKTSTATUS
VCO_VC_DAC
TXBYTES
RXBYTES
High byte of WOR timer
Low byte of WOR timer
Current GDOx status and packet status
Current setting from PLL calibration module
Underflow and number of bytes in the TX FIFO
Overflow and number of bytes in the RX FIFO
Table 36: Status Registers Overview
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 52 of 77
CC2500
Write
Read
Single byte
+0x00
Burst
Single byte
+0x80
Burst
+0x40
+0xC0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
IOCFG2
IOCFG1
IOCFG0
FIFOTHR
SYNC1
SYNC0
PKTLEN
PKTCTRL1
PKTCTRL0
ADDR
CHANNR
FSCTRL1
FSCTRL0
FREQ2
FREQ1
FREQ0
MDMCFG4
MDMCFG3
MDMCFG2
MDMCFG1
MDMCFG0
DEVIATN
MCSM2
MCSM1
MCSM0
FOCCFG
BSCFG
AGCCTRL2
AGCCTRL1
AGCCTRL0
WOREVT1
WOREVT0
WORCTRL
FREND1
FREND0
FSCAL3
FSCAL2
FSCAL1
FSCAL0
RCCTRL1
RCCTRL0
FSTEST
PTEST
AGCTEST
TEST2
TEST1
TEST0
SRES
SFSTXON
SXOFF
SCAL
SRES
SFSTXON
SXOFF
SCAL
PARTNUM
VERSION
FREQEST
LQI
SRX
SRX
RSSI
STX
STX
MARCSTATE
WORTIME1
WORTIME0
PKTSTATUS
VCO_VC_DAC
TXBYTES
RXBYTES
SIDLE
SIDLE
SAFC
SAFC
SWOR
SPWD
SFRX
SWOR
SPWD
SFRX
SFTX
SFTX
SWORRST
SNOP
SWORRST
SNOP
PATABLE
TX FIFO
PATABLE
TX FIFO
PATABLE
RX FIFO
PATABLE
RX FIFO
Table 37: SPI Address Space
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 53 of 77
CC2500
31.1 Configuration Register Details – Registers with preserved values in sleep state
0x00: IOCFG2 – GDO2output pin configuration
Bit
Field Name
Reset
R/W Description
7
6
Reserved
R0
0
R/W Invert output, i.e. select active low (1) / high (0)
GDO2_INV
GDO2_CFG[5:0]
5:0
41 (0x29)
R/W Default is CHIP_RDY (see Table 33 on page 46).
Should be set to 3-state for lowest power down current.
0x01: IOCFG1 – GDO1output pin configuration
Bit
Field Name
Reset
R/W Description
7
GDO_DS
0
R/W Set high (1) or low (0) output drive strength on the
GDO pins.
6
0
R/W Invert output, i.e. select active low (1) / high (0)
R/W Default is 3-state (see Table 33 on page 46)
GDO1_INV
5:0
46 (0x2E)
GDO1_CFG[5:0]
0x02: IOCFG0 – GDO0output pin configuration
Bit
Field Name
Reset
R/W
Description
7
TEMP_SENSOR_ENABLE
0
R/W Enable analog temperature sensor. Write 0 in all other
register bits when using temperature sensor.
6
0
R/W Invert output, i.e. select active low (1) / high (0)
GDO0_INV
5:0
63 (0x3F)
R/W Default is CLK_XOSC/192 (see Table 33 on page 46).
Should be set to 3-state for lowest power down current.
GDO0_CFG[5:0]
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 54 of 77
CC2500
0x03: FIFOTHR – RX FIFO and TX FIFO thresholds
Bit
Field Name
Reset
R/W
Description
7:3 Reserved
0
R/W
R/W
Write 0 for compatibility with possible future extensions
3:0 FIFO_THR[3:0]
7 (0111)
Set the threshold for the TX FIFO and RX FIFO. The threshold
is exceeded when the number of bytes in the FIFO is equal to
or higher than the threshold value.
Setting
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Bytes in TX FIFO
Bytes in RX FIFO
61
57
53
49
45
41
37
33
29
25
21
17
13
9
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
5
1
0x04: SYNC1 – Sync word, high byte
Bit
Field Name
Reset
R/W Description
7:0
SYNC[15:8]
211 (0xD3)
R/W 8 MSB of 16-bit sync word
0x05: SYNC0 – Sync word, low byte
Bit
Field Name
Reset
R/W Description
7:0
SYNC[7:0]
145 (0x91)
R/W 8 LSB of 16-bit sync word
0x06: PKTLEN – Packet length
Bit
Field Name
Reset
R/W
Description
7:0 PACKET_LENGTH
255 (0xFF)
R/W
Indicates the packet length when fixed length packets
are enabled. If variable length packets are used, this
value indicates the maximum length packets allowed.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 55 of 77
CC2500
0x07: PKTCTRL1 – Packet automation control
Bit Field Name
Reset
R/W Description
7:5 PQT[2:0]
0 (000)
R/W Preamble quality estimator threshold. The preamble quality
estimator increases an internal counter by one each time a bit is
received that is different from the previous bit, and decreases the
counter by 4 each time a bit is received that is the same as the
last bit. The counter saturates at 0 and 31.
A threshold of 4·PQT for this counter is used to gate sync word
detection. When PQT=0 a sync word is always accepted.
4
3
Reserved
0
0
R/W
CRC_AUTOFLUSH
R/W Enable automatic flush of RX FIFO when CRC in not OK. This
requires that only one packet is in the RXIFIFO and that packet
length is limited to the RX FIFO size.
2
APPEND_STATUS
1
R/W When enabled, two status bytes will be appended to the payload
of the packet. The status bytes contain RSSI and LQI values, as
well as the CRC OK flag.
1:0 ADR_CHK[1:0]
0 (00)
R/W Controls address check configuration of received packages.
Setting Address check configuration
0 (00)
1 (01)
2 (10)
3 (11)
No address check
Address check, no broadcast
Address check, 0 (0x00) broadcast
Address check, 0 (0x00) and 255 (0xFF) broadcast
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 56 of 77
CC2500
0x08: PKTCTRL0 – Packet automation control
Bit Field Name
Reset R/W Description
7
6
Reserved
R0
WHITE_DATA
1
R/W Turn data whitening on / off
0: Whitening off
1: Whitening on
5:4 PKT_FORMAT[1:0]
0 (00) R/W Format of RX and TX data
Setting Packet format
0 (00)
1 (01)
Normal mode, use FIFOs for RX and TX
Serial Synchronous mode, used for backwards
compatibility. Data in on GDO0
Random TX mode; sends random data using PN9
generator. Used for test.
Works as normal mode, setting 0 (00), in RX.
2 (10)
3 (11)
Asynchronous transparent mode. Data in on GDO0
and Data out on either of the GDO pins
3
2
CC2400_EN
CRC_EN
0
1
R/W Enable CC2400 support. Use same CRC implementation as
CC2400.
R/W 1: CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
1:0 LENGTH_CONFIG[1:0]
1 (01) R/W Configure the packet length
Setting Packet length configuration
0 (00)
Fixed length packets, length configured in
PKTLEN register
1 (01)
Variable length packets, packet length configured
by the first byte after sync word
2 (10)
3 (11)
Enable infinite length packets
Reserved
0x09: ADDR – Device address
Bit
Field Name
Reset
R/W
Description
7:0
DEVICE_ADDR[7:0]
0 (0x00)
R/W
Address used for packet filtration. Optional broadcast
addresses are 0 (0x00) and 255 (0xFF).
0x0A: CHANNR – Channel number
Bit
Field Name
Reset
R/W
Description
7:0
CHAN[7:0]
0 (0x00)
R/W
The 8-bit unsigned channel number, which is multiplied by the
channel spacing setting and added to the base frequency.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 57 of 77
CC2500
0x0B: FSCTRL1 – Frequency synthesizer control
Bit
Field Name
Reset
R/W
Description
7:5 Reserved
R0
4:0 FREQ_IF[4:0]
10 (0x0F)
R/W
The desired IF frequency to employ in RX. Subtracted from FS
base frequency in RX and controls the digital complex mixer in
the demodulator.
fXOSC
210
fIF
=
⋅ FREQ _ IF
The default value gives an IF frequency of 254 kHz, assuming
a 26.0 MHz crystal.
0x0C: FSCTRL0 – Frequency synthesizer control
Bit
Field Name
Reset
R/W
Description
7:0 FREQOFF[7:0]
0 (0x00)
R/W
Frequency offset added to the base frequency before being
used by the FS. (2-complement).
Resolution is FXTAL/214 (1.59 - 1.65 kHz); range is ±202 kHz to
±210 kHz, dependent of XTAL frequency.
0x0D: FREQ2 – Frequency control word, high byte
Bit
Field Name
Reset
R/W
Description
7:6 FREQ[23:22]
5:0 FREQ[21:16]
1 (01)
R
FREQ[23:22] is always binary 01 (the FREQ2 register is in the range 85 to
95 with 26-27 MHz crystal)
30
(0x1E)
R/W
FREQ[23:0] is the base frequency for the frequency synthesiser in
increments of FXOSC/216.
fXOSC
216
fcarrier
=
⋅ FREQ
[23 : 0
]
The default frequency word gives a base frequency of 2464 MHz,
assuming a 26.0 MHz crystal. With the default channel spacing settings,
the following FREQ2 values and channel numbers can be used:
FREQ2
Base frequency
2386 MHz
Frequency range (CHAN numbers)
2400.2-2437 MHz (71-255)
2412-2463 MHz (0-255)
91 (0x5B)
92 (0x5C)
93 (0x5D)
94 (0x5E)
2412 MHz
2438 MHz
2431-2483.4 MHz (0-227)
2464-2483.4 MHz (0-97)
2464 MHz
0x0E: FREQ1 – Frequency control word, middle byte
Bit
Field Name
Reset
R/W
Description
7:0 FREQ[15:8]
196 (0xC4)
R/W
Ref. FREQ2 register
0x0F: FREQ0 – Frequency control word, low byte
Bit
Field Name
Reset
R/W
Description
7:0 FREQ[7:0]
236 (0xEC)
R/W
Ref. FREQ2 register
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 58 of 77
CC2500
0x10: MDMCFG4 – Modem configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
CHANBW_E[1:0]
CHANBW_M[1:0]
2 (10)
0 (00)
R/W
R/W
Sets the decimation ratio for the delta-sigma ADC input stream
and thus the channel bandwidth.
fXOSC
BWchannel
=
8⋅(4 + CHANBW _ M )·2CHANBW _ E
The default values give 203 kHz channel filter bandwidth,
assuming a 26.0 MHz crystal.
3:0
DRATE_E[3:0]
12 (1100)
R/W
The exponent of the user specified symbol rate
0x11: MDMCFG3 – Modem configuration
Bit
Field Name
Reset
R/W
Description
7:0
DRATE_M[7:0]
34 (0x22)
R/W
The mantissa of the user specified symbol rate. The symbol
rate is configured using an unsigned, floating-point number
with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden
‘1’. The resulting data rate is:
256 + DRATE _ M
)
⋅ 2DRATE _ E
RDATA
=
⋅ fXOSC
228
The default values give a data rate of 115.051 kbps (closest
setting to 115.2 kbps), assuming a 26.0 MHz crystal.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 59 of 77
CC2500
0x12: MDMCFG2 – Modem configuration
Bit
Field Name
Reset
R/W
Description
7
DEM_DCFILT_OFF
0
R/W
Disable digital DC blocking filter before demodulator.
0 = Enable (better sensitivity for data rates ≤ 250 kbps)
1 = Disable (reduced current)
The recommended IF frequency changes when the DC
blocking is disabled.
6:4
MOD_FORMAT[2:0]
0 (000)
R/W
The modulation format of the radio signal
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Modulation format
2-FSK
GFSK
-
OOK
-
-
-
MSK
3
MANCHESTER_EN
SYNC_MODE[2:0]
0
R/W
R/W
Enables Manchester encoding/decoding.
0 = Disable
1 = Enable
2:0
2 (010)
Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables sync word
transmission in TX and sync word detection in RX.
The values 1 (001), 2 (001), 5 (101) and 6 (110)
enables 16-bit sync word transmission in TX and 16-
bits sync word detection in RX. Only 15 of 16 bits need
to match in RX when using setting 1 (001) or 5 (101).
The values 3 (011) and 7 (111) enables repeated sync
word transmission in RX and 32-bits sync word
detection in RX (only 30 of 32 bits need to match).
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
Sync-word qualifier mode
No preamble/sync
15/16 sync word bits detected
16/16 sync word bits detected
30/32 sync word bits detected
No preamble/sync, carrier-sense
above threshold
5 (101)
6 (110)
7 (111)
15/16 + carrier-sense above threshold
16/16 + carrier-sense above threshold
30/32 + carrier-sense above threshold
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 60 of 77
CC2500
0x13: MDMCFG1 – Modem configuration
Bit
Field Name
Reset
R/W
Description
7
FEC_EN
0
R/W
Enable Forward Error Correction (FEC) with interleaving for
packet payload
0 = Disable
1 = Enable
6:4
NUM_PREAMBLE[2:0] 2 (010)
R/W
Sets the minimum number of preamble bytes to be transmitted
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Number of preamble bytes
2
3
4
6
8
12
16
24
3:2
1:0
Reserved
CHANSPC_E[1:0]
R0
2 (10)
R/W
2 bit exponent of channel spacing
0x14: MDMCFG0 – Modem configuration
Bit Field Name
Reset
R/W Description
7:0 CHANSPC_M[7:0]
248 (0xF8)
R/W 8-bit mantissa of channel spacing (initial 1 assumed). The
channel spacing is multiplied by the channel number CHAN and
added to the base frequency. It is unsigned and has the format:
fXOSC
218
∆fCHANNEL
=
⋅
(
256 + CHANSPC _ M
⋅2CHANSPC _ E ⋅CHAN
)
The default values give 199.951 kHz channel spacing (the closest
setting to 200 kHz), assuming 26.0 MHz crystal frequency.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 61 of 77
CC2500
0x15: DEVIATN – Modem deviation setting
Bit Field Name
Reset
R/W
Description
7
Reserved
6:4 DEVIATION_E[2:0]
Reserved
2:0 DEVIATION_M[2:0]
R0
4 (100)
7 (111)
R/W
R0
Deviation exponent
3
R/W
When MSK modulation is enabled:
Sets fraction of symbol period used for phase change.
When FSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB implicit
1. The resulting FSK deviation is given by:
fxosc
217
fdev
=
⋅(8 + DEVIATION _ M )⋅2DEVIATION _ E
The default values give ±47.607 kHz deviation, assuming 26.0
MHz crystal frequency.
0x16: MCSM2 – Main Radio Control State Machine configuration
Bit
Field Name
Reset
R/W
Description
7:5
4
Reserved
R0
Reserved
RX_TIME_RSSI
0
R/W
Direct RX termination based on RSSI measurement (carrier
sense). For OOK modulation, RX times out if there is no
carrier sense in the first 8 symbol periods.
3
RX_TIME_QUAL
RX_TIME[2:0]
0
R/W
R/W
When the RX_TIME timer expires the chip stays in RX mode if
sync word is found when RX_TIME_QUAL=0, or either sync
word is found or PQT is set when RX_TIME_QUAL=1.
2:0
7 (111)
Timeout for sync word search in RX. The timeout is relative to
the programmed EVENT0 timeout, which means that the duty
cycle can be set in wake-on-radio (WOR) mode. The RX
timeout is scaled by 1 bit less than the EVENT0 timeout with
respect to the WORCTRL.WOR_RESsetting, as very long
timeouts probably also will use very low RX duty cycles.
Setting RX timeout
Duty cycle, WOR
12.5% / 2WOR_RES
6.25% / 2WOR_RES
3.125% / 2WOR_RES
1.563% / 2WOR_RES
0.781% / 2WOR_RES
0.391% / 2WOR_RES
0.195% / 2WOR_RES
N/A (no timeout)
0 (000) TEVENT0 / 2(3+WOR_RES)
1 (001) TEVENT0 / 2(4+WOR_RES)
2 (010) TEVENT0 / 2(5+WOR_RES)
3 (011) TEVENT0 / 2(6+WOR_RES)
4 (100) TEVENT0 / 2(7+WOR_RES)
5 (101) TEVENT0 / 2(8+WOR_RES)
6 (110) TEVENT0 / 2(9+WOR_RES)
7 (111) Until end of packet
Note that the RC oscillator must be enabled in order to use
setting 0-6, because the timeout counts RC oscillator periods.
WOR mode does not need to be enabled.
The timeout counter resolution is limited: With RX_TIME=0,
the timeout count is given by the 13 MSBs of EVENT0,
decreasing to the 7 MSBs of EVENT0 with RX_TIME=6.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 62 of 77
CC2500
0x17: MCSM1 – Main Radio Control State Machine configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
Reserved
R0
CCA_MODE[1:0]
3 (11)
R/W
Selects CCA_MODE; Reflected in CCA signal
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Clear channel indication
Always
If RSSI below threshold
Unless currently receiving a packet
If RSSI below threshold unless currently
receiving a packet
3:2
RXOFF_MODE[1:0]
0 (00)
R/W
Select what should happen when a packet has been received
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Next state after finishing packet reception
IDLE
FSTXON
TX
Stay in RX
It is not possible to set RXOFF_MODE to be TX or FSTXON
and at the same time use CCA.
1:0
TXOFF_MODE[1:0]
0 (00)
R/W
Select what should happen when a packet has been sent (TX)
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Next state after finishing packet transmission
IDLE
FSTXON
Stay in TX (start sending preamble)
RX
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 63 of 77
CC2500
0x18: MCSM0 – Main Radio Control State Machine configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
Reserved
R0
FS_AUTOCAL[1:0]
0 (00)
R/W
Automatically calibrate when going to RX or TX, or back to IDLE
Setting When to perform automatic calibration
0 (00)
1 (01)
2 (10)
3 (11)
Never (manually calibrate using SCALstrobe)
When going from IDLE to RX or TX (or FSTXON)
When going from RX or TX back to IDLE
Every 4th time when going from RX or TX to IDLE
In some automatic wake-on-radio (WOR) applications, using
setting 3 (11) can significantly reduce current consumption.
3:2
PO_TIMEOUT
1 (01)
R/W
Programs the number of times the six-bit ripple counter must
expire before CHP_RDY_N goes low. Values other than 0 (00)
are most useful when the XOSC is left on during power-down.
Setting Expire count
Timeout after XOSC start
Approx. 2.3 – 2.7 µs
Approx. 37 – 43 µs
0 (00)
1 (01)
2 (10)
3 (11)
1
16
64
256
Approx. 146 – 171 µs
Approx. 585 – 683 µs
Exact timeout depends on crystal frequency.
Enables the pin radio control option
1
0
PIN_CTRL_EN
0
0
R/W
R/W
XOSC_FORCE_ON
Force the XOSC to stay on in the SLEEP state.
0x19: FOCCFG – Frequency Offset Compensation configuration
Bit
Field Name
Reset
R/W
Description
7:6 Reserved
R0
5:0 FOCCFG[5:0]
54
(0x36)
R/W
Frequency offset compensation configuration. The value to use
in this register is given by the SmartRF® Studio software.
0x1A: BSCFG – Bit Synchronization configuration
Bit Field Name
Reset
R/W Description
7:0 BSCFG[7:0]
108
(0x6C)
R/W Bit Synchronization configuration. The value to use in this register is
given by the SmartRF® Studio software.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 64 of 77
CC2500
0x1B: AGCCTRL2 – AGC control
Bit
Field Name
Reset
R/W
Description
7:6 MAX_DVGA_GAIN[1:0]
0 (00)
R/W
Reduces the maximum allowable DVGA gain.
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Allowable DVGA settings
All gain settings can be used
The highest gain setting can not be used
The 2 highest gain settings can not be used
The 3 highest gain settings can not be used
5:3 MAX_LNA_GAIN[2:0]
0 (000)
R/W
Sets the maximum allowable LNA + LNA 2 gain relative to the
maximum possible gain.
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Maximum allowable LNA + LNA 2 gain
Maximum possible LNA + LNA 2 gain
Approx. 2.6 dB below maximum possible gain
Approx. 6.1 dB below maximum possible gain
Approx. 7.4 dB below maximum possible gain
Approx. 9.2 dB below maximum possible gain
Approx. 11.5 dB below maximum possible gain
Approx. 14.6 dB below maximum possible gain
Approx. 17.1 dB below maximum possible gain
2:0 MAGN_TARGET[2:0]
3 (011)
R/W
These bits set the target value for the averaged amplitude from
the digital channel filter (1 LSB = 0 dB).
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Target amplitude from channel filter
24 dB
27 dB
30 dB
33 dB
36 dB
38 dB
40 dB
42 dB
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 65 of 77
CC2500
0x1C: AGCCTRL1 – AGC control
Bit Field Name
Reset
R/W Description
7
6
Reserved
R0
AGC_LNA_PRIORITY
1
R/W Selects between two different strategies for LNA and LNA 2
gain adjustment. When 1, the LNA gain is decreased first.
When 0, the LNA 2 gain is decreased to minimum before
decreasing LNA gain.
5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00)
R/W Sets the relative change threshold for asserting carrier
sense
Setting
0 (00)
1 (01)
2 (10)
3 (11)
Carrier sense relative threshold
Relative carrier sense threshold disabled
6 dB increase in RSSI value
10 dB increase in RSSI value
14 dB increase in RSSI value
3:0 CARRIER_SENSE_ABS_THR[3:0]
0
R/W Sets the absolute RSSI threshold for asserting carrier
sense. The 2-complement signed threshold is programmed
in steps of 1 dB and is relative to the MAGN_TARGET
setting.
(0000)
Setting
Carrier sense absolute threshold
(Equal to channel filter amplitude when AGC
has not decreased gain)
-8 (1000)
-7 (1001)
…
Absolute carrier sense threshold disabled
7 dB below MAGN_TARGET setting
…
-1 (1111)
0 (0000)
1 (0001)
…
1 dB below MAGN_TARGET setting
At MAGN_TARGET setting
1 dB above MAGN_TARGET setting
…
7 (0111)
7 dB above MAGN_TARGET setting
0x1D: AGCCTRL0 – AGC control
Bit
Field Name
Reset
R/W
Description
7:0 AGCCTRL0[7:0]
145
(0x91)
R/W
AGC control register. The value to use in this register is given
by the SmartRF® Studio software.
0x1E: WOREVT1 – High byte Event0 timeout
Bit
Field Name
Reset
R/W
Description
7:0 EVENT0[15:8]
135 (0x87) R/W
High byte of Event 0 timeout register
750
tEvent0
=
⋅ EVENT0⋅25⋅WOR _ RES
f XOSC
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 66 of 77
CC2500
0x1F: WOREVT0 – Low byte Event0 timeout
Bit Field Name
Reset
R/W
Description
7:0 EVENT0[7:0]
107 (0x6B)
R/W
Low byte of Event 0 timeout register.
The default Event 0 value gives 1.0s timeout, assuming a
26.0 MHz crystal.
0x20: WORCTRL – Wake On Radio control
Bit Field Name
Reset
R/W Description
7
RC_PD
1
R/W Power down signal to RC oscillator. When written to 0, automatic
initial calibration will be performed
6:4 EVENT1[2:0]
7 (111)
R/W Timeout setting from register block. Decoded to Event 1 timeout.
RC oscillator clock frequency equals FXOSC/750, which is 34.7-36
kHz, depending on crystal frequency. The table below lists the
number of clock periods after Event 0 before Event 1 times out.
Setting
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
WOR_AUTOSYNC=0
4 (0.111 – 0.115 ms)
6 (0.167 – 0.173 ms)
8 (0.222 – 0.230 ms)
12 (0.333 – 0.346 ms)
16 (0.444 – 0.462 ms)
24 (0.667 – 0.692 ms)
32 (0.889 – 0.923 ms)
48 (1.333 – 1.385 ms)
WOR_AUTOSYNC=1
16 (0.44 – 0.46 ms)
24 (0.67 – 0.69 ms)
32 (0.89 – 0.92 ms)
48 (1.33 – 1.38 ms)
64 (1.78 – 1.85 ms)
96 (2.67 – 2.77 ms)
128 (3.56 – 3.69 ms)
192 (5.33 – 5.54 ms)
3
2
RC_CAL
Reserved
1
R/W Enables (1) or disables (0) the RC oscillator calibration.
Included for debug/test purposes only.
R0
1:0 WOR_RES
0 (00)
R/W Controls the Event 0 resolution and maximum timeout of the WOR
module:
Setting Resolution (1 LSB)
Max timeout
0 (00)
1 (01)
2 (10)
3 (11)
1 period (28 – 29 µs)
1.8 – 1.9 seconds
58 – 61 seconds
31 – 32 minutes
16.5 – 17.2 hours
25 periods (0.89 – 0.92 ms)
210 periods (28 – 30 ms)
215 periods (0.91 – 0.94 s)
Adjusting the resolution does not affect the resolution of the WOR
time readout registers WORTIME1/WORTIME0.
0x21: FREND1 – Front end RX configuration
Bit
Field Name
Reset
R/W Description
7:0 FREND1[7:0]
166
(0xA6)
R/W Front end RX configuration. The value to use in this register
is given by the SmartRF® Studio software.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 67 of 77
CC2500
0x22: FREND0 – Front end TX configuration
Bit
Field Name
Reset
R/W
Description
7:6
5:4
Reserved
R0
LODIV_BUF_CURRENT_TX[1:0]
1 (01)
R/W
Adjusts current TX LO buffer (input to PA). The value to
use in this field is given by the SmartRF® Studio software.
3
Reserved
R0
2:0
PA_POWER[2:0]
0 (000)
R/W
Selects PA power setting. This value is an index to the
PATABLE, which can be programmed with up to 8 different
PA settings. The PATABLE settings from index ‘0’ to the
PA_POWER value are used for power ramp-up/ramp-down
at the start/end of transmission in all TX modulation
formats.
0x23: FSCAL3 – Frequency synthesizer calibration
Bit
Field Name
Reset
R/W
Description
7:6 FSCAL3[7:6]
2 (10)
R/W
Frequency synthesizer calibration configuration. The value to write in
this register before calibration is given by the SmartRF® Studio
software.
5:4 CHP_CURR_CAL_EN[1:0]
3:0 FSCAL3[3:0]
2 (10)
R/W
R/W
Disable charge pump calibration stage when 0
9
Frequency synthesizer calibration result register.
(1001)
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
0x24: FSCAL2 – Frequency synthesizer calibration
Bit
Field Name
Reset
R/W
Description
7:6 Reserved
R0
5:0 FSCAL2[5:0]
10
R/W
Frequency synthesizer calibration result register.
(0x0A)
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
0x25: FSCAL1 – Frequency synthesizer calibration
Bit
Field Name
Reset
R/W
Description
7:6 Reserved
R0
5:0 FSCAL1[5:0]
32
R/W
Frequency synthesizer calibration result register.
(0x20)
Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 68 of 77
CC2500
0x26: FSCAL0 – Frequency synthesizer calibration
Bit Field Name
Reset
R/W Description
7
Reserved
R0
4:0 FSCAL0[6:0]
13 (0x0D)
R/W Frequency synthesizer calibration control. The value to use in
this register is given by the SmartRF® Studio software.
0x27: RCCTRL1 – RC oscillator configuration
Bit
Field Name
Reset
R/W
Description
7
Reserved
0
R0
6:0 RCCTRL1[6:0]
65
R/W
RC oscillator configuration. Do not write to this register.
(0x41)
0x28: RCCTRL0 – RC oscillator configuration
Bit
Field Name
Reset
R/W
Description
7
Reserved
0
R0
6:0 RCCTRL0[6:0]
0
R/W
RC oscillator configuration. Do not write to this register.
(0x00)
31.2 Configuration Register Details – Registers that lose programming in sleep state
0x29: FSTEST – Frequency synthesizer calibration control
Bit
Field Name
Reset
R/W
Description
7:0 FSTEST[7:0]
87
R/W
For test only. Do not write to this register.
(0x59)
0x2A: PTEST – Production test
Bit
Field Name
Reset
R/W
Description
7
PTEST[7:0]
127
(0x7F)
R/W
Writing 0xBF to this register makes the on-chip temperature sensor
available in the IDLE state. The default 0x7F value should then be
written back before leaving the IDLE state.
Other use of this register is for test only.
0x2B: AGCTEST – AGC test
Bit
Field Name
Reset
R/W
Description
7:0 AGCTEST[7:0]
63
R/W
For test only. Do not write to this register.
(0x3F)
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 69 of 77
CC2500
0x2C: TEST2 – Various test settings
Bit
Field Name
Reset
R/W
Description
The value to use in this register is given by the SmartRF® Studio
software.
7:0 TEST2[7:0]
152 (0x88) R/W
0x2D: TEST1 – Various test settings
Bit
Field Name
Reset
R/W
R/W
Description
The value to use in this register is given by the SmartRF® Studio
software.
7:0 TEST1[7:0]
49 (0x31)
0x2E: TEST0 – Various test settings
Bit
Field Name
Reset
R/W
Description
The value to use in this register is given by the SmartRF® Studio
software.
7:0 TEST0[7:0]
11 (0x0B)
R/W
31.3 Status register details
0x30 (0xF0): PARTNUM – Chip ID
Bit
Field Name
Reset
R/W
Description
7:0 PARTNUM[7:0]
128 (0x80)
R
Chip part number
0x31 (0xF1): VERSION – Chip ID
Bit
Field Name
Reset
R/W
Description
7:0 VERSION[7:0]
3 (0x03)
R
Chip version number.
0x32 (0xF2): FREQEST – Frequency Offset Estimate from demodulator
Bit
Field Name
Reset
R/W
Description
7:0 FREQOFF_EST
R
The estimated frequency offset (two’s complement) of the
carrier. Resolution is FXTAL/214 (1.59 - 1.65 kHz); range is ±202
kHz to ±210 kHz, dependent of XTAL frequency.
Frequency offset compensation is only supported for FSK and
MSK modulation. This register will read 0 when using OOK
modulation.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 70 of 77
CC2500
0x33 (0xF3): LQI – Demodulator estimate for Link Quality
Bit
Field Name
Reset
R/W
Description
7
Reserved
6:0 LQI_EST[6:0]
R
The Link Quality Indicator estimates how easily a received signal
can be demodulated. Calculated over the 64 symbols following
the sync word (first 8 packet bytes for 2-ary modulation).
0x34 (0xF4): RSSI – Received signal strength indication
Bit
Field Name
Reset
R/W
Description
7:0 RSSI
R
Received signal strength indicator
0x35 (0xF5): MARCSTATE – Main Radio Control State Machine state
Bit
Field Name
Reset
R/W
Description
7:5 Reserved
R0
R
4:0 MARC_STATE[4:0]
Main Radio Control FSM State
Value
State name
SLEEP
State (Figure 11, page 34)
SLEEP
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
IDLE
IDLE
XOFF
XOFF
VCOON_MC
REGON_MC
MANCAL
VCOON
MANCAL
MANCAL
MANCAL
FS_WAKEUP
FS_WAKEUP
CALIBRATE
SETTLING
SETTLING
SETTLING
CALIBRATE
RX
REGON
STARTCAL
BWBOOST
FS_LOCK
IFADCON
12 (0x0C) ENDCAL
13 (0x0D) RX
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
RX_END
RX
RX_RST
RX
TXRX_SWITCH
RX_OVERFLOW
FSTXON
TXRX_SETTLING
RX_OVERFLOW
FSTXON
TX
TX
TX_END
TX
RXTX_SWITCH
RXTX_SETTLING
TX_UNDERFLOW TX_UNDERFLOW
Note: it is not possible to read back the SLEEP or XOFF state
numbers because setting CSnlow will make the chip enter the
IDLE mode from the SLEEP or XOFF states.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 71 of 77
CC2500
0x36 (0xF6): WORTIME1 – High byte of WOR time
Bit
Field Name
Reset
R/W
Description
7:0 TIME[15:8]
R
High byte of timer value in WOR module
0x37 (0xF7): WORTIME0 – Low byte of WOR time
Bit
Field Name
Reset
R/W
Description
7:0 TIME[7:0]
R
Low byte of timer value in WOR module
0x38 (0xF8): PKTSTATUS – Current GDOx status and packet status
Bit
Field Name
Reset
R/W
Description
7
6
5
4
3
2
Reserved
CS
R
R
R
R
R
Carrier sense
PQT_REACHED
CCA
Preamble Quality reached
Clear channel assessment
Sync word found
SFD
GDO2
Current GDO2value. Note: the reading gives the non-inverted
value irrespective what IOCFG2.GDO2_INVis programmed
to.
1
0
Reserved
R
GDO0
Current GDO0value. Note: the reading gives the non-inverted
value irrespective what IOCFG0.GDO0_INVis programmed
to.
0x39 (0xF9): VCO_VC_DAC – Current setting from PLL calibration module
Bit
Field Name
Reset
R/W
Description
7:0 VCO_VC_DAC[7:0]
R
Status register for test only.
0x3A (0xFA): TXBYTES – Underflow and number of bytes
Bit
Field Name
Reset
R/W
Description
7
TXFIFO_UNDERFLOW
R
R
6:0 NUM_TXBYTES
Number of bytes in TX FIFO
0x3B (0xFB): RXBYTES – Overflow and number of bytes
Bit
Field Name
Reset
R/W
Description
7
RXFIFO_OVERFLOW
R
R
6:0 NUM_RXBYTES
Number of bytes in RX FIFO
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 72 of 77
CC2500
32 Package Description (QLP 20)
All dimensions are in millimetres, angles in degrees. NOTE: The CC2500 is available in RoHS
lead-free package only.
Figure 24: Package dimensions drawing
Package type
A
A1
A2
D
D1
D2
E
E1
E2
L
T
b
e
Min
Typ.
Max
0.75
0.85
0.95
0.005
0.025
0.045
0.55
0.65
0.75
3.90
4.00
4.10
3.65
3.75
3.85
3.90
4.00
4.10
3.65
3.75
3.85
0.45
0.55
0.65
0.190
0.18
0.23
0.30
QLP 20 (4x4)
2.40
2.40
0.50
0.245
Table 38: Package dimensions
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 73 of 77
CC2500
32.1 Recommended PCB layout for package (QLP 20)
Figure 25: Recommended PCB layout for QLP 20 package
Note: The figure is an illustration only and not to scale. There are five 14 mil diameter via holes
distributed symmetrically in the ground pad under the package. See also the CC2500 EM
reference design.
32.2 Package thermal properties
Thermal resistance
Air velocity [m/s]
Rth,j-a [K/W]
0
40.4
Table 39: Thermal properties of QLP 20 package
32.3 Soldering information
The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed.
32.4 Tray specification
CC2500 can be delivered in standard QLP 4x4mm shipping trays.
Tray Specification
Package
QLP 20
Tray Width
135.9 mm
Tray Height
7.62 mm
Tray Length
322.6 mm
Units per Tray
490
Table 40: Tray specification
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 74 of 77
CC2500
32.5 Carrier tape and reel specification
Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification
Package
Tape Width
Component
Pitch
Hole
Pitch
Reel
Diameter
Units per Reel
2500
QLP 20
12 mm
8 mm
4 mm
13 inches
Table 41: Carrier tape and reel specification
33 Ordering Information
Ordering part number
Description
Minimum Order Quantity (MOQ)
1167
1190
1192
10069
490 (tray)
CC2500 - RTY1 QLP20 RoHS Pb-free 490/tray
CC2500 - RTR1 QLP20 RoHS Pb-free 2500/T&R
CC2500 SK Sample kit 5pcs.
2500 (tape and reel)
1
1
CC2500_CC2550 DK Development Kit
Table 42: Ordering information
34 General Information
34.1 Document History
Revision Date
Description/Changes
1.1
2005-10-20 MDMCFG2[7] used. 26-27 MHz crystal range. Chapter 15: description of the 2 optional
append bytes. Added matching information. Added information about using a reference
signal instead of a crystal. CRC can only be checked by append bytes or
CRC_AUTOFLUSH. Added equation for calculating RSSI in dBm. Selectivity performance
graphs added.
1.0
2005-01-24 First preliminary release.
Table 43: Document history
34.2 Product Status Definitions
Data Sheet Identification
Product Status
Definition
Advance Information
Planned or Under
Development
This data sheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
Engineering Samples This data sheet contains preliminary data, and
and First Production
supplementary data will be published at a later date.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
No Identification Noted
Obsolete
Full Production
This data sheet contains the final specifications.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
Not In Production
This data sheet contains specifications on a product
that has been discontinued by Chipcon. The data
sheet is printed for reference information only.
Table 44: Product status definitions
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 75 of 77
CC2500
34.3 Disclaimer
Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However,
Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any
responsibility for the use of the described product; neither does it convey any license under its patent rights, or the rights
of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.
As far as possible, major changes of product specifications and functionality, will be stated in product specific Errata Notes
published at the Chipcon website. Customers are encouraged to sign up to the Developers Newsletter for the most recent
updates on products and support tools.
When a product is discontinued this will be done according to Chipcon’s procedure for obsolete products as described in
Chipcon’s Quality Manual. This includes informing about last-time-buy options. The Quality Manual can be downloaded
from Chipcon’s website.
Compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure
that the system complies with regulations.
34.4 Trademarks
SmartRF® is a registered trademark of Chipcon AS. SmartRF® is Chipcon's RF technology platform with RF library cells,
modules and design expertise. Based on SmartRF® technology Chipcon develops standard component RF circuits as well
as full custom ASICs based on customer requirements and this technology.
All other trademarks, registered trademarks and product names are the sole property of their respective owners.
34.5 Life Support Policy
This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction can
reasonably be expected to result in significant personal injury to the user, or as a critical component in any life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from any improper
use or sale.
Preliminary Data Sheet (rev.1.1.)
SWRS040
Page 76 of 77
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