CC2541-Q1 [TI]
符合汽车标准的 SimpleLink 低功耗 Bluetooth® 无线 MCU;
| 型号： | CC2541-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 符合汽车标准的 SimpleLink 低功耗 Bluetooth® 无线 MCU 无线 |
| 文件： | 总34页 (文件大小：1295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CC2541-Q1
ZHCSCU4 –JUNE 2014
CC2541-Q1 汽车用 SimpleLink™ 蓝牙®低能耗无线微控制器 (MCU)
1 器件概述
1.1 特性
1
– 电池监视器和温度感应器
– 含 8 通道和可配置分辨率的 12 位模数转换器
• 射频
– 2.4GHz 蓝牙低能耗专有 RF 无线 MCU
(ADC)
– 支持 250kbps、500kbps、1Mbps 和 2Mbps 数
据速率
– 高级加密标准 (AES) 安全协处理器
– 2 个功能强大的支持几个串行协议的通用异步接
收发器 (UART)
– 出色的链路预算，不使用外部前段而支持长距离
应用
– 23 个通用 I/O 引脚
(21 × 4mA，2 × 20mA)
– I2C 接口
– 高达 0dBm 的可编程输出功率
– 出色的接收器灵敏度（1Mbps 时为
-94dBm）、可选择性和阻断性能
– 2 个具有 LED 驱动功能的 I/O 引脚
– 安全装置定时器
– 集成的高性能比较器
• 开发工具
– 适合于针对符合世界范围内的无线电频率调节系
统：ETSI EN 300 328 和 EN 300 440 2 类 （欧
洲），FCC CFR47 15 部分（美国），和 ARIB
STD-T66（日本）
• 布局
– CC2541 评估模块
– SmartRF™ 软件
– 提供 IAR 嵌入式 Workbench™
– 极少的外部组件
– 6mm × 6mm 四方扁平无引线 (QFN)-40 封装
• 低功率
– 有源模式 RX 低至：18.3mA
– 有源模式 TX (0dBm)：18.6mA
– 功率模式 1（4µs 唤醒）：270µs
– 功率模式 2（睡眠定时器打开）：1µs
– 功率模式 3（外部中断）：0.5µs
– 宽电源电压范围（2V 至 3.6V）
• 微控制器
• 符合针对单模式蓝牙低能耗 (BLE) 解决方案的符合
蓝牙4.0 协议的堆栈
– 完全功率优化堆栈，包括控制器和主机
•
•
•
•
GAP - 中心设备，外设，或者广播器（包括组
合角色）
属性协议 (ATT) / 通用属性配置文件
(GATT) – 客户端和服务器
对称式对多重处理 (SMP) - AES-128 加密和
解密
– 具有代码预取功能的高性能和低功率 8051 微控
制器内核
L2CAP
– 示例应用和配置文件
– 256KB 系统内可编程闪存
– 在所有功率模式下具有保持功能的 8KB RAM
– 支持硬件调试
•
•
针对 GAP 中心和外围作用的一般应用
距离临近，加速计，简单关键字，和电池
GATT 服务
– 扩展基带自动化，包括自动确认和地址解码
– 所有功率模式中对所有相关寄存器的保持
• 外设
•
BLE 软件栈内支持更多应用
– 多重配置选项
•
单芯片配置，允许应用运行在 CC2541 上-
Q1：
– 功能强大的 5 通道直接内存访问 (DMA)
– 红外 (IR) 生成电路
– 通用定时器（1 个 16 位，2 个 8 位）
– 具有捕捉功能的 32kHz 睡眠定时器
– 精确数字接收到的数字信号强度指示器 (RSSI) 支
持
•
针对外部微处理器上运行应用的网络处理器接
口
– BTool - 用于评估、开发和测试的 Windows PC
应用
– 支持空中下载更新
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SWRS128
CC2541-Q1
ZHCSCU4 –JUNE 2014
www.ti.com.cn
1.2 应用
•
•
•
•
•
•
2.4GHz 蓝牙低能耗系统
专有 2.4GHz 系统
遥控门锁（被动式遥感）
轮胎气压监视
•
•
•
•
•
•
诊断和维护
电缆更换
传感器节点
信息娱乐与媒体
智能手机连接
信标
接近传感
接口和控制
1.3 说明
CC2541-Q1 是一款针对蓝牙低功耗和专有 2.4GHz 应用的功耗优化型无线 MCU 解决方案。 此器件可构建
稳定耐用的网络节点，同时保证总物料成本低廉。 CC2541-Q1 结合了领先的 RF 收发器的出色性能以及符
合行业标准的增强型 8051 MCU、系统内可编程闪存、8KB RAM 和多种其它功能强大的特性和外设。
CC2541-Q1 非常适用于需要超低功耗的系统，具体由各种工作模式指定。 运行模式间较短的转换时间进一
步使低能耗变为可能。
CC2541-Q1 采用 6mm x 6mm QFN40 封装。
器件信息(1)
封装
部件号
CC2541F256TRHARQ1
封装尺寸
RHA (40)
RHA (40)
6.00mm x 6.00mm
6.00mm x 6.00mm
CC2541F256TRHATQ1
(1) 更多信息请参见 节 8，机械封装和可订购信息。
2
器件概述
版权 © 2014, Texas Instruments Incorporated
CC2541-Q1
www.ti.com.cn
ZHCSCU4 –JUNE 2014
1.4 功能方框图
图 1-1 所示为 CC2541-Q1 框图。
VDD (2 V–3.6 V)
DCOUPL
WATCHDOG
TIMER
ON-CHIP VOLTAGE
REGULATOR
RESET_N
RESET
XOSC_Q2
XOSC_Q1
32-MHz
POWER-ON RESET
BROWN OUT
CRYSTAL OSC
CLOCK MUX
and
CALIBRATION
P2_4
P2_3
P2_2
P2_1
P2_0
32.768-kHz
SLEEP TIMER
CRYSTAL OSC
HIGH-
DEBUG
INTERFACE
32-kHz
SPEED
RC-OSC
POWER MANAGEMENT CONTROLLER
RC-OSC
SRAM
RAM
PDATA
XRAM
IRAM
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
SFR
DMA
UNIFIED
IRQ CTRL
FLASH CTRL
1 KB SRAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
FIFOCTRL
RADIO REGISTERS
AES
ENCRYPTION
AND
DECRYPTION
DS
Link Layer Engine
ADC
AUDIO/DC
DEMODULATOR
MODULATOR
SDA
SCL
I2C
USART 0
RECEIVE
TRANSMIT
USART 1
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
DIGITAL
ANALOG
MIXED
B0301-13
图 1-1. 方框图
版权 © 2014, Texas Instruments Incorporated
器件概述
3
CC2541-Q1
ZHCSCU4 –JUNE 2014
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 3
修订历史记录............................................... 5
Terminal Configuration and Functions.............. 6
3.1 Pin Diagram .......................................... 6
3.2 Pin Descriptions ...................................... 7
Specifications ............................................ 8
4.1 Absolute Maximum Ratings .......................... 8
4.2 Handling Ratings ..................................... 8
4.3 Recommended Operating Conditions ................ 8
4.15 Analog Temperature Sensor ........................ 13
4.16 Comparator Characteristics ......................... 13
4.17 ADC Characteristics................................. 14
4.18 DC Characteristics .................................. 15
4.19 Control Input AC Characteristics.................... 15
4.20 SPI AC Characteristics.............................. 16
4.21 Debug Interface AC Characteristics ................ 17
4.22 Timer Inputs AC Characteristics .................... 18
4.23 Typical Characteristics .............................. 19
Detailed Description ................................... 21
5.1 Functional Block Diagram........................... 21
5.2 Block Descriptions................................... 21
Application Information............................... 24
6.1 Input/Output Matching............................... 24
6.2 Crystal ............................................... 25
2
3
4
5
6
4.4
Thermal Characteristics for RHA Package........... 8
4.5 Electrical Characteristics ............................. 9
4.6 General Characteristics .............................. 9
4.7 RF Receive Section................................. 10
4.8 RF Transmit Section ................................ 11
4.9 32-MHz Crystal Oscillator ........................... 11
4.10 32.768-kHz Crystal Oscillator ....................... 12
4.11 32-kHz RC Oscillator................................ 12
4.12 16-MHz RC Oscillator ............................... 12
4.13 RSSI Characteristics ................................ 13
4.14 Frequency Synthesizer Characteristics ............. 13
6.3
On-Chip 1.8-V Voltage Regulator Decoupling ...... 25
Power-Supply Decoupling and Filtering............. 25
6.4
7
8
器件和文档支持 .......................................... 26
7.1 文档支持............................................. 26
7.2 商标.................................................. 27
7.3 静电放电警告 ........................................ 27
7.4 术语表 ............................................... 27
机械封装和可订购信息 .................................. 27
4
内容
版权 © 2014, Texas Instruments Incorporated
CC2541-Q1
www.ti.com.cn
ZHCSCU4 –JUNE 2014
2 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
日期
修订版本
注释
最初发布。
2014 年 6 月
*
Copyright © 2014, Texas Instruments Incorporated
修订历史记录
5
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Product Folder Links: CC2541-Q1
CC2541-Q1
ZHCSCU4 –JUNE 2014
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3 Terminal Configuration and Functions
The CC2541-Q1 pinout is shown in Figure 3-1 and a short description of the pins follows.
3.1 Pin Diagram
40 39 38 37 36 35 34 33 32 31
GND
SCL
R_BIAS
1
2
30
29
28
27
26
25
24
23
22
21
AVDD4
AVDD1
AVDD2
RF_N
SDA
3
GND
4
P1_5
P1_4
P1_3
P1_2
P1_1
DVDD2
5
AGND
Exposed Die Attached Pad
RF_P
6
7
AVDD3
XOSC_Q2
XOSC_Q1
8
9
10
AVDD5
11 12 13 14 15 16 17 18 19 20
P0076-14
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 3-1. RHA PACKAGE (TOP VIEW)
6
Terminal Configuration and Functions
Copyright © 2014, Texas Instruments Incorporated
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3.2 Pin Descriptions
Table 3-1. Pin Descriptions
PINS
TYPE
DESCRIPTION
NAME
AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6
DCOUPL
DVDD1
DVDD2
GND
NO.
28
27
24
29
21
31
40
39
10
1
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (analog)
Power (digital)
Power (digital)
Power (digital)
Ground pin
Ground
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
2-V–3.6-V digital power-supply connection
2-V–3.6-V digital power-supply connection
Connect to GND
GND
—
4
The ground pad must be connected to a solid ground plane.
GND
Ground pin
Digital I/O
Connect to GND
P0_0
19
18
17
16
15
14
13
12
11
9
Port 0.0
P0_1
Digital I/O
Port 0.1
P0_2
Digital I/O
Port 0.2
P0_3
Digital I/O
Port 0.3
P0_4
Digital I/O
Port 0.4
P0_5
Digital I/O
Port 0.5
P0_6
Digital I/O
Port 0.6
P0_7
Digital I/O
Port 0.7
P1_0
Digital I/O
Port 1.0 – 20-mA drive capability
P1_1
Digital I/O
Port 1.1 – 20-mA drive capability
Port 1.2
P1_2
8
Digital I/O
P1_3
7
Digital I/O
Port 1.3
P1_4
6
Digital I/O
Port 1.4
P1_5
5
Digital I/O
Port 1.5
P1_6
38
37
36
35
34
33
32
30
20
26
Digital I/O
Port 1.6
P1_7
Digital I/O
Port 1.7
P2_0
Digital I/O
Port 2.0
P2_1/DD
P2_2/DC
P2_3/ OSC32K_Q2
P2_4/ OSC32K_Q1
RBIAS
RESET_N
RF_N
Digital I/O
Port 2.1 / debug data
Port 2.2 / debug clock
Digital I/O
Digital I/O, Analog I/O Port 2.3/32.768 kHz XOSC
Digital I/O, Analog I/O Port 2.4/32.768 kHz XOSC
Analog I/O
Digital input
RF I/O
External precision bias resistor for reference current
Reset, active-low
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P
SCL
25
2
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
I2C clock or digital I/O Can be used as I2C clock pin or digital I/O. Leave floating if not used. If
grounded disable pull up
SDA
3
I2C clock or digital I/O Can be used as I2C data pin or digital I/O. Leave floating if not used. If
grounded disable pull up
XOSC_Q1
XOSC_Q2
22
23
Analog I/O
Analog I/O
32-MHz crystal oscillator pin 1 or external clock input
32-MHz crystal oscillator pin 2
Copyright © 2014, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
UNIT
Supply voltage
All supply pins must have the same voltage
3.9
V
Voltage on any digital pin
Input RF level
VDD + 0.3 ≤ 3.9
V
10
dBm
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2 Handling Ratings
MIN
–40
–1
MAX
125
1
UNIT
Tstg
Storage temperature range
°C
All pins
Human Body Model (HBM), per AEC
Q100-002(1)
kV
V
Electrostatic discharge
(ESD) performance:
All pins
(Excluding pins 25 and 26)
VESD
–2
2
Charged Device Model (CDM), per AEC Q100-011
–500
500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
UNIT
Operating ambient temperature range, TA
Operating supply voltage
–40
2
105
3.6
°C
V
4.4 Thermal Characteristics for RHA Package
NAME
RΘJC
RΘJB
RΘJA
PsiJT
PsiJB
RθJC
DESCRIPTION
°C/W
AIR FLOW (m/s)(1)
Junction-to-case (top)
Junction-to-board
16.1
5.5
0.00
0.00
0.00
0.00
0.00
0.00
Junction-to-free air
Junction-to-package top
Junction-to-board
30.6
0.2
5.4
Junction-to-case (bottom)
1.0
(1) m/s = meters per second
8
Specifications
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4.5 Electrical Characteristics
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V,
1 Mbps, GFSK, 250-kHz deviation, Bluetooth low energy mode, and 0.1% BER
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
RX mode, standard mode, no peripherals active, low MCU
activity
18.3
RX mode, high-gain mode, no peripherals active, low MCU
activity
20.8
mA
TX mode, –20 dBm output power, no peripherals active, low
MCU activity
17.2
TX mode, 0 dBm output power, no peripherals active, low
MCU activity
18.6
270
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-
MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD and
sleep timer active; RAM and register retention
Icore
Core current consumption
Power mode 2. Digital regulator off; 16-MHz RCOSC and 32-
MHz crystal oscillator off; 32.768-kHz XOSC, POR, and sleep
timer active; RAM and register retention
µA
1
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
0.5
Low MCU activity: 32-MHz XOSC running. No radio or
peripherals. Limited flash access, no RAM access.
6.7
mA
Timer 1. Timer running, 32-MHz XOSC used
Timer 2. Timer running, 32-MHz XOSC used
Timer 3. Timer running, 32-MHz XOSC used
Timer 4. Timer running, 32-MHz XOSC used
Sleep timer, including 32.753-kHz RCOSC
ADC, when converting
90
90
Peripheral current consumption
(Adds to core current Icore for each
peripheral unit activated)
60
μA
Iperi
70
0.6
1.2
mA
4.6 General Characteristics
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE-UP AND TIMING
Digital regulator on, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of 16-MHz RCOSC
Power mode 1 → Active
4
120
500
μs
μs
Digital regulator off, 16-MHz RCOSC and 32-MHz crystal
oscillator off. Start-up of regulator and 16-MHz RCOSC
Power mode 2 or 3 → Active
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC,
with 32-MHz XOSC OFF
μs
μs
Active → TX or RX
With 32-MHz XOSC initially on
Proprietary auto mode
BLE mode
180
130
150
RX/TX turnaround
μs
RADIO PART
RF frequency range
Programmable in 1-MHz steps
2379
2496
MHz
2 Mbps, GFSK, 500-kHz deviation
2 Mbps, GFSK, 320-kHz deviation
1 Mbps, GFSK, 250-kHz deviation
1 Mbps, GFSK, 160-kHz deviation
500 kbps, MSK
Data rate and modulation format
250 kbps, GFSK, 160-kHz deviation
250 kbps, MSK
Copyright © 2014, Texas Instruments Incorporated
Specifications
9
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4.7 RF Receive Section
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V, fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
1 Mbps, GFSK, 250-kHz Deviation, Bluetooth low energy Mode, 0.1% BER
High-gain mode
Receiver sensitivity(1)(2)
–94
dBm
–88
Standard mode
Saturation(2)
Co-channel rejection(2)
BER < 0.1%
5
–6
dBm
dB
Wanted signal –67 dBm
±1 MHz offset, 0.1% BER, wanted signal –67 dBm
±2 MHz offset, 0.1% BER, wanted signal –67 dBm
±3 MHz offset, 0.1% BER, wanted signal –67 dBm
>6 MHz offset, 0.1% BER, wanted signal –67 dBm
Minimum interferer level < 2 GHz (Wanted signal –67 dBm)
Minimum interferer level [2 GHz, 3 GHz] (Wanted signal –67 dBm)
Minimum interferer level > 3 GHz (Wanted signal –67 dBm)
Minimum interferer level
–2
26
In-band blocking rejection(2)
dB
34
33
–21
–27
–8
Out-of-band blocking
rejection(2)
dBm
Intermodulation(2)
–36
dBm
kHz
Including both initial tolerance and drift. Sensitivity better than -67dBm,
250 byte payload. BER 0.1%
Frequency error tolerance(3)
–250
–80
250
80
Symbol rate error
tolerance(4)
Maximum packet length. Sensitivity better than –67 dBm, 250 byte
payload. BER 0.1%
ppm
ALL RATES/FORMATS
Spurious emission in RX.
Conducted measurement
f < 1 GHz
f > 1 GHz
–67
–57
dBm
dBm
Spurious emission in RX.
Conducted measurement
(1) The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command. The default value is standard
mode.
(2) Results based on standard-gain mode.
(3) Difference between center frequency of the received RF signal and local oscillator frequency
(4) Difference between incoming symbol rate and the internally generated symbol rate
10
Specifications
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4.8 RF Transmit Section
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dBm
dB
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting
0
Output power
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting
–20
20
Programmable output power Delivered to a single-ended 50-Ω load through a balun using
range
minimum recommended output power setting
f < 1 GHz
–52
–48
dBm
dBm
Spurious emission conducted f > 1 GHz
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Differential impedance as seen from the RF port (RF_P and RF_N)
toward the antenna
Optimum load impedance
70 +j30
Ω
Designs with antenna connectors that require conducted ETSI compliance at 64 MHz should insert an LC
resonator in front of the antenna connector. Use a 1.6-nH inductor in parallel with a 1.8-pF capacitor. Connect
both from the signal trace to a good RF ground.
4.9 32-MHz Crystal Oscillator
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
TYP
MAX UNIT
32
MHz
Crystal frequency accuracy
requirement(1)
–40
40 ppm
ESR
C0
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
6
1
60
7
Ω
pF
pF
ms
CL
10
16
0.25
The crystal oscillator must be in power down for a guard
time before it is used again. This requirement is valid for
all modes of operation. The need for power-down guard
time can vary with crystal type and load.
Power-down guard time
3
ms
(1) Including aging and temperature dependency, as specified by [1]
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4.10 32.768-kHz Crystal Oscillator
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Crystal frequency
32.768
kHz
Crystal frequency accuracy requirement(1)
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
–40
40
130
2
ppm
kΩ
pF
pF
s
ESR
C0
40
0.9
12
CL
16
0.4
(1) Including aging and temperature dependency, as specified by [1]
4.11 32-kHz RC Oscillator
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V.
PARAMETER
Calibrated frequency(1)
TEST CONDITIONS
MIN
TYP
32.753
±0.2%
0.4
MAX UNIT
kHz
Frequency accuracy after calibration
Temperature coefficient(2)
Supply-voltage coefficient(3)
Calibration time(4)
%/°C
%/V
ms
3
2
(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
(2) Frequency drift when temperature changes after calibration
(3) Frequency drift when supply voltage changes after calibration
(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to 0.
4.12 16-MHz RC Oscillator
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
16
MAX
UNIT
Frequency(1)
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy
Start-up time
±18%
±0.6%
10
μs
μs
Initial calibration time(2)
50
(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
12
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4.13 RSSI Characteristics
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Reduced gain by AGC algorithm
64
64
79
99
±6
1
Useful RSSI range(1)
dB
High gain by AGC algorithm
Reduced gain by AGC algorithm
RSSI offset(1)
dBm
High gain by AGC algorithm
Absolute uncalibrated accuracy(1)
Step size (LSB value)
dB
dB
All Other Rates/Formats
Standard mode
64
64
98
107
±3
1
Useful RSSI range(1)
High-gain mode
dB
Standard mode
RSSI offset(1)
dBm
High-gain mode
Absolute uncalibrated accuracy(1)
Step size (LSB value)
dB
dB
(1) Assuming CC2541-Q1 EM reference design. Other RF designs give an offset from the reported value.
4.14 Frequency Synthesizer Characteristics
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz
PARAMETER
TEST CONDITIONS
At ±1-MHz offset from carrier
MIN
TYP
–109
–112
–119
MAX
UNIT
Phase noise, unmodulated carrier
At ±3-MHz offset from carrier
At ±5-MHz offset from carrier
dBc/Hz
4.15 Analog Temperature Sensor
Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12-bit
/ 1°C
0.1 V
°C
Output
1480
4.5
1
Temperature coefficient
Voltage coefficient
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
Initial accuracy without calibration
Accuracy using 1-point calibration
Current consumption when enabled
±10
±5
°C
0.5
mA
4.16 Comparator Characteristics
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2541-Q1 reference designs, post-calibration.
PARAMETER
Common-mode maximum voltage
Common-mode minimum voltage
Input offset voltage
TEST CONDITIONS
MIN
TYP MAX UNIT
VDD
–0.3
1
V
mV
µV/°C
mV/V
nA
Offset vs temperature
Offset vs operating voltage
Supply current
16
4
230
0.15
Hysteresis
mV
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4.17 ADC Characteristics
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
VDD is voltage on AVDD5 pin
VDD is voltage on AVDD5 pin
MIN
0
TYP
MAX
UNIT
V
Input voltage
VDD
VDD
VDD
External reference voltage
0
V
External reference voltage differential VDD is voltage on AVDD5 pin
0
V
Input resistance, signal
Full-scale signal(1)
Simulated using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
197
2.97
5.7
kΩ
V
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
9.3
10.3
6.5
ENOB(1)
Effective number of bits
bits
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
9.7
10-bit setting, clocked by RCOSC
12-bit setting, clocked by RCOSC
7-bit setting, both single and differential
Single ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
Single-ended input, 12-bit setting(1)
Differential input, 12-bit setting(1)
Single-ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
10.9
0–20
–75.2
–86.6
70.2
79.3
78.8
88.9
Useful power bandwidth
Total harmonic distortion
kHz
dB
THD
Signal to nonharmonic ratio
dB
dB
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
CMRR
Common-mode rejection ratio
Crosstalk
>84
>84
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
dB
Offset
Midscale
–3
0.68%
0.05
0.9
mV
Gain error
12-bit setting, mean(1)
12-bit setting, maximum(1)
12-bit setting, mean(1)
DNL
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
4.6
12-bit setting, maximum(1)
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Single ended input, 7-bit setting(1)
Single ended input, 9-bit setting(1)
Single ended input, 10-bit setting(1)
Single ended input, 12-bit setting(1)
Differential input, 7-bit setting(1)
Differential input, 9-bit setting(1)
Differential input, 10-bit setting(1)
Differential input, 12-bit setting(1)
7-bit setting
13.3
10
29
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
20
SINAD
(–THD+N)
Signal-to-noise-and-distortion
dB
9-bit setting
36
Conversion time
μs
10-bit setting
68
12-bit setting
132
(1) Measured with 300-Hz sine-wave input and VDD as reference.
14 Specifications
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ADC Characteristics (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
4
MAX
UNIT
mA
Power consumption
Internal reference VDD coefficient
mV/V
Internal reference temperature
coefficient
0.4
mV/10°C
V
Internal reference voltage
1.24
4.18 DC Characteristics
TA = 25°C, VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Logic-0 input voltage
0.5
Logic-1 input voltage
2.4
–50
–50
V
Logic-0 input current
Input equals 0 V
50
50
nA
nA
kΩ
V
Logic-1 input current
Input equals VDD
I/O-pin pullup and pulldown resistors
Logic-0 output voltage, 4- mA pins
Logic-1 output voltage, 4-mA pins
Logic-0 output voltage, 20- mA pins
Logic-1 output voltage, 20-mA pins
20
Output load 4 mA
Output load 4 mA
Output load 20 mA
Output load 20 mA
0.5
0.5
2.5
2.5
V
V
V
4.19 Control Input AC Characteristics
TA = –40°C to 105°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
16
32
MHz
See item 1, Figure 4-1. This is the shortest pulse that is recognized
as a complete reset pin request. Note that shorter pulses may be
recognized but do not lead to complete reset of all modules within the
chip.
RESET_N low duration
Interrupt pulse duration
1
µs
ns
See item 2, Figure 4-1.This is the shortest pulse that is recognized as
an interrupt request.
20
RESET_N
1
2
Px.n
T0299-01
Figure 4-1. Control Input AC Characteristics
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4.20 SPI AC Characteristics
TA = –40°C to 105°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
250
250
TYP MAX UNIT
Master, RX and TX
Slave, RX and TX
Master
t1
SCK period
ns
SCK duty cycle
SSN low to SCK
50%
Master
63
63
63
63
t2
t3
ns
Slave
Master
SCK to SSN high
ns
Slave
t4
t5
t6
t7
MOSI early out
MOSI late out
MISO setup
MISO hold
Master, load = 10 pF
Master, load = 10 pF
Master
7
ns
ns
ns
ns
ns
ns
ns
ns
10
90
10
Master
SCK duty cycle
MOSI setup
MOSI hold
Slave
50%
t10
t11
t9
Slave
35
10
Slave
MISO late out
Slave, load = 10 pF
Master, TX only
Master, RX and TX
Slave, RX only
Slave, RX and TX
95
8
4
Operating frequency
MHz
8
4
SCK
t2
t3
SSN
t4
t5
MOSI
D0
X
D1
t6
t7
MISO
X
D0
X
T0478-01
Figure 4-2. SPI Master AC Characteristics
16
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SCK
t2
t3
SSN
MISO
MOSI
t8
t9
D0
X
D1
t10
t11
X
D0
X
T0479-01
Figure 4-3. SPI Slave AC Characteristics
4.21 Debug Interface AC Characteristics
TA = –40°C to 105°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
fclk_dbg
Debug clock frequency (see Figure 4-4)
Allowed high pulse on clock (see Figure 4-4)
Allowed low pulse on clock (see Figure 4-4)
12
t1
t2
35
35
ns
EXT_RESET_N low to first falling edge on debug clock (see
Figure 4-6)
t3
t4
t5
167
83
ns
ns
ns
Falling edge on clock to EXT_RESET_N high (see Figure 4-
6)
EXT_RESET_N high to first debug command (see Figure 4-
6)
83
t6
t7
t8
Debug data setup (see Figure 4-5)
Debug data hold (see Figure 4-5)
Clock-to-data delay (see Figure 4-5)
2
4
ns
ns
ns
Load = 10 pF
30
Time
DEBUG_CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4-4. Debug Clock – Basic Timing
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Time
DEBUG_CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 4-5. Debug Enable Timing
Time
DEBUG_CLK
P2_2
DEBUG_DATA
(to CC2541)
P2_1
DEBUG_DATA
(from CC2541)
P2_1
t6
t7
t8
Figure 4-6. Data Setup and Hold Timing
4.22 Timer Inputs AC Characteristics
TA = –40°C to 105°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system
clock rate (16 MHz or 32 MHz).
Input capture pulse duration
1.5
tSYSCLK
18
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4.23 Typical Characteristics
22
21.5
21
20.5
20
20.5
20
19.5
19
19.5
19
18.5
18.5
18
18
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (qC)
Temperature (qC)
Figure 4-7. RX Current vs Temperature
Figure 4-8. TX Current vs Temperature
-80
-82
-84
-86
-88
-90
-92
2.5
2
1.5
1
0.5
0
-0.5
-1
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (qC)
Temperature (qC)
Figure 4-9. RX Sensitivity vs Temperature
Figure 4-10. TX Power vs Temperature
20
19.5
19
19.2
19.1
19
18.9
18.8
18.7
18.6
18.5
18
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Voltage (V)
Voltage (V)
Figure 4-11. RX Current vs Supply Voltage
Figure 4-12. TX Current vs Supply Voltage
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Typical Characteristics (continued)
−84
4
2
−86
−88
−90
−92
0
−2
−4
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Frequency (MHz)
Voltage (V)
G007
G008
1-Mbps GFSK 250-kHz Standard Gain Setting
TA = 25°C
TX Power Setting = 0 dBm
TA = 25°C
Figure 4-13. RX Sensitivity vs Supply Voltage
Figure 4-14. TX Power vs Supply Voltage
−84
4
2
−86
−88
−90
−92
0
−2
−4
2400 2410 2420 2430 2440 2450 2460 2470 2480
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
Frequency (MHz)
1-Mbps GFSK 250-kHz Standard Gain Setting
TA = 25°C
G009
G010
TX Power Setting = 0 dBm
TA = 25°C
Vcc = 3 V
Vcc = 3 V
Figure 4-15. RX Sensitivity vs Frequency
Figure 4-16. TX Power vs Frequency
Table 4-1. Output Power(1)(2)
TX POWER Setting
Typical Output Power (dBm)
0xE1
0xD1
0xC1
0xB1
0xA1
0x91
0x81
0x71
0x61
0x51
0x41
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
(1) Measured on Texas Instruments CC2541-Q1 EM reference design with TA = 25°C, VDD = 3 V and fc =
2440 MHz. See SWRU191 for recommended register settings.
(2) 1 Mbsp, GFSK, 250-kHz deviation, Bluetooth low energy mode, 1% BER
20
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5 Detailed Description
5.1 Functional Block Diagram
A block diagram of the CC2541-Q1 is shown in Figure 5-1. The modules can be roughly divided into one
of three categories: CPU-related modules; modules related to power, test, and clock distribution; and
radio-related modules. In the following subsections, a short description of each module is given.
VDD (2 V–3.6 V)
WATCHDOG
TIMER
ON-CHIP VOLTAGE
REGULATOR
RESET_N
RESET
DCOUPL
XOSC_Q2
XOSC_Q1
32-MHz
POWER-ON RESET
BROWN OUT
CRYSTAL OSC
CLOCK MUX
and
CALIBRATION
P2_4
P2_3
P2_2
P2_1
P2_0
32.768-kHz
SLEEP TIMER
CRYSTAL OSC
HIGH-
DEBUG
INTERFACE
32-kHz
SPEED
RC-OSC
POWER MANAGEMENT CONTROLLER
RC-OSC
SRAM
RAM
PDATA
XRAM
IRAM
P1_7
P1_6
P1_5
P1_4
P1_3
P1_2
P1_1
P1_0
8051 CPU
CORE
MEMORY
ARBITRATOR
FLASH
FLASH
SFR
DMA
UNIFIED
IRQ CTRL
FLASH CTRL
1 KB SRAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
FIFOCTRL
RADIO REGISTERS
AES
ENCRYPTION
AND
DECRYPTION
DS
Link Layer Engine
ADC
AUDIO/DC
DEMODULATOR
MODULATOR
SDA
SCL
I2C
USART 0
RECEIVE
TRANSMIT
USART 1
TIMER 1 (16-Bit)
TIMER 2
(BLE LL TIMER)
RF_P
RF_N
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
DIGITAL
ANALOG
MIXED
B0301-13
Figure 5-1. CC2541-Q1 Block Diagram
5.2 Block Descriptions
A block diagram of the CC2541-Q1 is shown in Figure 5-1. The modules can be roughly divided into one
of three categories: CPU-related modules; modules related to power, test, and clock distribution; and
radio-related modules. In the following subsections, a short description of each module is given.
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5.2.1 CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses
(SFR, DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the
physical memories and all peripherals through the SFR bus. The memory arbiter has four memory-access
points, access of which can map to one of three physical memories: an SRAM, flash memory, and
XREG/SFR registers. It is responsible for performing arbitration and sequencing between simultaneous
memory accesses to the same physical memory.
The SFR bus is drawn conceptually in Figure 5-1 as a common bus that connects all hardware
peripherals to the memory arbiter. The SFR bus in the block diagram also provides access to the radio
registers in the radio register bank, even though these are indeed mapped into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The
SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off
(power mode 2 and mode 3).
The 256 KB flash block provides in-circuit programmable non-volatile program memory for the device,
and maps into the CODE and XDATA memory spaces.
5.2.2 Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-
bytewise programming. See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA
memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer
mode, addressing mode, source and destination pointers, and transfer count) is configured with DMA
descriptors that can be located anywhere in memory. Many of the hardware peripherals (AES core, flash
controller, USARTs, timers, ADC interface, etc.) can be used with the DMA controller for efficient
operation by performing data transfers between a single SFR or XREG address and flash/SRAM.
Each CC2541-Q1 contains a unique 48-bit IEEE address that can be used as the public device address
for a Bluetooth device. Designers are free to use this address, or provide their own, as described in the
Bluetooth specfication.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of
which is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced
even if the device is in a sleep mode (power modes 1 and 2) by bringing the CC2541-Q1 back to the
active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit
debugging. Through this debug interface, it is possible to erase or program the entire flash memory,
control which oscillators are enabled, stop and start execution of the user program, execute instructions
on the 8051 core, set code breakpoints, and single-step through instructions in the code. Using these
techniques, it is possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether
peripheral modules control certain pins or whether they are under software control, and if so, whether
each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected.
Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to ensure
flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external 32.768-kHz crystal oscillator or
an internal 32.753-kHz RC oscillator. The sleep timer runs continuously in all operating modes except
power mode 3. Typical applications of this timer are as a real-time counter or as a wake-up timer to get
out of power mode 1 or mode 2.
22
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A built-in watchdog timer allows the CC2541-Q1 to reset itself if the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times
out.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit
period value, and five individually programmable counter/capture channels, each with a 16-bit compare
value. Each of the counter/capture channels can be used as a PWM output or to capture the timing of
edges on input signals. It can also be configured in IR generation mode, where it counts timer 3 periods
and the output is ANDed with the output of timer 3 to generate modulated consumer IR signals with
minimal CPU interaction.
Timer 2 is a 40-bit timer. It has a 16-bit counter with a configurable timer period and a 24-bit overflow
counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or
the exact time at which transmission ends. There are two 16-bit output compare registers and two 24-bit
overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or
general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value.
Each of the counter channels can be used as PWM output.
USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide
double buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput
full-duplex applications. Each USART has its own high-precision baud-rate generator, thus leaving the
ordinary timers free for other uses. When configured as SPI slaves, the USARTs sample the input signal
using SCK directly instead of using some oversampling scheme, and are thus well-suited for high data
rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES
algorithm with 128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as
well as hardware support for CCM.
The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-
kHz, respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are
possible. The inputs can be selected as single-ended or differential. The reference voltage can be internal,
AVDD, or a single-ended or differential external signal. The ADC also has a temperature-sensor input
channel. The ADC can automate the process of periodic sampling or conversion over a sequence of
channels.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation. I2C support is compliant with the NXP I2C specification version 2.1 and supports standard mode
(up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are
supported, as well as master and slave modes.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an
analog signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The
comparator output is connected to the I/O controller interrupt detector and can be treated by the MCU as a
regular I/O pin interrupt.
Copyright © 2014, Texas Instruments Incorporated
Detailed Description
23
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CC2541-Q1
ZHCSCU4 –JUNE 2014
www.ti.com.cn
6 Application Information
Few external components are required for the operation of the CC2541-Q1. A typical application circuit is
shown in Figure 6-1.
2 V±3.6 V
Power Supply
Optional 32-kHz Crystal(1)
C331
C401
C321
R301
1 GND
RBIAS 30
AVDD4 29
AVDD1 28
AVDD2 27
RF_N 26
Antenna
(50 ꢀ)
2 SCL
L251
C251
C252
L261
3 SDA
4 GND
5 P1_5
6 P1_4
7 P1_3
8 P1_2
9 P1_1
10 DVDD2
L253
L252
CC2541Q1
C261
RF_P 25
DIE ATTACH PAD:
AVDD3 24
XOSC_Q2 23
XOSC_Q1 22
AVDD5 21
C262
C253
XTAL1
C221
C231
(1) 32-kHz crystal is mandatory when running the BLE protocol stack in low-power modes, except if the link layer is in
the standby state (Vol. 6 Part B Section 1.1 in [1]).
NOTE: Different antenna alternatives will be provided as reference designs.
Power supply decoupling capacitors are not shown. Digital I/O not connected
Figure 6-1. CC2541-Q1 Application Circuit
Table 6-1. Overview of External Components (Excluding Supply Decoupling Capacitors)
Component
C401
Description
Value
1 µF
Decoupling capacitor for the internal 1.8-V digital voltage regulator
Precision resistor ±1%, used for internal biasing
R301
56 kΩ
6.1 Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize
performance. The balun can be implemented using low-cost discrete inductors and capacitors. See
reference design, CC2541-Q1EM, for recommended balun.
6.2 Crystal
24
Application Information
Copyright © 2014, Texas Instruments Incorporated
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Product Folder Links: CC2541-Q1
CC2541-Q1
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ZHCSCU4 –JUNE 2014
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz
crystal oscillator. See Section 4.9 for details. The load capacitance seen by the 32-MHz crystal is given
by:
1
CL =
+ Cparasitic
1
1
+
C221 C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the
32.768-kHz crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low
sleep-current consumption and accurate wake-up times are needed. The load capacitance seen by the
32.768-kHz crystal is given by:
1
CL =
+ Cparasitic
1
1
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
6.3 On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling
capacitor (C471) for stable operation.
6.4 Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in
an application. TI provides a compact reference design that should be followed very closely.
版权 © 2014, Texas Instruments Incorporated
Application Information
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CC2541-Q1
ZHCSCU4 –JUNE 2014
www.ti.com.cn
7 器件和文档支持
7.1 文档支持
7.1.1 相关文档ꢀ
1. Bluetooth® Core 技术规范文档，版本 4.0
http://www.bluetooth.com/SiteCollectionDocuments/Core_V40.zip
2. 适用于 2.4GHz IEEE 802.15.4 和 ZigBee® 应用的 CC253x 片上系统解决方案/适用于 2.4GHz 低功耗蓝
牙应用的 CC2541-Q1 片上系统解决方案（文献编号 SWRU191）
3. CC254x 使用 TPS62730 节省电流（文献编号 SWRA365）。
7.1.1.1 其他信息
德州仪器 (TI) 为工业和消费类应用中所使用的专有应用和标准无线应用提供各种经济实用的低功耗射频解决
方案。 其中包括适用于 1GHz 以下频段和 2.4GHz 频段的射频收发器、射频发送器、射频前端和片上系统
以及各种软件解决方案。
此外，德州仪器 (TI) 还提供广泛的相关支持，例如开发工具、技术文档、参考设计、应用专业技术、客户支
持、第三方服务以及大学计划。
低功耗射频 E2E 在线社区设有技术支持论坛并提供视频和博客，您有机会在此与全球同领域工程师交流互
动。
凭借丰富的供选产品解决方案、可实现的最终应用以及广泛的技术支持，德州仪器 (TI) 能够为您提供最全面
的低功耗射频产品组合。 专业打造射频技术！
有关低功耗射频的详细信息，请参见节 7.1.1.2、节 7.1.1.3 和节 7.1.1.4。
7.1.1.2 德州仪器 (TI) 低功耗射频网站
•
•
•
论坛、视频和博客
射频设计帮助
E2E 交流互动
访问 www.ti.com/lprf-forum 立即体验。
7.1.1.3 德州仪器 (TI) 低功耗射频开发者网络
德州仪器 (TI) 建立了一个大型低功耗射频开发合作伙伴网络，帮助客户加快应用开发。 此网络中包括推荐
的公司、射频顾问和独立设计工作室，他们可提供一系列硬件模块产品和设计服务，其中包括：
•
•
•
射频电路、低功耗射频和 ZigBee® 设计服务
低功耗射频和 ZigBee 模块解决方案以及开发工具
射频认证服务和射频电路制造
需要有关模块、工程服务或开发工具的帮助？
请搜索低功耗射频开发者网络工具查找适合的合作伙伴。
www.ti.com/lprfnetwork
26
器件和文档支持
版权 © 2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: CC2541-Q1
CC2541-Q1
www.ti.com.cn
ZHCSCU4 –JUNE 2014
7.1.1.4 低功耗射频电子新闻简报
通过低功耗射频电子新闻简报，您能够了解到最新的产品、新闻稿、开发者相关新闻以及关于德州仪器 (TI)
低功耗射频产品其它新闻和活动。 低功耗射频电子新闻简报文章包含可获取更多在线信息的链接。
访问
www.ti.com/lprfnewsletter 立即注册
7.2 商标
SimpleLink is a trademark of Texas Instruments.
蓝牙 is a registered trademark of Bluetooth SIG, Inc..
ZigBee is a registered trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
7.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
7.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
8 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知
且不对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
机械封装和可订购信息
27
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产品主页链接: CC2541-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC2541F256TRHARQ1
CC2541F256TRHATQ1
ACTIVE
VQFN
VQFN
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
CC2541Q1
F256
ACTIVE
RHA
NIPDAU
CC2541Q1
F256
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040H
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
0.5
0.3
A
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
PIN 1 INDEX AREA
6.1
5.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
2X 4.5
EXPOSED
THERMAL PAD
11
20
36X 0.5
10
21
SEE SIDE WALL
DETAIL
2X
41
SYMM
4.5
4.5 0.1
SEE TERMINAL
DETAIL
1
30
0.3
0.2
40X
40
31
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
SYMM
0.5
0.3
40X
4219055/B 08/22/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.5)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
4X
(1.27)
(
0.2) TYP
VIA
(0.73)
(5.8)
TYP
4X
41
SYMM
(1.46)
36X (0.5)
10
21
(R0.05)
TYP
11
(0.73) TYP
4X (1.46)
20
4X (1.27)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219055/B 08/22/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.46) TYP
9X ( 1.26)
(R0.05) TYP
40
31
40X (0.6)
1
30
40X (0.25)
41
(1.46)
TYP
SYMM
(5.8)
36X (0.5)
10
21
METAL
TYP
11
20
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
70% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X
4219055/B 08/22/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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