CC2620F128RSMR [TI]
具有 128kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M3 Zigbee® RF4CE 无线 MCU | RSM | 32 | -40 to 85;型号: | CC2620F128RSMR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 128kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M3 Zigbee® RF4CE 无线 MCU | RSM | 32 | -40 to 85 无线 闪存 |
文件: | 总54页 (文件大小:3048K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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CC2620
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
CC2620 SimpleLink™ ZigBee® RF4CE 无线 MCU
1 器件概述
1.1 特性
1
• 微控制器
• 外部系统
– 强大的 ARM® Cortex®-M3
– EEMBC CoreMark®评分:142
– 高达 48MHz 的时钟速度
– 片上内部 DC-DC 转换器
– 极少的外部组件
– 无缝集成 SimpleLink™CC2590 和 CC2592 范围
扩展器
– 128KB 系统内可编程闪存
– ROM 中的 TI-RTOS 和 蓝牙®软件
• 低功耗
– 宽电源电压范围
– 高达 28KB 系统 SRAM,其中 20KB 为超低泄漏
静态随机存取存储器 (SRAM)
– 8KB SRAM,适用于缓存或系统 RAM 使用
– 2 引脚 cJTAG 和 JTAG 调试
– 支持无线升级 (OTA)
– 正常工作电压:1.8V 至 3.8V
– 外部稳压器模式:1.7V 至 1.95V
– 有源模式 RX:5.9mA
– 有源模式 TX (0dBm):6.1mA
– 有源模式 TX (+5dBm):9.1mA
– 有源模式 MCU:61µA/MHz
– 有源模式 MCU:48.5 CoreMark/mA
• 超低功耗传感器控制器
– 可独立于系统其余部分自主运行
– 16 位架构
– 2KB 超低泄漏代码和数据 SRAM
• 高效代码尺寸架构,只读存储器 (ROM) 中装载驱动
程序、IEEE 802.15.4 MAC、 和引导加载程序
– 有源模式传感器控制器:
0.4mA + 8.2μA/MHz
– 待机电流:1.1μA(RTC 运行,RAM/CPU 保
持)
• 封装符合 RoHS 标准
– 关断电流:100nA(发生外部事件时唤醒)
• 射频 (RF) 部分
– 4mm × 4mm RSM VQFN32 封装(10 个
GPIO)
– 7mm × 7mm RGZ VQFN48 封装(31 个
GPIO)
– 2.4GHz RF 收发器,符合 IEEE 802.15.4 PHY
和 MAC
• 外设
– 出色的接收器灵敏度(–100dBm)、可选择性和阻
断性能
– 所有数字外设引脚均可连接任意 GPIO
– 105dB 的链路预算
– 最高达 +5dBm 的可编程输出功率
– 单端或差分 RF 接口
– 四个通用定时器模块
(8 × 16 位或 4 × 32 位,均采用脉宽调制
(PWM))
– 12 位模数转换器 (ADC)、200MSPS、8 通道模
拟多路复用器
– 适用于符合各项全球射频规范的系统
– ETSI EN 300 328(欧洲)
– EN 300 440 2 类(欧洲)
– FCC CFR47 第 15 部分(美国)
– ARIB STD-T66(日本)
• 工具和开发环境
– 持续时间比较器
– 超低功耗模拟比较器
– 可编程电流源
– UART
– 2 个同步串行接口 (SSI)(SPI、MICROWIRE 和
TI)
– 功能全面的低成本开发套件
– 针对不同 RF 配置的多种参考设计
– 数据包监听器 PC 软件
– Sensor Controller Studio
– RemoTI™Target Emulator
– SmartRF™Studio
– SmartRF Flash Programmer2
– IAR Embedded Workbench®(用于 ARM)
– Code Composer Studio™
– CCS Cloud
– I2C
– I2S
– 实时时钟 (RTC)
– AES-128 安全模块
– 真随机数发生器 (TRNG)
– 10、15 或 31 个 GPIO,具体取决于所用封装选
项
– 支持八个电容感测按钮
– 集成温度传感器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SWRS178
CC2620
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
www.ti.com.cn
1.2 应用
•
•
•
•
遥控
•
•
•
•
DVD
机顶盒
互联网电视 (OTT)
消费类电子产品
HID 应用
电视 (TV)
媒体播放器
1.3 说明
CC2620 器件是一款无线微控制器 (MCU),主要适用于 ZigBee®RF4CE 远程控制 应用,涉及控制器和目标
节点。
此器件属于 SimpleLink™ CC26xx 系列中的经济高效型超低功耗 2.4GHz RF 器件。它具有极低的有源 RF
和 MCU 电流以及低功耗模式流耗,可确保卓越的电池使用寿命,适合小型纽扣电池供电以及在能源采集型
应用中 使用。
SimpleLink Bluetooth 低功耗 CC2620 器件含有一个 32 位 ARM® Cortex®-M3 内核(与主处理器工作频率
同为 48MHz),并且具有丰富的外设功能集,其中包括一个独特的超低功耗传感器控制器。此传感器控制
器非常适合连接外部传感器,还适合用于在系统其余部分处于睡眠模式的情况下自主收集模拟和数字数据。
因此,CC2620 器件成为 ZigBee RF4CE 远程控制的理想选择, 支持 语音、运动控制、RF-IR 混合远程控
制以及电容触控式 qwerty 键盘和 STB/目标节点。
CC2620 无线 MCU 的电源和时钟管理以及无线系统需要采用特定配置并由软件处理才能正确运行,这已在
TI-RTOS 中实现。TI 建议将此软件框架应用于针对器件的全部应用程序开发过程。完整的 TI-RTOS 和器件
驱动程序以源代码形式免费提供,下载地址:www.ti.com。
IEEE 802.15.4 MAC 嵌入在 ROM 中,并在 ARM® Cortex®-M0 处理器上单独运行。此架构可改善整体系统
性能和功耗,并释放闪存以供应用。
此器件的软件协议栈支持包括 ZigBee RF4CE 协议栈 (RemoTI),可从 www.ti.com.cn 免费获取。
器件信息(1)
封装
产品型号
封装尺寸(标称值)
7.00mm x 7.00mm
4.00mm x 4.00mm
CC2620F128RGZ
CC2620F128RSM
VQFN (48)
VQFN (32)
(1) 详细信息请参见 节 9。
2
器件概述
版权 © 2015–2016, Texas Instruments Incorporated
CC2620
www.ti.com.cn
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
1.4 功能框图
图 1-1给出了 CC2620 器件的框图。
中的功能框图
SimpleLink CC26xx Wireless MCU
RF Core
cJTAG
Main CPU:
ROM
ADC
ADC
ARM
Cortex-M3
128-KB
Flash
Digital PLL
DSP modem
8-KB
cache
Up to 48 MHz
61 µA/MHz
4-KB
SRAM
ARM
Cortex-M0
20-KB
SRAM
ROM
General Peripherals / Modules
Sensor Controller
2
4× 32-bit Timers
I C
Sensor Controller Engine
UART
I2S
2× SSI (SPI, µW, TI)
Watchdog Timer
12-bit ADC, 200 ks/s
2× Comparator
10 / 14 / 15 / 31 GPIOs
AES
TRNG
2
SPI-I C Digital Sensor IF
Temp. / Batt. Monitor
Constant Current Source
32 ch. µDMA
RTC
Time-to-digital Converter
2-KB SRAM
DC-DC Converter
Copyright © 2016, Texas Instruments Incorporated
图 1-1. 方框图
版权 © 2015–2016, Texas Instruments Incorporated
器件概述
3
CC2620
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Related Products ..................................... 6
Terminal Configuration and Functions.............. 7
4.1 Pin Diagram – RGZ Package ........................ 7
4.2 Signal Descriptions – RGZ Package ................. 8
4.3 Pin Diagram – RSM Package....................... 10
4.4 Signal Descriptions – RSM Package ............... 11
Specifications ........................................... 12
5.1 Absolute Maximum Ratings......................... 12
5.2 ESD Ratings ........................................ 12
5.3 Recommended Operating Conditions............... 12
5.4 Power Consumption Summary...................... 13
5.5 General Characteristics ............................. 13
5.20 Thermal Resistance Characteristics ................ 21
5.21 Timing Requirements ............................... 22
5.22 Switching Characteristics ........................... 22
5.23 Typical Characteristics .............................. 23
Detailed Description ................................... 27
6.1 Overview ............................................ 27
6.2 Functional Block Diagram........................... 27
6.3 Main CPU ........................................... 28
6.4 RF Core ............................................. 28
6.5 Sensor Controller ................................... 29
6.6 Memory.............................................. 30
6.7 Debug ............................................... 30
6.8 Power Management................................. 31
6.9 Clock Systems ...................................... 32
6.10 General Peripherals and Modules .................. 32
6.11 Voltage Supply Domains............................ 33
6.12 System Architecture................................. 33
Application, Implementation, and Layout ......... 34
7.1 Application Information.............................. 34
6
2
3
4
5
7
8
5.6
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
RX ................................................... 14
IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) –
TX ................................................... 14
7.2
4 × 4 External Single-ended (4XS) Application
Circuit ............................................... 36
5.7
器件和文档支持 .......................................... 38
8.1 器件命名规则 ........................................ 38
8.2 工具与软件 .......................................... 39
8.3 文档支持............................................. 40
8.4 德州仪器 (TI) 低功耗射频网站....................... 40
8.5 低功耗射频电子新闻简报 ............................ 40
8.6 社区资源............................................. 40
8.7 其他信息............................................. 41
8.8 商标.................................................. 41
8.9 静电放电警告 ........................................ 41
8.10 出口管制提示 ........................................ 41
8.11 Glossary ............................................. 41
机械、封装和可订购信息................................ 41
9.1 封装信息............................................. 41
5.8 24-MHz Crystal Oscillator (XOSC_HF) ............. 15
32.768-kHz Crystal Oscillator (XOSC_LF).......... 15
5.9
5.10 48-MHz RC Oscillator (RCOSC_HF) ............... 16
5.11 32-kHz RC Oscillator (RCOSC_LF)................. 16
5.12 ADC Characteristics................................. 16
5.13 Temperature Sensor ................................ 17
5.14 Battery Monitor...................................... 17
5.15 Continuous Time Comparator....................... 17
5.16 Low-Power Clocked Comparator ................... 18
5.17 Programmable Current Source ..................... 18
5.18 Synchronous Serial Interface (SSI) ................ 18
5.19 DC Characteristics .................................. 20
9
4
内容
版权 © 2015–2016, Texas Instruments Incorporated
CC2620
www.ti.com.cn
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
2 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from January 20, 2016 to July 5, 2016
Page
•
•
•
•
已添加 分离 VDDS 电源轨特性 ..................................................................................................... 1
Added option for up to 80-Ω ESR when CL is 6 pF or lower .................................................................. 15
Added tolerance for RCOSC_LF and RTC accuracy content ................................................................ 16
Added Figure 5-20, Supply Current vs Temperature .......................................................................... 24
Changes from December 2, 2015 to January 19, 2016
Page
•
•
•
•
•
Updated the Soc ADC internal voltage reference specification in Section 5.12 ........................................... 16
Moved all SSI parameters to Section 5.18 ...................................................................................... 18
Added 0-dBm setting to the TX Current Consumption vs Supply Voltage (VDDS) graph ................................ 23
Changed Figure 5-11, Receive Mode Current vs Supply Voltage (VDDS) ................................................. 23
已更改 节 8.3中列出的勘误表...................................................................................................... 40
Changes from February 22, 2015 to December 2, 2015
Page
•
•
•
•
•
•
•
•
•
•
•
Removed RHB package option from CC2620 .................................................................................... 6
Added motional inductance recommendation to the 24-MHz XOSC table ................................................. 15
Added SPI timing parameters ..................................................................................................... 18
Added VOH and VOL min and max values for 4-mA and 8-mA load ....................................................... 20
Added min and max values for VIH and VIL .................................................................................... 21
Added IEEE 802.15.4 Sensitivity vs Channel Frequency...................................................................... 23
Added RF Output Power vs Channel Frequency ............................................................................... 23
Added Figure 5-11, Receive Mode Current vs Supply Voltage (VDDS) ..................................................... 23
Changed Figure 5-19, SoC ADC ENOB vs Sampling Frequency (Input Frequency = FS / 10) .......................... 24
Clarified Brown Out Detector status and functionality in the Power Modes table. ......................................... 31
Added application circuit schematics and layout for 5XD and 4XS .......................................................... 34
Copyright © 2015–2016, Texas Instruments Incorporated
修订历史记录
5
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CC2620
ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
www.ti.com.cn
3 Device Comparison
Table 3-1. Device Family Overview
Device
PHY Support
Flash (KB) RAM (KB)
GPIO
Package(1)
CC2640F128xxx
CC2650F128xxx
CC2630F128xxx
CC2620F128xxx
Bluetooth low energy (Normal)
Multi-Protocol(2)
128
128
128
128
20
20
20
20
31, 15, 10
31, 15, 10
31, 15, 10
31, 10
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RHB, RSM
RGZ, RSM
IEEE 802.15.4 Zigbee(/6LoWPAN)
IEEE 802.15.4 (RF4CE)
(1) Package designator replaces the xxx in device name to form a complete device name, RGZ is 7-mm × 7-mm VQFN48, RHB is
5-mm × 5-mm VQFN32, RSM is 4-mm × 4-mm VQFN32, and YFV is 2.7-mm × 2.7-mm DSBGA.
(2) The CC2650 device supports all PHYs and can be reflashed to run all the supported standards.
3.1 Related Products
Wireless Connectivity
The wireless connectivity portfolio offers a wide selection of low-power RF solutions suitable
for a broad range of applications. The offerings range from fully customized solutions to turn
key offerings with pre-certified hardware and software (protocol).
Sub-1 GHz
Long-range, low-power wireless connectivity solutions are offered in a wide range of
Sub-1 GHz ISM bands.
Companion Products
Review products that are frequently purchased or used in conjunction with this product.
SimpleLink™ CC2650 Wireless MCU LaunchPad™ Kit
The CC2650 LaunchPad™ development kit brings easy Bluetooth® low energy connectivity
to the LaunchPad kit ecosystem with the SimpleLink ultra-low power CC26xx family of
devices. This LaunchPad kit also supports development for multi-protocol support for the
SimpleLink multi-standard CC2650 wireless MCU and the rest of CC26xx family of products:
CC2630 wireless MCU for ZigBee®/6LoWPAN and CC2640 wireless MCU for Bluetooth low
energy.
Reference Designs for CC2620
TI Designs Reference Design Library is a robust reference design library spanning analog,
embedded processor and connectivity. Created by TI experts to help you jump-start your
system design, all TI Designs include schematic or block diagrams, BOMs, and design files
to speed your time to market. Search and download designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2015–2016, Texas Instruments Incorporated
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ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
4 Terminal Configuration and Functions
4.1 Pin Diagram – RGZ Package
DIO_24 37
DIO_25 38
DIO_26 39
DIO_27 40
DIO_28 41
DIO_29 42
DIO_30 43
VDDS 44
24 JTAG_TMSC
23 DCOUPL
22 VDDS3
21 DIO_15
20 DIO_14
19 DIO_13
18 DIO_12
17 DIO_11
16 DIO_10
15 DIO_9
VDDR 45
X24M_N 46
X24M_P 47
VDDR_RF 48
14 DIO_8
13 VDDS2
Figure 4-1. RGZ Package
48-Pin VQFN
(7-mm × 7-mm) Pinout, 0.5-mm Pitch
I/O pins marked in Figure 4-1 in bold have high-drive capabilities; they are the following:
•
•
•
•
•
•
Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17
I/O pins marked in Figure 4-1 in italics have analog capabilities; they are the following:
•
•
•
•
•
•
•
•
Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30
Copyright © 2015–2016, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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4.2 Signal Descriptions – RGZ Package
Table 4-1. Signal Descriptions – RGZ Package
NAME
NO.
33
23
5
TYPE
DESCRIPTION
Output from internal DC-DC(1)
1.27-V regulated digital-supply decoupling capacitor(2)
DCDC_SW
DCOUPL
DIO_0
Power
Power
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_1
6
GPIO, Sensor Controller
DIO_2
7
GPIO, Sensor Controller
DIO_3
8
GPIO, Sensor Controller
DIO_4
9
GPIO, Sensor Controller
DIO_5
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
24
25
35
GPIO, Sensor Controller, high-drive capability
DIO_6
GPIO, Sensor Controller, high-drive capability
DIO_7
GPIO, Sensor Controller, high-drive capability
DIO_8
GPIO
DIO_9
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
JTAG_TMSC
JTAG_TCKC
RESET_N
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital I/O
Digital I/O
Digital input
JTAG TMSC, high-drive capability
JTAG TCKC
Reset, active-low. No internal pullup.
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RF_P
RF_N
1
2
RF I/O
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
VDDR
45
48
44
Power
Power
Power
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(3)
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4)
1.8-V to 3.8-V main chip supply(1)
VDDR_RF
VDDS
(1) For more details, see the technical reference manual (listed in 节 8.3).
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
8
Terminal Configuration and Functions
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ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
Table 4-1. Signal Descriptions – RGZ Package (continued)
NAME
NO.
13
22
34
3
TYPE
Power
DESCRIPTION
VDDS2
1.8-V to 3.8-V DIO supply(1)
1.8-V to 3.8-V DIO supply(1)
1.8-V to 3.8-V DC-DC supply
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
VDDS3
Power
VDDS_DCDC
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
Power
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
4
46
47
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
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Terminal Configuration and Functions
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4.3 Pin Diagram – RSM Package
DIO_8 25
DIO_9 26
16 DIO_4
15 DIO_3
VDDS 27
14 JTAG_TCKC
13 JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 28
VSS 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10 DIO_2
9
DIO_1
Figure 4-2. RSM Package
32-Pin VQFN
(4-mm × 4-mm) Pinout, 0.4-mm Pitch
I/O pins marked in Figure 4-2 in bold have high-drive capabilities; they are as follows:
•
•
•
•
•
•
Pin 8, DIO_0
Pin 9, DIO_1
Pin 10, DIO_2
Pin 13, JTAG_TMSC
Pin 15, DIO_3
Pin 16, DIO_4
I/O pins marked in Figure 4-2 in italics have analog capabilities; they are as follows:
•
•
•
•
•
Pin 22, DIO_5
Pin 23, DIO_6
Pin 24, DIO_7
Pin 25, DIO_8
Pin 26, DIO_9
10
Terminal Configuration and Functions
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4.4 Signal Descriptions – RSM Package
Table 4-2. Signal Descriptions – RSM Package
NAME
NO.
TYPE
DESCRIPTION
Output from internal DC-DC.(1). Tie to ground for external regulator mode
(1.7-V to 1.95-V operation)
DCDC_SW
18
Power
DCOUPL
DIO_0
12
8
Power
1.27-V regulated digital-supply decoupling capacitor(2)
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, High-drive capability, JTAG_TDO
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
DIO_1
9
DIO_2
10
15
16
22
23
24
25
26
13
14
21
DIO_3
DIO_4
GPIO, High-drive capability, JTAG_TDI
DIO_5
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
Digital/Analog I/O GPIO, Sensor Controller, Analog
DIO_6
DIO_7
DIO_8
DIO_9
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital I/O
Digital I/O
JTAG TMSC
JTAG TCKC
Digital Input
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
RX_TX
VDDR
4
RF I/O
Power
Power
Power
Power
Optional bias pin for the RF LNA
28
32
27
11
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC.(2)(3)
1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(2)(4)
1.8-V to 3.8-V main chip supply(1)
VDDR_RF
VDDS
VDDS2
1.8-V to 3.8-V GPIO supply(1)
1.8-V to 3.8-V DC-DC supply. Tie to ground for external regulator mode
(1.7-V to 1.95-V operation).
VDDS_DCDC
VSS
19
Power
Power
3, 7, 17, 20,
29
Ground
X32K_Q1
X32K_Q2
X24M_N
X24M_P
EGP
5
6
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Power
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Ground – Exposed Ground Pad
30
31
(1) See technical reference manual (listed in 节 8.3) for more details.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX UNIT
VDDR supplied by internal DC-DC regulator or
internal GLDO. VDDS_DCDC connected to VDDS on
PCB.
Supply voltage (VDDS, VDDS2,
and VDDS3)
–0.3
4.1
V
Supply voltage (VDDS(3) and
VDDR)
External regulator mode (VDDS and VDDR pins
connected on PCB)
–0.3
2.25
V
Voltage on any digital pin(4)(5)
–0.3
–0.3
–0.3
–0.3
–0.3
VDDSx + 0.3, max 4.1
V
V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Voltage on ADC input (Vin)
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
V
VDDS / 2.9
5
Input RF level
Tstg
dBm
°C
Storage temperature
–40
150
(1) All voltage values are with respect to ground, unless otherwise noted.
(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) In external regulator mode, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog-capable DIO.
(5) Each pin is referenced to a specific VDDSx (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see Table 6-3.
5.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS001(1)
All pins
±2500
VESD
Electrostatic discharge
V
RF pins
±750
±750
Charged device model (CDM), per JESD22-C101(2)
Non-RF pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Ambient temperature
–40
85
°C
Operating supply
voltage (VDDS and
VDDR), external
regulator mode
For operation in 1.8-V systems
(VDDS and VDDR pins connected on PCB, internal DC-DC cannot be used)
1.7
1.95
V
Operating supply
voltage VDDS
1.8
1.8
3.8
3.8
V
V
Operating supply
voltages VDDS2 and
VDDS3
For operation in battery-powered and 3.3-V systems
(internal DC-DC can be used to minimize power consumption)
VDDS < 2.7 V
Operating supply
voltages VDDS2 and
VDDS3
VDDS ≥ 2.7 V
1.9
3.8
V
12
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5.4 Power Consumption Summary
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V with internal DC-DC converter, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
100
150
1.1
MAX
UNIT
Reset. RESET_N pin asserted or VDDS below
Power-on-Reset threshold
nA
Shutdown. No clocks running, no retention
Standby. With RTC, CPU, RAM and (partial)
register retention. RCOSC_LF
Standby. With RTC, CPU, RAM and (partial)
register retention. XOSC_LF
1.3
2.8
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. RCOSC_LF
µA
Icore
Core current consumption
Standby. With Cache, RTC, CPU, RAM and
(partial) register retention. XOSC_LF
3.0
Idle. Supply Systems and RAM powered.
550
1.45 mA +
31 µA/MHz
Active. Core running CoreMark
(1)
Radio RX
5.9
6.1
6.1
9.1
Radio RX(2)
Radio TX, 0-dBm output power(1)
Radio TX, 5-dBm output power(2)
mA
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)(3)
Peripheral power domain
Serial power domain
Delta current with domain enabled
Delta current with domain enabled
20
13
µA
µA
Delta current with power domain enabled, clock
enabled, RF core idle
RF Core
237
µA
µDMA
Timers
I2C
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
130
113
12
µA
µA
µA
µA
µA
µA
Iperi
I2S
36
SSI
93
UART
164
(1) Single-ended RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS.
(2) Differential RF mode is optimized for RF performance. Measured on CC2650EM-5XD.
(3) Iperi is not supported in Standby or Shutdown.
5.5 General Characteristics
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
FLASH MEMORY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supported flash erase cycles before
failure
100
k Cycles
Flash page/sector erase current
Flash page/sector size
Flash write current
Flash page/sector erase time(1)
Flash write time(1)
Average delta current
12.6
4
mA
KB
mA
ms
µs
Average delta current, 4 bytes at a time
8.15
8
4 bytes at a time
8
(1) This number is dependent on Flash aging and will increase over time and erase cycles.
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5.6 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential mode. Measured at the CC2650EM-5XD
SMA connector, PER = 1%
Receiver sensitivity
–100
dBm
Single-ended mode. Measured on CC2650EM-4XS,
at the SMA connector, PER = 1%
Receiver sensitivity
–97
+4
dBm
dBm
dB
Measured at the CC2650EM-5XD SMA connector,
PER = 1%
Receiver saturation
Wanted signal at –82 dBm, modulated interferer at
±5 MHz, PER = 1%
Adjacent channel rejection
Alternate channel rejection
39
Wanted signal at –82 dBm, modulated interferer at
±10 MHz, PER = 1%
52
dB
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all
channels 2405 to 2480 MHz, PER = 1%
Channel rejection, ±15 MHz or
more
57
dB
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
64
64
65
68
63
63
65
67
dB
dB
dB
dB
dB
dB
dB
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the
sensitivity level), CW jammer, PER = 1%
Conducted measurement in a 50-Ω single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions, 30 MHz to
1000 MHz
–71
–62
dBm
dBm
Conducted measurement in a 50 Ω single-ended
load. Suitable for systems targeting compliance with
EN 300 328, EN 300 440 class 2, FCC CFR47, Part
15 and ARIB STD-T-66
Spurious emissions, 1 GHz to
12.75 GHz
Difference between the incoming carrier frequency
and the internally generated carrier frequency
Frequency error tolerance
Symbol rate error tolerance
>200
ppm
ppm
Difference between incoming symbol rate and the
internally generated symbol rate
>1000
RSSI dynamic range
RSSI accuracy
100
±4
dB
dB
5.7 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output power, highest setting
Delivered to a single-ended 50-Ω load through a balun
5
dBm
Measured on CC2650EM-4XS, delivered to a single-
ended 50-Ω load
Output power, highest setting
2
dBm
dBm
Output power, lowest setting
Error vector magnitude
Delivered to a single-ended 50-Ω load through a balun
–21
2%
At maximum output power
14
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IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX (continued)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
MIN
TYP
–43
–65
–76
–46
MAX
UNIT
dBm
Spurious emission conducted
measurement
Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328
and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
5.8 24-MHz Crystal Oscillator (XOSC_HF)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
Ω
ESR Equivalent series resistance(2)
ESR Equivalent series resistance(2)
6 pF < CL ≤ 9 pF
5 pF < CL ≤ 6 pF
20
80
Ω
Relates to load capacitance
(CL in Farads)
LM Motional inductance(2)
< 1.6 × 10–24 / CL
H
2
CL Crystal load capacitance(2)
Crystal frequency(2)(3)
Crystal frequency tolerance(2)(4)
Start-up time(3)(5)
5
9
pF
MHz
ppm
µs
24
–40
40
150
(1) Probing or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device.
(2) The crystal manufacturer's specification must satisfy this requirement
(3) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V
(4) Includes initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per
IEEE 802.15.4 specification.
(5) Kick-started based on a temperature and aging compensated RCOSC_HF using precharge injection.
5.9 32.768-kHz Crystal Oscillator (XOSC_LF)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Crystal frequency(1)
ESR Equivalent series resistance(1)
CL Crystal load capacitance(1)
TEST CONDITIONS
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
100
12
6
pF
(1) The crystal manufacturer's specification must satisfy this requirement
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5.10 48-MHz RC Oscillator (RCOSC_HF)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
48
MAX
UNIT
Frequency
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Start-up time
±1%
±0.25%
5
µs
(1) Accuracy relative to the calibration source (XOSC_HF).
5.11 32-kHz RC Oscillator (RCOSC_LF)
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Calibrated frequency(1)
Temperature coefficient
TEST CONDITIONS
MIN
TYP
32.8
50
MAX
UNIT
kHz
ppm/°C
(1) The frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator.
The RTC can be calibrated to an accuracy within ±500 ppm of 32.768 kHz by measuring the frequency error of RCOSC_LF relative to
XOSC_HF and compensating the RTC tick speed. The procedure is explained in Running Bluetooth® Low Energy on CC2640 Without
32 kHz Crystal.
5.12 ADC Characteristics
Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX UNIT
0
VDDS
V
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample rate
200
Offset
Internal 4.3-V equivalent reference(2)
Internal 4.3-V equivalent reference(2)
2
2.4
>–1
±3
Gain error
DNL(3) Differential nonlinearity
INL(4)
Integral nonlinearity
Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone
9.8
10
ENOB
Effective number of bits VDDS as reference, 200 ksps, 9.6-kHz input tone
Bits
dB
dB
dB
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone
11.1
–65
–69
–71
THD
Total harmonic distortion VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference(2), 200 ksps,
60
63
69
9.6-kHz input tone
Signal-to-noise
and
Distortion ratio
SINAD,
SNDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone
67
72
73
Spurious-free dynamic
range
SFDR
VDDS as reference, 200 ksps, 9.6-kHz input tone
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone
(1) Using IEEE Std 1241™-2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 5-21).
(4) For a typical example, see Figure 5-22.
16
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ADC Characteristics (continued)
Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
clock-
cycles
Conversion time
Serial conversion, time-to-output, 24-MHz clock
50
Current consumption
Current consumption
Internal 4.3-V equivalent reference(2)
VDDS as reference
0.66
0.75
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should
be initiated through the TIRTOS API in order to include the
gain/offset compensation factors stored in FCFG1.
Reference voltage
4.3(2)(5)
V
Fixed internal reference (input voltage scaling disabled).
For best accuracy, the ADC conversion should be initiated
through the TIRTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is
derived from the scaled value (4.3 V) as follows:
Vref = 4.3 V × 1408 / 4095
Reference voltage
1.48
V
VDDS as reference (Also known as RELATIVE) (input
voltage scaling enabled)
Reference voltage
Reference voltage
VDDS
V
V
VDDS as reference (Also known as RELATIVE) (input
voltage scaling disabled)
VDDS /
2.82(5)
200 ksps, voltage scaling enabled. Capacitive input, Input
impedance depends on sampling frequency and sampling
time
Input impedance
>1
MΩ
(5) Applied voltage must be within absolute maximum ratings (Section 5.1) at all times.
5.13 Temperature Sensor
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Range
4
–40
85
°C
Accuracy
±5
°C
Supply voltage coefficient(1)
3.2
°C/V
(1) Automatically compensated when using supplied driver libraries.
5.14 Battery Monitor
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
50
1.8
3.8
Accuracy
13
mV
5.15 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
VDDS
VDDS
UNIT
V
Input voltage range
External reference voltage
0
V
Internal reference voltage
Offset
DCOUPL as reference
1.27
3
V
mV
mV
µs
Hysteresis
<2
Decision time
Current consumption when enabled(1)
Step from –10 mV to 10 mV
0.72
8.6
µA
(1) Additionally, the bias module must be enabled when running in standby mode.
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5.16 Low-Power Clocked Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range
0
VDDS
V
Clock frequency
32
1.49–1.51
1.01–1.03
0.78–0.79
1.25–1.28
0.63–0.65
0.42–0.44
0.33–0.34
<2
kHz
Internal reference voltage, VDDS / 2
Internal reference voltage, VDDS / 3
Internal reference voltage, VDDS / 4
Internal reference voltage, DCOUPL / 1
Internal reference voltage, DCOUPL / 2
Internal reference voltage, DCOUPL / 3
Internal reference voltage, DCOUPL / 4
Offset
V
V
V
V
V
V
V
mV
Hysteresis
<5
mV
Decision time
Step from –50 mV to 50 mV
<1
clock-cycle
nA
Current consumption when enabled
362
5.17 Programmable Current Source
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
Current source programmable output range
Resolution
0.25–20
0.25
µA
Including current source at maximum
programmable output
Current consumption(1)
23
µA
(1) Additionally, the bias module must be enabled when running in standby mode.
5.18 Synchronous Serial Interface (SSI)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
S1(1) tclk_per (SSIClk period)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
system
clocks
Device operating as SLAVE
12
65024
S2(1) tclk_high (SSIClk high time)
S3(1) tclk_low (SSIClk low time)
Device operating as SLAVE
Device operating as SLAVE
0.5
0.5
tclk_per
tclk_per
One-way communication to SLAVE -
Device operating as MASTER
system
clocks
S1 (TX only)(1) tclk_per (SSIClk period)
S1 (TX and RX)(1) tclk_per (SSIClk period)
4
8
65024
65024
Normal duplex operation -
Device operating as MASTER
system
clocks
S2(1) tclk_high (SSIClk high time)
S3(1) tclk_low (SSIClk low time)
Device operating as MASTER
Device operating as MASTER
0.5
0.5
tclk_per
tclk_per
(1) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
18
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S1
S2
SSIClk
SSIFss
S3
SSITx
SSIRx
MSB
LSB
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
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S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.19 DC Characteristics
PARAMETER
TEST CONDITIONS
TA = 25°C, VDDS = 1.8 V
MIN
1.32
1.32
TYP
MAX
UNIT
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.54
0.26
1.58
0.21
71.7
21.1
V
V
0.32
0.32
V
IOCURR = 1
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
µA
µA
GPIO pulldown current
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
IH = 1, transition voltage for input read as 0 → 1
IH = 1, transition voltage for input read as 1 → 0
0.88
1.07
V
V
GPIO low-to-high input transition,
with hysteresis
GPIO high-to-low input transition,
with hysteresis
0.74
0.33
V
V
GPIO input hysteresis
IH = 1, difference between 0 → 1 and 1 → 0 points
TA = 25°C, VDDS = 3.0 V
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.68
0.33
2.72
0.28
V
V
V
V
IOCURR = 1
TA = 25°C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
277
µA
20
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DC Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
113
µA
GPIO high/low input transition,
no hysteresis
IH = 0, transition between reading 0 and reading 1
IH = 1, transition voltage for input read as 0 → 1
IH = 1, transition voltage for input read as 1 → 0
1.67
1.94
V
V
GPIO low-to-high input transition,
with hysteresis
GPIO high-to-low input transition,
with hysteresis
1.54
0.4
V
V
GPIO input hysteresis
IH = 1, difference between 0 → 1 and 1 → 0 points
TA = 25°C
Lowest GPIO input voltage reliably interpreted as a
«High»
VIH
VIL
0.8 VDDS(1)
VDDS(1)
Highest GPIO input voltage reliably interpreted as a
«Low»
0.2
(1) Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in 节 8.3 for more details.
5.20 Thermal Resistance Characteristics
NAME
RθJA
DESCRIPTION
Junction-to-ambient thermal resistance
RSM (°C/W)(1) (2)
RGZ (°C/W)(1) (2)
36.9
30.3
7.6
29.6
15.7
6.2
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
PsiJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
0.3
PsiJB
7.4
6.2
RθJC(bot)
2.1
1.9
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air).
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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5.21 Timing Requirements
MIN
0
NOM
MAX
UNIT
mV/µs
mV/µs
mV/µs
Rising supply-voltage slew rate
100
20
3
Falling supply-voltage slew rate
Falling supply-voltage slew rate, with low-power flash settings(1)
0
No limitation for negative
temperature gradient, or
outside standby mode
Positive temperature gradient in standby(2)
5
°C/s
µs
CONTROL INPUT AC CHARACTERISTICS(3)
RESET_N low duration
1
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Figure 7-1) must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
Section 5.11).
(3) TA = –40°C to +85°C, VDDS = 1.7 V to 3.8 V, unless otherwise noted.
5.22 Switching Characteristics
Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
WAKEUP AND TIMING
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Idle → Active
14
151
µs
µs
µs
Standby → Active
Shutdown → Active
1015
22
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5.23 Typical Characteristics
-95
-96
-95
-96
IEEE 802.15.4 5XD Sensitivity
IEEE 802.15.4 4XS Sensitivity
-97
-97
-98
-99
-98
-100
-101
-102
-103
-99
-100
Sensitivity 4XS
Sensitivity 5XD
-101
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
1.8
2.3
2.8
3.3
3.8
Temperature (èC)
VDDS (V)
D005
Figure 5-4. IEEE 802.15.4 Sensitivity vs Temperature
Figure 5-5. IEEE 802.15.4 Sensitivity vs Supply Voltage (VDDS)
-95
6
Sensitivity 4XS
Sensitivity 5XD
5
4
-96
-97
-98
4XS 2-dBm Setting
5XD 5-dBm Setting
3
2
1
0
-99
-100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
-101
2400 2410 2420 2430 2440 2450 2460 2470 2480
Frequency (MHz)
D019
Figure 5-6. IEEE 802.15.4 Sensitivity vs Channel Frequency
Figure 5-7. TX Output Power vs Temperature
8
7
6
5-dBm setting (5XD)
0-dBm setting (4XS)
5
4
3
2
6
5
4
3
2
1
1
5XD 5-dBm Setting
4XS 2-dBm Setting
0
-1
0
2400 2410 2420 2430 2440 2450 2460 2470 2480
1.8
2.3
2.8
VDDS (V)
3.3
3.8
Frequency (MHz)
D021
D003
Figure 5-9. TX Output Power
vs Channel Frequency
Figure 5-8. TX Output Power vs Supply Voltage (VDDS)
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Typical Characteristics (continued)
16
10.5
10
9.5
9
4XS 0-dBm Setting
4XS 2-dBm Setting
5XD 5-dBm Setting
4XS
5XD
15
14
13
12
11
10
9
8.5
8
7.5
7
6.5
6
8
7
5.5
5
6
5
4.5
4
4
1.8
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
1.8
2.05
2.3
2.55
2.8
3.05
3.3
3.55
3.8
Voltage (V)
D015
D016
Figure 5-10. TX Current Consumption
vs Supply Voltage (VDDS)
Figure 5-11. RX Mode Current vs Supply Voltage (VDDS)
7
12
10
8
5XD RX Current
4XS RX Current
6.8
6.6
6.4
6.2
6
6
4
5.8
5.6
2
5XD 5-dBm Setting
4XS 2-dBm Setting
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (èC)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
D001
Temperature (èC)
D002
Figure 5-12. RX Mode Current Consumption vs Temperature
Figure 5-13. TX Mode Current Consumption vs Temperature
5
3.1
Active Mode Current
Active Mode Current
4.5
4
3.05
3
3.5
3
2.95
2.9
2.5
2
1.8
2.85
2.3
2.8
3.3
3.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
VDDS (V)
D007
Temperature (èC)
D006
Figure 5-15. Active Mode (MCU Running, No Peripherals) Current
Consumption vs Supply Voltage (VDDS)
Figure 5-14. Active Mode (MCU Running, No Peripherals)
Current Consumption vs Temperature
24
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Typical Characteristics (continued)
1006.4
1006.2
1006
11.4
Fs= 200 kHz, No Averaging
Fs= 200 kHz, 32 samples averaging
11.2
11
10.8
10.6
10.4
10.2
10
1005.8
1005.6
1005.4
1005.2
1005
9.8
9.6
9.4
1004.8
200300 500 1000 2000
5000 10000 20000
100000
1.8
2.3
2.8
3.3
3.8
Input Frequency (Hz)
VDDS (V)
D009
D012
Figure 5-16. SoC ADC Effective Number of Bits vs Input
Frequency (Internal Reference, Scaling enabled)
Figure 5-17. SoC ADC Output vs Supply Voltage (Fixed Input,
Internal Reference)
10.5
1007.5
1007
ENOB Internal Reference (No Averaging)
ENOB Internal Reference (32 Samples Averaging)
10.4
10.3
10.2
10.1
10
1006.5
1006
9.9
1005.5
1005
9.8
9.7
1004.5
9.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
1k
10k
100k 200k
Temperature (èC)
Sampling Frequency (Hz)
D013
D009A
Figure 5-18. SoC ADC Output vs Temperature (Fixed Input,
Internal Reference)
Figure 5-19. SoC ADC ENOB vs Sampling Frequency
(Scaling enabled, input frequency = FS / 10)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
Temperature (èC)
D021
Figure 5-20. Standby Mode Supply Current vs Temperature
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Typical Characteristics (continued)
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
D010
ADC Code
Figure 5-21. SoC ADC DNL vs ADC Code (Internal Reference)
3
2
1
0
-1
-2
-3
-4
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200
ADC Code
D011
Figure 5-22. SoC ADC INL vs ADC Code (Internal Reference)
26
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6 Detailed Description
6.1 Overview
The core modules of the CC26xx product family are shown in Section 6.2.
6.2 Functional Block Diagram
SimpleLink CC26xx Wireless MCU
RF Core
cJTAG
Main CPU:
ROM
ADC
ADC
ARM
Cortex-M3
128-KB
Flash
Digital PLL
DSP modem
8-KB
cache
Up to 48 MHz
61 µA/MHz
4-KB
SRAM
ARM
Cortex-M0
20-KB
SRAM
ROM
General Peripherals / Modules
Sensor Controller
2
4× 32-bit Timers
I C
Sensor Controller Engine
UART
I2S
2× SSI (SPI, µW, TI)
Watchdog Timer
12-bit ADC, 200 ks/s
2× Comparator
10 / 14 / 15 / 31 GPIOs
AES
TRNG
2
SPI-I C Digital Sensor IF
Temp. / Batt. Monitor
Constant Current Source
32 ch. µDMA
RTC
Time-to-digital Converter
2-KB SRAM
DC-DC Converter
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6.3 Main CPU
The SimpleLink CC2620 Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the
application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
CM3 features include the following:
•
•
•
32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
Outstanding processing performance combined with fast interrupt handling
ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
–
–
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
–
Unaligned data access, enabling data to be efficiently packed into memory
•
•
•
•
•
•
•
•
•
•
•
•
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system, and memories
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Enhanced system debug with extensive breakpoint and trace capabilities
Serial wire trace reduces the number of pins required for debugging and tracing
Migration from the ARM7™ processor family for better performance and power efficiency
Optimized for single-cycle flash memory use
Ultralow-power consumption with integrated sleep modes
1.25 DMIPS per MHz
6.4 RF Core
The RF Core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high level, command-based API to the main CPU.
The RF core is capable of autonomously handling the time-critical aspects of the radio protocols (802.15.4
RF4CE) thus offloading the main CPU and leaving more resources for the user application.
The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM
Cortex-M0 processor is not programmable by customers.
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6.5 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals
in this domain may be controlled by the Sensor Controller Engine, which is a proprietary power-optimized
CPU. This CPU can read and monitor sensors or perform other tasks autonomously, thereby significantly
reducing power consumption and offloading the main CM3 CPU. The GPIOs that can be connected to the
Sensor Controller are listed in Table 6-1.
The Sensor Controller is set up using a PC-based configuration tool, called Sensor Controller Studio, and
potential use cases may be (but are not limited to):
•
•
•
•
•
•
•
•
•
Analog sensors using integrated ADC
Digital sensors using GPIOs, bit-banged I2C, and SPI
UART communication for sensor reading or debugging
Capacitive sensing
Waveform generation
Pulse counting
Keyboard scan
Quadrature decoder for polling rotation sensors
Oscillator calibration
NOTE
Texas Instruments provides application examples for some of these use cases, but not for all
of them.
The peripherals in the Sensor Controller include the following:
•
The low-power clocked comparator can be used to wake the device from any state in which the
comparator is active. A configurable internal reference can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
•
Capacitive sensing functionality is implemented through the use of a constant current source, a time-
to-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller will take
care of baseline tracking, hysteresis, filtering and other related functions.
•
The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC
can be triggered by many different sources, including timers, I/O pins, software, the analog
comparator, and the RTC.
•
•
The Sensor Controller also includes a SPI–I2C digital interface.
The analog modules can be connected to up to eight different GPIOs.
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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Table 6-1. GPIOs Connected to the Sensor Controller(1)
7 × 7 RGZ
DIO NUMBER
4 × 4 RSM
DIO NUMBER
ANALOG CAPABLE
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
30
29
28
27
26
25
24
23
7
9
8
7
6
5
2
1
0
6
5
4
3
2
1
0
(1) Depending on the package size, up to 16 pins can be connected to the Sensor Controller. Up to 8 of
these pins can be connected to analog modules.
6.6 Memory
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system
programmable.
The SRAM (static RAM) can be used for both storage of data and execution of code and is split into two
4-KB blocks and two 6-KB blocks. Retention of the RAM contents in standby mode can be enabled or
disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled,
the 8-KB cache can be used as a general-purpose RAM.
The ROM provides preprogrammed embedded TI RTOS kernel, Driverlib and lower layer protocol stack
software (802.15.4 MAC). It also contains a bootloader that can be used to reprogram the device using
SPI or UART.
6.7 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface.
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6.8 Power Management
To minimize power consumption, the CC2620 device supports a number of power modes and power
management features (see Table 6-2).
Table 6-2. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Active
Off
Off
Off
Off
Flash
On
Available
On
Off
SRAM
On
On
Off
Off
Radio
Available
Available
On
Off
Off
Off
Supply System
Current
Wake-up Time to CPU Active(1)
Register Retention
SRAM Retention
On
Duty Cycled
1 µA
Off
Off
1.45 mA + 31 µA/MHz
550 µA
14 µs
Full
0.15 µA
1015 µs
No
0.1 µA
1015 µs
No
–
151 µs
Partial
Full
Full
Full
Full
No
No
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
High-Speed Clock
Low-Speed Clock
Off
Off
Off
Off
Off
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
Available
Active
Available
Available
Available
Available
Available
Active
Off
Available
Available
Available
Available
Duty Cycled(2)
Active
Off
Off
Off
Off
Sensor Controller
Wake up on RTC
Off
Off
Wake up on Pin Edge
Wake up on Reset Pin
Brown Out Detector (BOD)
Power On Reset (POR)
Available
Available
Off
Off
Available
N/A
Active
Active
Active
N/A
(1) Not including RTOS overhead
(2) The Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold
between two recharge periods while in STANDBY may cause the BOD to lock the device upon wake-up until a Reset/POR releases it.
To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the
specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a
battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply
voltage again (for example, inserting new batteries).
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
any available clock source (see Table 6-2).
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event will bring the processor back into active mode.
In standby mode, only the always-on domain (AON) is active. An external wake-up event, RTC event, or
sensor-controller event is required to bring the device back to active mode. MCU peripherals with retention
do not need to be reconfigured when waking up again, and the CPU continues execution from where it
went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller.
The I/Os are latched with the value they had before entering shutdown mode. A change of state on any
I/O pin defined as a wake-up from Shutdown pin wakes up the device and functions as a reset trigger. The
CPU can differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the
reset status register. The only state retained in this mode is the latched I/O state and the Flash memory
contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independently of the main CPU, which means that the main CPU does not have to wake up, for
example, to execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current
and wake-up time that would otherwise be wasted. The Sensor Controller Studio enables the user to
configure the sensor controller and choose which peripherals are controlled and which conditions wake up
the main CPU.
6.9 Clock Systems
The CC2620 supports two external and two internal clock sources.
A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to
create a 48-MHz clock.
The 32-kHz crystal is optional. The low-speed crystal oscillator is designed for use with a 32-kHz watch-
type crystal.
The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal
oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
6.10 General Peripherals and Modules
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five
GPIOs have high drive capabilities (marked in bold in Section 4).
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas
Instruments synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver/transmitter function. It supports flexible baud-
rate generation up to a maximum of 3 Mbps .
Timer 0 is a general-purpose timer module (GPTM), which provides two 16-bit timers. The GPTM can be
configured to operate as a single 32-bit timer, dual 16-bit timers or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs. Each of these timers is functionally equivalent to Timer 0.
In addition to these four timers, the RF core has its own timer to handle timing for RF protocols; the RF
timer can be synchronized to the RTC.
The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface
is capable of 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys,
initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring
oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external
device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
32
Detailed Description
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The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data transfer tasks from the CM3 CPU, allowing for more efficient use of the processor and the
available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The
µDMA controller has dedicated channels for each supported on-chip module and can be programmed to
automatically perform transfers between peripherals and memory as the peripheral is ready to transfer
more data. Some features of the µDMA controller include the following (this is not an exhaustive list):
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes:
–
–
–
–
Memory-to-memory
Memory-to-peripheral
Peripheral-to-memory
Peripheral-to-peripheral
•
Data sizes of 8, 16, and 32 bits
The AON domain contains circuitry that is always enabled, except for in Shutdown (where the digital
supply is off). This circuitry includes the following:
•
The RTC can be used to wake the device from any state where it is active. The RTC contains three
compare and one capture registers. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be
compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used
instead of a crystal.
•
The battery monitor and temperature sensor are accessible by software and give a battery status
indication as well as a coarse temperature measure.
6.11 Voltage Supply Domains
The CC2620 device can interface to two or three different voltage domains depending on the package
type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output
pin is set with respect to the corresponding supply pin (VDDS, VDDS2 or VDDS3). lists the pin-to-VDDS
mapping.
Table 6-3. Pin Function to VDDS Mapping Table
Package
VQFN 7 × 7 (RGZ)
VQFN 5 × 5 (RHB)
VQFN 4 × 4 (RSM)
DIO 23–30
Reset_N
DIO 7–14
Reset_N
DIO 5–9
Reset_N
VDDS(1)
VDDS2
VDDS3
DIO 0–6
JTAG
DIO 0–4
JTAG
DIO 0–11
DIO 12–22
JTAG
N/A
N/A
(1) VDDS_DCDC must be connected to VDDS on the PCB.
6.12 System Architecture
Depending on the product configuration, CC26xx can function either as a Wireless Network Processor
(WNP—an IC running the wireless protocol stack, with the application running on a separate MCU), or as
a System-on-Chip (SoC), with the application and protocol stack running on the ARM CM3 core inside the
device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
Copyright © 2015–2016, Texas Instruments Incorporated
Detailed Description
33
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7 Application, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
Very few external components are required for the operation of the CC2620 device. This section provides
some general information about the various configuration options when using the CC2620 in an
application, and then shows two examples of application circuits with schematics and layout. This is only a
small selection of the many application circuit examples available as complete reference designs from the
product folder on www.ti.com.
Figure 7-1 shows the various RF front-end configuration options. The RF front end can be used in
differential- or single-ended configurations with the options of having internal or external biasing. These
options allow for various trade-offs between cost, board space, and RF performance. Differential operation
with external bias gives the best performance while single-ended operation with internal bias gives the
least amount of external components and the lowest power consumption. Reference designs exist for
each of these options.
Red = Not necessary if internal bias is used
6.8 pF
!ntenna
(50 hꢀm)
Pin 3 (RXTX)
2.4 nH
1 pF
To VDDR
pins
Pin 2 (RF N)
Pin 1 (RF P)
2 nH
1 pF
2 nH
6.2œ6.8 nH
2.4œ2.7 nH
10µF
12 pC
Optional
inductor.
Only
needed for
DCDC
Differential
operation
1 pF
10µH
operation
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
CC26xx
Pin 2 (RF N)
DCDC_SW
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
15 nH
(GND exposed die
attached pad)
Pin 1 (RF P)
2 nH
VDDS_DCDC
input
decoupling
10µFœ22µF
Single ended
operation
12 pC
1.2 pF
1.2 pF
!ntenna
(50 hꢀm)
Red = Not necessary if internal bias is used
Pin 3 (RXTX)
15 nH
24MHz
XTAL
2 nH
Pin 2 (RF N)
(Load caps
on chip)
12 pC
1.2 pF
1.2 pF
Single ended
operation with 2
antennas
!ntenna
(50 hꢀm)
15 nH
2 nH
Pin 1 (RF P)
12 pC
1.2 pF
1.2 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. CC2620 Application Circuit
34
Application, Implementation, and Layout
Copyright © 2015–2016, Texas Instruments Incorporated
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Figure 7-2 shows the various supply voltage configuration options. Not all power supply decoupling
capacitors or digital I/Os are shown. Exact pin positions will vary between the different package options.
For a detailed overview of power supply decoupling and wiring, see the TI reference designs and the
CC26xx technical reference manual (节 8.3).
Internal DC-DC Regulator
Internal LDO Regulator
External Regulator
To All VDDR Pins
To All VDDR Pins
1.7 Vœ1.95 V to All VDDR- and VDDS Pins Except VDDS_DCDC
9xt.
wegulator
10 ꢀF
10 ꢀF
2.2 ꢀF
VDDS
VDDS
VDDS
VDDS
10 ꢀH
CC26xx
CC26xx
CC26xx
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
NC
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
DCDC_SW Pin
Pin 3/4 (RXTX)
Pin 2 (RF N)
Pin 1 (RF P)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
(GND Exposed Die
Attached Pad)
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC Pin
VDDS_DCDC
Input Decoupling
10 ꢀFœ22 ꢀF
VDDS_DCDC
Input Decoupling
10 ꢀFœ22 ꢀF
24-MHz XTAL
(Load Caps
on Chip)
24-MHz XTAL
(Load Caps on Chip)
24-MHz XTAL
(Load Caps on Chip)
1.8 Vœ3.8 V
1.8 Vœ3.8 V
to All VDDS Pins
Supply Voltage
To All VDDS Pins
Copyright © 2016, Texas Instruments Incorporated
Figure 7-2. Supply Voltage Configurations
Copyright © 2015–2016, Texas Instruments Incorporated
Application, Implementation, and Layout
35
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7.2 4 × 4 External Single-ended (4XS) Application Circuit
VDD_EB
VDDR
VDDS
VDDS Decoupling Capacitors
VDDR Decoupling Capacitors
FL1
L1
Pin 11
Pin 27
Pin 19
Pin 28
Pin 32
DCDC_SW
2
1
1
2
BLM18HE152SN1
10 µH
C2
C5
10 µF
C8
C10
C16
100 nF
C6
C3
100 nF
C4
C9
DNM
100 nF
10 µF
DNM
100 nF
100 nF
Place L1 and
C8 close to pin 18
VDDS
VDDR
U1
DIO_0
27
8
9
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
VDDS
RF_N used for RX biasing.
DIO_1
DIO_2
11
19
28
32
VDDS2
VDDS_DCDC
VDDR
10
15
16
22
23
24
25
26
L21 may be removed at the
cost of 1 dB degraded
sensitivity
DIO_3/JTAG_TDO
DIO_4/JTAG_TDI
DIO_5
50-Ω
Antenna
VDDS
VDDR
DCDC_SW
DIO_6
18
DCDC_SW
DIO_7
R1
100 k
DIO_8
L21
1 2
4
DIO_9
RX/TX
RF_N
RF_P
C14
nRESET
2
1
L12
15 nH
nRESET
RF_P
1
2
21
14
13
RESET_N
JTAG_TCK
JTAG_TMS
JTAG_TCKC
JTAG_TMSC
2 nH
C12
C13
12 pF
X24M_P
X24M_N
31
30
C20
X24M_P
X24M_N
12
1.2 pF
1.2 pF
100 nF
DCOUPL
6
5
3
7
X32K_Q2
X32K_Q1
VSS
VSS
VSS
VSS
VSS
EGP
C19
1 µF
17
20
29
33
CC26XX_4X4
Y2
24 MHz
Y1
32.768 kHz
1
3
C22
DNM
C23
DNM
C17
12 pF
C18
2
4
12 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 7-3. 4 × 4 External Single-ended (4XS) Application Circuit
36
Application, Implementation, and Layout
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ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
7.2.1 Layout
Figure 7-4. 4 × 4 External Single-ended (4XS) Layout
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8 器件和文档支持
8.1 器件命名规则
为了标明产品开发周期的各个产品阶段,TI 为所有预生产部件号或日期代码标记分配了前缀。每个器件都具
有以下三个前缀/标识中的一个:X、P 或无(无前缀)(例如 CC2620 正在批量生产,因此未分配前缀/标
识)。
器件开发进化流程:
X
试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。
原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。
完全合格的芯片模型的生产版本。
P
无
生产器件已进行完全特性化,并且器件的质量和可靠性已经完全论证。TI 的标准保修证书适用。
预测显示原型器件(X 或者 P)的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定义,
德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的生产器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型(例如,RSM)。
要获得 CC2620 器件(采用 RSM 或 RGZ 封装类型)的订购部件号,请参见本文档的封装选项附录(访问
TI 网站 www.ti.com),或者联系您的 TI 销售代表。
yyy (R/T)
CC26 xx F128
PREFIX
X = Experimental device
Blank = Qualified device
R = Large Reel
T = Small Reel
DEVICE FAMILY
SimpleLink™ Multistandard
Wireless MCU
DEVICE
PACKAGE DESIGNATOR
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RHB = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
RSM = 32-pin VQFN (Very Thin Quad Flatpack No-Lead)
20 = RF4CE
30 = Zigbee
40 = Bluetooth
50 = Multi-Protocol
ROM version 1
Flash = 128KB
图 8-1. 器件命名规则
38
器件和文档支持
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ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
8.2 工具与软件
德州仪器 (TI) 提供大量的开发工具,其中包括评估处理器性能、生成代码、开发算法工具、以及完全集成和
调试软件及硬件模块的工具。
以下产品支持开发 CC2620 器件 应用的开发提供支持:
软件工具:
SmartRF Studio 7:
SmartRF Studio 是一款 PC 应用程序,可帮助无线电系统设计人员评估早期设计过程的 RF-IC。
•
•
•
•
测试无线数据包收发功能,连续波收发功能
将相关数据写入支持的评估板或调试器,评估定制板上的 RF 性能
可以不搭配任何硬件使用,但此时只能生成、编辑并导出无线配置设置
可与德州仪器 (TI) CCxxxx 系列 RF-IC 的多款开发套件搭配使用
Sensor Controller Studio:
Sensor Controller Studio 为 CC26xx 传感器控制器提供开发环境。此传感器控制器是 CC26xx 系列中的一
款专用功率优化型 CPU,可独立于系统 CPU 状态自主执行简单的后台任务。
•
•
•
允许使用 C 语言这类编程语言实现传感器控制器任务算法
输出传感器控制器接口驱动程序,其中整合了生成的传感器控制器机械代码和相关定义
通过使用集成传感器控制器任务测试和调试功能实现快速开发这有助于实现有效的传感器数据和算法验
证可视化。
IDE 和编译器:
Code Composer Studio:
•
•
•
•
带有项目管理工具和编辑器的集成开发环境
Code Composer Studio (CCS) 7.0 及更高版本内置对 CC26xx 系列器件的支持功能
优先支持的 XDS 调试器:XDS100v3、XDS110 和 XDS200
与 TI-RTOS 高度集成,支持 TI-RTOS 对象视图
IAR ARM Embedded Workbench
•
•
•
•
•
带有项目管理工具和编辑器的集成开发环境
IAR EWARM 7.80.1 及更高版本内置对 CC26xx 系列器件的支持功能
广泛的调试器支持,支持 XDS100v3、XDS200、IAR I-Jet 和 Segger J-Link
带有项目管理工具和编辑器的集成开发环境
适用于 TI-RTOS 的 RTOS 插件
要获取有关 CC2620 平台的开发支持工具的完整列表,请访问德州仪器 (TI) 网站 www.ti.com。有关定价和
购买信息,请联系最近的 TI 销售办事处或授权分销商。
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8.3 文档支持
如需接收文档更新通知,请访问 ti.com 网站上的器件产品文件夹 (CC2620)。点击右上角的提醒我 (Alert
me) 注册后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订
历史记录。
下面列出了描述 CC2620 器件、相关外设和其他技术材料的最新文档。
技术参考手册
《CC13xx、CC26xx SimpleLink™ 无线 MCU 技术参考手册》
空白
勘误
《CC2620 SimpleLink™ 无线 MCU 勘误表》
8.4 德州仪器 (TI) 低功耗射频网站
德州仪器 (TI) 的低功耗射频网站提供所有最新产品、应用和设计笔记、FAQ 部分、新闻资讯以及活动更
新。请访问 www.ti.com.cn/lprf。
8.5 低功耗射频电子新闻简报
通过低功耗射频电子新闻简报,您能够了解到最新的产品、新闻稿、开发者相关新闻以及关于德州仪器 (TI)
低功耗射频产品其它新闻和活动。低功耗射频电子新闻简报文章包含可获取更多在线信息的链接。
访问:www.ti.com.cn/lprfnewsletter 立即注册
8.6 社区资源
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术
规范和标准且不一定反映 TI 的观点;请见 TI 的使用条款。
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI 嵌入式处理器维基网页 德州仪器 (TI) 嵌入式处理器维基网站。此网站的建立是为了帮助开发人员从德州
仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体知识的创新
和增长。
低功耗射频在线社区 TI E2E 支持社区的无线连接部门
•
•
•
论坛、视频和博客
射频设计帮助
E2E 交流互动
请点击此处加入我们。
低功耗射频开发者网络 德州仪器 (TI) 建立了一个大型低功耗射频开发合作伙伴网络,帮助客户加快应用开
发。此网络中包括推荐的公司、射频顾问和独立设计工作室,他们可提供一系列硬件模块产品
和设计服务,其中包括:
•
•
•
射频电路、低功耗射频和ZigBee 设计服务
低功耗射频和 ZigBee 模块解决方案以及开发工具
射频认证服务和射频电路制造
如果需要有关模块、工程服务或开发工具的帮助:
请搜索低功耗射频开发者网络查找适合的合作伙伴。www.ti.com.cn/lprfnetwork
40
器件和文档支持
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ZHCSEU2C –FEBRUARY 2015–REVISED JULY 2016
8.7 其他信息
德州仪器 (TI) 为汽车、工业和消费类应用中所使用的专有应用和标准无线 应用 提供各种经济实用的低功耗
射频 解决方案。其中包括适用于 1GHz 以下频段和 2.4GHz 频段的射频收发器、射频发送器、射频前端和
片上系统以及各种软件解决方案。
此外,德州仪器 (TI) 还提供广泛的相关支持,例如开发工具、技术文档、参考设计、应用专业技术、客户支
持、第三方服务以及大学计划。
低功耗射频 E2E 在线社区设有技术支持论坛并提供视频和博客,您有机会在此与全球同领域工程师交流互
动。
凭借丰富的供选产品解决方案、可实现的最终应用以及广泛的技术支持,德州仪器 (TI) 能够为您提供最全面
的低功耗射频产品组合。
8.8 商标
SimpleLink, RemoTI, SmartRF, Code Composer Studio, LaunchPad, E2E are trademarks of Texas
Instruments.
ARM7 is a trademark of ARM Limited (or its subsidiaries).
ARM, Cortex, ARM Thumb are registered trademarks of ARM Limited (or its subsidiaries).
蓝牙 is a registered trademark of Bluetooth SIG, Inc.
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
IAR Embedded Workbench is a registered trademark of IAR Systems AB.
IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated.
ZigBee is a registered trademark of ZigBee Alliance, Inc.
All other trademarks are the property of their respective owners.
8.9 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.10 出口管制提示
接收方同意:如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
(其中包括软件)(见美国、欧盟和其他出口管理条例之定义)、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地,那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下,接收方不得在知情的情况下,以直接或间接的方式将其出口。
8.11 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 机械、封装和可订购信息
9.1 封装信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知
且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2015–2016, Texas Instruments Incorporated
机械、封装和可订购信息
41
提交文档反馈意见
产品主页链接: CC2620
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC2620F128RGZR
CC2620F128RGZT
CC2620F128RSMR
CC2620F128RSMT
ACTIVE
VQFN
VQFN
VQFN
VQFN
RGZ
48
48
32
32
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CC2620
F128
ACTIVE
ACTIVE
ACTIVE
RGZ
CC2620
F128
RSM
CC2620
F128
RSM
CC2620
F128
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2620F128RGZR
CC2620F128RGZR
CC2620F128RGZT
CC2620F128RGZT
CC2620F128RSMR
CC2620F128RSMR
CC2620F128RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RSM
RSM
RSM
48
48
48
48
32
32
32
2500
2500
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
16.4
16.4
16.4
16.4
12.4
12.4
12.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
12.0
12.0
8.0
16.0
16.0
16.0
16.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
7.3
7.3
1.1
250
7.3
7.3
1.1
3000
3000
250
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
8.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC2620F128RGZR
CC2620F128RGZR
CC2620F128RGZT
CC2620F128RGZT
CC2620F128RSMR
CC2620F128RSMR
CC2620F128RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RSM
RSM
RSM
48
48
48
48
32
32
32
2500
2500
250
367.0
367.0
210.0
210.0
367.0
346.0
210.0
367.0
367.0
185.0
185.0
367.0
346.0
185.0
38.0
35.0
35.0
35.0
35.0
33.0
35.0
250
3000
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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