CC2651R3SIPAT0MOUR_技术文档

CC2651R3SIPA

SWRS278A – FEBRUARY 2022 – REVISED JUNE 2022

CC2651R3SIPA SimpleLink™ Multiprotocol 2.4 GHz Wireless System-in-Package

Module with integrated Antenna & 352-KB Memory

•

Real-time clock (RTC)

Integrated temperature and battery monitor

1 Features

Wireless microcontroller

Security enablers

•

Powerful 48-MHz Arm® Cortex®-M4 processor

352KB flash program memory

32KB of ultra-low leakage SRAM

8KB of Cache SRAM (Alternatively available as

general-purpose RAM)

•

AES 128-bit cryptographic accelerator

True random number generator (TRNG)

Additional cryptography drivers available in

Software Development Kit (SDK)

•

Programmable radio includes support for 2-

(G)FSK, 4-(G)FSK, MSK, Bluetooth® 5.2 Low

Energy, IEEE 802.15.4 PHY and MAC

Supports over-the-air upgrade (OTA)

Development tools and software

•

LP-CC2651R3SIPA Development Kit

SimpleLink™ CC13xx and CC26xx Software

Development Kit (SDK)

•

Low power consumption

•

SmartRF™ Studio for simple radio configuration

SysConfig system configuration tool

•

MCU consumption:

Operating range

– 3.60 mA active mode, CoreMark

– 61 μA/MHz running CoreMark

– 0.8 μA standby mode, RTC, 32KB RAM

– 0.1 μA shutdown mode, wake-up on pin

Radio Consumption:

•

On-chip buck DC/DC converter

1.8-V to 3.8-V single supply voltage

T_j: -40 to +105°C

•

Package

– 6.8 mA RX

– 7.1 mA TX at 0 dBm

– 9.6 mA TX at +5 dBm

•

7-mm × 7-mm MOU (32 GPIOs)

RoHS-compliant package

Wireless protocol support

•

Zigbee®

Bluetooth® 5.2 Low Energy

SimpleLink™ TI 15.4-stack

Proprietary systems

High performance radio

•

-104 dBm for Bluetooth® Low Energy 125-kbps

Output power up to +5 dBm with temperature

compensation

Regulatory compliance

•

Regulatory certification for compliance with

worldwide radio frequency:

– ETSI RED (Europe)

– ISED (Canada)

– FCC (USA)

MCU peripherals

•

Digital peripherals can be routed to any GPIO

Four 32-bit or eight 16-bit general-purpose timers

12-bit ADC, 200 kSamples/s, 8 channels

8-bit DAC

Two comparators

Programmable current source

UART, SSI, I²C, I²S

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

CC2651R3SIPA

SWRS278A – FEBRUARY 2022 – REVISED JUNE 2022

www.ti.com

•

Electronic point of sale (EPOS) – Electronic Shelf

Label (ESL)

Communication equipment

– Wired networking – wireless LAN or Wi-Fi

access points, edge router , small business

router

2 Applications

•

2400 to 2480 MHz ISM and SRD systems ¹

Building automation

– Building security systems – motion detector,

electronic smart lock, door and window sensor,

garage door system, gateway

•

Personal electronics

– HVAC – thermostat, wireless environmental

sensor, HVAC system controller, gateway

– Fire safety system – smoke and heat detector,

fire alarm control panel (FACP)

– Video surveillance – IP network camera

– Elevators and escalators – elevator main

control panel for elevators and escalators

Industrial transport – asset tracking

Factory automation and control

– Portable electronics – RF smart remote control

– Home theater & entertainment – smart

speakers, smart display, set-top box

– Connected peripherals – consumer wireless

module, pointing devices, keyboards and

keypads

– Gaming – electronic and robotic toys

– Wearables (non-medical) – smart trackers,

smart clothing

•

Medical

3 Description

The SimpleLink™ CC2651R3SIPA device is a multiprotocol 2.4-GHz wireless microcontroller (MCU) supporting

Zigbee®, Bluetooth® 5.2 Low Energy, IEEE 802.15.4g, TI 15.4-Stack (2.4 GHz). The CC2651R3SIPA is

based on an Arm® Cortex® M4 main processor and optimized for low-power wireless communication and

advanced sensing in grid infrastructure, building automation, retail automation, personal electronics and medical

applications.

The CC2651R3SIPA is an ultra-compact 7-mm x 7-mm certified wireless module 2.4 GHz with integrated

antenna, DCDC components, Balun, and high frequency crystal oscillator.

The CC2651R3SIPA has a software defined radio powered by an Arm® Cortex® M0, which allows support for

multiple physical layers and RF standards. The device supports operation in the 2360 to 2500-MHz frequency

band. The CC2651R3SIPA supports +5 dBm TX at 9.6 mA in the 2.4-GHz band. CC2651R3SIPA has a receive

sensitivity of -104 dBm for 125-kbps Bluetooth® Low Energy Coded PHY.

The CC2651R3SIPA has a low sleep current of 0.9 μA with RTC and 32KB RAM retention.

TI has a product life cycle policy with a commitment to product longevity and continuity of supply.

The CC2651R3SIPA device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth® Low

Energy, Thread, Zigbee, Wi-SUN®, Amazon Sidewalk, mioty, Sub-1 GHz MCUs, and host MCU.CC2651R3SIPA

is part of a scalable portfolio with flash sizes from 32KB to 704KB with pin-to-pin compatible package options.

The common SimpleLink™CC13xx and CC26xx Software Development Kit (SDK) and SysConfig system

configuration tool supports migration between devices in the portfolio. A comprehensive number of software

stacks, application examples and SimpleLink™ Academy training sessions are included in the SDK. For more

information, visit wireless connectivity.

Device Information

PART NUMBER ⁽¹⁾

PACKAGE

BODY SIZE (NOM)

CC2651R3SIPAT0MOUR

QFM (59)

7.00 mm × 7.00 mm

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section

13, or see the TI website.

1

See RF Core for additional details on supported protocol standards, modulation formats, and data rates.

2

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4 Functional Block Diagram

Figure 4-1 shows the functional block diagram of the CC2651R3SIPA module.

Figure 4-1. CC2651R3SIPA Block Diagram

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Figure 4-2 shows an overview of the CC2651R3SIPA hardware.

2.4 GHz (Optional

External Antenna)

CC2651R3SIPA

Integrated Antenna

48-MHz

Crystal

Oscillator

5-dBm

RF Balun

RF Core

cJTAG

Main CPU

40KB

ROM

ADC

Arm^®Cortex^®-M4

Up to

352KB

Flash

Processor

Digital PLL

with 8KB

Cache

DSP Modem

48 MHz

SRAM

ROM

Arm^®Cortex^®-M0

Processor

Up to

32KB

SRAM

General Hardware Peripherals and Modules

I²C

4× 32-bit Timers

8-bit DAC

UART

SSI (SPI)

Watchdog Timer

32 ch. µDMA

RTC

12-bit ADC, 200 ks/s

2x Low-Power Comparator

Time-to-Digital Converter

I²S

Up to 32 GPIOs

AES & TRNG

Temperature and

Battery Monitor

LDO, Clocks, and References

Optional DC/DC Converter

Figure 4-2. CC2651R3SIPA Hardware Overview

4

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................2

3 Description.......................................................................2

4 Functional Block Diagram.............................................. 3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................6

7 Terminal Configuration and Functions..........................7

7.1 Pin Diagram................................................................ 7

7.2 Signal Descriptions – SIPA Package.......................... 8

7.3 Connections for Unused Pins and Modules................9

8 Specifications................................................................ 10

8.1 Absolute Maximum Ratings...................................... 10

8.2 ESD Ratings............................................................. 10

8.3 Recommended Operating Conditions.......................10

8.4 Power Supply and Modules...................................... 10

8.5 Power Consumption - Power Modes.........................11

8.6 Power Consumption - Radio Modes......................... 12

8.7 Nonvolatile (Flash) Memory Characteristics............. 12

8.8 Thermal Resistance Characteristics......................... 12

8.9 RF Frequency Bands................................................12

8.10 Bluetooth Low Energy - Receive (RX).................... 13

8.11 Bluetooth Low Energy - Transmit (TX)....................16

8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz

9.7 Serial Peripherals and I/O.........................................42

9.8 Battery and Temperature Monitor............................. 42

9.9 µDMA........................................................................42

9.10 Debug..................................................................... 42

9.11 Power Management................................................43

9.12 Clock Systems........................................................ 44

9.13 Network Processor..................................................44

9.14 Device Certification and Qualification..................... 45

9.15 Module Markings.....................................................47

9.16 End Product Labeling..............................................47

9.17 Manual Information to the End User....................... 47

10 Application, Implementation, and Layout................. 48

10.1 Typical Application Circuit.......................................48

10.2 Device Connections................................................49

10.3 PCB Layout Guidelines...........................................49

10.4 Reference Designs................................................. 51

10.5 Junction Temperature Calculation...........................52

11 Environmental Requirements and SMT

Specifications ...............................................................53

11.1 PCB Bending...........................................................53

11.2 Handling Environment.............................................53

11.3 Storage Condition................................................... 53

11.4 PCB Assembly Guide..............................................53

11.5 Baking Conditions................................................... 54

11.6 Soldering and Reflow Condition..............................55

12 Device and Documentation Support..........................56

12.1 Device Nomenclature..............................................56

12.2 Tools and Software................................................. 56

12.3 Documentation Support.......................................... 59

12.4 Support Resources................................................. 59

12.5 Trademarks.............................................................59

12.6 Electrostatic Discharge Caution..............................60

12.7 Glossary..................................................................60

13 Mechanical, Packaging, and Orderable

(OQPSK DSSS1:8, 250 kbps) - RX.............................17

8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz

(OQPSK DSSS1:8, 250 kbps) - TX.............................18

8.14 Timing and Switching Characteristics..................... 18

8.15 Peripheral Characteristics.......................................22

8.16 Typical Characteristics............................................30

9 Detailed Description......................................................37

9.1 Overview...................................................................37

9.2 System CPU............................................................. 37

9.3 Radio (RF Core)........................................................38

9.4 Memory.....................................................................39

9.5 Cryptography............................................................ 40

9.6 Timers....................................................................... 41

Information.................................................................... 61

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (February 2022) to Revision A (June 2022)

Page

•

Updated numbering of sections, figures, and tables throughout the data sheet.................................................1

Updated formatting throughout data sheet to match current documentation standards.....................................1

Devices are now PRODUCTION DATA..............................................................................................................1

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6 Device Comparison

RADIO SUPPORT

PACKAGE SIZE

FLASH

(KB)

RAM +

Cache (KB)

Device

GPIO

CC1310

X

32-128

352

704

352

704

128

352

704

352

704

16-20 + 8

32 + 8

80 + 8

144 + 8

80 + 8

144 + 8

20 + 8

80 + 8

32 + 8

80 + 8

144 + 8

80 + 8

144 + 8

10-30

22-30

26

X

CC1311R3

CC1311P3

CC1312R

X

30

CC1312R7

CC1352R

X

30

X

28

CC1352P

X

26

CC1352P7

CC2640R2F

CC2642R

26

10-31

31

X

CC2642R-Q1

CC2651R3

CC2651P3

CC2652R

31

X

23-31

22-26

31

X

CC2652RB

CC2652R7

CC2652P

31

X

26

CC2652P7

26

ANTENNA

RADIO SUPPORT

CERTIFICATIONS

PACKAGE SIZE

FLASH

(KB) Cache (KB)

RAM +

Module

GPIO

CC2650MODA

CC2651R3SIPA

CC2652RSIP

CC2652PSIP

X

128

352

20+8

32 + 8

80 + 8

15

32

30

X

6

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7 Terminal Configuration and Functions

7.1 Pin Diagram

2.4 GHz PCB Antenna

GND

13

16

ANT_GND

GND

12

11

10

9

17

18

19

20

21

22

23

24

25

26

27

NC

GND

X32K_Q1

X32K_Q2

DIO_10

DIO_11

DIO_30

DIO_29

GND

8

DIO_12

7

53

52

51

54

59

58

55

56

57

DIO_13

6

DIO_14

GND

5

DIO_15

RESET_N

DIO_28

4

JTAG_TMSC

JTAC_TCKC

3

CC2651R3SIPA

DIO_27

DIO_26

2

DIO_16

DIO_17

1

28

Figure 7-1. MOU (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)

The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities:

•

Pin 25, JTAG_TMSC

Pin 27, DIO_16

Pin 28, DIO_17

Pin 46, DIO_5

Pin 47, DIO_6

Pin 48, DIO_7

The following I/O pins marked in Figure 7-1 in italics have analog capabilities:

•

Pin 1, DIO_26

Pin 2, DIO_27

Pin 3, DIO_28

Pin 7, DIO_29

Pin 8, DIO_30

Pin 35, DIO_23

Pin 36, DIO_24

Pin 39, DIO_25

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7.2 Signal Descriptions – SIPA Package

Table 7-1. Signal Descriptions – SIPA Package

I/O

TYPE

DESCRIPTION

NAME

NO.

16

41

42

19

20

21

22

23

24

27

28

30

31

43

32

33

34

35

36

39

1

ANT_GND

DIO_0

—

Digital

Antenna GND

GPIO

I/O

DIO_1

Digital

GPIO

DIO_10

DIO_11

DIO_12

DIO_13

DIO_14

DIO_15

DIO_16

DIO_17

DIO_18

DIO_19

DIO_2

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital

GPIO, JTAG_TDO, high-drive capability

GPIO, JTAG_TDI, high-drive capability

GPIO

Digital

GPIO

Digital

GPIO

DIO_20

DIO_21

DIO_22

DIO_23

DIO_24

DIO_25

DIO_26

DIO_27

DIO_28

DIO_29

DIO_3

Digital

GPIO

Digital

GPIO

Digital

GPIO

Digital or Analog

Digital

GPIO, analog capability

GPIO

2

3

7

44

8

DIO_30

Digital or Analog

GPIO, analog capability

Supports only peripheral functionality. Does not support general

purpose I/O functionality.

DIO_31⁽¹⁾

29

I/O

Digital

DIO_4

DIO_5

DIO_6

DIO_7

DIO_8

DIO_9

GND

45

46

47

48

49

50

5

I/O

—

Digital

—

GPIO

GPIO, high-drive capability

GPIO

GND

6

—

GND

11

—

GND

12

13

18

40

51-59

15

—

GND

—

GND

—

GND

—

GND

—

GND

INT_ANT

RF

RF connection to integral PCB antenna

8

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Table 7-1. Signal Descriptions – SIPA Package (continued)

I/O

TYPE

DESCRIPTION

NAME

NO.

26

25

17

4

JTAG_TCKC

JTAG_TMSC

NC

I/O

—

I

Digital

—

JTAG_TCKC

JTAG_TMSC, high-drive capability

No Connect

RESET_N

RF

Digital

RF

Reset, active low. Internal pullup resistor to VDDS_PU

50 ohm RF port

14

37

38

10

9

—

I/O

—

VDDS

Digital

Power

—

1.8-V to 3.8-V main SIP supply

Power to reset internal pullup resistor

32-kHz crystal oscillator pin 1

32-kHz crystal oscillator pin 2

VDSS_PU

X32K_Q1

X32K_Q2

—

(1) PORT_ID = 0x00 is not supported. See the SimpleLink™ CC13x1x3, CC26x1x3 Wireless MCU Technical Reference Manual for further

details.

7.3 Connections for Unused Pins and Modules

Table 7-2. Connections for Unused Pins – SIPA Package

PREFERRED

FUNCTION

SIGNAL NAME

PIN NUMBER

ACCEPTABLE PRACTICE⁽¹⁾

PRACTICE⁽¹⁾

1-3

7-8

19-24

27-36

39

GPIO

DIO_n

NC or GND

NC

41-50

X32K_Q2

X32K_Q1

NC

9

32.768-kHz crystal

NC

10

17

No Connects

(1) NC = No connect

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

MAX UNIT

VDDS⁽³⁾

Supply voltage

4.1

V

Voltage on any digital pin^{(4) (5)}

Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2

Voltage scaling enabled

VDDS + 0.3, max 4.1

VDDR + 0.3, max 2.25

VDDS

1.49

V_in

Voltage on ADC input

Voltage scaling disabled, internal reference

Voltage scaling disabled, VDDS as reference

V

VDDS / 2.9

5

Input level, RF pin

dBm

°C

T_stg

Storage temperature

–40

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground, unless otherwise noted.

(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.

(4) Including analog capable DIOs.

(5) Injection current is not supported on any GPIO pin

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

All pins

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

105

3.8

UNIT

°C

Operating ambient temperature⁽¹⁾

Operating supply voltage (VDDS)

Rising supply voltage slew rate

Falling supply voltage slew rate

–40

1.8

0

V

100

20

mV/µs

0

(1) For thermal resistance characteristics refer to Section 8.24.

8.4 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

VDDS Power-on-Reset (POR) threshold

1.1 - 1.55

1.77

V

VDDS Brown-out Detector (BOD)

Rising threshold

Falling threshold

VDDS Brown-out Detector (BOD), before initial boot ⁽¹⁾

VDDS Brown-out Detector (BOD)

1.70

1.75

(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin

10

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8.5 Power Consumption - Power Modes

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V with DC/DC enabled unless

otherwise noted.

PARAMETER

TEST CONDITIONS

TYP

UNIT

Core Current Consumption

Reset. RESET_N pin asserted or VDDS below power-on-reset threshold

Shutdown. No clocks running, no retention

150

100

Reset and Shutdown

nA

RTC running, CPU, 32KB RAM and (partial) register retention.

RCOSC_LF

0.8

0.9

µA

mA

Standby

without cache retention

RTC running, CPU, 32KB RAM and (partial) register retention

XOSC_LF

RTC running, CPU, 32KB RAM and (partial) register retention.

RCOSC_LF

I_core

2.4

Standby

with cache retention

RTC running, CPU, 32KB RAM and (partial) register retention.

XOSC_LF

2.6

Supply Systems and RAM powered

RCOSC_HF

Idle

650

2.91

MCU running CoreMark at 48 MHz

RCOSC_HF

Active

Peripheral Current Consumption

Peripheral power

domain

Delta current with domain enabled

56

5.0

Serial power domain

RF Core

Delta current with power domain enabled,

clock enabled, RF core idle

144

µDMA

Delta current with clock enabled, module is idle

Delta current with clock enabled, module is idle⁽³⁾

Delta current with clock enabled, module is idle

Delta current with clock enabled, module is idle⁽¹⁾

Delta current with clock enabled, module is idle⁽²⁾

Delta current with clock enabled, module is idle

68.6

102

Timers

I_peri

µA

I2C

12.1

30.8

71.7

147

I2S

SSI

UART

CRYPTO (AES)

TRNG

28.1

27.1

(1) Only one UART running

(2) Only one SSI running

(3) Only one GPTimer running

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8.6 Power Consumption - Radio Modes

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V with DC/DC enabled unless

otherwise noted.

PARAMETER

TEST CONDITIONS

TYP UNIT

Radio receive current

2440 MHz

6.7

7.7

mA

0 dBm output power setting

2440 MHz

Radio transmit current

2.4 GHz PA (Bluetooth Low Energy)

+5 dBm output power setting

2440 MHz

10

mA

8.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and V_DDS= 3.0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Flash sector size

8

KB

Supported flash erase cycles before failure, full bank^{(1) (5)}

Supported flash erase cycles before failure, single sector⁽²⁾

30

60

k Cycles

Write

Operations

Years

mA

Maximum number of write operations per row before sector

erase⁽³⁾

83

Flash retention

105 °C

11.4

Flash sector erase current

Average delta current

Zero cycles

10.7

10

ms

Flash sector erase time⁽⁴⁾

30k cycles

4000

ms

Flash write current

Flash write time⁽⁴⁾

Average delta current, 4 bytes at a time

4 bytes at a time

6.2

mA

21.6

ms

(1) A full bank erase is counted as a single erase cycle on each sector

(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k

cycles

(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum

per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum

number of write operations per row is reached.

(4) This number is dependent on Flash aging and increases over time and erase cycles

(5) Aborting flash during erase or program modes is not a safe operation.

8.8 Thermal Resistance Characteristics

PACKAGE

MOU

(SIP)

59 PINS

48.7

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W⁽²⁾

12.4

32.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.40

ψ_JB

32.0

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

8.9 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted).

PARAMETER

MIN

TYP

MAX

UNIT

Frequency bands

2360

2500

MHz

12

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8.10 Bluetooth Low Energy - Receive (RX)

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

125 kbps (LE Coded)

Receiver sensitivity

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential mode. BER = 10^–3

–103

>5

dBm

Receiver saturation

Differential mode. BER = 10^–3

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

Selectivity, ±2 MHz⁽¹⁾

Selectivity, ±3 MHz⁽¹⁾

Selectivity, ±4 MHz⁽¹⁾

Selectivity, ±6 MHz⁽¹⁾

Selectivity, ±7 MHz

> (–300 / 300)

> (–320 / 240)

> (–125 / 125)

–1.5

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Wanted signal at –79 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –79 dBm, modulated interferer at ±1

MHz, BER = 10^–3

8 / 4.5⁽²⁾

dB

Wanted signal at –79 dBm, modulated interferer at ±2

MHz, BER = 10^–3

44 / 39⁽²⁾

46 / 44⁽²⁾

44 / 46⁽²⁾

48 / 44⁽²⁾

51 / 45⁽²⁾

39

dB

Wanted signal at –79 dBm, modulated interferer at ±3

MHz, BER = 10^–3

dB

Wanted signal at –79 dBm, modulated interferer at ±4

MHz, BER = 10^–3

dB

Wanted signal at –79 dBm, modulated interferer at ≥ ±6

MHz, BER = 10^–3

dB

Wanted signal at –79 dBm, modulated interferer at ≥ ±7

MHz, BER = 10^–3

dB

Wanted signal at –79 dBm, modulated interferer at image

frequency, BER = 10^–3

Selectivity, Image frequency⁽¹⁾

dB

Note that Image frequency + 1 MHz is the Co- channel

–1 MHz. Wanted signal at –79 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽¹⁾

4.5 / 44 ⁽²⁾

dB

500 kbps (LE Coded)

Receiver sensitivity

Receiver saturation

Differential mode. BER = 10^–3

–99

> 5

dBm

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

Selectivity, ±2 MHz⁽¹⁾

Selectivity, ±3 MHz⁽¹⁾

Selectivity, ±4 MHz⁽¹⁾

Selectivity, ±6 MHz⁽¹⁾

Selectivity, ±7 MHz

> (–300 / 300)

> (–450 / 450)

> (–175 / 175)

–3.5

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Difference between incoming data rate and the internally

generated data rate (255-byte packets)

Wanted signal at –72 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –72 dBm, modulated interferer at ±1

MHz, BER = 10^–3

8 / 4⁽²⁾

dB

Wanted signal at –72 dBm, modulated interferer at ±2

MHz, BER = 10^–3

44 / 37⁽²⁾

46 / 42⁽²⁾

45 / 43⁽²⁾

46 / 45⁽²⁾

49 / 45⁽²⁾

37

dB

Wanted signal at –72 dBm, modulated interferer at ±3

MHz, BER = 10^–3

dB

Wanted signal at –72 dBm, modulated interferer at ±4

MHz, BER = 10^–3

dB

Wanted signal at –72 dBm, modulated interferer at ≥ ±6

MHz, BER = 10^–3

dB

Wanted signal at –72 dBm, modulated interferer at ≥ ±7

MHz, BER = 10^–3

dB

Wanted signal at –72 dBm, modulated interferer at image

frequency, BER = 10^–3

Selectivity, Image frequency⁽¹⁾

dB

Note that Image frequency + 1 MHz is the Co- channel

–1 MHz. Wanted signal at –72 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, Image frequency ±1

MHz⁽¹⁾

4 / 46⁽²⁾

dB

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When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

1 Mbps (LE 1M)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Receiver sensitivity

Receiver saturation

Differential mode. BER = 10^–3

–96

> 5

dBm

Differential mode. BER = 10^–3

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±1 MHz⁽¹⁾

> (–350 / 350)

> (–750 / 750)

–6

kHz

ppm

dB

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel, BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±1

MHz, BER = 10^–3

7 / 4⁽²⁾

dB

Wanted signal at –67 dBm, modulated interferer at ±2

MHz,BER = 10^–3

Selectivity, ±2 MHz⁽¹⁾

40 / 33⁽²⁾

36 / 41⁽²⁾

40 / 45⁽²⁾

40

dB

Wanted signal at –67 dBm, modulated interferer at ±3

MHz, BER = 10^–3

Selectivity, ±3 MHz⁽¹⁾

dB

Wanted signal at –67 dBm, modulated interferer at ±4

MHz, BER = 10^–3

Selectivity, ±4 MHz⁽¹⁾

dB

Wanted signal at –67 dBm, modulated interferer at ≥ ±5

MHz, BER = 10^–3

Selectivity, ±5 MHz or more⁽¹⁾

Selectivity, image frequency⁽¹⁾

dB

Wanted signal at –67 dBm, modulated interferer at image

frequency, BER = 10^–3

33

dB

Note that Image frequency + 1 MHz is the Co- channel

–1 MHz. Wanted signal at –67 dBm, modulated interferer

at ±1 MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±1 MHz⁽¹⁾

4 / 41⁽²⁾

dB

Out-of-band blocking⁽³⁾

Out-of-band blocking

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

–10

–18

–12

–2

dBm

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2405 and 2408 MHz respectively, at the given power

level

Intermodulation

–42

dBm

Spurious emissions,

30 to 1000 MHz

Measurement in a 50-Ω single-ended load.

< –59

< –47

dBm

Spurious emissions,

1 to 12.75 GHz

RSSI dynamic range

RSSI accuracy

70

±4

dB

2 Mbps (LE 2M)

Differential mode. Measured at SMA connector, BER =

10^–3

Receiver sensitivity

–91

> 5

dBm

kHz

ppm

dB

Differential mode. Measured at SMA connector, BER =

10^–3

Receiver saturation

Difference between the incoming carrier frequency and

the internally generated carrier frequency

Frequency error tolerance

Data rate error tolerance

Co-channel rejection⁽¹⁾

Selectivity, ±2 MHz⁽¹⁾

Selectivity, ±4 MHz⁽¹⁾

Selectivity, ±6 MHz⁽¹⁾

Selectivity, image frequency⁽¹⁾

> (–500 / 500)

> (–700 / 750)

–7

Difference between incoming data rate and the internally

generated data rate (37-byte packets)

Wanted signal at –67 dBm, modulated interferer in

channel,BER = 10^–3

Wanted signal at –67 dBm, modulated interferer at ±2

MHz, Image frequency is at –2 MHz, BER = 10^–3

8 / 4⁽²⁾

dB

Wanted signal at –67 dBm, modulated interferer at ±4

MHz, BER = 10^–3

36 / 36⁽²⁾

37 / 36⁽²⁾

4

dB

Wanted signal at –67 dBm, modulated interferer at ±6

MHz, BER = 10^–3

dB

Wanted signal at –67 dBm, modulated interferer at image

frequency, BER = 10^–3

dB

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When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Note that Image frequency + 2 MHz is the Co-channel.

Wanted signal at –67 dBm, modulated interferer at ±2

MHz from image frequency, BER = 10^–3

Selectivity, image frequency

±2 MHz⁽¹⁾

–7 / 36⁽²⁾

dB

Out-of-band blocking⁽³⁾

Out-of-band blocking

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

–16

–21

–15

–12

dBm

Wanted signal at 2402 MHz, –64 dBm. Two interferers

at 2408 and 2414 MHz respectively, at the given power

level

Intermodulation

–38

dBm

(1) Numbers given as I/C dB

(2) X / Y, where X is +N MHz and Y is –N MHz

(3) Excluding one exception at F_wanted/ 2, per Bluetooth Specification

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8.11 Bluetooth Low Energy - Transmit (TX)

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

General Parameters

Max output power

TEST CONDITIONS

MIN

TYP

Differential mode, delivered to a single-ended 50 Ω load through a balun

5

dBm

dB

Output power

programmable range

26

Spurious emissions and harmonics

f < 1 GHz, outside restricted bands

< –36

< –54

< –55

< –42

dBm

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

Spurious emissions

+5 dBm setting

Harmonics

Third harmonic

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8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

General Parameters

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Receiver sensitivity

Receiver saturation

PER = 1%

–99

> 5

dBm

Wanted signal at –82 dBm, modulated interferer at ±5 MHz,

PER = 1%

Adjacent channel rejection

Alternate channel rejection

36

57

dB

Wanted signal at –82 dBm, modulated interferer at ±10 MHz,

PER = 1%

Wanted signal at –82 dBm, undesired signal is IEEE

802.15.4 modulated channel, stepped through all channels

2405 to 2480 MHz, PER = 1%

Channel rejection, ±15 MHz or more

59

dB

Blocking and desensitization,

5 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

57

63

dB

Blocking and desensitization,

10 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

Blocking and desensitization,

20 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

63

dB

Blocking and desensitization,

50 MHz from upper band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

66

dB

Blocking and desensitization,

–5 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

60

dB

Blocking and desensitization,

–10 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

60

dB

Blocking and desensitization,

–20 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

63

dB

Blocking and desensitization,

–50 MHz from lower band edge

Wanted signal at –97 dBm (3 dB above the sensitivity level),

CW jammer, PER = 1%

65

dB

Spurious emissions, 30 MHz to 1000

MHz

Measurement in a 50-Ω single-ended load

–66

–53

> 350

> 1000

dBm

ppm

Spurious emissions, 1 GHz to 12.75

GHz

Difference between the incoming carrier frequency and the

internally generated carrier frequency

Frequency error tolerance

Symbol rate error tolerance

Difference between incoming symbol rate and the internally

generated symbol rate

RSSI dynamic range

RSSI accuracy

95

±4

dB

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8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX

When measured on the CC2651RSIPA-EM reference design with T_c= 25 °C, V_DDS= 3.0 V, f_RF= 2440 MHz with

DC/DC enabled unless otherwise noted. All measurements are performed conducted.

PARAMETER

General Parameters

Max output power

TEST CONDITIONS

MIN

TYP

Differential mode, delivered to a single-ended 50-Ω load through a balun

5

dBm

dB

Output power

programmable range

25

Spurious emissions and harmonics

f < 1 GHz, outside restricted

< -36

dBm

bands

Spurious emissions ⁽¹⁾

f < 1 GHz, restricted bands ETSI

f < 1 GHz, restricted bands FCC

f > 1 GHz, including harmonics

Second harmonic

< -47

< -55

< –42

< -42

dBm

+5 dBm setting

Harmonics

Third harmonic

IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)

Error vector magnitude +5 dBm setting

2

%

(1) To meet the FCC 15.247 Part 15 (US) Band Edge requirement, Channel 26 is reduced by 3 dBm when using the integrated antenna.

When using the external antenna option, Channel 26 output power is reduding by 4 dBm, with a max allowable antenna gain of 3.3

dBi.

8.14 Timing and Switching Characteristics

8.14.1 Reset Timing

PARAMETER

MIN

TYP

MAX

UNIT

RESET_N low duration

1

µs

8.14.2 Wakeup Timing

Measured over operating free-air temperature with V_DDS= 3.0 V (unless otherwise noted). The times listed here do not

include software overhead.

PARAMETER

TEST CONDITIONS

MIN

TYP

850 - 3000

160

MAX

UNIT

MCU, Reset to Active⁽¹⁾

µs

MCU, Shutdown to Active⁽¹⁾

MCU, Standby to Active

MCU, Active to Standby

MCU, Idle to Active

36

14

(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has

been in Reset or Shutdown before starting up again.

18

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8.14.3 Clock Specifications

8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF)

Measured on a Texas Instruments reference design with integrated 48 MHz crystal including parameters based on external

manufacturer's crystal specification at T_c= 25 °C, V_DDS= 3.0 V at initial time, unless otherwise noted.

PARAMETER

MIN

TYP

48

MAX

UNIT

MHz

Crystal frequency

Start-up time⁽¹⁾

200

µs

Crystal frequency tolerance⁽²⁾

Crystal aging⁽²⁾

-16

-4

18

2

ppm

ppm/year

(1) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.

(2) External manufacturer's crystal specification

8.14.3.2 48 MHz RC Oscillator (RCOSC_HF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

MHz

%

Frequency

48

Uncalibrated frequency accuracy

Calibrated frequency accuracy⁽¹⁾

Start-up time

±1

±0.25

5

%

µs

(1) Accuracy relative to the calibration source (XOSC_HF)

8.14.3.3 32.768 kHz Crystal Oscillator (XOSC_LF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

32.768

30

MAX

UNIT

kHz

kΩ

Crystal frequency

ESR

C_L

Equivalent series resistance

Crystal load capacitance

100

12

6

7⁽¹⁾

pF

(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be

used.

8.14.3.4 32 kHz RC Oscillator (RCOSC_LF)

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

MIN

TYP

MAX

UNIT

Frequency

32.8

kHz

Calibrated

RTC

Calibrated periodically against XOSC_HF⁽²⁾

±600⁽³⁾

50

ppm

variation⁽¹⁾

Temperature coefficient.

ppm/°C

(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time

Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This

functionality is available through the TI-provided Power driver.

(2) TI driver software calibrates the RTC every time XOSC_HF is enabled.

(3) Some device's variation can exceed 1000 ppm. Further calibration will not improve variation.

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8.14.4 Synchronous Serial Interface (SSI) Characteristics

8.14.4.1 Synchronous Serial Interface (SSI) Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

NO.

MIN

TYP

MAX

UNIT

S1

t_{clk_per}

t_{clk_high}

t_{clk_low}

SSIClk cycle time

SSIClk high time

SSIClk low time

12

65024

System Clocks ⁽²⁾

t_{clk_per}

S2⁽¹⁾

S3⁽¹⁾

0.5

t_{clk_per}

(1) Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3.

(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.

S1

S2

SSIClk

S3

SSIFss

SSITx

MSB

LSB

SSIRx

4 to 16 bits

Figure 8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

S2

S1

SSIClk

SSIFss

SSITx

SSIRx

S3

MSB

LSB

8-bit control

0

MSB

LSB

4 to 16 bits output data

Figure 8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer

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S1

S2

SSIClk

(SPO = 0)

S3

SSIClk

(SPO = 1)

SSITx

(Controller)

MSB

LSB

SSIRx

(Peripheral)

MSB

LSB

SSIFss

Figure 8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1

8.14.5 UART

8.14.5.1 UART Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

UART rate

3

MBaud

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8.15 Peripheral Characteristics

8.15.1 ADC

Analog-to-Digital Converter (ADC) Characteristics

T_c= 25 °C, V_DDS= 3.0 V and voltage scaling enabled, unless otherwise noted.⁽¹⁾

Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.

PARAMETER

Input voltage range

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

0

VDDS

12

Bits

ksps

LSB

Sample Rate

200

Offset

Internal 4.3 V equivalent reference⁽²⁾

–0.24

7.14

>–1

±4

Gain error

Internal 4.3 V equivalent reference⁽²⁾

DNL⁽⁴⁾

INL

Differential nonlinearity

Integral nonlinearity

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

9.8

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone, DC/DC enabled

9.8

10.1

11.1

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

ENOB

Effective number of bits

Bits

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal reference, voltage scaling disabled,

11.3

11.6

14-bit mode, 200 kSamples/s, 300 Hz input tone ⁽⁵⁾

Internal reference, voltage scaling disabled,

15-bit mode, 200 kSamples/s, 300 Hz input tone ⁽⁵⁾

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

–65

–70

–72

THD

Total harmonic distortion

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

dB

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

60

63

68

Signal-to-noise

and

distortion ratio

SINAD,

SNDR

VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Internal 4.3 V equivalent reference⁽²⁾, 200 kSamples/s,

9.6 kHz input tone

70

73

75

SFDR

Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone

Internal reference, voltage scaling disabled,

32 samples average, 200 kSamples/s, 300 Hz input tone

Conversion time

Serial conversion, time-to-output, 24 MHz clock

Internal 4.3 V equivalent reference⁽²⁾

VDDS as reference

50

0.42

0.6

Clock Cycles

Current consumption

mA

Equivalent fixed internal reference (input voltage scaling

enabled). For best accuracy, the ADC conversion should be

initiated through the TI-RTOS API in order to include the gain/

offset compensation factors stored in FCFG1

Reference voltage

4.3^{(2) (3)}

V

Fixed internal reference (input voltage scaling disabled).

For best accuracy, the ADC conversion should be initiated

through the TI-RTOS API in order to include the gain/offset

compensation factors stored in FCFG1. This value is derived

from the scaled value (4.3 V) as follows:

Reference voltage

1.48

V

V_ref= 4.3 V × 1408 / 4095

Reference voltage

VDDS as reference, input voltage scaling enabled

VDDS as reference, input voltage scaling disabled

VDDS

V

VDDS /

2.82⁽³⁾

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T_c= 25 °C, V_DDS= 3.0 V and voltage scaling enabled, unless otherwise noted.⁽¹⁾

Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

200 kSamples/s, voltage scaling enabled. Capacitive input,

Input impedance depends on sampling frequency and sampling

time

Input impedance

>1

MΩ

(1) Using IEEE Std 1241-2010 for terminology and test methods

(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V

(3) Applied voltage must be within Absolute Maximum Ratings (see Section 8.1) at all times

(4) No missing codes

(5) ADC_output = Σ(4ⁿsamples ) >> n, n = desired extra bits

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8.15.2 DAC

8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

General Parameters

Resolution

8

Bits

Any load, any V_REF, pre-charge OFF, DAC charge-pump ON

1.8

2.0

3.8

External Load⁽⁴⁾, any V_REF, pre-charge OFF, DAC charge-pump

OFF

V_DDS

Supply voltage

V

Any load, V_REF= DCOUPL, pre-charge ON

Buffer ON (recommended for external load)

Buffer OFF (internal load)

2.6

16

3.8

250

F_DAC

Clock frequency

kHz

1000

V_REF= VDDS, buffer OFF, internal load

V_REF= VDDS, buffer ON, external capacitive load = 20 pF⁽³⁾

13

13.8

20

Voltage output settling time

1 / F_DAC

External capacitive load

External resistive load

Short circuit current

200

400

pF

MΩ

µA

10

VDDS = 3.8 V, DAC charge-pump OFF

VDDS = 3.0 V, DAC charge-pump ON

VDDS = 3.0 V, DAC charge-pump OFF

VDDS = 2.0 V, DAC charge-pump ON

VDDS = 2.0 V, DAC charge-pump OFF

VDDS = 1.8 V, DAC charge-pump ON

VDDS = 1.8 V, DAC charge-pump OFF

50.8

51.7

53.2

48.7

70.2

46.3

88.9

Max output impedance Vref =

VDDS, buffer ON, CLK 250

kHz

Z_MAX

kΩ

Internal Load - Continuous Time Comparator / Low Power Clocked Comparator

V_REF= VDDS,

load = Continuous Time Comparator or Low Power Clocked

Comparator

F_DAC= 250 kHz

Differential nonlinearity

±1

DNL

LSB⁽¹⁾

V_REF= VDDS,

load = Continuous Time Comparator or Low Power Clocked

Comparator

±1.2

F_DAC= 16 kHz

V_REF= VDDS = 3.8 V

±0.64

±0.81

±1.27

±3.43

±2.88

±2.37

±0.78

±0.77

±3.46

±3.44

±4.70

±4.11

±1.53

±1.71

±2.10

±6.00

±3.85

±5.84

V_REF= VDDS= 3.0 V

Offset error⁽²⁾

Load = Continuous Time

Comparator

V_REF= VDDS = 1.8 V

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS= 3.8 V

V_REF= VDDS = 3.0 V

Offset error⁽²⁾

Load = Low Power Clocked

Comparator

V_REF= VDDS= 1.8 V

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS = 3.8 V

V_REF= VDDS = 3.0 V

Max code output voltage

variation⁽²⁾

Load = Continuous Time

Comparator

V_REF= VDDS= 1.8 V

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

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T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

±2.92

±3.06

±3.91

±7.84

±4.06

±6.94

0.03

3.62

0.02

2.86

0.01

1.71

0.01

1.21

1.27

2.46

0.01

1.41

0.03

3.61

0.02

2.85

0.01

1.71

0.01

1.21

1.27

2.46

0.01

1.41

MAX

UNIT

V_REF= VDDS= 3.8 V

V_REF=VDDS= 3.0 V

Max code output voltage

variation⁽²⁾

V_REF= VDDS= 1.8 V

LSB⁽¹⁾

Load = Low Power Clocked

Comparator

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS = 3.8 V, code 255

V_REF= VDDS= 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS= 1.8 V, code 1

Output voltage range⁽²⁾

Load = Continuous Time

Comparator

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

V

V_REF= ADCREF, code 255

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS= 3.8 V, code 255

V_REF= VDDS= 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS = 1.8 V, code 1

Output voltage range⁽²⁾

Load = Low Power Clocked

Comparator

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

V

V_REF= ADCREF, code 255

External Load

V_REF= VDDS, F_DAC= 250 kHz

V_REF= DCOUPL, F_DAC= 250 kHz

V_REF= ADCREF, F_DAC= 250 kHz

V_REF= VDDS, F_DAC= 250 kHz

V_REF= VDDS= 3.8 V

±1

INL

Integral nonlinearity

LSB⁽¹⁾

±1

DNL

Differential nonlinearity

±1

±0.20

±0.25

±0.45

±1.55

±1.30

±1.10

±0.60

±0.55

±0.60

±3.45

±2.10

±1.90

V_REF= VDDS= 3.0 V

V_REF= VDDS = 1.8 V

Offset error

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

V_REF= VDDS= 3.8 V

V_REF= VDDS= 3.0 V

V_REF= VDDS= 1.8 V

Max code output voltage

variation

LSB⁽¹⁾

V_REF= DCOUPL, pre-charge ON

V_REF= DCOUPL, pre-charge OFF

V_REF= ADCREF

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UNIT

SWRS278A – FEBRUARY 2022 – REVISED JUNE 2022

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.03

3.61

0.02

2.85

0.02

1.71

0.02

1.20

1.27

2.46

0.02

1.42

MAX

V_REF= VDDS = 3.8 V, code 1

V_REF= VDDS = 3.8 V, code 255

V_REF= VDDS = 3.0 V, code 1

V_REF= VDDS= 3.0 V, code 255

V_REF= VDDS= 1.8 V, code 1

Output voltage range

Load = Low Power Clocked

Comparator

V_REF= VDDS = 1.8 V, code 255

V_REF= DCOUPL, pre-charge OFF, code 1

V_REF= DCOUPL, pre-charge OFF, code 255

V_REF= DCOUPL, pre-charge ON, code 1

V_REF= DCOUPL, pre-charge ON, code 255

V_REF= ADCREF, code 1

V

V_REF= ADCREF, code 255

(1) 1 LSB (V_REF3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV

(2) Includes comparator offset

(3) A load > 20 pF will increases the settling time

(4) Keysight 34401A Multimeter

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8.15.3 Temperature and Battery Monitor

8.15.3.1 Temperature Sensor

Measured on a Texas Instruments reference design with T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

°C

Resolution

Accuracy

2

-40 °C to 0 °C

0 °C to 105 °C

±5.0

±2.5

3.6

°C

Supply voltage coefficient⁽¹⁾

°C/V

(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.

8.15.3.2 Battery Monitor

Measured on a Texas Instruments reference design with T_c= 25 °C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

mV

V

Resolution

Range

25

1.8

3.8

Integral nonlinearity (max)

Accuracy

23

22.5

-32

-1

mV

%

VDDS = 3.0 V

Offset error

Gain error

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8.15.4 Comparators

8.15.4.1 Continuous Time Comparator

T_c= 25°C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Input voltage range⁽¹⁾

0

V_DDS

Offset

Measured at V_DDS/ 2

Step from –10 mV to 10 mV

Internal reference

±5

0.78

8.6

mV

µs

Decision time

Current consumption

µA

(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using

the DAC

8.15.5 Current Source

8.15.5.1 Programmable Current Source

T_c= 25 °C, V_DDS= 3.0 V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

0.25 - 20

0.25

MAX UNIT

Current source programmable output range (logarithmic

range)

µA

Resolution

28

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8.15.6 GPIO

8.15.6.1 GPIO DC Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

T_A= 25 °C, V_DDS= 1.8 V

GPIO VOH at 8 mA load

IOCURR = 2, high-drive GPIOs only

IOCURR = 1

1.56

0.24

1.59

0.21

73

V

GPIO VOL at 8 mA load

GPIO VOH at 4 mA load

V

GPIO VOL at 4 mA load

IOCURR = 1

V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 → 1

IH = 1, transition voltage for input read as 1 → 0

µA

V

GPIO pulldown current

19

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

1.08

0.73

V

IH = 1, difference between 0 → 1

and 1 → 0 points

GPIO input hysteresis

0.35

V

T_A= 25 °C, V_DDS= 3.0 V

GPIO VOH at 8 mA load

IOCURR = 2, high-drive GPIOs only

IOCURR = 1

2.59

0.42

2.63

0.40

V

GPIO VOL at 8 mA load

GPIO VOH at 4 mA load

GPIO VOL at 4 mA load

IOCURR = 1

T_A= 25 °C, V_DDS= 3.8 V

GPIO pullup current

Input mode, pullup enabled, Vpad = 0 V

282

110

µA

V

GPIO pulldown current

Input mode, pulldown enabled, Vpad = VDDS

IH = 1, transition voltage for input read as 0 → 1

IH = 1, transition voltage for input read as 1 → 0

GPIO low-to-high input transition, with hysteresis

GPIO high-to-low input transition, with hysteresis

1.97

1.55

V

IH = 1, difference between 0 → 1

and 1 → 0 points

GPIO input hysteresis

T_A= 25 °C

0.42

V

Lowest GPIO input voltage reliably interpreted as a

High

VIH

0.8*V_DDS

Highest GPIO input voltage reliably interpreted as a

Low

VIL

0.2*V_DDS

V

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8.16 Typical Characteristics

All measurements in this section are done with T_c= 25 °C and V_DDS= 3.0 V, unless otherwise noted. See

Recommended Operating Conditions, Section 8.3, for device limits. Values exceeding these limits are for

reference only.

8.16.1 MCU Current

Running CoreMark, SCLK_HF = 48 MHz RCOSC

80 kB RAM Retention, no Cache Retention, RTC ON, SCLK_LF - 32 kHz XOSC

7

5

4.7

4.4

4.1

3.8

3.5

3.2

2.9

2.6

2.3

2

6

5

4

3

2

1

0

-40

-25

-10

5

20

35

50

65

80

95 105

Temperature [^oC]

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

Figure 8-5. Standby Mode (MCU) Current vs.

Temperature

Figure 8-4. Active Mode (MCU) Current vs.

Supply Voltage (VDDS)

8.16.2 RX Current

11

10.5

10

9.5

9

7.6

7.5

7.4

7.3

7.2

7.1

7

8.5

8

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

7.5

7

6.5

6

5.5

5

4.5

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

-40

-25

-10

5

20

35

50

65

80

95 105

Temperature [^oC]

Voltage [V]

Figure 8-7. RX Current vs.

Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)

Figure 8-6. RX Current vs.

Temperature (BLE 1 Mbps, 2.44 GHz)

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8.16.3 TX Current

9.3

9.15

9

8.85

8.7

8.55

8.4

8.25

8.1

11.2

11.05

10.9

10.75

10.6

10.45

10.3

10.15

10

7.95

7.8

9.85

9.7

7.65

7.5

9.55

9.4

7.35

7.2

9.25

9.1

7.05

6.9

8.95

8.8

6.75

6.6

8.65

8.5

6.45

6.3

8.35

8.2

-40

-25

-10

5

20

35

50

65

80

95 105

-40

-25

-10

5

20

35

50

65

80

95 105

Temperature [^oC]

Figure 8-8. TX Current vs. Temperature

(BLE 1 Mbps, 2.44 GHz, 0 dBm)

Figure 8-9. TX Current vs. Temperature

(BLE 1 Mbps, 2.44 GHz, +5 dBm)

13

12

11

10

9

16

15

14

13

12

11

10

9

8

7

6

8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

Figure 8-10. TX Current vs. Supply Voltage

(VDDS) (BLE 1 Mbps, 2.44 GHz, 0 dBm)

Figure 8-11. TX Current vs. Supply Voltage

(VDDS) (BLE 1 Mpbs, 2.44 GHz, +5 dBm)

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Table 8-1 shows the typical TX current and output power for different output power settings.

Table 8-1. Typical TX Current and Output Power

CC2652R at 2.4 GHz, VDDS = 3.0 V (Measured on CC2651RSIPA-EM)

txPower

0xA42E

0x601E

0x246A

0x2E64

0x20A5

0x20A2

0x08DC

0x00D2

0x00CD

0x00C8

TX Power Setting (SmartRF Studio)

Typical Output Power [dBm]

Typical Current Consumption [mA]

5

4

4.4

3.3

9.9

9.2

8.8

8.4

8.0

7.7

6.4

5.6

5.2

4.8

3

2.5

2

1.7

1

0.7

0

0.1

-5

-10

-15

-20

-4.6

-9.0

-12.7

-18.2

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8.16.4 RX Performance

-101

-100

-99

-98

-97

-96

-95

-94

-93

-92

-91

-103

-102

-101

-100

-99

-98

-97

-96

-95

-94

-93

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

Frequency [MHz]

Figure 8-12. Sensitivity vs.

Figure 8-13. Sensitivity vs.

Frequency (BLE 1 Mbps, 2.44 GHz)

Frequency (250 kbps, 2.44 GHz)

-90

-91

-92

-91

-92

-93

-94

-95

-96

-97

-98

-99

-100

-93

-94

-95

-96

-97

-98

-99

-100

-101

-102

-103

-40

-25

-10

5

20

35

50

65

80

95 105

-40

-25

-10

5

20

35

50

65

80

95 105

Temperature [^oC]

Figure 8-14. Sensitivity vs.

Temperature (BLE 1 Mbps, 2.44 GHz)

Figure 8-15. Sensitivity vs.

Temperature (250 kbps, 2.44 GHz)

-90

-91

-92

-93

-94

-95

-96

-97

-98

-99

-100

-90

-91

-92

-93

-94

-95

-96

-97

-98

-99

-100

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

Figure 8-16. Sensitivity vs.

Figure 8-17. Sensitivity vs.

Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)

Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz,

DCDC Off)

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-93

-94

-95

-96

-97

-98

-99

-100

-101

-102

-103

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

Figure 8-18. Sensitivity vs.

Supply Voltage (VDDS) (250 kbps, 2.44 GHz)

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8.16.5 TX Performance

2

1.8

1.6

1.4

1.2

1

7

6.8

6.6

6.4

6.2

6

0.8

0.6

0.4

0.2

0

5.8

5.6

5.4

5.2

5

-0.2

-0.4

-0.6

-0.8

-1

4.8

4.6

4.4

4.2

4

-1.2

-1.4

-1.6

-1.8

-2

3.8

3.6

3.4

3.2

3

-40

-25

-10

5

20

35

50

65

80

95 105

-40

-25

-10

5

20

35

50

65

80

95 105

Temperature [^oC]

Figure 8-19. Output Power vs. Temperature

(BLE 1 Mbps, 2.44 GHz, 0 dBm)

Figure 8-20. Output Power vs. Temperature

(BLE 1 Mbps, 2.44 GHz, +5 dBm)

2

1.8

1.6

1.4

1.2

1

7

6.8

6.6

6.4

6.2

6

0.8

0.6

0.4

0.2

0

5.8

5.6

5.4

5.2

5

-0.2

-0.4

-0.6

-0.8

-1

4.8

4.6

4.4

4.2

4

-1.2

-1.4

-1.6

-1.8

-2

3.8

3.6

3.4

3.2

3

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

Voltage [V]

Figure 8-21. Output Power vs. Supply Voltage

(VDDS) (BLE 1 Mbps, 2.44 GHz, 0 dBm)

Figure 8-22. Output Power vs. Supply Voltage

(VDDS) (BLE 1 Mbps, 2.44 GHz, +5 dBm)

2

1.8

1.6

1.4

1.2

1

7

6.8

6.6

6.4

6.2

6

0.8

0.6

0.4

0.2

0

5.8

5.6

5.4

5.2

5

-0.2

-0.4

-0.6

-0.8

-1

4.8

4.6

4.4

4.2

4

-1.2

-1.4

-1.6

-1.8

-2

3.8

3.6

3.4

3.2

3

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

2.4

2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48

Frequency [MHz]

Figure 8-23. Output Power vs. Frequency

(BLE 1 Mbps, 2.44 GHz, 0 dBm)

Figure 8-24. Output Power vs. Frequency

(BLE 1 Mbps, 2.44 GHz, +5 dBm)

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8.16.6 ADC Performance

11.4

Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10

Internal Reference, No Averaging

Internal Unscaled Reference, 14-bit Mode

10.2

10.15

10.1

10.05

10

11.1

10.8

10.5

10.2

9.9

9.95

9.9

9.85

9.8

9.6

0.2 0.3

0.5 0.7

1

2

3

4

5

6 7 8 10

20 30 40 50 70 100

1

2

3

4

5

6

7 8 10

Frequency [kHz]

20

30 40 50 70 100

200

Frequency [kHz]

Figure 8-25. ENOB vs.

Input Frequency

Figure 8-26. ENOB vs.

Sampling Frequency

Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s

1.5

1

2.5

2

0.5

0

1.5

1

-0.5

-1

0.5

0

-1.5

-0.5

0

400

800

1200 1600 2000 2400 2800 3200 3600 4000

400

800

1200 1600 2000 2400 2800 3200 3600 4000

ADC Code

Figure 8-27. INL vs.

ADC Code

Figure 8-28. DNL vs.

ADC Code

Vin = 1 V, Internal reference, 200 kSamples/s

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

1.01

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90 100

Temperature [°C]

Voltage [V]

Figure 8-30. ADC Accuracy vs.

Supply Voltage (VDDS)

Figure 8-29. ADC Accuracy vs.

Temperature

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9 Detailed Description

9.1 Overview

Section 4 shows the core modules of the CC2651R3SIPA device.

9.2 System CPU

The CC2651R3SIPA SimpleLink^™Wireless MCU contains an Arm^®Cortex^®-M4 system CPU, which runs the

application and the higher layers of radio protocol stacks.

The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements

of minimal memory implementation, and low-power consumption, while delivering outstanding computational

performance and exceptional system response to interrupts.

Its features include the following:

•

ARMv7-M architecture optimized for small-footprint embedded applications

Arm Thumb^®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm

core in a compact memory size

•

Fast code execution permits increased sleep mode time

Deterministic, high-performance interrupt handling for time-critical applications

Single-cycle multiply instruction and hardware divide

Hardware division and fast digital-signal-processing oriented multiply accumulate

Saturating arithmetic for signal processing

Full debug with data matching for watchpoint generation

– Data Watchpoint and Trace Unit (DWT)

– JTAG Debug Access Port (DAP)

– Flash Patch and Breakpoint Unit (FPB)

•

Trace support reduces the number of pins required for debugging and tracing

– Instrumentation Trace Macrocell Unit (ITM)

– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)

Optimized for single-cycle flash memory access

Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait

states

•

Ultra-low-power consumption with integrated sleep modes

48 MHz operation

1.25 DMIPS per MHz

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9.3 Radio (RF Core)

The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor

that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and

assembles the information bits in a given packet structure. The RF core offers a high level, command-based

API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not

programmable by customers and is interfaced through the TI-provided RF driver that is included with the

SimpleLink Software Development Kit (SDK).

The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the

main CPU, which reduces power and leaves more resources for the user application. Several signals are also

available to control external circuitry such as RF switches or range extenders autonomously.

The various physical layer radio formats are partly built as a software defined radio where the radio behavior is

either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with

the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards

even with over-the-air (OTA) updates while still using the same silicon.

9.3.1 Bluetooth 5.2 Low Energy

The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-sped 2-Mbps physical layer

and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or

through a high-level Bluetooth API. The Bluetooth 5.2 PHY and part of the controller are in radio and system

ROM, providing significant savings in memory usage and more space available for applications.

The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times

the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers

significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.

Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application

needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible

at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not

previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster

responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates.

9.3.2 802.15.4 (Zigbee)

Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2

Mchips per second Offset-QPSK with DSSS 1:8), used in the Zigbee protocol. The 802.15.4 PHY and MAC are

in radio and system ROM. TI also provides royalty-free protocol stacks for Zigbee as part of the SimpleLink SDK,

enabling a robust end-to-end solution.

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9.4 Memory

The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is

in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration

section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is

done through the ccfg.c source file that is included in all TI provided examples.

The ultra-low leakage system static RAM (SRAM) is a single 32-KB block and can be used for both storage

of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and

included in Standby mode power consumption numbers.

To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way

nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.

The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area

(CCFG).

The ROM contains a serial (SPI and UART) bootloader that can be used for initial programming of the device.

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9.5 Cryptography

The CC2651R3SIPA device comes with a wide set of cryptography-related hardware accelerators, reducing

code footprint and execution time for cryptographic operations. It also has the benefit of being lower power

and improves availability and responsiveness of the system because the cryptography operations run in a

background hardware thread. The hardware accelerator modules are:

•

True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the

purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is

built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.

Advanced Encryption Standard (AES) with 128 bit key lengths

•

Together with the hardware accelerator module, a large selection of open-source cryptography libraries provided

with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily

built on top of the platform. The TI provided cryptography drivers are:

•

Key Agreement Schemes

– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)

– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)

Signature Generation

– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)

Curve Support

•

– Short Weierstrass form (full hardware support), such as:

•

NIST-P224, NIST-P256, NIST-P384, NIST-P521

Brainpool-256R1, Brainpool-384R1, Brainpool-512R1

secp256r1

– Montgomery form (hardware support for multiplication), such as:

•

Curve25519

•

SHA2 based MACs

– HMAC with SHA224, SHA256, SHA384, or SHA512

Block cipher mode of operation

– AESCCM

– AESGCM

– AESECB

– AESCBC

– AESCBC-MAC

•

True random number generation

Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as

Curve1174 or Ed25519, are a provided part of the TI SimpleLink SDK for the CC2651R3SIPA device.

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9.6 Timers

A large selection of timers are available as part of the CC2651R3SIPA device. These timers are:

•

Real-Time Clock (RTC)

A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)

This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for

frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with

frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.

When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be

accessed through the kernel APIs such as the Clock module. By default, the RTC halts when a debugger

halts the device.

•

General Purpose Timers (GPTIMER)

The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48

MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,

pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of

the timer are connected to the device event fabric, which allows the timers to interact with signals such as

GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.

Radio Timer

A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is

typically used as the timing base in wireless network communication using the 32-bit timing word as the

network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device

radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running

when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields

in the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the

source of SCLK_HF.

•

Watchdog timer

The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is

typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the

system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock

rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and

when a debugger halts the device.

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9.7 Serial Peripherals and I/O

The SSI is a synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous

serial interfaces. The SSIs support both SPI controller and peripheral up to 4 MHz. The SSI modules support

configurable phase and polarity.

The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-

rate generation up to a maximum of 3 Mbps.

The I²S interface is used to handle digital audio and can also be used to interface pulse-density modulation

microphones (PDM).

The I²C interface is also used to communicate with devices compatible with the I²C standard. The I²C interface

can handle 100 kHz and 400 kHz operation, and can serve as both controller and peripheral.

The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals

to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a

programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge

(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs

have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to

any digital pin on the device.

For more information, see the CC13x1x2, CC26x1x2 SimpleLink™ Wireless MCU Technical Reference Manual.

9.8 Battery and Temperature Monitor

A combined temperature and battery voltage monitor is available in the CC2651R3SIPA device. The battery

and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage

and respond to changes in environmental conditions as needed. The module contains window comparators to

interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can

also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.

9.9 µDMA

The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload

data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available

bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA

controller has dedicated channels for each supported on-chip module and can be programmed to automatically

perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller include the following (this is not an exhaustive list):

•

Highly flexible and configurable channel operation of up to 32 channels

Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral

•

Data sizes of 8, 16, and 32 bits

Ping-pong mode for continuous streaming of data

9.10 Debug

The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.

The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.

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9.11 Power Management

To minimize power consumption, the CC2651R3SIPA supports a number of power modes and power

management features (see Table 9-1).

Table 9-1. Power Modes

SOFTWARE CONFIGURABLE POWER MODES

RESET PIN

HELD

MODE

ACTIVE

Active

On

IDLE

Off

STANDBY

Off

SHUTDOWN

CPU

Off

No

Off

No

Flash

Available

On

Off

SRAM

On

Retention

Duty Cycled

Partial

Full

Supply System

Register and CPU retention

SRAM retention

On

Full

48 MHz high-speed clock

(SCLK_HF)

XOSC_HF or

RCOSC_HF

XOSC_HF or

RCOSC_HF

Off

32 kHz low-speed clock

(SCLK_LF)

XOSC_LF or

RCOSC_LF

XOSC_LF or

RCOSC_LF

XOSC_LF or

RCOSC_LF

Peripherals

Available

On

Available

On

Off

Available

On

Off

On

Off

Wake-up on RTC

Wake-up on pin edge

Wake-up on reset pin

Brownout detector (BOD)

Power-on reset (POR)

Watchdog timer (WDT)

Available

On

Duty Cycled

On

Off

On

Off

Available

Paused

Off

In Active mode, the application system CPU is actively executing code. Active mode provides normal operation

of the processor and all of the peripherals that are currently enabled. The system clock can be any available

clock source (see Table 9-1).

In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked

and no code is executed. Any interrupt event brings the processor back into active mode.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event or RTC event is

required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured

when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are

latched in standby mode.

In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with

the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from

shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in

this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in

this mode is the latched I/O state and the flash memory contents.

Note

The power, RF and clock management for the CC2651R3SIPA device require specific configuration

and handling by software for optimized performance. This configuration and handling is implemented

in the TI-provided drivers that are part of the CC2651R3SIPA software development kit (SDK).

Therefore, TI highly recommends using this software framework for all application development on

the device. The complete SDK with TI-RTOS (optional), device drivers, and examples are offered free

of charge in source code.

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9.12 Clock Systems

The CC2651R3SIPA device has several internal system clocks.

The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the

internal 48 MHz RC Oscillator (RCOSC_HF) or in-package 48 MHz crystal (XOSC_HF). Note that the radio

operation runs off the included, in-package 48 MHz crystal within the module.

SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used for the RTC and to synchronize

the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC

Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digitial IO.

When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other

devices, thereby reducing the overall system cost.

9.13 Network Processor

Depending on the product configuration, the CC2651R3SIPA device can function as a wireless network

processor (WNP - a device running the wireless protocol stack with the application running on a separate host

MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside

the device.

In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,

the application must be written according to the application framework supplied with the wireless protocol stack.

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9.14 Device Certification and Qualification

The CC2651R3SIPA module from TI is certified for FCC, IC/ISED, and ETSI/CE as lised in Table 9-2. Moreover,

the module is a Bluetooth Qualified Design by the Bluetooth Special Interest Group (Bluetooth SIG). TI

Customers that build products based on the TI CC2651R3SIPA module can save in testing cost and time per

product family.

Table 9-2. CC2651R3SIPA List of Certifications

Regulatory Body

Specification

ID (IF APPLICABLE)

Part 15C + MPE FCC RF Exposure (Bluetooth)

Part 15C + MPE FCC RF Exposure (802.15.4)

RSS-102 (MPE) and RSS-247 (Bluetooth)

RSS-102 (MPE) and RSS-247 (802.15.4)

EN 300328 v2.2.2 (2019-07) (Bluetooth)

EN 300328 v2.2.2 (2019-07) (802.15.4)

EN 62311:2019 (MPE)

FCC (USA)

ZAT-CC2651R3SIPA

IC/ISED (Canada)

ETSI/CE (Europe)

451H-2651R3SIPA

—

EN 301 489-1 v2.2.3 (2019-11)

EN 301489-17 v3.2.4 (2020-09)

EN 55024:2010 + A1:2015

EN 55032:2015 + AC:2016-07

EN 62368-1: 2020

9.14.1 FCC Certification and Statement

FCC RF Radiation Exposure Statement:

CAUTION

This equipment complies with FCC radiation exposure limits set forth for an uncontrolled

environment. End users must follow the specific operating instructions for satisfying RF exposure

limits. This transmitter must not be co-located or operating with any other antenna or transmitter.

The CC2651R3SIPA module from TI is certified for the FCC as a single-modular transmitter. The module is an

FCC-certified radio module that carries a modular grant.

You are cautioned that changes or modifications not expressly approved by the party responsible for compliance

could void the user’s authority to operate the equipment.

This device is planned to comply with Part 15 of the FCC Rules. Operation is subject to the following two

conditions:

•

This device may not cause harmful interference.

This device must accept any interference received, including interference that may cause undesired

operation of the device.

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9.14.2 IC/ISED Certification and Statement

CAUTION

IC RF Radiation Exposure Statement:

To comply with IC RF exposure requirements, this device and its antenna must not be co-located or

operating in conjunction with any other antenna or transmitter.

Pour se conformer aux exigences de conformité RF canadienne l'exposition, cet appareil et son

antenne ne doivent pas étre co-localisés ou fonctionnant en conjonction avec une autre antenne ou

transmetteur.

The CC2651R3SIPA module from TI is certified for IC as a single-modular transmitter. The CC2651R3SIPA

module from TI meets IC modular approval and labeling requirements. The IC follows the same testing and rules

as the FCC regarding certified modules in authorized equipment.

This device complies with Industry Canada licence-exempt RSS standards.

Operation is subject to the following two conditions:

•

This device may not cause interference.

This device must accept any interference, including interference that may cause undesired operation of the

device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de

licence.

L'exploitation est autorisée aux deux conditions suivantes:

•

L'appareil ne doit pas produire de brouillage

L'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est

susceptible d'en compromettre le fonctionnement.

9.14.3 ETSI/CE Certification

The CC2651R3SIPA module from TI is CE certified with certifications to the appropriate EU radio and EMC

directives summarized in the Declaration of Conformity and evidenced by the CE mark. The module is tested

and certified against the Radio Equipment Directive (RED).

See the full text of the for the EU Declaration of Conformity for the CC2651R3SIPAT0MOU device.

9.14.4 UK Certification

The CC2651R3SIPA module from TI is UK certified with certifications to the appropriate UK radio and EMC

directives summarized in the Declaration of Conformity and evidenced by the UK mark. The module is tested

and certified against the Radio Equipment Regulations 2017.

See the full text of the for the UK Declaration of Conformity for the CC2651R3SIPAT0MOU device.

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9.15 Module Markings

Figure 9-1 shows the top-side marking for the CC2651R3SIPA module.

CC2651

R SIPA

NNN NNNN

Figure 9-1. Top-Side Marking

Table 9-3 lists the CC2651R3SIPA module markings.

Table 9-3. Module Descriptions

MARKING

CC2651

R

DESCRIPTION

Generic Part Number

Model

SIPA

SIPA = Module type, X = pre-release

LTC (Lot Trace Code)

NNN NNNN

9.16 End Product Labeling

The CC2651R3SIPA module complies with the FCC single modular FCC grant, FCC ID: ZAT-2651R3SIPA. The

host system using this module must display a visible label indicating the following text:

Contains FCC ID: ZAT-2651R3SIPA

The CC2651R3SIPA module complies with the IC single modular IC grant, IC: 451H-2651R3SIPA. The host

system using this module must display a visible label indicating the following text:

Contains IC: 451H-2651R3SIPA

For more information on end product labeling and a sample label, please see section 4 of the OEM Integrators

Guide

9.17 Manual Information to the End User

The OEM integrator must be aware not to provide information to the end user regarding how to install or remove

this RF module in the user’s manual of the end product which integrates this module.

The end user manual must include all required regulatory information and warnings as shown in this manual.

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10 Application, Implementation, and Layout

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Typical Application Circuit

Figure 10-1 shows the typical application schematic using the the CC2651R3SIPA module. Note that C15 should

be assembled when using the integrated antenna option within the module. C14 should be assembled if the

module is to be used with an external antenna. In addition if using the external antenna option, Pin 16 of the

module can be left unconnected. For the full reference schematic, download the LP-CC2651R3SIPA Design

Files.

Note

The following guidelines are recommended for implementation of the RF design when using an

external anenna on the RF path, pin 14:

•

Ensure an RF path is designed with an impedance of 50 Ω.

Tuning of the antenna impedance π matching network is recommended after manufacturing of the

PCB to account for PCB parasitics.

•

π or L matching and tuning may be required between RF out path, pin 14, and the external

antenna.

CC2651R3SIPA

Figure 10-1. CC2651R3SIPA Typical Application Schematic

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Table 10-1 provides the bill of materials for a typical application using the CC2651R3SIPA module in Figure 10-1.

For full operation reference design, see the LP-CC2651R3SIPA Design Files.

Table 10-1. Bill of Materials

PART

REFERENCE

VALUE

15 pF

U.FL

MANUFACTURER

PART NUMBER

GRM0335C1E150JA01D

U.FL-R-SMT-1(01)

DESCRIPTION

C14, C15, C81,

C91⁽¹⁾

Capacitor, ceramic, 15 pF, 50 V, ±5%,

C0G/NP0, 0201

Murata

U.FL (UMCC) connector receptacle, male

pin 50 Ω, surface mount solder

J7

U49

Y6

Hirose

SimpleLink™ multiprotocol 2.4-GHz

CC2651R3SIPA

32.768kHz

Texas Instruments

TAI-SAW

CC2651R3SIPAT0MOUR wireless MCU with integrated power

amplifier and Antenna

Crystal, resonator, 32.768kHz, -40^oC /

TZ1166C

+125^oC, SMD

(1) C15 is placed when using the integrated antenna. C14 is placed when using an external antenna

10.2 Device Connections

10.2.1 Reset

In order to meet the module power-on-reset requirements, VDDS (Pin 37) and VDDS_PU (Pin 38) should be

connected together. If the reset signal is not based upon a power-on-reset and is derived from an external MCU,

then VDDS_PU (Pin 38) should be No Connect (NC). Please refer to Figure 10-1 for the recommended circuit

implementation.

10.2.2 Unused Pins

All unused pins can be left unconnected without the concern of having leakage current.

10.3 PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC2651R3SIPA module. The

integrator of the CC2651R3SIPA modules must comply with the PCB layout recommendations described in

the following subsections to minimize the risk with regulatory certifications for the FCC, IC/ISED, ETSI/CE.

Moreover, TI recommends customers to follow the guidelines described in this section to achieve similar

performance to that obtained with the TI reference design.

10.3.1 General Layout Recommendations

Ensure that the following general layout recommendations are followed:

•

Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.

Do not run signal traces underneath the module on a layer where the module is mounted.

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10.3.2 RF Layout Recommendations with Integrated Antenna

It is critical that the RF section be laid out correctly to ensure optimal module performance. A poor layout can

cause low-output power and sensitivity degradation. Figure 10-2 shows the RF placement and routing of the

CC2651R3SIPA module with the 2.4-GHz integrated antenna.

A: 0.5 mm

B: 1.00mm

C: 6.23 mm

D: 3.2mm

E: 0.25 mm

F: 26.98 mm

G: 10.0 mm

Figure 10-2. Module Layout Guidelines

Follow these RF layout recommendations for the CC2651R3SIPA module when using the integrated Antenna:

•

Dimensions A thru G in Figure 10-2 must be strickly adhered to for optimal RF performance

The module must have a minimum 10-mm ground plane on either side of the module on all layers as shown

with dimension G in Figure 10-2

•

There must be at least on ground-reference plane under the module on the main PCB

For the CC2651R3SIPA it is recommended to use 4-layer PCB board with the dimensions A thru G copied on all

4 layers. This will provided for the best antenna bandwidth in the 2.4GHz band. In addition, it s recommended

that the L1 to L2 layer be 0.175 mm, with a dielectric constant of 4.0, and have an overall 4-layer board

thickness of 1.6 mm as per our reference design, for optimal antenna RF performance. Deviation from this will

cause a potential detuning of the integrated antenna.

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10.4 Reference Designs

The following reference designs should be followed closely when implementing designs using the

CC2651R3SIPA device.

Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator

components, as well as ground connections for all of these.

CC2651RSIPA-EM Design

Files

The CC2651RSIP-EM reference design provides schematic, layout and

production files for the characterization board used for deriving the

performance number found in this document.

LP-CC2651R3SIPA Design

Files

The CC2651R3SIPA LaunchPad Design Files contain detailed schematics and

layouts to build application specific boards using the CC2651R3SIPA device.

Sub-1 GHz and 2.4 GHz

The antenna kit allows real-life testing to identify the optimal antenna for your

Antenna Kit for LaunchPad™ application. The antenna kit includes 16 antennas for frequencies from 169

Development Kit and

SensorTag

MHz to 2.4 GHz, including:

•

PCB antennas

Helical antennas

Chip antennas

Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz

The antenna kit includes a JSC cable to connect to the Wireless MCU

LaunchPad Development Kits and SensorTags.

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10.5 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating

conditions. For more details, see Semiconductor and IC Package Thermal Metrics.

There are three recommended ways to derive the junction temperature from other measured temperatures:

1. From package temperature:

T = ψ × P + T

case

(1)

(2)

(3)

J

JT

2. From board temperature:

T = ψ × P + T

board

J

JB

3. From ambient temperature:

T = R

× P + T

A

J

θJA

P is the power dissipated from the device and can be calculated by multiplying current consumption with supply

voltage. Thermal resistance coefficients are found in Section 8.8.

Example:

Using Equation 3, the temperature difference between ambient temperature and junction temperature is

calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm

output power. Let us assume the ambient temperature is 85 °C and the supply voltage is 3 V. To calculate P, we

need to look up the current consumption for Tx at 85 °C in. From the plot, we see that the current consumption is

7.8 mA. This means that P is 7.95 mA × 3 V = 23.85 mW.

The junction temperature is then calculated as:

°C

T = 48.7

J

× 23.85mW + T = 1.2°C + T

A A

W

As can be seen from the example, the junction temperature is 1.2°C higher than the ambient temperature when

running continuous Tx at 85 °C and, thus, well within the recommended operating conditions.

For various application use cases current consumption for other modules may have to be added to calculate the

appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral

modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the

peak power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current

consumption.

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11 Environmental Requirements and SMT Specifications

11.1 PCB Bending

The PCB follows IPC-A-600J for PCB twist and warpage < 0.75% or 7.5 mil per inch.

11.2 Handling Environment

11.2.1 Terminals

The product is mounted with motherboard through land-grid array (LGA). To prevent poor soldering, do not make

skin contact with the LGA portion.

11.2.2 Falling

The mounted components will be damaged if the product falls or is dropped. Such damage may cause the

product to malfunction.

11.3 Storage Condition

11.3.1 Moisture Barrier Bag Before Opened

A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH. The

calculated shelf life for the dry-packed product will be 24 months from the date the bag is sealed.

11.3.2 Moisture Barrier Bag Open

Humidity indicator cards must be blue, < 30%.

11.4 PCB Assembly Guide

The wireless MCU modules are packaged in a substrate base Leadless Quad Flatpack (QFM) package. The

modules are designed with pull back leads for easy PCB layout and board mounting.

11.4.1 PCB Land Pattern & Thermal Vias

We recommended a solder mask defined land pattern to provide a consistent soldering pad dimension in order

to obtain better solder balancing and solder joint reliability. PCB land pattern are 1:1 to module soldering pad

dimension. Thermal vias on PCB connected to other metal plane are for thermal dissipation purpose. It is critical

to have sufficient thermal vias to avoid device thermal shutdown. Recommended vias size are 0.2mm and

position not directly under solder paste to avoid solder dripping into the vias.

11.4.2 SMT Assembly Recommendations

The module surface mount assembly operations include:

•

Screen printing the solder paste on the PCB

Monitor the solder paste volume (uniformity)

Package placement using standard SMT placement equipment

X-ray pre-reflow check - paste bridging

Reflow

X-ray post-reflow check - solder bridging and voids

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11.4.3 PCB Surface Finish Requirements

A uniform PCB plating thickness is key for high assembly yield. For an electroless nickel immersion gold finish,

the gold thickness should range from 0.05 µm to 0.20 µm to avoid solder joint embrittlement. Using a PCB with

Organic Solderability Preservative (OSP) coating finish is also recommended as an alternative to Ni-Au.

11.4.4 Solder Stencil

Solder paste deposition using a stencil-printing process involves the transfer of the solder paste through pre-

defined apertures with the application of pressure. Stencil parameters such as aperture area ratio and the

fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of

package is highly recommended to improve board assembly yields.

11.4.5 Package Placement

Packages can be placed using standard pick and place equipment with an accuracy of ±0.05 mm. Component

pick and place systems are composed of a vision system that recognizes and positions the component and a

mechanical system that physically performs the pick and place operation. Two commonly used types of vision

systems are:

•

A vision system that locates a package silhouette

A vision system that locates individual pads on the interconnect pattern

The second type renders more accurate placements but tends to be more expensive and time consuming. Both

methods are acceptable since the parts align due to a self-centering features of the solder joint during solder

reflow. It is recommended to avoid solder bridging to 2 mils into the solder paste or with minimum force to avoid

causing any possible damage to the thinner packages.

11.4.6 Solder Joint Inspection

After surface mount assembly, transmission X-ray should be used for sample monitoring of the solder

attachment process. This identifies defects such as solder bridging, shorts, opens, and voids. It is also

recommended to use side view inspection in addition to X-rays to determine if there are "Hour Glass" shaped

solder and package tilting existing. The "Hour Glass" solder shape is not a reliable joint. 90° mirror projection can

be used for side view inspection.

11.4.7 Rework and Replacement

TI recommends removal of modules by rework station applying a profile similar to the mounting process. Using a

heat gun can sometimes cause damage to the module by overheating.

11.4.8 Solder Joint Voiding

TI recommends to control solder joint voiding to be less than 30% (per IPC-7093). Solder joint voids could

be reduced by baking of components and PCB, minimized solder paste exposure duration, and reflow profile

optimization.

11.5 Baking Conditions

Products require baking before mounting if:

•

Humidity indicator cards read > 30%

Temp < 30°C, humidity < 70% RH, over 96 hours

Baking condition: 90°C, 12 to 24 hours

Baking times: 1 time

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11.6 Soldering and Reflow Condition

•

Heating method: Conventional convection or IR convection

Temperature measurement: Thermocouple d = 0.1 mm to 0.2 mm CA (K) or CC (T) at soldering portion or

equivalent method

•

Solder paste composition: SAC305

Allowable reflow soldering times: 2 times based on the reflow soldering profile (see Figure 11-1)

Temperature profile: Reflow soldering will be done according to the temperature profile (see

Figure 11-1)

•

Peak temperature: 260°C

Figure 11-1. Temperature Profile for Evaluation of Solder Heat Resistance of a Component (at Solder

Joint)

Table 11-1. Temperature Profile

Profile Elements

Convection or IR⁽¹⁾

Peak temperature range

235 to 240°C typical (260°C maximum)

Pre-heat / soaking (150 to 200°C)

Time above melting point

Time with 5°C to peak

Ramp up

60 to 120 seconds

60 to 90 seconds

30 seconds maximum

< 3°C / second

Ramp down

< -6°C / second

(1) For details, refer to the solder paste manufacturer's recommendation.

Note

TI does not recommend the use of conformal coating or similar material on the SimpleLink™ module.

This coating can lead to localized stress on the solder connections inside the module and impact

the module reliability. Use caution during the module assembly process to the final PCB to avoid the

presence of foreign material inside the module.

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed as follows.

12.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or

date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example,

XCC2651R3SIPA is in preview; therefore, an X prefix/identification is assigned).

Device development evolutionary flow:

X

P

Experimental device that is not necessarily representative of the final device's electrical specifications and

may not use production assembly flow.

Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical

specifications.

null Production version of the silicon die that is fully qualified.

Production devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (X or P) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, RGZ).

For orderable part numbers of CC2651R3SIPA devices in the RGZ (7-mm x 7-mm) package type, see the

Package Option Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com),

or contact your TI sales representative.

CC2651 R

3

SIP

A

T

0

MOU

R

PREFIX

X = Experimental device

Blank = Qualified devie

R = Large Reel

PACKAGE DESIGNATOR

MOU = LGA Package

DEVICE

SimpleLink™ Ultra-Low-Power

Wireless MCU

PRODUCTION REVISION

TEMPERATURE

T = 105^oC Ambient

CONFIGURATION

R = Regular

MODULE

P = +10 dBm PA included

SIP = System-in-Package

ANTENNA

A = Integrated antenna

Blank = No antenna

FLASH SIZE

3 = 352 kB

Figure 12-1. Device Nomenclature

12.2 Tools and Software

The CC2651R3SIPA device is supported by a variety of software and hardware development tools.

Development Kit

CC2651R3SIPA

LaunchPad™

Development Kit

The CC2651R3SIPA LaunchPad^™Development Kit enables development of high-

performance wireless applications that benefit from low-power operation. The kit

features the CC2651R3SIPA SimpleLink Wireless system-in-Package, which allows you

to quickly evaluate and prototype 2.4-GHz wireless applications such as Bluetooth 5

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Low Energy and Zigbee, plus combinations of these. The kit works with the LaunchPad

ecosystem, easily enabling additional functionality like sensors, display and more.

Software

SimpleLink™

CC13XX-

CC26XX SDK

The SimpleLink CC13xx and CC26xx Software Development Kit (SDK) provides a complete

package for the development of wireless applications on the CC13XX / CC26XX family

of devices. The SDK includes a comprehensive software package for the CC2651R3SIPA

module, including the following protocol stacks:

•

Bluetooth Low Energy 4 and 5.2

Thread (based on OpenThread)

Zigbee 3.0

TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and

2.4 GHz

The SimpleLink CC13XX-CC26XX SDK is part of TI’s SimpleLink MCU platform, offering a

single development environment that delivers flexible hardware, software and tool options

for customers developing wired and wireless applications. For more information about the

SimpleLink MCU Platform, visit http://www.ti.com/simplelink.

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Development Tools

Code Composer

Code Composer Studio is an integrated development environment (IDE) that supports TI's

Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a

suite of tools used to develop and debug embedded applications. It includes an optimizing

C/C++ compiler, source code editor, project build environment, debugger, profiler, and many

other features. The intuitive IDE provides a single user interface taking you through each

step of the application development flow. Familiar tools and interfaces allow users to get

started faster than ever before. Code Composer Studio combines the advantages of the

Eclipse^®software framework with advanced embedded debug capabilities from TI resulting

in a compelling feature-rich development environment for embedded developers.

Studio^™Integrated

Development

Environment (IDE)

CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace^™

software (application energy usage profiling). A real-time object viewer plugin is available

for TI-RTOS, part of the SimpleLink SDK.

Code Composer Studio is provided free of charge when used in conjunction with the XDS

debuggers included on a LaunchPad Development Kit.

Code Composer

Studio™ Cloud

IDE

Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and

build CCS and Energia™ projects. After you have successfully built your project, you can

download and run on your connected LaunchPad. Basic debugging, including features like

setting breakpoints and viewing variable values is now supported with CCS Cloud.

IAR Embedded

Workbench^®for

Arm^®

IAR Embedded Workbench^®is a set of development tools for building and debugging

embedded system applications using assembler, C and C++. It provides a completely

integrated development environment that includes a project manager, editor, and build

tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,

including XDS110, IAR I-jet^™and Segger J-Link^™. A real-time object viewer plugin is

available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box

on most software examples provided as part of the SimpleLink SDK.

A 30-day evaluation or a 32 KB size-limited version is available through iar.com.

SmartRF™ Studio

SmartRF™ Studio is a Windows^®application that can be used to evaluate and configure

SimpleLink Wireless MCUs from Texas Instruments. The application will help designers

of RF systems to easily evaluate the radio at an early stage in the design process. It is

especially useful for generation of configuration register values and for practical testing

and debugging of the RF system. SmartRF Studio can be used either as a standalone

application or together with applicable evaluation boards or debug probes for the RF device.

Features of the SmartRF Studio include:

•

Link tests - send and receive packets between nodes

Antenna and radiation tests - set the radio in continuous wave TX and RX states

Export radio configuration code for use with the TI SimpleLink SDK RF driver

Custom GPIO configuration for signaling and control of external switches

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CCS UniFlash

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.

UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free

of charge.

12.2.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of

wired and wireless Arm^®MCUs (System-on-Chip) in a single software development environment. Delivering

flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software

development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.

12.3 Documentation Support

To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate

to the device product folder on ti.com/product/CC2651R3SIPA In the upper right corner, click on Alert me to

register and receive a weekly digest of any product information that has changed. For change details, review the

revision history included in any revised document.

The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as

follows.

TI Resource Explorer

Software examples, libraries, executables, and documentation are available for your

device and development board.

Errata

CC2651R3SIPA Silicon

Errata

The silicon errata describes the known exceptions to the functional specifications

for each silicon revision of the device and description on how to recognize a

device revision.

Application Reports

All application reports for the CC2651R3SIPA device are found on the device product folder at: ti.com/product/

CC2651R3SIPA/technicaldocuments.

Technical Reference Manual (TRM)

CC13x1x3, CC26x1x3 SimpleLink™

Wireless MCU TRM

The TRM provides a detailed description of all modules and

peripherals available in the device family.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

LaunchPad^™, Code Composer Studio^™, EnergyTrace^™, and TI E2E^™are trademarks of Texas Instruments.

I-jet^™is a trademark of IAR Systems AB.

J-Link^™is a trademark of SEGGER Microcontroller Systeme GmbH.

Arm Thumb^®is a registered trademark of Arm Limited (or its subsidiaries).

Eclipse^®is a registered trademark of Eclipse Foundation.

IAR Embedded Workbench^®is a registered trademark of IAR Systems AB.

Windows^®is a registered trademark of Microsoft Corporation.

All trademarks are the property of their respective owners.

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12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Note

The total height of the module is 1.51 mm.

The weight of the CC2651R3SIPA module is typically 0.182 g.

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PACKAGE OUTLINE

MOU0050A

QFM - 1.51 mm max height

S

C

A

L

E

2

.

2

0

QUAD FLAT MODULE

7.1

6.9

B

A

PIN 1 CORNER

7.1

6.9

1.51

1.35

C

SEATING PLANE

0.1 C

0.372

0.292

PKG

0.338

0.262

46 X

15

13

16

0.538

46 X

0.462

50

40

0.15

0.05

C A B

C

1.6

PKG

51

53

6.2

56

59

54

57

1

0.338

0.262

9 X

0.15

C A B

C

0.05

28

1

39

0.538

0.462

0.15

0.05

0.5 TYP

7 X 0.6

4 X

1

C A B

C

6.2

4226342/B 12/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

MOU0050A

QFM - 1.51 mm max height

QUAD FLAT MODULE

(6.2)

(1)

4 X ( 0.5)

39

28

1

METAL UNDER

SOLDER MASK

7 X (0.6)

SOLDER MASK

OPENING

(0.5)

TYP

46 X (0.5)

57

54

51

59

(1)

56

53

PKG

(6.2)

(R0.05)

TYP

9 X ( 0.3)

(1.6)

40

50

46 x (0.3)

16

13

15

PKG

0.05 MIN

ALL AROUND

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:15X

4226342/B 12/2020

NOTES: (continued)

3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

MOU0050A

QFM - 1.51 mm max height

QUAD FLAT MODULE

(6.2)

(1)

4 X ( 0.5)

39

1

28

7 X (0.6)

46 X (0.5)

(0.5)

TYP

57

54

51

59

(1)

56

53

PKG

(6.2)

(R0.05)

TYP

9 X ( 0.3)

(1.6)

40

50

46 X (0.3)

16

13

15

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4226342/B 12/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CC2651R3SIPAT0MOUR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成天线的 SimpleLink™ 多协议 2.4GHz 无线系统级封装模块 \| MOU \| 50 \| -40 to 105 无线
文件：	总68页 (文件大小：2639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC2651R3SIPAT0MOUR [TI]

相关型号：

CC2652P

CC2652P1FRGZR

CC2652P7

CC2652P74T0RGZR

CC2652PSIP

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