CC2662R-Q1 [TI]
用于无线电池管理系统且通过汽车认证的 SimpleLink™ 无线 MCU;型号: | CC2662R-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 用于无线电池管理系统且通过汽车认证的 SimpleLink™ 无线 MCU 电池 无线 |
文件: | 总54页 (文件大小:3061K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CC2662R-Q1
ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
CC2662R-Q1 SimpleLink™ 无线BMS MCU
高性能无线电
1 特性
• –92dBm RX 灵敏度,用于专有WBMS 协议
• 高达+5dBm 的输出功率,具有温度补偿
无线微控制器
• 功能强大的48MHz Arm® Cortex®-M4F 处理器
• EEMBC CoreMark® 评分:148
• 352KB 闪存程序存储器
• 256KB ROM,用于协议和库函数
• 8KB 高速缓存SRAM
法规遵从性
• 适用于符合以下标准的系统:
– ETSI EN 300 328、EN 300 440 类别2 和3
– FCC CFR47 第15 部分
• 具有奇偶校验功能的80KB 超低泄漏SRAM,可实
现高度可靠运行
• 2 引脚cJTAG 和JTAG 调试
• 支持无线升级(OTA)
– ARIB STD-T66
MCU 外设
• 数字外设可连接至31 个GPIO 中的任何一个
• 四个32 位或八个16 位通用计时器
• 12 位ADC、200ksps、8 通道
• 8 位DAC
• 支持SimpleLink™ WBMS 的可编程无线电
超低功耗传感器控制器
• 具有4KB SRAM 的自主MCU
• 采样、存储和处理传感器数据
• 快速唤醒进入低功耗运行
• 两个比较器
• 两个UART、两个SSI、I2C、I2S
• 实时时钟(RTC)
• 集成温度和电池监控器
• 软件定义外设;电容式触控、流量计、LCD
符合汽车应用要求
安全驱动工具
• 具有符合AEC-Q100 标准的下列特性:
• AES 128 位和256 位加密加速计
• ECC 和RSA 公钥硬件加速器
• SHA2 加速器(最高到SHA-512 的全套装)
• 真随机数发生器(TRNG)
– 器件温度等级2:-40°C 至+105°C 环境工作温
度范围
– 器件人体模型(HBM) 静电放电(ESD) 分类等级
2
开发工具和软件
– 器件CDM ESD 分类等级C3
• 功能安全质量管理型
• CC2662RQ1-EVM-WBMS 开发套件
• SimpleLink™ WBMS 软件开发套件
• 用于简单无线电配置的SmartRF™ Studio
• 用于构建低功耗检测应用的Sensor Controller
Studio
– 可帮助进行功能安全系统设计的文档
低功耗
• MCU 功耗:
– 3.4 mA 有源模式,CoreMark®
– 71μA/MHz(运行CoreMark® 时)
– 0.94μA 待机模式,RTC,80KB RAM
– 0.15 μA 关断模式,引脚唤醒
• SysConfig 系统配置工具
工作温度范围
• 片上降压直流/直流转换器
• 1.8V 至3.63V 单电源电压
• -40°C 至+105°C
• 超低功耗传感器控制器功耗:
– 2 MHz 模式下为31.9μA
– 24MHz 模式下为808.5μA
• 无线电功耗
封装
• 具有可湿性侧面的7mm × 7mm RGZ VQFN48(31
个GPIO)
• 符合RoHS 标准的封装
– RX:6.9 mA
– TX:7.0 mA(在0dBm 条件下)
– TX:9.2 mA(在+5dBm 条件下)
无线协议支持
• SimpleLink™ WBMS
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SWRS259
CC2662R-Q1
ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
www.ti.com.cn
– 无线电池管理系统(BMS)
• 电缆替代
2 应用
• 汽车
3 说明
SimpleLink™ 2.4GHz CC2662R-Q1 器件是一款符合 AEC-Q100 标准的无线微控制器 (MCU),面向无线汽车应
用。该器件针对应用中的低功耗无线通信进行了优化,例如电池管理系统 (BMS) 和电缆更换。该器件的突出特性
包括:
• 支持TI 的SimpleLink 无线BMS (WBMS) 协议,可实现稳健、低延迟和高吞吐量的通信。
• 功能安全质量管理分级,包括TI 质量管理开发过程,以及将要提供的功能安全时基故障率计算、FMEDA 和功
能安全文档。
• 符合AEC-Q100 标准,提供2 级温度范围(–40°C 至+105°C),并采用具有可湿性侧面的
7mm x 7mm VQFN 封装。
• 完全RAM 保持时,具有0.94µA 的低待机电流。
• 出色的97dBm 无线电链路预算。
CC2662R-Q1 器件是 SimpleLink™ MCU 平台的一部分,该平台包括 Wi-Fi®、低功耗蓝牙、Thread、Zigbee®、
Sub-1GHz MCU 和主机 MCU,它们共用一个通用的易用型开发环境和丰富的工具集。如需更多信息,请访问
SimpleLink™ MCU 平台。
器件信息(1)
封装尺寸(标称值)
器件型号
封装
CC2662R1FTWRGZRQ1
VQFN (48)
7.00mm × 7.00mm
(1) 有关最新器件、封装和所有可用器件的订购信息,请参阅封装选项附录或浏览TI 网站。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SWRS259
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ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
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4 Functional Block Diagram
2.4 GHz
RF Core
cJTAG
Main CPU
256KB
ROM
ADC
ADC
Arm®
Cortex®-M4F
Processor
Up to
352KB
Flash
Digital PLL
with 8KB
Cache
DSP Modem
48 MHz
71 µA/MHz (3.0 V)
16KB
SRAM
Arm®
Cortex®-M0
Processor
Up to
80KB
SRAM
ROM
with Parity
General Hardware Peripherals and Modules
Sensor Interface
I2C and I2S
4× 32-bit Timers
2× SSI (SPI)
Watchdog Timer
TRNG
Sensor Controller
8-bit DAC
2× UART
12-bit ADC, 200 ks/s
2x Low-Power Comparator
SPI-I2C Digital Sensor IF
Capacitive Touch IF
Time-to-Digital Converter
4KB SRAM
32 ch. µDMA
31 GPIOs
Temperature and
Battery Monitor
AES-256, SHA2-512
ECC, RSA
RTC
LDO, Clocks, and References
Optional DC/DC Converter
图4-1. CC2662R-Q1 Block Diagram
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English Data Sheet: SWRS259
CC2662R-Q1
ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
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Table of Contents
9.2 System CPU............................................................. 31
9.3 Radio (RF Core)........................................................32
9.4 Memory.....................................................................33
9.5 Sensor Controller......................................................34
9.6 Cryptography............................................................ 35
9.7 Timers....................................................................... 36
9.8 Serial Peripherals and I/O.........................................37
9.9 Battery and Temperature Monitor............................. 37
9.10 µDMA......................................................................37
9.11 Debug......................................................................37
9.12 Power Management................................................38
9.13 Clock Systems........................................................ 39
9.14 Network Processor..................................................39
10 Application, Implementation, and Layout................. 40
10.1 Reference Designs................................................. 40
10.2 Junction Temperature Calculation...........................41
11 Device and Documentation Support..........................42
11.1 Device Nomenclature..............................................42
11.2 Tools and Software..................................................42
11.3 Documentation Support.......................................... 44
11.4 支持资源..................................................................44
11.5 Trademarks............................................................. 44
11.6 静电放电警告...........................................................45
11.7 术语表..................................................................... 45
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison.........................................................5
7 Terminal Configuration and Functions..........................6
7.1 Pin Diagram –RGZ Package (Top View)..................6
7.2 Signal Descriptions..................................................... 7
7.3 Connections for Unused Pins and Modules................8
8 Specifications.................................................................. 9
8.1 Absolute Maximum Ratings........................................ 9
8.2 ESD Ratings............................................................... 9
8.3 Recommended Operating Conditions.........................9
8.4 Power Supply and Modules........................................ 9
8.5 Power Consumption - Power Modes........................ 10
8.6 Power Consumption - Radio Modes......................... 11
8.7 Nonvolatile (Flash) Memory Characteristics............. 11
8.8 Thermal Resistance Characteristics......................... 11
8.9 Receive (RX) ............................................................12
8.10 Transmit (TX).......................................................... 13
8.11 Timing and Switching Characteristics..................... 13
8.12 Peripheral Characteristics.......................................18
8.13 Typical Characteristics............................................25
9 Detailed Description......................................................31
9.1 Overview...................................................................31
Information.................................................................... 46
5 Revision History
Changes from December 11, 2020 to May 19, 2023 (from Revision A (June 2022) to Revision B
(May 2023))
Page
• 更改了节1 特性 中的“无线电功耗”(TX 电流)............................................................................................ 1
• 更新了整个数据表中各部分、图和表格的编号....................................................................................................1
• 根据最新文档标准更新了整个数据表的格式....................................................................................................... 1
• 添加了量产数据.................................................................................................................................................. 1
• Changed package options for CC2340R2..........................................................................................................5
• Changed the TYP values of the "Radio transmit current" parameter in 节8.6 Power Consumption - Radio
Modes .............................................................................................................................................................. 11
• Updated 表8-1 Typical TX Current and Output Power ....................................................................................27
Changes from May 19, 2023 to July 12, 2023 (from Revision B (May 2023) to Revision C (July
2023))
Page
• 将“48MHz Arm Cortex-M4”更新为“Arm Cortex-M4F”............................................................................... 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SWRS259
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6 Device Comparison
RADIO SUPPORT
PACKAGE SIZE
FLASH
(KB)
RAM +
GPIO
Device
Cache (KB)
CC1310
CC1311R3
CC1311P3
CC1312R
CC1312R7
CC1352R
CC1352P
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32-128
352
352
352
704
352
352
704
512
16-20 + 8 10-30
X
X
X
X
X
X
X
X
X
X
32 + 8
32 + 8
80 + 8
144 + 8
80 + 8
80 + 8
144 + 8
36
22-30
26
X
X
X
30
X
X
X
X
X
X
X
X
X
X
30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
28
X
X
26
CC1352P7
CC2340R5(1)
26
X
X
12-26
X
CC2640R2F
CC2642R
X
X
X
X
X
X
X
X
X
X
128
352
352
352
352
352
352
704
352
704
352
20 + 8
80 + 8
80 + 8
32 + 8
32 + 8
80 + 8
80 + 8
144 + 8
80 + 8
144 + 8
80 + 8
10-31
31
X
X
X
X
X
X
X
X
X
X
X
X
X
CC2642R-Q1
CC2651R3
CC2651P3
CC2652R
31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
23-31
22-26
31
X
X
X
X
X
X
X
X
X
X
X
X
X
CC2652RB
CC2652R7
CC2652P
31
31
X
X
26
CC2652P7
CC2662R-Q1
26
31
(1) ZigBee and Thread support enabled by future software update
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English Data Sheet: SWRS259
CC2662R-Q1
ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
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7 Terminal Configuration and Functions
7.1 Pin Diagram –RGZ Package (Top View)
RF_P
RF_N
1
2
3
4
5
6
7
8
9
36 DIO_23
35 RESET_N
34 VDDS_DCDC
33 DCDC_SW
32 DIO_22
X32K_Q1
X32K_Q2
DIO_0
DIO_1
31 DIO_21
DIO_2
30 DIO_20
DIO_3
29 DIO_19
DIO_4
28 DIO_18
DIO_5 10
DIO_6 11
DIO_7 12
27 DIO_17
26 DIO_16
25 JTAG_TCKC
图7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in 图7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in 图7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30
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English Data Sheet: SWRS259
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7.2 Signal Descriptions
表7-1. Signal Descriptions –RGZ Package
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
33
23
5
DCDC_SW
DCOUPL
DIO_0
Power
Power
Output from internal DC/DC converter(1)
1.27-V regulated digital-supply (decoupling capacitor)(2)
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Digital
DIO_1
6
Digital
DIO_2
7
Digital
DIO_3
8
Digital
DIO_4
9
Digital
DIO_5
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
Digital
DIO_6
Digital
DIO_7
Digital
DIO_8
Digital
DIO_9
Digital
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
EGP
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
Digital
Digital
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
GND
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
Ground –exposed ground pad
JTAG TMSC, high-drive capability
JTAG TCKC
—
24
25
35
—
I/O
I
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital
Digital
I
Digital
Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_P
RF_N
VDDR
1
2
RF
RF
—
—
—
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
converter or the internal Global LDO(3) (2)
45
Power
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表7-1. Signal Descriptions –RGZ Package (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
1.7-V to 1.95-V supply, must be powered from the internal DC/DC
converter or the internal Global LDO(4) (2)
VDDR_RF
48
Power
—
VDDS
44
13
22
34
46
47
3
Power
Power
Power
Power
Analog
Analog
Analog
Analog
1.8-V to 3.63-V main chip supply(1)
1.8-V to 3.63-V DIO supply(1)
1.8-V to 3.63-V DIO supply(1)
1.8-V to 3.63-V DC/DC converter supply
48-MHz crystal oscillator pin 1
48-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
—
—
—
—
—
—
—
—
VDDS2
VDDS3
VDDS_DCDC
X48M_N
X48M_P
X32K_Q1
X32K_Q2
4
(1) For more details, see the technical reference manual listed in 节11.3.
(2) Do not supply external circuitry from this pin.
(3) If internal DC/DC converter is not used, this pin is supplied internally from the Global LDO.
(4) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the Global LDO.
7.3 Connections for Unused Pins and Modules
表7-2. Connections for Unused Pins
PREFERRED
PRACTICE(1)
FUNCTION
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE(1)
5–12
14–21
26–32
36–43
GPIO
DIO_n
NC or GND
NC
NC
X32K_Q1
3
4
32.768-kHz crystal
NC
X32K_Q2
DCDC_SW
VDDS_DCDC
33
34
NC
NC
DC/DC converter(2)
VDDS
VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the VDDR decoupling capacitor must be connected and moved close to VDDR.
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English Data Sheet: SWRS259
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX UNIT
VDDS(3)
Supply voltage
4.1
VDDS + 0.3, max 4.1
VDDR + 0.3, max 2.25
VDDS
V
V
V
Voltage on any digital pin (4) (5)
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
Voltage scaling enabled
Vin
Voltage on ADC input
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
1.49
V
VDDS / 2.9
Tstg
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIO.
(5) Injection current is not supported on any GPIO pin
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per AEC Q100-002(1) (2)
Charged device model (CDM), per AEC Q100-011(3)
All pins
All pins
VESD
Electrostatic discharge
V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
105
3.63
100
20
UNIT
°C
Operating ambient temperature range
Operating supply voltage (VDDS)
Rising supply voltage slew rate
Falling supply voltage slew rate(1)
–40
1.8
0
V
mV/µs
mV/µs
0
(1) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TYP
1.1 - 1.55
1.77
UNIT
VDDS Power-on-Reset (POR) threshold
V
V
V
V
VDDS Brown-out Detector (BOD)
Rising threshold
Rising threshold
Falling threshold
VDDS Brown-out Detector (BOD), before initial boot (1)
VDDS Brown-out Detector (BOD)
1.70
1.75
(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
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8.5 Power Consumption - Power Modes
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold
Shutdown. No clocks running, no retention
150
150
Reset and Shutdown
nA
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
0.94
1.09
3.2
µA
µA
µA
µA
µA
mA
Standby
without cache retention
RTC running, CPU, 80KB RAM and (partial) register retention
XOSC_LF
RTC running, CPU, 80KB RAM and (partial) register retention.
RCOSC_LF
Icore
Standby
with cache retention
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF
3.3
Supply Systems and RAM powered
RCOSC_HF
Idle
675
3.39
MCU running CoreMark at 48 MHz
RCOSC_HF
Active
Peripheral Current Consumption
Peripheral power
domain
Delta current with domain enabled
Delta current with domain enabled
97.7
7.2
Serial power domain
RF Core
Delta current with power domain enabled,
clock enabled, RF Core idle
210.9
µDMA
Timers
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(3)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(1)
Delta current with clock enabled, module is idle(2)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
63.9
81.0
10.8
27.6
82.9
167.5
25.6
84.7
35.6
Iperi
µA
I2C
I2S
SSI
UART
CRYPTO (AES)
PKA
TRNG
Sensor Controller Engine Consumption
Active mode
ISCE
24 MHz, infinite loop
2 MHz, infinite loop
808.5
31.9
µA
Low-power mode
(1) Only one UART running
(2) Only one SSI running
(3) Only one GPTimer running
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8.6 Power Consumption - Radio Modes
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
TYP UNIT
Radio receive current
2440 MHz
6.9
7.0
mA
mA
0 dBm output power setting
2440 MHz
Radio transmit current
+5 dBm output power setting
2440 MHz
9.2
mA
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Flash sector size
8
KB
Supported flash erase cycles before failure, full bank(1)
Supported flash erase cycles before failure, single sector(2)
30
60
k Cycles
k Cycles
Write
Maximum number of write operations per row before sector
erase(3)
83
Operations
Years at 105
°C
Flash retention
105 °C
11.4
Flash sector erase current
Flash sector erase time(4)
Flash sector erase time(4)
Flash write current
Average delta current
Zero cycles
10.7
10
mA
ms
ms
mA
µs
30k cycles
4000
Average delta current, 4 bytes at a time
4 bytes at a time
6.2
Flash write time
21.6
(1) A full bank erase is counted as a single erase cycle on each sector
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
8.8 Thermal Resistance Characteristics
PACKAGE
RGZ
THERMAL METRIC(1)
UNIT
(VQFN)
48 PINS
24.2
13.6
7.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJT
7.7
ψJB
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
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8.9 Receive (RX)
When measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF = 2440 MHz with DC/DC
enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2 Mbps
Differential mode. Measured at SMA connector, BER =
10–3
Receiver sensitivity
dBm
dBm
kHz
ppm
dB
–92
> 5
Differential mode. Measured at SMA connector, BER =
10–3
Receiver saturation
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
Data rate error tolerance
Co-channel rejection(1)
> (–440 / 500)
> (–700 / 750)
–7
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3
Selectivity, ±2 MHz(1)
8 / 4(2)
33 / 31(2)
37 / 32(2)
4
dB
dB
dB
dB
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(1)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±6
Selectivity, ±6 MHz or more(1)
Selectivity, image frequency(1)
MHz or more, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at
image frequency, BER = 10–3
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
Selectivity, image frequency
±2 MHz(1)
–7 / 36(2)
dB
Out-of-band blocking(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
dBm
dBm
dBm
–16
–21
–15
–12
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
Intermodulation
dBm
–38
RSSI dynamic range
RSSI Accuracy (+/-)
63
±4
dB
dB
(1) Numbers given as I/C dB
(2) X / Y, where X is +N MHz and Y is –N MHz
(3) Excluding one exception at Fwanted / 2
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8.10 Transmit (TX)
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
5dBm output power
5
dBm
dB
Differential mode, delivered to a single-ended 50 Ωload through a balun
Differential mode, delivered to a single-ended 50 Ωload through a balun
Output power
programmable range
26
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands +5 dBm setting
dBm
dBm
dBm
dBm
dBm
dBm
< –36
< –54
< –55
< –42
< –42
< –42
f < 1 GHz, restricted bands ETSI
+5 dBm setting
+5 dBm setting
+5 dBm setting
+5 dBm setting
+5 dBm setting
Spurious emissions (1)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
Harmonics (1)
Third harmonic
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Category 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
8.11 Timing and Switching Characteristics
8.11.1 Reset Timing
PARAMETER
MIN
TYP
MAX
UNIT
RESET_N low duration
1
µs
8.11.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
TEST CONDITIONS
MIN
TYP
850 - 3000
850 - 3000
160
MAX
UNIT
MCU, Reset to Active(1)
µs
µs
µs
µs
µs
MCU, Shutdown to Active(1)
MCU, Standby to Active
MCU, Active to Standby
MCU, Idle to Active
36
14
(1) The wakeup time is dependent on remaining charge on the VDDR capacitor when starting the device, and thus how long the device
has been in Reset or Shutdown before starting up again.
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8.11.3 Clock Specifications
8.11.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
MAX
UNIT
Crystal frequency
48
MHz
Equivalent series resistance
6 pF < CL ≤9 pF
ESR
ESR
20
60
80
Ω
Equivalent series resistance
5 pF < CL ≤ 6 pF
Ω
Motional inductance, relates to the load capacitance that is used for the crystal (CL
in Farads)(5)
2
LM
CL
< 0.3 × 10–24 / CL
H
Crystal load capacitance(4)
Start-up time(2)
5
7(3)
9
pF
µs
200
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated within the device.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.11.3.2 48 MHz RC Oscillator (RCOSC_HF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
%
Frequency
48
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Start-up time
±1
±0.25
5
%
µs
(1) Accuracy relative to the calibration source (XOSC_HF)
8.11.3.3 2 MHz RC Oscillator (RCOSC_MF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
µs
Calibrated frequency
Start-up time
2
5
8.11.3.4 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
Crystal frequency
ESR
CL
Equivalent series resistance
Crystal load capacitance
100
12
6
7(1)
pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.11.3.5 32 kHz RC Oscillator (RCOSC_LF)
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.8 (1) (2)
±50
MAX
UNIT
kHz
Calibrated frequency
Temperature coefficient
ppm/C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
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(2) The SIMPLELINK-WBMS-SDK does not use RCOSC_LF, but XOSC_LF.
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8.11.4 Synchronous Serial Interface (SSI) Characteristics
8.11.4.1 Synchronous Serial Interface (SSI) Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
PARAMETER
NO.
MIN
TYP
MAX
UNIT
S1
tclk_per
tclk_high
tclk_low
SSIClk cycle time
SSIClk high time
SSIClk low time
12
65024
System Clocks (2)
tclk_per
S2(1)
S3(1)
0.5
0.5
tclk_per
(1) Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3.
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
图8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
图8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
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图8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
8.11.5 UART
8.11.5.1 UART Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
UART rate
3
MBaud
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8.12 Peripheral Characteristics
8.12.1 ADC
Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
12
Bits
Sample rate
200
kSamples/s
LSB
Offset
Internal 4.3 V equivalent reference(2)
–0.24
7.14
>–1
±4
Gain error
Internal 4.3 V equivalent reference(2)
LSB
DNL(4)
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
9.8
10.1
11.1
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
ENOB
Effective number of bits
Bits
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal reference, voltage scaling disabled,
11.3
11.6
14-bit mode, 200 kSamples/s, 600 Hz input tone (5)
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 150 Hz input tone (5)
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
–65
–70
–72
THD
Total harmonic distortion
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
dB
dB
dB
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
63
68
Signal-to-noise
and
distortion ratio
SINAD,
SNDR
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
73
75
SFDR
Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Internal 4.3 V equivalent reference(2)
VDDS as reference
50
0.42
0.6
clock-cycles
Current consumption
Current consumption
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Reference voltage
4.3(2) (3)
V
Fixed internal reference (input voltage scaling disabled). For
best accuracy, the ADC conversion should be initiated through
the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Reference voltage
1.48
V
Vref = 4.3 V × 1408 / 4095
Reference voltage
Reference voltage
VDDS as reference, input voltage scaling enabled
VDDS as reference, input voltage scaling disabled
VDDS
V
V
VDDS /
2.82(3)
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Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
Input impedance
>1
MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings (see Section 8.1 ) at all times
(4) No missing codes
(5) ADC_output = ∑(4n samples) >> n,n = desired extra bits
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8.12.2 DAC
8.12.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Parameters
Resolution
8
Bits
V
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
Any load, VREF = DCOUPL, pre-charge ON
Buffer OFF (internal load)
1.8
2.6
16
3.63
3.63
1000
VDDS
FDAC
Supply voltage
Clock frequency
kHz
Voltage output settling time
VREF = VDDS, buffer OFF, internal load
13
±1
1 / FDAC
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
Differential nonlinearity
Differential nonlinearity
DNL
LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
±1.2
FDAC = 16 kHz
VREF = VDDS= 3.63 V
±0.67
±0.81
±1.27
±3.43
±2.88
±0.77
±0.77
±3.46
±3.44
±4.70
±1.61
±1.71
±2.10
±6.00
±3.85
±2.92
±3.06
±3.91
±7.84
±4.06
0.03
VREF = VDDS= 3.0 V
Offset error(2)
Load = Continuous Time
Comparator
VREF = VDDS = 1.8 V
LSB(1)
LSB(1)
LSB(1)
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = VDDS = 3.63 V
VREF = VDDS = 3.0 V
Offset error(2)
Load = Low Power Clocked
Comparator
VREF = VDDS= 1.8 V
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = VDDS = 3.63 V
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
VREF = VDDS = 3.0 V
VREF = VDDS= 1.8 V
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF =VDDS= 3.63 V
Max code output voltage
variation(2)
Load = Low Power Clocked
Comparator
VREF =VDDS= 3.0 V
VREF = VDDS= 1.8 V
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = VDDS= 3.63 V, code 1
VREF = VDDS= 3.63 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
3.46
0.02
2.86
Output voltage range(2)
Load = Continuous Time
Comparator
0.01
V
1.71
0.01
1.21
1.27
2.46
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Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.03
3.46
0.02
2.85
0.01
1.71
0.01
1.21
1.27
2.46
MAX
UNIT
VREF = VDDS= 3.63 V, code 1
VREF = VDDS= 3.63 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
Output voltage range(2)
Load = Low Power Clocked
Comparator
VREF = VDDS = 1.8 V, code 1
V
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
(1) 1 LSB (VREF 3.63 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 13.44 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
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8.12.3 Temperature and Battery Monitor
8.12.3.1 Temperature Sensor
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Accuracy
Accuracy
2
-40 °C to 0 °C
0 °C to 105 °C
±4.0
±2.5
4.1
°C
°C
Supply voltage coefficient(1)
°C/V
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.12.3.2 Battery Monitor
Measured on the CC26x2REM-7ID-Q1 reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
25
1.8
3.63
72
Integral nonlinearity (max)
Accuracy
28
22.5
-32
mV
mV
mV
%
VDDS = 3.0 V
Offset error
Gain error
-1.3
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8.12.4 Comparators
8.12.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input voltage range(1)
0
VDDS
Offset
Measured at VDDS / 2
Step from –10 mV to 10 mV
Internal reference
±5
0.78
8.6
mV
µs
Decision time
Current consumption
µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.12.4.2 Low-Power Clocked Comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input voltage range
Clock frequency
0
VDDS
V
SCLK_LF
Using internal DAC with VDDS as reference voltage,
DAC code = 0 - 255
Internal reference voltage(1)
Offset
0.024 - 2.865
V
Measured at VDDS / 2, includes error from internal DAC
±5
1
mV
Clock
Cycle
Decision time
Step from –50 mV to 50 mV
(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See DAC Characteristics
8.12.5 Current Source
8.12.5.1 Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25 - 20
0.25
MAX UNIT
Current source programmable output range (logarithmic
range)
µA
µA
Resolution
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8.12.6 GPIO
8.12.6.1 GPIO DC Characteristics
PARAMETER
TEST CONDITIONS
MIN
1.44
1.44
TYP
MAX UNIT
TA = 25 °C, VDDS = 1.8 V
GPIO VOH at 8 mA load
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
V
0.36
V
V
IOCURR = 1
0.36
110
39
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
32
11
68
18.5
1.08
0.72
µA
µA
V
GPIO pulldown current
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
0.72
0.54
1.17
0.87
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
GPIO minimum VIH
GPIO maximum VIL
0.18
1.17
0.36
0.51
V
V
V
Lowest GPIO input voltage reliably interpreted as
High
Highest GPIO Input voltage reliably interpreted as
Low
0.63
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.4
2.4
V
V
V
V
GPIO VOL at 8 mA load
0.6
0.6
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
IOCURR = 1
TA = 25 °C, VDDS = 3.63 V
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.9
2.9
V
V
GPIO VOL at 8 mA load
0.6
GPIO VOH at 4 mA load
V
GPIO VOL at 4 mA load
IOCURR = 1
0.6
380
178
2.21
1.83
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
135
64
264
102
µA
µA
V
GPIO pulldown current
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.52
1.14
1.90
1.48
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
GPIO minimum VIH
GPIO maximum VIL
0.38
2.47
0.42
1.07
V
V
V
Lowest GPIO input voltage reliably interpreted as a
High
Highest GPIO input voltage reliably interpreted as a
Low
1.33
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8.13 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See 节 8.3
for device limits. Values exceeding these limits are for reference only.
8.13.1 MCU Current
Running CoreMark, SCLK_HF = 48 MHz RCOSC
80 kB RAM retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz XOSC VDDS = 3.0 V
6
5.5
5
12
10
8
4.5
4
6
4
3.5
3
2
2.5
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
-40
-25
-10
5
20
35
50
65
80
95 105
Temperature [oC]
Voltage [V]
图8-4. Active Mode (MCU) Current vs. Supply
图8-5. Standby Mode (MCU) Current vs.
Voltage (VDDS)
Temperature
80 kbps RAM Retention, no Cache Retention, RTC On
SCLK_LF = 32 kHz RCOSC VDDS = 3.6 V
12
10
8
6
4
2
0
-40
-25
-10
5
20
35
50
65
80
95 105
Temperature [oC]
图8-6. Standby Mode (MCU) Current vs. Temperature (VDDS = 3.6 V)
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8.13.2 RX Current
11.5
11
10.5
10
9.5
9
8
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6
8.5
8
7.5
7
6.5
6
5.5
5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
-40
-25
-10
5
20
35
50
65
80
95 105
Temperature [oC]
Voltage [V]
图8-8. RX Current versus Supply Voltage (VDDS)
图8-7. RX Current versus Temperature (WBMS,
(WBMS, 2.44 GHz)
2.44 GHz)
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8.13.3 TX Current
12
11.5
11
9
8.8
8.6
8.4
8.2
8
10.5
10
9.5
9
7.8
7.6
7.4
7.2
7
8.5
8
7.5
7
6.8
6.6
6.4
6.2
6
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
-40
-25
-10
5
20
35
50
65
80
95 105
Temperature [oC]
Voltage [V]
图8-10. TX Current vs. Supply Voltage (VDDS)
图8-9. TX Current vs. Temperature (WBMS, 2.44
(WBMS, 2.44 GHz, 0 dBm)
GHz, 0 dBm)
表8-1 shows typical TX current and output power for different output power settings.
表8-1. Typical TX Current and Output Power
CC2662R-Q1 at 2.4 GHz, VDDS = 3.0 V (Measured on CC2652REM-7ID-Q1)
txPower
0x8623
0x5E1A
0x7217
0x4867
0x3860
0x2E5C
0x2E59
0x2853
0x10D9
0x0AD1
0x0ACC
0x0AC8
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
5
4
5.0
4.1
9.2
8.6
8.8
8.2
7.6
7.3
7.0
6.8
5.9
5.3
4.9
4.6
3.5
3
3.6
3.2
2
2.0
1
1.2
0
0.3
-2
-5
-10
-15
-20
-2.2
-5.0
-9.5
-13.7
-18.6
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8.13.4 RX Performance
-87
-88
-89
-90
-91
-92
-93
-94
-95
-96
-97
-84
-85
-86
-87
-88
-89
-90
-91
-92
-93
-94
-95
-96
-97
-98
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
-40
-25
-10
5
20
35
50
65
80
95 105
Frequency [GHz]
Temperature [°C]
图8-11. Sensitivity versus Frequency (WBMS, 2.44 图8-12. Sensitivity versus Temperature (WBMS,
GHz) 2.44 GHz)
-86
-87
-88
-89
-90
-91
-92
-93
-94
-95
-96
-84
-86
-88
-90
-92
-94
-96
-98
-100
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Voltage [V]
图8-13. Sensitivity versus Supply Voltage (VDDS) 图8-14. Sensitivity versus Supply Voltage (VDDS)
(WBMS, 2.44 GHz) (WBMS, 2.44 GHz, DCDC off)
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8.13.5 TX Performance
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
0.8
0.6
0.4
0.2
0
5.8
5.6
5.4
5.2
5
-0.2
-0.4
-0.6
-0.8
-1
4.8
4.6
4.4
4.2
4
-1.2
-1.4
-1.6
-1.8
-2
3.8
3.6
3.4
3.2
3
-40
-25
-10
5
20
35
50
65
80
95 105
-40
-25
-10
5
20
35
50
65
80
95 105
Temperature [oC]
Temperature [oC]
图8-15. Output Power vs. Temperature (WBMS,
图8-16. Output Power vs. Temperature (WBMS,
2.44 GHz, 0dBm)
2.44 GHz, +5dBm)
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
0.8
0.6
0.4
0.2
0
5.8
5.6
5.4
5.2
5
-0.2
-0.4
-0.6
-0.8
-1
4.8
4.6
4.4
4.2
4
-1.2
-1.4
-1.6
-1.8
-2
3.8
3.6
3.4
3.2
3
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Voltage [V]
图8-17. Output Power vs. Supply Voltage (VDDS) 图8-18. Output Power vs. Supply Voltage (VDDS)
(WBMS, 2.44 GHz, 0dBm)
(WBMS, 2.44 GHz, +5dBm)
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
0.8
0.6
0.4
0.2
0
5.8
5.6
5.4
5.2
5
-0.2
-0.4
-0.6
-0.8
-1
4.8
4.6
4.4
4.2
4
-1.2
-1.4
-1.6
-1.8
-2
3.8
3.6
3.4
3.2
3
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
Frequency [GHz]
图8-19. Output Power vs. Frequency (WBMS,
图8-20. Output Power vs. Frequency (WBMS,
0dBm)
+5dBm)
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8.13.6 ADC Performance
11.4
Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
10.2
10.15
10.1
10.05
10
11.1
10.8
10.5
10.2
9.9
9.95
9.9
9.85
9.8
9.6
0.2 0.3
0.5 0.7
1
2
3
4
5
6 7 8 10
20 30 40 50 70 100
1
2
3
4
5
6
7 8 10
Frequency [kHz]
20
30 40 50 70 100
200
Frequency [kHz]
图8-21. ENOB versus Input Frequency
图8-22. ENOB versus Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
1.5
1
2.5
2
1.5
1
0.5
0
-0.5
-1
0.5
0
-1.5
-0.5
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
ADC Code
图8-23. INL versus ADC Code
图8-24. DNL versus ADC Code
Vin = 1 V, Internal reference, 200 kSamples/s
Vin = 1 V, Internal reference, 200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
Voltage [V]
图8-26. ADC Accuracy versus VDDS
图8-25. ADC Accuracy versus Temperature
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9 Detailed Description
9.1 Overview
图4-1 shows the core modules of the CC2662R-Q1 device.
9.2 System CPU
The CC2662R-Q1 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the
application and the higher layers of the Wireless BMS protocol stack.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• IEEE 754-compliant single-precision Floating Point Unit (FPU)
• Memory Protection Unit (MPU) for safety-critical applications
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
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9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that
interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF Core offers a high level, command-based API
to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF Core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power consumption and leaves more resources for the user application. Several signals are
also available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) upgrades while still using the same silicon.
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9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-
system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both
storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by
default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in
memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always
initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically
used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by
the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks,
which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that
can be used for initial programming of the device.
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9.5 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power
modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary
power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby
significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has a syntax
similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential
algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable
state machines, or event routing.
The main advantages are:
• Flexibility - data can be read and processed in unlimited manners while still
• 2 MHz low-power mode enables lowest possible handling of digital sensors
• Dynamic reuse of hardware resources
• 40-bit accumulator supporting multiplication, addition and shift
• Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C
driver source code, which the System CPU application uses to control and exchange data with the Sensor
Controller. Typical use cases may be (but are not limited to) the following:
• Read analog sensors using integrated ADC or comparators
• Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged)
• Capacitive sensing
• Waveform generation
• Very low-power pulse counting (flow metering)
• Key scan
The Sensor Controller peripherals include the following:
• The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator.
The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time-to-digital
converter, and a comparator. The continuous time comparator in this block can also be used as a higher-
accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline
tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive
sensing.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be
triggered by many different sources including timers, I/O pins, software, and comparators.
• The analog modules can connect to up to eight different GPIOs
• Dedicated SPI Controller with up to 6 MHz clock speed
The Sensor Controller peripherals can also be controlled from the main application processor.
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9.6 Cryptography
The CC2662R-Q1 device comes with a wide set of modern cryptography-related hardware accelerators,
drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit of
being lower power and improves availability and responsiveness of the system because the cryptography
operations runs in a background hardware thread.
Together with a large selection of open-source cryptography libraries provided with the Software Development
Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The
hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512
• Advanced Encryption Standard (AES) with 128 and 256 bit key lengths
• Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic
curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available
for an application or stack:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
– Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P224, NIST-P256, NIST-P384, NIST-P521
• Brainpool-256R1, Brainpool-384R1, Brainpool-512R1
• secp256r1
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• SHA2 based MACs
– HMAC with SHA224, SHA256, SHA384, or SHA512
• Block cipher mode of operation
– AESCCM
– AESGCM
– AESECB
– AESCBC
– AESCBC-MAC
• True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as
Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of
the TI SimpleLink SDK for the CC2662R-Q1 device.
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9.7 Timers
A large selection of timers are available as part of the CC2662R-Q1 device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the RCOSC_LF as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the
Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the
RTC halts when a debugger halts the device.
• General-Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Sensor Controller Timers
The Sensor Controller contains 3 timers:
AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each
edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor
Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or
periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as
well as for PWM output or waveform generation.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal as the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
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9.8 Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous
serial interfaces. The SSIs support both SPI Controller and Peripheral up to 4 MHz. The SSI modules support
configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-
rate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both Controller and Target.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in 节 7. All digital peripherals can be connected to any
digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLink™ Wireless MCU Technical Reference Manual.
9.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2662R-Q1 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and
respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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9.12 Power Management
To minimize power consumption, the CC2662R-Q1 supports a number of power modes and power management
features (see 表9-1).
表9-1. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
Active
On
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Off
Off
Off
Off
No
No
Off
Off
Off
Off
No
No
Flash
Available
On
Off
SRAM
On
Retention
Duty Cycled
Partial
Full
Supply System
Register and CPU retention
SRAM retention
On
On
Full
Full
Full
Full
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
Off
Off
Off
Off
2 MHz medium-speed clock
(SCLK_MF)
RCOSC_MF
RCOSC_MF
Available
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
On
Available
Available
Available
Available
On
Off
Available
Available
Available
On
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Sensor Controller
Wake-up on RTC
Off
Wake-up on pin edge
Wake-up on reset pin
Brownout detector (BOD)
Power-on reset (POR)
Watchdog timer (WDT)
Available
On
On
On
Duty Cycled
On
Off
On
On
Off
Available
Available
Paused
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the CPU and all of the peripherals that are currently enabled. The system clock can be any available clock
source (see 表9-1).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor
Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need
to be reconfigured when waking up again, and the CPU continues execution from where it went into standby
mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the
I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin
defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can
differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status
register. The only state retained in this mode is the latched I/O state and the flash memory contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Interface
independently of the system CPU. This means that the system CPU does not have to wake up, for example to
perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would
otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller,
control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be
controlled by the system CPU.
备注
The power, RF and clock management for the CC2662R-Q1 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC2662R-Q1 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS, device drivers, and examples are offered free of charge in source code.
9.13 Clock Systems
The CC2662R-Q1 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the
internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for
internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator
(RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for
ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after
Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768
kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost. Note that theSDK relies on a 32.768 kHz crystal (XOSC_LF)
being used.
9.14 Network Processor
Depending on the product configuration, the CC2662R-Q1 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
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10 Application, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2662R-Q1
device.
Special attention must be paid to RF component placement, decoupling capacitors and DC/DC regulator
components, as well as ground connections for all of these.
CC26x2REM-7ID-Q1 Design
Files
The CC26x2REM-7ID-Q1 reference design provides schematic, layout and
production files for the characterization board used for deriving the
performance number found in this document.
CC2662RQ1-EVM-WBMS
Design Files
The CC2662RQ1-EVM-WBMS Design Files contain detailed schematics and
layouts to build application specific boards using the CC2662R-Q1 device.
Sub-1 GHz and 2.4 GHz
Antenna Kit for LaunchPad™
Development Kit and
SensorTag
The antenna kit allows real-life testing to identify the optimal antenna for your
application. The antenna kit includes 16 antennas covering frequencies from
169 MHz to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.
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10.2 Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various operating
conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature:
T = ψ × P + T
case
(1)
(2)
(3)
J
JT
2. From board temperature:
T = ψ × P + T
board
J
JB
3. From ambient temperature:
T = R
× P + T
A
J
θJA
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply
voltage. Thermal resistance coefficients are found in 节8.8.
Example:
Using 方程式 3, the temperature difference between ambient temperature and junction temperature is
calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm
output power. Let us assume the ambient temperature is 105 °C and the supply voltage is 3 V. To calculate P, we
need to look up the current consumption for Tx at 105 °C in . From the plot, we see that the current consumption
is 7.9 mA. This means that P is 7.9 mA × 3 V = 23.7 mW.
The junction temperature is then calculated as:
°C
T = 23.0
× 23.7mW + T = 0.5°C + T
A
(4)
W
J
A
As can be seen from the example, the junction temperature will be 0.5 °C higher than the ambient temperature
when running continuous Tx at 105 °C.
For various application use cases current consumption for other modules may have to be added to calculate the
appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral
modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the peak
power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current
consumption.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-
code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC2662R-Q1
is in preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RGZ).
For orderable part numbers of CC2662R-Q1 devices in the RGZ (7-mm x 7-mm) package type, see the Package
Option Addendum of this document, the Device Information in 节 3, the TI website (www.ti.com), or contact your
TI sales representative.
CC2662
R
1
FTW RGZ
R
Q1
PREFIX
X = Experimental device
Blank = Qualified devie
AUTOMOTIVE Q1
Q1 = Q100
DEVICE
SimpleLink™ Ultra-Low-Power
Wireless MCU
R = Large Reel
T = Small Reel
CONFIGURATION
R = Regular
PACKAGE
P = +20 dBm PA included
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
ROM Revision
F = Flash
T = -40 C to 105 C
W = Wettable flanks
图11-1. Device Nomenclature
11.2 Tools and Software
The CC2662R-Q1 device is supported by a variety of software and hardware development tools.
Development Kit
CC2662RQ1-EVM-WBMS Development Kit
The SimpleLink CC2662RQ1-EVM-WBMS development kit is an easy-to-use evaluation module for Wireless
BMS evaluation board featuring BQ7961x-Q1 FuSa Compliant and SimpleLink™ CC2662R-Q1 wireless MCU. It
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contains everything needed to start developing on the SimpleLink™ CC2662R-Q1, including a XDS110 JTAG
debug probe for programming, debugging, and energy measurements.
The SimpleLink™ CC2662R-Q1 is an AEC-Q100 compliant wireless microcontroller (MCU) targeting wireless
automotive applications. The device is optimized for low-power wireless communication in applications such as
battery management systems (BMS) and cable replacement.
Software
SimpleLink™ WMBS SDK
The SimpleLink WMBS Software Development Kit (SDK) provides a complete package for the development of
wireless applications on the 2.4 GHz CC2662R-Q1 device
The SimpleLink WMBS SDK is part of TI’s SimpleLink MCU platform, offering a single development
environment that delivers flexible hardware, software and tool options for customers developing wired and
wireless applications. For more information about the SimpleLink MCU Platform, visit http://www.ti.com/
simplelink.
Development Tools
Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster than
ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™ software (application
energy usage profiling). A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS debuggers included
on a LaunchPad Development Kit.
SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure SimpleLink Wireless
MCUs from Texas Instruments. The application will help designers of RF systems to easily evaluate the radio at
an early stage in the design process. It is especially useful for generation of configuration register values and for
practical testing and debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF device. Features of the
SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
Sensor Controller Studio
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller peripheral. The tool
generates a Sensor Controller Interface driver, which is a set of C source files that are compiled into the System
CPU application. These source files also contain the Sensor Controller binary image and allow the System CPU
application to control and exchange data with the Sensor Controller. Features of the Sensor Controller Studio
include:
• Ready-to-use examples for several common use cases
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• Full toolchain with built-in compiler and assembler for programming in a C-like programming language
• Provides rapid development by using the integrated sensor controller task testing and debugging
functionality, including visualization of sensor data and verification of algorithms
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash has a GUI,
command line, and scripting interface. CCS UniFlash is available free of charge.
11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired
and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible
hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use it throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC2662R-Q1. In the upper right corner, click on Alert me to
register and receive a weekly digest of any product information that has changed. For change details, review the
revision history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
Errata
CC2662R-Q1 Silicon Errata
The silicon errata describes the known exceptions to the functional specifications for each silicon revision of the
device and description on how to recognize a device revision.
Application Reports
All application reports for the CC2662R-Q1 device are found on the device product folder at: ti.com/product/
CC2662R-Q1.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLink™ Wireless MCU TRM
The TRM provides a detailed description of all modules and peripherals available in the device family.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.5 Trademarks
Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Wi-Fi® is a registered trademark of Wi-Fi Alliance.
Arm Thumb® is a registered trademark of Arm Limited (or its subsidiaries).
Eclipse® is a registered trademark of Eclipse Foundation.
Windows® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
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11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2023 Texas Instruments Incorporated
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45
Product Folder Links: CC2662R-Q1
English Data Sheet: SWRS259
CC2662R-Q1
ZHCSQR6C –DECEMBER 2020 –REVISED JULY 2023
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12 Mechanical, Packaging, and Orderable Information
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SWRS259
46
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Product Folder Links: CC2662R-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC2662R1FTWRGZRQ1
ACTIVE
VQFN
RGZ
48
4000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
CC2662 Q1
R1F
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2662R1FTWRGZRQ1 VQFN
RGZ
48
4000
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGZ 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
CC2662R1FTWRGZRQ1
4000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
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PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048R
PLASTIC QUAD FLATPACK-NO LEAD
A
7.1
6.9
B
PIN 1 INDEX AREA
7.1
6.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
5.25
5.05
5.5
(0.2) TYP
24
13
12
25
(0.16)
A
A
SYMM
49
5.25
5.05
5.5
1
36
0.3
44X 0.5
48X
0.2
37
48
PIN 1 IDENTIFICATION
(OPTIONAL)
0.1
C A B
C
0.5
0.3
SYMM
48X
0.05
4226144/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048R
PLASTIC QUAD FLATPACK-NO LEAD
(6.8)
(5.15)
SYMM
48X (0.6)
48X (0.25)
48
37
1
36
44X (0.5)
(6.8)
(Ø 0.2) VIA
TYP
49
SYMM
(5.15)
8X
(1.26)
6X
(1.065)
25
12
(R0.05) TYP
24
13
6X (1.065)
8X (1.26)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226144/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048R
PLASTIC QUAD FLATPACK-NO LEAD
(6.8)
16X
(1.06)
SYMM
48X (0.6)
48X (0.25)
48
37
1
49
36
16X
(1.06)
44X (0.5)
(0.63)
SYMM
(6.8)
(1.26)
(R0.05) TYP
25
12
24
13
METAL TYP
(1.26)
(0.63)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 12X
4226144/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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