CD4066B-Q1_14 [TI]
CMOS QUAD BILATERAL SWITCH;
| 型号： | CD4066B-Q1_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CMOS QUAD BILATERAL SWITCH |
| 文件： | 总15页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4066B-Q1
www.ti.com
SCHS383 –APRIL 2011
CMOS QUAD BILATERAL SWITCH
Check for Samples: CD4066B-Q1
1
FEATURES
•
•
•
5-V, 10-V, and 15-V Parametric Ratings
Latch-Up Exceeds 100mA per JESD78 - Class I
•
•
•
Qualified for Automotive Applications
Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications for
Description of "B" Series CMOS Devices
15-V Digital or ±7.5-V Peak-to-Peak Switching
125-Ω Typical On-State Resistance for 15-V
Operation
•
•
•
•
Switch On-State Resistance Matched to Within
5 Ω Over 15-V Signal-Input Range
APPLICATIONS
•
Analog Signal Switching/Multiplexing: Signal
Gating, Modulator, Squelch Control,
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
Demodulator, Chopper, Commutating Switch
High On/Off Output-Voltage Ratio: 80 dB
Typical at fis = 10 kHz, RL = 1 kΩ
•
•
•
Digital Signal Switching/Multiplexing
Transmission-Gate Logic Implementation
High Degree of Linearity: <0.5% Distortion
Typical at fis = 1 kHz, Vis = 5 V p-p,
Analog-to-Digital and Digital-to-Analog
Conversion
VDD – VSS ≥ 10 V, RL = 10 kΩ
•
Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
•
•
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and High
Effective Off-State Resistance: 10 pA Typical
at VDD – VSS = 10 V, TA = 25°C
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal Circuit):
1012 Ω Typical
1
2
3
4
5
6
7
14
13
12
11
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
SIG D IN/OUT
•
•
Low Crosstalk Between Switches: –50 dB
Typical at fis = 8 MHz, RL = 1 kΩ
10 SIG D OUT/IN
Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients
9
8
SIG C OUT/IN
SIG C IN/OUT
•
•
Frequency Response, Switch On = 40 MHz
Typical
100% Tested for Quiescent Current at 20 V
DESCRIPTION/ORDERING INFORMATION
The CD4066B-Q1 is a quad bilateral switch intended for the transmission or multiplexing of analog or digital
signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition,
the on-state resistance is relatively constant over the full signal-input range.
The CD4066B-Q1 consists of four bilateral switches, each with independent controls. Both the p and the n
devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well
of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the
switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal
and, thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CD4066B-Q1
SCHS383 –APRIL 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TA
PACKAGE
–40°C to 125°C
SOIC – D
Reel of 2500
CD4066BQDRQ1
CD4066BQ
Switch
Control
In
V
is
p
n
p
n
Out
V
os
n
Control
†
V
C
V
SS
V
DD
V
SS
†
All control inputs are protected by the CMOS protection network.
NOTES: A.All p substrates are connected to V
.
DD
B. Normal operation control-line biasing: switch on (logic 1), V = V ; switch off (logic 0), V = V
SS
C
DD
C
C. Signal-level range: V ≤V ≤ V
DD
SS
is
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
2
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SCHS383 –APRIL 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
DC supply-voltage range, VDD (voltages referenced to VSS terminal)
Input voltage range, Vis (all inputs)
–0.5 to 20
–0.5 to VDD + 0.5
V
DC input current, IIN (any one input)
±10
86
mA
°C/W
(2)
Package thermal impedance, θJA
D package
Human-Body Model (HBM)
Machine Model (MM)
500
ESD Electrostatic discharge(3)
150
V
Field_Induced_Charged Device Model (CDM)
1000
265
Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max
°C
°C
Storage temperature range, Tstg
–65 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) Tested in accordance with AEC-Q100.
THERMAL INFORMATION
CD4066B-Q1
THERMAL METRIC(1)
D PACKAGE
14 PINS
92.4
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
52.5
46.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
46.4
ψJB
46.4
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
3
MAX UNIT
VDD
TA
Supply voltage
18
V
Operating free-air temperature
–40
125
°C
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LIMITS AT INDICATED TEMPERATURES
25°C
UNIT
VIN
(V)
VDD
(V)
PARAMETER
TEST CONDITIONS
–40°C
125°C
TYP MAX
0.5
5
0.25
0.5
1
7.5
15
0.01
0.01
0.01
0.02
0.25
0.10
0.15
0.20
10
15
20
0.5
1
IDD
Quiescent device current
µA
30
5
150
5
SIGNAL INPUTS (Vis) AND OUTPUTS (Vos
)
VC = VDD, RL = 10 kΩ returned
5
850
330
1300
550
470 1050
10
180
125
400
240
ron
On-state resistance (max)
Ω
Ω
VDD VSS
to
,
15
210
320
2
Vis = VSS to VDD
5
15
10
5
On-state resistance
difference between any two RL = 10 kΩ, VC = VDD
switches
Δron
10
15
VC = VDD = 5 V, VSS = –5 V,
THD
Total harmonic distortion
Vis(p-p) = 5 V (sine wave centered on 0 V),
0.4%
RL = 10 kΩ, fis = 1-kHz sine wave
3-dB cutoff frequency
(switch on)
VC = VDD = 5 V, VSS = –5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
40
1
MHz
MHz
µA
–50-dB feedthrough
frequency (switch off)
VC = VSS = –5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
Input/output leakage current VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V,
(switch off) (max)
±10-5
Iis
18
±0.1
±1
±0.1
Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
–50-dB crosstalk frequency
VC(B) = VSS = -5 V,
Vis(A) = 5 Vp-p, 50-Ω source, RL = 1 kΩ
8
MHz
ns
5
20
10
7
40
20
15
RL = 200 kΩ, VC = VDD, VSS = GND,
CL = 50 pF, Vis = 10 V
(square wave centered on 5 V), tr, tf = 20 ns
Propagation delay (signal
input to signal output)
tpd
10
15
Cis
Input capacitance
Output capacitance
Feedthrough
VDD = 5 V, VC = VSS = –5 V
VDD = 5 V, VC = VSS = –5 V
VDD = 5 V, VC = VSS = –5 V
8
pF
pF
pF
Cos
Cios
8
0.5
4
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SCHS383 –APRIL 2011
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
LIMITS AT INDICATED TEMPERATURES
25°C
UNIT
VIN
(V)
VDD
(V)
PARAMETER
CONTROL (VC)
TEST CONDITIONS
–40°C
125°C
TYP MAX
5
1
2
2
1
2
1
2
2
|Iis| < 10 mA, Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = VSS
Control input, low voltage
(max)
VILC
10
15
5
V
V
2
3.5 (MIN)
7 (MIN)
11 (MIN)
±1
VIHC
Control input, low voltage
Input current (max)
See Figure 6
10
15
18
±10-5
±0.1
IIN
Vis ≤ VDD, VDD – VSS = 18 V, VCC ≤ VDD – VSS
±0.1
µA
VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ
Crosstalk (control input to
signal output)
10
50
mW
5
35
20
15
6
70
40
30
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 kΩ
Turn-on and turn-off
propagation delay
10
15
5
ns
Vis = VDD, VSS = GND, RL = 1 kΩ to GND,
CL = 50 pF, VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz
Maximum control input
repetition rate
10
9
MHz
pF
15
9.5
5
Ci
Input capacitance
SWITCHING CHARACTERISTICS
SWITCH INPUT
Iis (mA)
SWITCH OUTPUT,
Vos (V)
VDD
(V)
Vis
(V)
–40°C
25°C
0.51
–0.51
1.3
125°C
0.36
–0.36
0.9
MIN
MAX
5
0
5
0.61
–0.61
1.5
0.4
5
4.6
10
10
15
15
0
10
0
–1.6
4
–1.3
3.4
–0.9
2.4
1.5
15
–4
–3.4
–2.4
13.5
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TYPICAL CHARACTERISTICS
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (V − V ) = 5 V
DD SS
600
500
400
300
200
300
250
Supply Voltage (V − V ) = 10 V
DD SS
T
= 125°C
A
T
A
= 125°C
200
150
+25°C
+25°C
−55°C
−55°C
100
100
0
50
0
−4
−3
−2
−1
0
1
2
3
4
−10 −7.5 −5 −2.5
0
2.5
5
7.5
10
V
is
− Input Signal Voltage − V
V
is
− Input Signal Voltage − V
92CS-27326RI
92CS-27327RI
Figure 2.
Figure 3.
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
T
A
= 125°C
Supply Voltage (V − V ) = 15 V
DD SS
600
500
300
250
200
150
100
Supply Voltage (V − V ) = 5 V
DD SS
400
300
200
T
A
= 125°C
+25°C
−55°C
10 V
−15 V
100
0
50
0
−10 −7.5 −5 −2.5
0
2.5
5
7.5
10
−10 −7.5 −5 −2.5
0
2.5
5
7.5
10
− Input Signal Voltage − V
V
is
− Input Signal Voltage − V
V
is
92CS-27330RI
92CS-27329RI
Figure 4.
Figure 5.
I
is
CD4066B
1 of 4 Switches
V
is
V
os
|V − V
is
|
os
r
=
on
|I |
is
92CS-30966
Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
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SCHS383 –APRIL 2011
TYPICAL CHARACTERISTICS (continued)
Keithley
160 Digital
Multimeter
V
DD
TG
10 kΩ
1-kΩ
On
Y
X
Range
H. P.
X-Y
V
SS
Moseley
7030A
Plotter
92CS-22716
Figure 7. Channel On-State Resistance Measurement Circuit
TYPICAL ON CHARACTERISTICS
FOR 1 OF 4 CHANNELS
POWER DISSIPATION PER PACKAGE
vs
SWITCHING FREQUENCY
4
10
10
10
10
3
2
1
6
4
T
A
= 25°C
2
3
Supply Voltage
6
4
(V ) = 15 V
DD
2
2
10 V
0
V
V
= V
DD
DD
C
V
DD
6
5 V
V
os
4
CD4066B
1 of 4
Switches
5
6
−1
V
is
2
R
L
CD4066B
1
12
13
V
SS
−2
6
4
All unused terminals are
connected to V
SS
7
2
−3
−3
V
6
SS
−2
−1
0
1
2
3
4
10
2
4
6
2
4
2
3
10
10
10
V − Input Voltage − V
I
92CS-30919
f − Switching Frequency − kHz
92C-30920
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
C
V
DD
ios
V
= V
C
SS
V
os
CD4066B
1 of 4
Switches
V
is
= V
DD
V
DD
= 5 V
V
= −5 V
C
I
CD4066B
1 of 4
V
SS
Switches
92CS-30922
All unused terminals are connected to V
.
SS
C
is
C
os
V
SS = −5 V
92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
Figure 10. Typical On Characteristics for One of Four
Channels
Figure 11. Off-Switch Input or Output Leakage
+10 V
V
DD
V
V
V
DD
C
V
C
= V
DD
V
os
V
t = t = 20 ns
r f
is
os
CD4066B
1 of 4
Switches
CD4066B
1 of 4
V
is
Switches
10 kΩ
1 kΩ
200 kΩ
50 pF
V
V
SS
SS
V
DD
92CS-30924
t = t = 20 ns
f
r
All unused terminals are connected to V
.
92CS-30923
SS
All unused terminals are connected to V
.
SS
Figure 12. Propagation Delay Time Signal Input (Vis) to
Figure 13. Crosstalk-Control Input to Signal Output
Signal Output (Vos
)
V
DD
V
DD
V
= V
DD
C
t = t = 20 ns
f
r
V
os
CD4066B
1 of 4
Switches
V
DD
1 kΩ
50 pF
V
SS
92CS-30925
NOTES: A.All unused terminals are connected to V
.
SS
B. Delay is measured at V level of +10% from ground (turn-on) or on-state output level (turn-off).
os
Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
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SCHS383 –APRIL 2011
TYPICAL CHARACTERISTICS (continued)
t
t
f
r
10 V
0 V
V
C
90%
50%
10%
Repetition
Rate
t = t = 20 ns
f
r
V
OS at 1kHz
V
os
VOS
2
V
DD
= 10 V
V
V
OS at 1kHz
2
C
VOS
CD4066B
1 of 4
Switches
V
is
= 10 V
1 kΩ
50 pF
V
SS
All unused terminals are connected to V
.
92CS-30925
SS
Figure 15. Maximum Allowable Control-Input Repetition Rate
V
DD
Inputs
V
DD
I
V
SS
92CS-27555
V
SS
Measure inputs sequentially to both V and V . Connect all unused inputs to either V or V . Measure control inputs only.
DD
DD
SS
SS
Figure 16. Input Leakage-Current Test Circuit
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TYPICAL CHARACTERISTICS (continued)
10
2
3
12
7
9
10
3
7
9
2
12
Clock
14
15
Clock
14
P
J
J
J
J
J
5
E
1
2
3
4
P
J
J
J
J
J
5
E
1
2
3
4
External
Reset
CD4018B
Reset
15
1
CD4018B
13
Q
Q
2
1
1
Q
5
Q
4
1
2
5
4
1
1/4 CD4066B
2
13
12
9
8
5
1
6
2
1
3
4
7
6
2
1/3 CD4049B
3
5
6
2
4
CD4001B
10
9
10
1/3 CD4049B
3
4
11
5
8
10
9
Signal
12
6
5
11
2
5
13
6
12
Outputs
11
Channel 1
Channel 2
Channel 3
Channel 4
13
LPF
Signal
Inputs
11
12
12
10 kΩ
Channel 1
Channel 2
Channel 3
Channel 4
1/6 CD4049B
5
2
3
1
4
1
4
CD4066B
3
9
LPF
8
9
10 kΩ
CD4066B
1/4 CD4066B
4
3
8
10
11
11
LPF
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
10 kΩ
10 kΩ
LPF
V
10
DD
Clock
Maximum
Allowable
10 kΩ
30% (V − V
DD
)
SS
V
SS
Signal Level
Chan 1 Chan 2 Chan 3 Chan 4
92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
5 V
Analog Inputs (±5 V)
0
−5 V
V
DD
= 5 V
V
DD
= 5 V
CD4066B
5 V
0
SW
A
SW
B
IN
CD4054B
SW
C
SW
D
Digital
Control
Inputs
V
SS
= 0 V
V
SS
= −5 V
V
EE
= −5 V
Analog Outputs (±5 V)
92CS-30927
Figure 18. Bidirectional Signal Transmission Via Digital Control Logic
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APPLICATION INFORMATION
In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B-Q1 bilateral switches). This provision
avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the
CD4066B-Q1.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To
avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the
bidirectional switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CD4066BQDRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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OTHER QUALIFIED VERSIONS OF CD4066B-Q1 :
Catalog: CD4066B
•
Military: CD4066B-MIL
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2011
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 2
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