CD4070BPWG4 [TI]

CMOS Quad Exclusive-OR and Exclusive-NOR Gate; CMOS四路异或及异或非门
CD4070BPWG4
型号: CD4070BPWG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

CMOS Quad Exclusive-OR and Exclusive-NOR Gate
CMOS四路异或及异或非门

文件: 总30页 (文件大小:1223K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CD4070B,  
CD4077B  
Data sheet acquired from Harris Semiconductor  
SCHS055E  
CMOS Quad Exclusive-OR  
and Exclusive-NOR Gate  
January 1998 - Revised September 2003  
Features  
Ordering Information  
• High-Voltage Types (20V Rating)  
• CD4070B - Quad Exclusive-OR Gate  
• CD4077B - Quad Exclusive-NOR Gate  
• Medium Speed Operation  
TEMP. RANGE  
o
PART NUMBER  
CD4070BE  
( C)  
PACKAGE  
14 Ld PDIP  
[ /Title  
(CD40  
70B,  
CD407  
7B)  
/Sub-  
ject  
(CMO  
SQuad  
Exclu-  
sive-  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
CD4070BF3A  
CD4070BM  
14 Ld CERDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- t  
, t  
PHL PLH  
= 65ns (Typ) at V = 10V, C = 50pF  
DD L  
• 100% Tested for Quiescent Current at 20V  
• Standardized Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
CD4070BMT  
CD4070BM96  
CD4070BNSR  
CD4070BPW  
CD4070BPWR  
CD4077BE  
• Maximum Input Current of 1µA at 18V Over Full  
Package Temperature Range  
o
- 100nA at 18V and 25 C  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
14 Ld CERDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
• Noise Margin (Over Full Package Temperature Range)  
OR  
and  
- 1V at V  
DD  
= 5V, 2V at V  
DD  
= 10V, 2.5V at V  
= 15V  
DD  
• Meets All Requirements of JEDEC Standard No. 13B,  
“Standard Specifications for Description of ‘B’ Series  
CMOS Devices  
Exclu-  
sive-  
NOR  
Gate)  
/Autho  
r ()  
/Key-  
words  
(Har-  
ris  
Semi-  
con-  
CD4077BF3A  
CD4077BM  
Applications  
CD4077BMT  
CD4077BM96  
CD4077BNSR  
CD4077BPW  
CD4077BPWR  
• Logical Comparators  
• Adders/Subtractors  
• Parity Generators and Checkers  
14 Ld TSSOP  
14 Ld TSSOP  
Description  
The Harris CD4070B contains four independent Exclusive-  
OR gates. The Harris CD4077B contains four independent  
Exclusive-NOR gates.  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
ductor,  
CD400  
0,  
The CD4070B and CD4077B provide the system designer  
with a means for direct implementation of the Exclusive-OR  
and Exclusive-NOR functions, respectively.  
metal  
gate,  
CMOS  
, pdip,  
cerdip,  
mil,  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD4070B, CD4077B  
Pinouts  
CD4070B  
(PDIP, CERDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
CD4077B  
(PDIP, CERDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
A
B
B
D
C
D
1
2
3
4
5
6
7
14  
13  
12  
V
A
B
B
D
C
D
1
2
3
4
5
6
7
14  
13  
12  
V
DD  
DD  
H
G
H
G
J = A  
K = C  
J = A  
11 M = G  
10 L = E  
H
K = C  
11 M = G  
10 L = E  
H
F
F
9
8
F
E
9
8
F
E
V
V
SS  
SS  
Functional Diagrams  
CD4070B  
CD4077B  
1
1
2
A
3
4
A
B
3
J
2
J
B
J = A  
B
D
J = A  
K = C  
B
5
6
C
5
6
K =  
C
D
C
D
4
D
K
L
K
L
M = G  
L = E  
H
F
8
9
8
9
E
F
M = G  
L = E  
H
F
10  
11  
E
F
10  
11  
V
V
= 7  
= 14  
SS  
DD  
12  
13  
12  
13  
G
H
G
H
M
M
2
CD4070B, CD4077B  
V
DD  
V
DD  
V
DD  
p
n
V
DD  
p
B  
p
B †  
n
2(5,9,12)  
p
n
V
n
2(5,9,12)  
n
V
p
SS  
DD  
p
p
SS  
DD  
J
V
p
p
J
V
p
p
n
3(4,10,11)  
n
A †  
3(4,10,11)  
n
A †  
1(6,8,13)  
n
n
1(6,8,13)  
n
V
SS  
V
SS  
V
V
DD  
DD  
V
V
SS  
SS  
INPUTS PROTECTED  
BY CMOS PROTECTION  
NETWORK  
INPUTS PROTECTED  
BY CMOS PROTECTION  
NETWORK  
V
V
SS  
SS  
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B  
(1 OF 4 IDENTICAL GATES)  
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B  
(1 OF 4 IDENTICAL GATES)  
CD4070B TRUTH TABLE (1 OF 4 GATES)  
CD4077B TRUTH TABLE (1 OF 4 GATES)  
A
0
1
0
1
B
0
0
1
1
J
0
1
1
0
A
B
0
0
1
1
J
1
0
0
1
0
1
0
1
NOTE:  
NOTE:  
1 = High Level  
0 = Low Level  
1 = High Level  
0 = Low Level  
J = A  
B
J = A  
B
3
CD4070B, CD4077B  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage Range (V ) . . . . . . . . . . . . . . . . . -0.5V to 20V  
DD  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113 C/W  
Maximum Junction Temperature (Hermetic Package or Die) . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
o
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to V  
0.5V  
DD  
o
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA  
o
o
Operating Conditions  
o
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
o
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V  
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
o
LIMITS AT INDICATED TEMPERATURES ( C)  
CONDITIONS  
25  
V
V
V
DD  
O
IN  
PARAMETER  
(V)  
(V)  
0, 5  
0, 10  
0, 15  
0, 20  
0, 5  
0, 10  
0, 15  
0, 5  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
-
(V)  
-55  
0.25  
0.5  
1
-40  
0.25  
0.5  
1
85  
7.5  
15  
125  
7.5  
MIN  
TYP  
0.01  
0.01  
0.01  
0.02  
1
MAX  
UNITS  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
Quiescent Device Current  
-
5
-
0.25  
I
Max  
DD  
-
10  
15  
20  
5
15  
-
0.5  
-
30  
30  
-
-
1
-
5
5
150  
0.42  
1.1  
2.8  
-0.42  
-1.3  
-1.1  
-2.8  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
150  
0.36  
0.9  
5
Output Low (Sink) Current  
Min  
0.4  
0.64  
1.6  
4.2  
-0.64  
-2  
0.61  
1.5  
4
0.51  
1.3  
3.4  
-0.51  
-1.6  
-1.3  
-3.4  
-
-
I
OL  
0.5  
10  
15  
5
2.6  
6.8  
-1  
-
1.5  
2.4  
-
Output High (Source) Current  
Min  
4.6  
-0.61  
-1.8  
-1.5  
-4  
-0.36  
-1.15  
-0.9  
-2.4  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
-
I
OH  
2.5  
5
-3.2  
-2.6  
-6.8  
0
-
9.5  
10  
15  
5
-1.6  
-4.2  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
-
13.5  
-
Output Voltage: Low Level,  
Max  
-
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
0.05  
V
OL  
-
10  
15  
5
-
0
0.05  
V
-
-
0
0.05  
V
Output Voltage: High Level,  
Min  
-
4.95  
9.95  
14.95  
-
5
-
V
V
OH  
-
-
10  
15  
5
10  
15  
-
-
V
-
V
Input Low Voltage,  
Max  
0.5, 4.5  
1, 9  
1.5  
V
V
IL  
-
10  
15  
5
3
-
-
3
V
1.5, 13.5  
0.5, 4.5  
1, 9  
-
4
4
4
4
-
-
4
V
Input High Voltage,  
Min  
-
3.5  
7
3.5  
7
3.5  
7
3.5  
3.5  
7
-
-
V
V
IH  
-
10  
15  
18  
7
-
-
-
V
1.5, 13.5  
-
-
11  
11  
11  
11  
11  
-
-
V
-5  
±10  
Input Current, I Max  
IN  
0, 18  
±0.1  
±0.1  
±1  
±1  
±0.1  
µA  
4
CD4070B, CD4077B  
o
AC Electrical Specifications  
T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ  
A
r
f
L
L
TEST CONDITIONS  
LIMITS ON ALL TYPES  
PARAMETER  
SYMBOL  
V
(V)  
TYP  
140  
65  
MAX  
280  
130  
100  
200  
100  
80  
UNITS  
ns  
DD  
Propagation Delay Time  
t
, t  
PHL PLH  
5
10  
15  
5
ns  
50  
ns  
Transition Time  
t
, t  
THL TLH  
100  
50  
ns  
10  
15  
ns  
40  
ns  
Input Capacitance  
C
Any Input  
5
7.5  
pF  
IN  
Typical Performance Curves  
o
o
T
= 25 C  
T = 25 C  
A
A
30  
25  
20  
15  
10  
5
GATE TO SOURCE VOLTAGE (V ) = 15V  
GS  
15  
12.5  
10  
GATE TO SOURCE VOLTAGE (V ) = 15V  
GS  
10V  
10V  
7.5  
5
5V  
5V  
2.5  
0
0
0
0
5
10  
15  
5
10  
15  
V
, DRAIN TO SOURCE VOLTAGE (V)  
V , DRAIN TO SOURCE VOLTAGE (V)  
DS  
DS  
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT  
CHARACTERISTICS  
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT  
CHARACTERISTICS  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
-15  
-10  
-5  
0
-15  
-10  
-5  
0
0
0
o
o
T
= 25 C  
A
T
= 25 C  
A
-5  
GATE TO SOURCE VOLTAGE (V ) = -5V  
GS  
GATE TO SOURCE VOLTAGE (V ) = -5V  
GS  
-10  
-15  
-20  
-25  
-30  
-5  
-10V  
-10V  
-10  
-15  
-15V  
-15V  
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT  
CHARACTERISTICS  
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT  
CHARACTERISTICS  
5
Typical Performance Curves (Continued)  
o
T
= 25 C  
A
o
T
= 25 C  
A
300  
200  
100  
0
200  
150  
100  
50  
SUPPLY VOLTAGE (V ) = 5V  
DD  
SUPPLY VOLTAGE (V ) = 5V  
DD  
10V  
10V  
15V  
15V  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
110  
C , LOAD CAPACITANCE (pF)  
C , LOAD CAPACITANCE (pF)  
L
L
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF  
LOAD CAPACITANCE  
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A  
FUNCTION OF LOAD CAPACITANCE  
5
10  
o
o
T
= 25 C  
T
= 25 C  
A
A
LOAD CAPACITANCE C = 50pF  
L
4
3
2
10  
10  
10  
300  
200  
100  
0
10V  
C
= 50pF  
L
10V  
= 15pF  
C
L
10  
1
5V  
-1  
10  
-1  
2
3
4
0
5
10  
15  
20  
10  
1
10  
10  
10  
10  
V
, SUPPLY VOLTAGE (V)  
f , INPUT FREQUENCY (kHz)  
DD  
I
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A  
FUNCTION OF SUPPLY VOLTAGE  
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A  
FUNCTION OF INPUT FREQUENCY  
6
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
PACKAGING INFORMATION  
Orderable Device  
CD4070BE  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
PDIP  
N
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4070BEE4  
PDIP  
N
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4070BF  
CD4070BF3A  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
CDIP  
SOIC  
J
J
14  
14  
14  
14  
1
1
TBD  
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
CD4070BF3AS2534  
CD4070BM  
OBSOLETE  
ACTIVE  
J
Call TI  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4070BM96  
CD4070BM96E4  
CD4070BM96G4  
CD4070BME4  
CD4070BMG4  
CD4070BMT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4070BMTE4  
CD4070BMTG4  
CD4070BNSR  
CD4070BNSRE4  
CD4070BNSRG4  
CD4070BPW  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PDIP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4070BPWE4  
CD4070BPWG4  
CD4070BPWR  
CD4070BPWRE4  
CD4070BPWRG4  
CD4077BE  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4077BEE4  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4077BF  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
J
J
14  
14  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
CD4077BF3A  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
Orderable Device  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
CD4077BM  
CD4077BM96  
SOIC  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4077BM96E4  
CD4077BM96G4  
CD4077BME4  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4077BMG4  
CD4077BMT  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4077BMTE4  
CD4077BMTG4  
CD4077BNSR  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
J
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4077BNSRE4  
CD4077BNSRG4  
CD4077BPW  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
CDIP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4077BPWE4  
CD4077BPWG4  
CD4077BPWR  
CD4077BPWRE4  
CD4077BPWRG4  
JM38510/17203BCA  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
1
TBD  
A42  
N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
CD4070BM96  
CD4070BNSR  
CD4070BPWR  
CD4077BM96  
CD4077BNSR  
CD4077BPWR  
SOIC  
SO  
D
14  
14  
14  
14  
14  
14  
2500  
2000  
2000  
2500  
2000  
2000  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
16.4  
12.4  
16.4  
16.4  
12.4  
6.5  
8.2  
7.0  
6.5  
8.2  
7.0  
9.0  
10.5  
5.6  
2.1  
2.5  
1.6  
2.1  
2.5  
1.6  
8.0  
12.0  
8.0  
16.0  
16.0  
12.0  
16.0  
16.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
NS  
PW  
D
TSSOP  
SOIC  
SO  
9.0  
8.0  
NS  
PW  
10.5  
5.6  
12.0  
8.0  
TSSOP  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD4070BM96  
CD4070BNSR  
CD4070BPWR  
CD4077BM96  
CD4077BNSR  
CD4077BPWR  
SOIC  
SO  
D
14  
14  
14  
14  
14  
14  
2500  
2000  
2000  
2500  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
33.0  
29.0  
33.0  
33.0  
29.0  
NS  
PW  
D
TSSOP  
SOIC  
SO  
NS  
PW  
TSSOP  
Pack Materials-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CD4070BE  
CD4070BEE4  
CD4070BF  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
CDIP  
CDIP  
CDIP  
SOIC  
N
N
J
14  
14  
14  
14  
14  
14  
25  
25  
1
Pb-Free (RoHS)  
Pb-Free (RoHS)  
TBD  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
ACTIVE  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
CD4070BF3A  
CD4070BF3AS2534  
CD4070BM  
ACTIVE  
J
1
TBD  
OBSOLETE  
ACTIVE  
J
TBD  
Call TI  
D
50  
2500  
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CD4070BM96  
CD4070BM96E4  
CD4070BM96G4  
CD4070BME4  
CD4070BMG4  
CD4070BMT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
D
50  
Green (RoHS  
& no Sb/Br)  
D
250  
250  
250  
2000  
2000  
2000  
90  
Green (RoHS  
& no Sb/Br)  
CD4070BMTE4  
CD4070BMTG4  
CD4070BNSR  
CD4070BNSRE4  
CD4070BNSRG4  
CD4070BPW  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
NS  
NS  
NS  
PW  
PW  
Green (RoHS  
& no Sb/Br)  
SO  
Green (RoHS  
& no Sb/Br)  
SO  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
CD4070BPWE4  
90  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2012  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CD4070BPWG4  
CD4070BPWR  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
14  
14  
14  
14  
90  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
2000  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CD4070BPWRE4  
CD4070BPWRG4  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
CD4077BE  
CD4077BEE4  
CD4077BF  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
CDIP  
CDIP  
SOIC  
N
N
J
14  
14  
14  
14  
14  
25  
25  
1
Pb-Free (RoHS)  
Pb-Free (RoHS)  
TBD  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
CD4077BF3A  
CD4077BM  
J
1
TBD  
D
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CD4077BM96  
CD4077BM96E4  
CD4077BM96G4  
CD4077BME4  
CD4077BMG4  
CD4077BMT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
2500  
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
D
50  
Green (RoHS  
& no Sb/Br)  
D
250  
250  
250  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
CD4077BMTE4  
CD4077BMTG4  
CD4077BNSR  
CD4077BNSRE4  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
NS  
NS  
Green (RoHS  
& no Sb/Br)  
SO  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2012  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CD4077BNSRG4  
CD4077BPW  
SO  
NS  
PW  
PW  
PW  
14  
14  
14  
14  
2000  
90  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
TSSOP  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CD4077BPWE4  
CD4077BPWG4  
90  
Green (RoHS  
& no Sb/Br)  
90  
Green (RoHS  
& no Sb/Br)  
JM38510/17203BCA  
M38510/17203BCA  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
J
J
14  
14  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF CD4070B, CD4070B-MIL, CD4077B, CD4077B-MIL :  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Jan-2012  
Catalog: CD4070B, CD4077B  
Military: CD4070B-MIL, CD4077B-MIL  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Military - QML certified for Military and Defense Applications  
Addendum-Page 4  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CD4070BM96  
CD4070BMT  
CD4070BNSR  
CD4070BPWR  
CD4077BM96  
CD4077BMT  
CD4077BNSR  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
2500  
250  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
16.4  
16.4  
12.4  
16.4  
16.4  
16.4  
6.5  
6.5  
8.2  
6.9  
6.5  
6.5  
8.2  
9.0  
9.0  
2.1  
2.1  
2.5  
1.6  
2.1  
2.1  
2.5  
8.0  
8.0  
16.0  
16.0  
16.0  
12.0  
16.0  
16.0  
16.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
NS  
PW  
D
2000  
2000  
2500  
250  
10.5  
5.6  
12.0  
8.0  
TSSOP  
SOIC  
SOIC  
SO  
9.0  
8.0  
D
9.0  
8.0  
NS  
2000  
10.5  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD4070BM96  
CD4070BMT  
CD4070BNSR  
CD4070BPWR  
CD4077BM96  
CD4077BMT  
CD4077BNSR  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
2500  
250  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
38.0  
38.0  
35.0  
38.0  
38.0  
38.0  
NS  
PW  
D
2000  
2000  
2500  
250  
TSSOP  
SOIC  
SOIC  
SO  
D
NS  
2000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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